bin/ksh/vi.c

1772

display(wbuf[1 - win], wbuf[win], leftside);

bin/ksh/vi.c

66

static void display(char *, char *, int);

bin/ls/ls.c

364

display(NULL, chp);

bin/ls/ls.c

397

display(p, chp);

bin/ls/ls.c

57

static void display(FTSENT *, FTSENT *);

games/fortune/fortune/fortune.c

115

void display(FILEDESC *);

games/fortune/fortune/fortune.c

177

display(Fortfile);

games/worm/worm.c

200

display(head, HEAD);

games/worm/worm.c

213

display(np, BODY);

games/worm/worm.c

338

display(tail, ' ');

games/worm/worm.c

346

display(head, BODY);

games/worm/worm.c

365

display(nh, HEAD);

games/worm/worm.c

73

void display(struct body *, char);

include/sndio.h

120

char display[SIOCTL_DISPLAYMAX]; /* free-format hint */

lib/libexpat/tests/minicheck.c

240

int display = (int)(percentage * 100);

lib/libexpat/tests/minicheck.c

241

printf("%d%%: Checks: %d, Failed: %d\n", display, runner->nchecks,

lib/libfido2/src/cbor.c

454

const char *display = user->display_name;

lib/libfido2/src/cbor.c

462

(display && cbor_add_string(item, "displayName", display) < 0)) {

lib/libsndio/amsg.h

155

char display[AMSG_CTL_DISPLAYMAX]; /* free-format hint */

lib/libsndio/sioctl_aucat.c

90

strlcpy(desc.display, c->display, SIOCTL_DISPLAYMAX);

lib/libsndio/sioctl_sun.c

174

strlcpy(hdl->display, "unknown", SIOCTL_DISPLAYMAX);

lib/libsndio/sioctl_sun.c

176

strlcpy(hdl->display, getdev.name, SIOCTL_DISPLAYMAX);

lib/libsndio/sioctl_sun.c

177

DPRINTF("init: server.device: display = %s\n", hdl->display);

lib/libsndio/sioctl_sun.c

437

strlcpy(desc.display, hdl->display, SIOCTL_DISPLAYMAX);

lib/libsndio/sioctl_sun.c

56

char display[SIOCTL_DISPLAYMAX];

regress/lib/libpthread/group/group.c

106

CHECKr(pthread_mutex_unlock(&display));

regress/lib/libpthread/group/group.c

153

CHECKr(pthread_mutex_init(&display, NULL));

regress/lib/libpthread/group/group.c

159

pthread_mutex_lock(&display);

regress/lib/libpthread/group/group.c

172

pthread_cond_wait(&done, &display);

regress/lib/libpthread/group/group.c

24

pthread_mutex_t display;

regress/lib/libpthread/group/group.c

46

CHECKr(pthread_mutex_lock(&display));

sbin/disklabel/disklabel.c

267

display(stdout, &lab, print_unit, 1);

sbin/disklabel/disklabel.c

616

display(fp, lp, 0, 1);

sbin/disklabel/editor.c

337

display(stdout, &newlab, arg ? *arg : 0, 0);

sbin/disklabel/editor.c

435

display(fp, &newlab, 0, 1);

sbin/disklabel/extern.h

29

void display(FILE *, const struct disklabel *, char, int);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

532

struct mod_hdcp_display *display = &hdcp_work[link_index].display;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

543

memset(display, 0, sizeof(*display));

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

546

display->index = aconnector->base.index;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

547

display->state = MOD_HDCP_DISPLAY_ACTIVE;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

557

display->controller = CONTROLLER_ID_D0 + config->otg_inst;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

558

display->dig_fe = config->dig_fe;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

561

display->stream_enc_idx = config->stream_enc_idx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

574

display->adjust.disable = MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

578

hdcp_w->encryption_status[display->index] = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

588

mod_hdcp_add_display(&hdcp_w->hdcp, link, display, &hdcp_w->output);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h

52

struct mod_hdcp_display display;

sys/dev/pci/drm/amd/display/dc/dm_services.h

247

(struct dc_context *ctx, enum dm_acpi_display_type display,

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

256

struct mod_hdcp_display *display,

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

263

display->adjust.disable == true &&

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

265

display->adjust.disable = false;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

272

display->adjust.disable = true;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

276

memcmp(adj, &display->adjust,

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

321

struct mod_hdcp_link *link, struct mod_hdcp_display *display,

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

327

HDCP_TOP_INTERFACE_TRACE_WITH_INDEX(hdcp, display->index);

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

331

if (display->state != MOD_HDCP_DISPLAY_ACTIVE) {

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

337

if (get_active_display_at_index(hdcp, display->index)) {

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

362

*display_container = *display;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

383

struct mod_hdcp_display *display = NULL;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

389

display = get_active_display_at_index(hdcp, index);

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

390

if (!display) {

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

410

memset(display, 0, sizeof(struct mod_hdcp_display));

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

429

struct mod_hdcp_display *display = NULL;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

435

display = get_active_display_at_index(hdcp, index);

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

436

if (!display) {

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

444

memcmp(display_adjust, &display->adjust,

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

452

memcmp(display_adjust, &display->adjust,

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

454

status = update_display_adjustments(hdcp, display, display_adjust);

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

472

display->adjust = *display_adjust;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

489

struct mod_hdcp_display *display = NULL;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

492

display = get_active_display_at_index(hdcp, index);

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

493

if (!display) {

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

500

query->display = display;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

504

if (is_display_encryption_enabled(display)) {

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.h

515

static inline uint8_t is_display_active(struct mod_hdcp_display *display)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.h

517

return display->state >= MOD_HDCP_DISPLAY_ACTIVE;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.h

520

static inline uint8_t is_display_encryption_enabled(struct mod_hdcp_display *display)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.h

522

return display->state >= MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.h

540

struct mod_hdcp_display *display = NULL;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.h

544

display = &hdcp->displays[i];

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.h

547

return display;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.h

554

struct mod_hdcp_display *display = NULL;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.h

559

display = &hdcp->displays[i];

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.h

562

return display;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.h

569

struct mod_hdcp_display *display = NULL;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.h

573

display = &hdcp->displays[i];

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.h

576

return display;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

103

dtm_cmd->dtm_in_message.topology_update_v3.display_handle = display->index;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

113

display->state = MOD_HDCP_DISPLAY_INACTIVE;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

115

display->state = MOD_HDCP_DISPLAY_ACTIVE;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

116

HDCP_TOP_REMOVE_DISPLAY_TRACE(hdcp, display->index);

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

123

struct mod_hdcp *hdcp, struct mod_hdcp_display *display)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

132

display->state = MOD_HDCP_DISPLAY_INACTIVE;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

142

dtm_cmd->dtm_in_message.topology_update_v2.display_handle = display->index;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

144

dtm_cmd->dtm_in_message.topology_update_v2.controller = display->controller;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

147

dtm_cmd->dtm_in_message.topology_update_v2.dig_fe = display->dig_fe;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

151

dtm_cmd->dtm_in_message.topology_update_v2.dp_mst_vcid = display->vc_id;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

159

display->state = MOD_HDCP_DISPLAY_INACTIVE;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

162

HDCP_TOP_ADD_DISPLAY_TRACE(hdcp, display->index);

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

170

struct mod_hdcp *hdcp, struct mod_hdcp_display *display)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

179

display->state = MOD_HDCP_DISPLAY_INACTIVE;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

189

dtm_cmd->dtm_in_message.topology_update_v3.display_handle = display->index;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

191

dtm_cmd->dtm_in_message.topology_update_v3.controller = display->controller;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

194

dtm_cmd->dtm_in_message.topology_update_v3.stream_enc = display->stream_enc_idx;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

198

dtm_cmd->dtm_in_message.topology_update_v3.dp_mst_vcid = display->vc_id;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

214

status = add_display_to_topology_v2(hdcp, display);

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

216

display->state = MOD_HDCP_DISPLAY_INACTIVE;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

218

HDCP_TOP_ADD_DISPLAY_TRACE(hdcp, display->index);

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

238

struct mod_hdcp_display *display)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

243

status = add_display_to_topology_v3(hdcp, display);

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

245

status = add_display_to_topology_v2(hdcp, display);

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

254

struct mod_hdcp_display *display = get_first_active_display(hdcp);

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

263

if (!display)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

271

hdcp_cmd->in_msg.hdcp1_create_session.display_handle = display->index;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

371

struct mod_hdcp_display *display = get_first_active_display(hdcp);

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

374

if (!display)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

389

display->state = MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

390

HDCP_HDCP1_ENABLED_TRACE(hdcp, display->index);

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

505

struct mod_hdcp_display *display = get_first_active_display(hdcp);

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

514

if (!display)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

522

hdcp_cmd->in_msg.hdcp2_create_session_v2.display_handle = display->index;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

53

struct mod_hdcp_display *display =

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

59

if (!display || !is_display_active(display))

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

67

dtm_cmd->dtm_in_message.topology_update_v2.display_handle = display->index;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

76

display->state = MOD_HDCP_DISPLAY_ACTIVE;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

77

HDCP_TOP_REMOVE_DISPLAY_TRACE(hdcp, display->index);

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

836

struct mod_hdcp_display *display = get_first_active_display(hdcp);

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

839

if (!display)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

855

display->state = MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

856

HDCP_HDCP2_ENABLED_TRACE(hdcp, display->index);

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

89

struct mod_hdcp_display *display =

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

95

if (!display || !is_display_active(display))

sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h

296

const struct mod_hdcp_display *display;

sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h

325

struct mod_hdcp_link *link, struct mod_hdcp_display *display,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

705

ps->display.disableFrameModulation = false;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

715

ps->display.refreshrateSource = PP_RefreshrateSource_Explicit;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

716

ps->display.explicitRefreshrate = look_up[rrr_index];

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

717

ps->display.limitRefreshrate = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

719

if (ps->display.explicitRefreshrate == 0)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

720

ps->display.limitRefreshrate = false;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

722

ps->display.limitRefreshrate = false;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

727

ps->display.enableVariBright = (0 != tmp);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

109

uint32_t display : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3629

power_state->display.disableFrameModulation = false;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3630

power_state->display.limitRefreshrate = false;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3631

power_state->display.enableVariBright =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

132

uint32_t display : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3177

power_state->display.disableFrameModulation = false;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3178

power_state->display.limitRefreshrate = false;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3179

power_state->display.enableVariBright =

sys/dev/pci/drm/amd/pm/powerplay/inc/power_state.h

159

struct PP_StateDisplayBlock display;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

199

struct smu_state_display_block display;

sys/dev/pci/drm/drm_modes.c

2723

bool drm_mode_is_420_only(const struct drm_display_info *display,

sys/dev/pci/drm/drm_modes.c

2728

return test_bit(vic, display->hdmi.y420_vdb_modes);

sys/dev/pci/drm/drm_modes.c

2743

bool drm_mode_is_420_also(const struct drm_display_info *display,

sys/dev/pci/drm/drm_modes.c

2748

return test_bit(vic, display->hdmi.y420_cmdb_modes);

sys/dev/pci/drm/drm_modes.c

2762

bool drm_mode_is_420(const struct drm_display_info *display,

sys/dev/pci/drm/drm_modes.c

2765

return drm_mode_is_420_only(display, mode) ||

sys/dev/pci/drm/drm_modes.c

2766

drm_mode_is_420_also(display, mode);

sys/dev/pci/drm/i915/display/g4x_dp.c

1035

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_dp.c

1042

drm_dbg_kms(display->drm, "Using signal levels %08x\n",

sys/dev/pci/drm/i915/display/g4x_dp.c

1048

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

sys/dev/pci/drm/i915/display/g4x_dp.c

1049

intel_de_posting_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/g4x_dp.c

1083

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_dp.c

1090

drm_dbg_kms(display->drm, "Using signal levels %08x\n",

sys/dev/pci/drm/i915/display/g4x_dp.c

1096

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

sys/dev/pci/drm/i915/display/g4x_dp.c

1097

intel_de_posting_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/g4x_dp.c

1135

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_dp.c

1142

drm_dbg_kms(display->drm, "Using signal levels %08x\n",

sys/dev/pci/drm/i915/display/g4x_dp.c

1148

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

sys/dev/pci/drm/i915/display/g4x_dp.c

1149

intel_de_posting_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/g4x_dp.c

1190

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_dp.c

1191

u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin];

sys/dev/pci/drm/i915/display/g4x_dp.c

1193

return intel_de_read(display, SDEISR) & bit;

sys/dev/pci/drm/i915/display/g4x_dp.c

1198

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_dp.c

1216

return intel_de_read(display, PORT_HOTPLUG_STAT(display)) & bit;

sys/dev/pci/drm/i915/display/g4x_dp.c

1221

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_dp.c

1222

u32 bit = display->hotplug.hpd[encoder->hpd_pin];

sys/dev/pci/drm/i915/display/g4x_dp.c

1224

return intel_de_read(display, DEISR) & bit;

sys/dev/pci/drm/i915/display/g4x_dp.c

1231

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_dp.c

1234

if (HAS_PCH_SPLIT(display) && encoder->port != PORT_A)

sys/dev/pci/drm/i915/display/g4x_dp.c

125

intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;

sys/dev/pci/drm/i915/display/g4x_dp.c

1265

struct intel_display *display = to_intel_display(encoder->dev);

sys/dev/pci/drm/i915/display/g4x_dp.c

1268

intel_dp->DP = intel_de_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/g4x_dp.c

1273

if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/g4x_dp.c

1284

bool g4x_dp_init(struct intel_display *display,

sys/dev/pci/drm/i915/display/g4x_dp.c

1293

if (!assert_port_valid(display, port))

sys/dev/pci/drm/i915/display/g4x_dp.c

1296

devdata = intel_bios_encoder_data_lookup(display, port);

sys/dev/pci/drm/i915/display/g4x_dp.c

1300

drm_dbg_kms(display->drm, "No VBT child device for DP-%c\n",

sys/dev/pci/drm/i915/display/g4x_dp.c

1316

if (drm_encoder_init(display->drm, &intel_encoder->base,

sys/dev/pci/drm/i915/display/g4x_dp.c

133

if (display->platform.ivybridge && port == PORT_A) {

sys/dev/pci/drm/i915/display/g4x_dp.c

1333

if (display->platform.cherryview) {

sys/dev/pci/drm/i915/display/g4x_dp.c

1340

} else if (display->platform.valleyview) {

sys/dev/pci/drm/i915/display/g4x_dp.c

1355

if ((display->platform.ivybridge && port == PORT_A) ||

sys/dev/pci/drm/i915/display/g4x_dp.c

1356

(HAS_PCH_CPT(display) && port != PORT_A)) {

sys/dev/pci/drm/i915/display/g4x_dp.c

1364

if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/g4x_dp.c

1366

else if (display->platform.valleyview)

sys/dev/pci/drm/i915/display/g4x_dp.c

1368

else if (display->platform.ivybridge && port == PORT_A)

sys/dev/pci/drm/i915/display/g4x_dp.c

1370

else if (display->platform.sandybridge && port == PORT_A)

sys/dev/pci/drm/i915/display/g4x_dp.c

1375

if (display->platform.valleyview || display->platform.cherryview ||

sys/dev/pci/drm/i915/display/g4x_dp.c

1376

(HAS_PCH_SPLIT(display) && port != PORT_A)) {

sys/dev/pci/drm/i915/display/g4x_dp.c

1387

intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port);

sys/dev/pci/drm/i915/display/g4x_dp.c

1388

if (display->platform.cherryview) {

sys/dev/pci/drm/i915/display/g4x_dp.c

1402

if (HAS_GMCH(display)) {

sys/dev/pci/drm/i915/display/g4x_dp.c

144

} else if (HAS_PCH_CPT(display) && port != PORT_A) {

sys/dev/pci/drm/i915/display/g4x_dp.c

147

intel_de_rmw(display, TRANS_DP_CTL(crtc->pipe),

sys/dev/pci/drm/i915/display/g4x_dp.c

152

if (display->platform.g4x && pipe_config->limited_color_range)

sys/dev/pci/drm/i915/display/g4x_dp.c

164

if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/g4x_dp.c

173

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/g4x_dp.c

175

bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN;

sys/dev/pci/drm/i915/display/g4x_dp.c

177

INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

sys/dev/pci/drm/i915/display/g4x_dp.c

184

static void assert_edp_pll(struct intel_display *display, bool state)

sys/dev/pci/drm/i915/display/g4x_dp.c

186

bool cur_state = intel_de_read(display, DP_A) & EDP_PLL_ENABLE;

sys/dev/pci/drm/i915/display/g4x_dp.c

188

INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

sys/dev/pci/drm/i915/display/g4x_dp.c

198

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/g4x_dp.c

201

assert_transcoder_disabled(display, pipe_config->cpu_transcoder);

sys/dev/pci/drm/i915/display/g4x_dp.c

203

assert_edp_pll_disabled(display);

sys/dev/pci/drm/i915/display/g4x_dp.c

205

drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n",

sys/dev/pci/drm/i915/display/g4x_dp.c

215

intel_de_write(display, DP_A, intel_dp->DP);

sys/dev/pci/drm/i915/display/g4x_dp.c

216

intel_de_posting_read(display, DP_A);

sys/dev/pci/drm/i915/display/g4x_dp.c

225

if (display->platform.ironlake)

sys/dev/pci/drm/i915/display/g4x_dp.c

226

intel_wait_for_vblank_if_active(display, !crtc->pipe);

sys/dev/pci/drm/i915/display/g4x_dp.c

230

intel_de_write(display, DP_A, intel_dp->DP);

sys/dev/pci/drm/i915/display/g4x_dp.c

231

intel_de_posting_read(display, DP_A);

sys/dev/pci/drm/i915/display/g4x_dp.c

238

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/g4x_dp.c

240

assert_transcoder_disabled(display, old_crtc_state->cpu_transcoder);

sys/dev/pci/drm/i915/display/g4x_dp.c

242

assert_edp_pll_enabled(display);

sys/dev/pci/drm/i915/display/g4x_dp.c

244

drm_dbg_kms(display->drm, "disabling eDP PLL\n");

sys/dev/pci/drm/i915/display/g4x_dp.c

248

intel_de_write(display, DP_A, intel_dp->DP);

sys/dev/pci/drm/i915/display/g4x_dp.c

249

intel_de_posting_read(display, DP_A);

sys/dev/pci/drm/i915/display/g4x_dp.c

253

static bool cpt_dp_port_selected(struct intel_display *display,

sys/dev/pci/drm/i915/display/g4x_dp.c

258

for_each_pipe(display, p) {

sys/dev/pci/drm/i915/display/g4x_dp.c

259

u32 val = intel_de_read(display, TRANS_DP_CTL(p));

sys/dev/pci/drm/i915/display/g4x_dp.c

267

drm_dbg_kms(display->drm, "No pipe for DP port %c found\n",

sys/dev/pci/drm/i915/display/g4x_dp.c

276

bool g4x_dp_port_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/g4x_dp.c

283

val = intel_de_read(display, dp_reg);

sys/dev/pci/drm/i915/display/g4x_dp.c

288

if (display->platform.ivybridge && port == PORT_A)

sys/dev/pci/drm/i915/display/g4x_dp.c

290

else if (HAS_PCH_CPT(display) && port != PORT_A)

sys/dev/pci/drm/i915/display/g4x_dp.c

291

ret &= cpt_dp_port_selected(display, port, pipe);

sys/dev/pci/drm/i915/display/g4x_dp.c

292

else if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/g4x_dp.c

303

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_dp.c

308

wakeref = intel_display_power_get_if_enabled(display,

sys/dev/pci/drm/i915/display/g4x_dp.c

313

ret = g4x_dp_port_enabled(display, intel_dp->output_reg,

sys/dev/pci/drm/i915/display/g4x_dp.c

316

intel_display_power_put(display, encoder->power_domain, wakeref);

sys/dev/pci/drm/i915/display/g4x_dp.c

339

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_dp.c

350

tmp = intel_de_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/g4x_dp.c

354

if (HAS_PCH_CPT(display) && port != PORT_A) {

sys/dev/pci/drm/i915/display/g4x_dp.c

355

u32 trans_dp = intel_de_read(display,

sys/dev/pci/drm/i915/display/g4x_dp.c

387

if (display->platform.g4x && tmp & DP_COLOR_RANGE_16_235)

sys/dev/pci/drm/i915/display/g4x_dp.c

395

if ((intel_de_read(display, DP_A) & EDP_PLL_FREQ_MASK) == EDP_PLL_FREQ_162MHZ)

sys/dev/pci/drm/i915/display/g4x_dp.c

415

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_dp.c

420

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/g4x_dp.c

421

(intel_de_read(display, intel_dp->output_reg) &

sys/dev/pci/drm/i915/display/g4x_dp.c

425

drm_dbg_kms(display->drm, "\n");

sys/dev/pci/drm/i915/display/g4x_dp.c

428

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

sys/dev/pci/drm/i915/display/g4x_dp.c

429

intel_de_posting_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/g4x_dp.c

436

if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B && port != PORT_A) {

sys/dev/pci/drm/i915/display/g4x_dp.c

441

intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);

sys/dev/pci/drm/i915/display/g4x_dp.c

442

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);

sys/dev/pci/drm/i915/display/g4x_dp.c

448

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

sys/dev/pci/drm/i915/display/g4x_dp.c

449

intel_de_posting_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/g4x_dp.c

452

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

sys/dev/pci/drm/i915/display/g4x_dp.c

453

intel_de_posting_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/g4x_dp.c

455

intel_wait_for_vblank_if_active(display, PIPE_A);

sys/dev/pci/drm/i915/display/g4x_dp.c

456

intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);

sys/dev/pci/drm/i915/display/g4x_dp.c

457

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

sys/dev/pci/drm/i915/display/g4x_dp.c

462

if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/g4x_dp.c

470

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_dp.c

478

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

sys/dev/pci/drm/i915/display/g4x_dp.c

487

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_dp.c

497

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

sys/dev/pci/drm/i915/display/g4x_dp.c

56

const struct dpll *vlv_get_dpll(struct intel_display *display)

sys/dev/pci/drm/i915/display/g4x_dp.c

58

return display->platform.cherryview ? &chv_dpll[0] : &vlv_dpll[0];

sys/dev/pci/drm/i915/display/g4x_dp.c

580

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/g4x_dp.c

599

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

sys/dev/pci/drm/i915/display/g4x_dp.c

600

intel_de_posting_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/g4x_dp.c

607

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/g4x_dp.c

612

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

sys/dev/pci/drm/i915/display/g4x_dp.c

613

intel_de_posting_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/g4x_dp.c

621

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/g4x_dp.c

64

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_dp.c

640

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

sys/dev/pci/drm/i915/display/g4x_dp.c

641

intel_de_posting_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/g4x_dp.c

648

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/g4x_dp.c

653

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

sys/dev/pci/drm/i915/display/g4x_dp.c

654

intel_de_posting_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/g4x_dp.c

660

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/g4x_dp.c

675

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

sys/dev/pci/drm/i915/display/g4x_dp.c

676

intel_de_posting_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/g4x_dp.c

68

if (display->platform.g4x) {

sys/dev/pci/drm/i915/display/g4x_dp.c

684

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/g4x_dp.c

686

u32 dp_reg = intel_de_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/g4x_dp.c

689

if (drm_WARN_ON(display->drm, dp_reg & DP_PORT_EN))

sys/dev/pci/drm/i915/display/g4x_dp.c

693

if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/g4x_dp.c

703

if (display->platform.valleyview || display->platform.cherryview) {

sys/dev/pci/drm/i915/display/g4x_dp.c

706

if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/g4x_dp.c

71

} else if (HAS_PCH_SPLIT(display)) {

sys/dev/pci/drm/i915/display/g4x_dp.c

74

} else if (display->platform.cherryview) {

sys/dev/pci/drm/i915/display/g4x_dp.c

77

} else if (display->platform.valleyview) {

sys/dev/pci/drm/i915/display/g4x_dp.c

96

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_dp.h

21

const struct dpll *vlv_get_dpll(struct intel_display *display);

sys/dev/pci/drm/i915/display/g4x_dp.h

22

bool g4x_dp_port_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/g4x_dp.h

25

bool g4x_dp_init(struct intel_display *display,

sys/dev/pci/drm/i915/display/g4x_dp.h

28

static inline const struct dpll *vlv_get_dpll(struct intel_display *display)

sys/dev/pci/drm/i915/display/g4x_dp.h

32

static inline bool g4x_dp_port_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/g4x_dp.h

38

static inline bool g4x_dp_init(struct intel_display *display,

sys/dev/pci/drm/i915/display/g4x_hdmi.c

134

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

138

if (HAS_PCH_SPLIT(display))

sys/dev/pci/drm/i915/display/g4x_hdmi.c

141

if (display->platform.g4x)

sys/dev/pci/drm/i915/display/g4x_hdmi.c

153

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

160

tmp = intel_de_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

184

if (!HAS_PCH_SPLIT(display) &&

sys/dev/pci/drm/i915/display/g4x_hdmi.c

220

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

224

temp = intel_de_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

228

intel_de_write(display, intel_hdmi->hdmi_reg, temp);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

229

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

236

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

242

drm_WARN_ON(display->drm, !crtc_state->has_hdmi_sink);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

245

intel_de_rmw(display, hdmi->hdmi_reg, 0, HDMI_AUDIO_ENABLE);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

254

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

263

intel_de_rmw(display, hdmi->hdmi_reg, HDMI_AUDIO_ENABLE, 0);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

279

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

283

temp = intel_de_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

291

intel_de_write(display, intel_hdmi->hdmi_reg, temp);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

292

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

293

intel_de_write(display, intel_hdmi->hdmi_reg, temp);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

294

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

305

intel_de_write(display, intel_hdmi->hdmi_reg,

sys/dev/pci/drm/i915/display/g4x_hdmi.c

307

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

31

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

313

intel_de_write(display, intel_hdmi->hdmi_reg, temp);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

314

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

315

intel_de_write(display, intel_hdmi->hdmi_reg, temp);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

316

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

325

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

331

temp = intel_de_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

346

intel_de_rmw(display, TRANS_CHICKEN1(pipe),

sys/dev/pci/drm/i915/display/g4x_hdmi.c

353

intel_de_write(display, intel_hdmi->hdmi_reg, temp);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

354

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

360

intel_de_write(display, intel_hdmi->hdmi_reg, temp);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

361

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

363

intel_de_rmw(display, TRANS_CHICKEN1(pipe),

sys/dev/pci/drm/i915/display/g4x_hdmi.c

380

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

387

temp = intel_de_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

390

intel_de_write(display, intel_hdmi->hdmi_reg, temp);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

391

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

398

if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B) {

sys/dev/pci/drm/i915/display/g4x_hdmi.c

40

if (!HAS_PCH_SPLIT(display) && crtc_state->limited_color_range)

sys/dev/pci/drm/i915/display/g4x_hdmi.c

403

intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

404

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

412

intel_de_write(display, intel_hdmi->hdmi_reg, temp);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

413

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

414

intel_de_write(display, intel_hdmi->hdmi_reg, temp);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

415

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

418

intel_de_write(display, intel_hdmi->hdmi_reg, temp);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

419

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

421

intel_wait_for_vblank_if_active(display, PIPE_A);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

422

intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

423

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

55

if (HAS_PCH_CPT(display))

sys/dev/pci/drm/i915/display/g4x_hdmi.c

57

else if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/g4x_hdmi.c

598

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

607

if (!display->platform.g4x)

sys/dev/pci/drm/i915/display/g4x_hdmi.c

62

intel_de_write(display, intel_hdmi->hdmi_reg, hdmi_val);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

621

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

63

intel_de_posting_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

630

drm_dbg_kms(display->drm, "Adding [CONNECTOR:%d:%s]\n",

sys/dev/pci/drm/i915/display/g4x_hdmi.c

655

static bool is_hdmi_port_valid(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/g4x_hdmi.c

657

if (display->platform.g4x || display->platform.valleyview)

sys/dev/pci/drm/i915/display/g4x_hdmi.c

663

static bool assert_hdmi_port_valid(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/g4x_hdmi.c

665

return !drm_WARN(display->drm, !is_hdmi_port_valid(display, port),

sys/dev/pci/drm/i915/display/g4x_hdmi.c

669

bool g4x_hdmi_init(struct intel_display *display,

sys/dev/pci/drm/i915/display/g4x_hdmi.c

677

if (!assert_port_valid(display, port))

sys/dev/pci/drm/i915/display/g4x_hdmi.c

680

if (!assert_hdmi_port_valid(display, port))

sys/dev/pci/drm/i915/display/g4x_hdmi.c

683

devdata = intel_bios_encoder_data_lookup(display, port);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

687

drm_dbg_kms(display->drm, "No VBT child device for HDMI-%c\n",

sys/dev/pci/drm/i915/display/g4x_hdmi.c

69

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

702

if (drm_encoder_init(display->drm, &intel_encoder->base,

sys/dev/pci/drm/i915/display/g4x_hdmi.c

709

if (HAS_PCH_SPLIT(display)) {

sys/dev/pci/drm/i915/display/g4x_hdmi.c

717

if (display->platform.cherryview) {

sys/dev/pci/drm/i915/display/g4x_hdmi.c

723

} else if (display->platform.valleyview) {

sys/dev/pci/drm/i915/display/g4x_hdmi.c

730

if (HAS_PCH_CPT(display))

sys/dev/pci/drm/i915/display/g4x_hdmi.c

732

else if (HAS_PCH_IBX(display))

sys/dev/pci/drm/i915/display/g4x_hdmi.c

74

wakeref = intel_display_power_get_if_enabled(display,

sys/dev/pci/drm/i915/display/g4x_hdmi.c

742

intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

744

if (display->platform.cherryview) {

sys/dev/pci/drm/i915/display/g4x_hdmi.c

759

if (display->platform.g4x)

sys/dev/pci/drm/i915/display/g4x_hdmi.c

79

ret = intel_sdvo_port_enabled(display, intel_hdmi->hdmi_reg, pipe);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

81

intel_display_power_put(display, encoder->power_domain, wakeref);

sys/dev/pci/drm/i915/display/g4x_hdmi.h

19

bool g4x_hdmi_init(struct intel_display *display,

sys/dev/pci/drm/i915/display/g4x_hdmi.h

24

static inline bool g4x_hdmi_init(struct intel_display *display,

sys/dev/pci/drm/i915/display/hsw_ips.c

116

if (display->platform.haswell &&

sys/dev/pci/drm/i915/display/hsw_ips.c

139

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/hsw_ips.c

157

if (display->platform.haswell &&

sys/dev/pci/drm/i915/display/hsw_ips.c

187

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/hsw_ips.c

189

return HAS_IPS(display) && crtc->pipe == PIPE_A;

sys/dev/pci/drm/i915/display/hsw_ips.c

194

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/hsw_ips.c

201

if (!display->params.enable_ips)

sys/dev/pci/drm/i915/display/hsw_ips.c

21

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/hsw_ips.c

214

if (display->platform.broadwell &&

sys/dev/pci/drm/i915/display/hsw_ips.c

215

crtc_state->pixel_rate > display->cdclk.max_cdclk_freq * 95 / 100)

sys/dev/pci/drm/i915/display/hsw_ips.c

223

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/hsw_ips.c

225

if (!display->platform.broadwell)

sys/dev/pci/drm/i915/display/hsw_ips.c

238

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/hsw_ips.c

260

if (display->platform.broadwell) {

sys/dev/pci/drm/i915/display/hsw_ips.c

279

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/hsw_ips.c

285

if (display->platform.haswell) {

sys/dev/pci/drm/i915/display/hsw_ips.c

286

crtc_state->ips_enabled = intel_de_read(display, IPS_CTL) & IPS_ENABLE;

sys/dev/pci/drm/i915/display/hsw_ips.c

300

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/hsw_ips.c

302

*val = display->ips.false_color;

sys/dev/pci/drm/i915/display/hsw_ips.c

310

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/hsw_ips.c

318

display->ips.false_color = val;

sys/dev/pci/drm/i915/display/hsw_ips.c

32

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/hsw_ips.c

345

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/hsw_ips.c

348

wakeref = intel_display_rpm_get(display);

sys/dev/pci/drm/i915/display/hsw_ips.c

351

str_yes_no(display->params.enable_ips));

sys/dev/pci/drm/i915/display/hsw_ips.c

353

if (DISPLAY_VER(display) >= 8) {

sys/dev/pci/drm/i915/display/hsw_ips.c

356

if (intel_de_read(display, IPS_CTL) & IPS_ENABLE)

sys/dev/pci/drm/i915/display/hsw_ips.c

362

intel_display_rpm_put(display, wakeref);

sys/dev/pci/drm/i915/display/hsw_ips.c

37

if (display->ips.false_color)

sys/dev/pci/drm/i915/display/hsw_ips.c

40

if (display->platform.broadwell) {

sys/dev/pci/drm/i915/display/hsw_ips.c

41

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/hsw_ips.c

42

intel_pcode_write(display->drm, DISPLAY_IPS_CONTROL,

sys/dev/pci/drm/i915/display/hsw_ips.c

51

intel_de_write(display, IPS_CTL, val);

sys/dev/pci/drm/i915/display/hsw_ips.c

59

if (intel_de_wait_for_set(display, IPS_CTL, IPS_ENABLE, 50))

sys/dev/pci/drm/i915/display/hsw_ips.c

60

drm_err(display->drm,

sys/dev/pci/drm/i915/display/hsw_ips.c

67

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/hsw_ips.c

73

if (display->platform.broadwell) {

sys/dev/pci/drm/i915/display/hsw_ips.c

74

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/hsw_ips.c

75

intel_pcode_write(display->drm, DISPLAY_IPS_CONTROL, 0));

sys/dev/pci/drm/i915/display/hsw_ips.c

81

if (intel_de_wait_for_clear(display, IPS_CTL, IPS_ENABLE, 100))

sys/dev/pci/drm/i915/display/hsw_ips.c

82

drm_err(display->drm,

sys/dev/pci/drm/i915/display/hsw_ips.c

85

intel_de_write(display, IPS_CTL, 0);

sys/dev/pci/drm/i915/display/hsw_ips.c

86

intel_de_posting_read(display, IPS_CTL);

sys/dev/pci/drm/i915/display/hsw_ips.c

98

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

15

static void i9xx_display_save_swf(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

20

if (DISPLAY_VER(display) == 2 && display->platform.mobile) {

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

22

display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i));

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

23

display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i));

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

26

display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i));

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

27

} else if (DISPLAY_VER(display) == 2) {

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

29

display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i));

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

30

} else if (HAS_GMCH(display)) {

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

32

display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i));

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

33

display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i));

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

36

display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i));

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

40

static void i9xx_display_restore_swf(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

45

if (DISPLAY_VER(display) == 2 && display->platform.mobile) {

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

47

intel_de_write(display, SWF0(display, i), display->restore.saveSWF0[i]);

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

48

intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]);

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

51

intel_de_write(display, SWF3(display, i), display->restore.saveSWF3[i]);

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

52

} else if (DISPLAY_VER(display) == 2) {

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

54

intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]);

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

55

} else if (HAS_GMCH(display)) {

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

57

intel_de_write(display, SWF0(display, i), display->restore.saveSWF0[i]);

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

58

intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]);

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

61

intel_de_write(display, SWF3(display, i), display->restore.saveSWF3[i]);

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

65

void i9xx_display_sr_save(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

67

struct pci_dev *pdev = display->drm->pdev;

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

69

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

73

if (DISPLAY_VER(display) <= 4)

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

74

display->restore.saveDSPARB = intel_de_read(display, DSPARB(display));

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

76

if (DISPLAY_VER(display) == 4)

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

77

pci_read_config_word(pdev, GCDGMBUS, &display->restore.saveGCDGMBUS);

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

79

i9xx_display_save_swf(display);

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

82

void i9xx_display_sr_restore(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

84

struct pci_dev *pdev = display->drm->pdev;

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

86

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

89

i9xx_display_restore_swf(display);

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

91

if (DISPLAY_VER(display) == 4)

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

92

pci_write_config_word(pdev, GCDGMBUS, display->restore.saveGCDGMBUS);

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

95

if (DISPLAY_VER(display) <= 4)

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

96

intel_de_write(display, DSPARB(display), display->restore.saveDSPARB);

sys/dev/pci/drm/i915/display/i9xx_display_sr.h

11

void i9xx_display_sr_save(struct intel_display *display);

sys/dev/pci/drm/i915/display/i9xx_display_sr.h

12

void i9xx_display_sr_restore(struct intel_display *display);

sys/dev/pci/drm/i915/display/i9xx_plane.c

1001

if (HAS_GMCH(display)) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

1002

if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/i9xx_plane.c

1004

else if (DISPLAY_VER(display) == 3)

sys/dev/pci/drm/i915/display/i9xx_plane.c

1009

if (display->platform.broadwell || display->platform.haswell)

sys/dev/pci/drm/i915/display/i9xx_plane.c

1015

if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/i9xx_plane.c

1017

else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

sys/dev/pci/drm/i915/display/i9xx_plane.c

1019

else if (DISPLAY_VER(display) == 4)

sys/dev/pci/drm/i915/display/i9xx_plane.c

1025

if (intel_scanout_needs_vtd_wa(display))

sys/dev/pci/drm/i915/display/i9xx_plane.c

1028

if (display->platform.i830 || display->platform.i845g) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

1038

if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/i9xx_plane.c

1043

if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

sys/dev/pci/drm/i915/display/i9xx_plane.c

1045

else if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/i9xx_plane.c

1050

if (HAS_ASYNC_FLIPS(display)) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

1051

if (display->platform.valleyview || display->platform.cherryview) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

1056

} else if (display->platform.broadwell) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

1062

} else if (DISPLAY_VER(display) >= 7) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

1067

} else if (DISPLAY_VER(display) >= 5) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

1077

modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_TILING_X);

sys/dev/pci/drm/i915/display/i9xx_plane.c

1079

if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

sys/dev/pci/drm/i915/display/i9xx_plane.c

1080

ret = drm_universal_plane_init(display->drm, &plane->base,

sys/dev/pci/drm/i915/display/i9xx_plane.c

1087

ret = drm_universal_plane_init(display->drm, &plane->base,

sys/dev/pci/drm/i915/display/i9xx_plane.c

1100

if (display->platform.cherryview && pipe == PIPE_B) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

1104

} else if (DISPLAY_VER(display) >= 4) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

1111

if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/i9xx_plane.c

116

static bool i9xx_plane_has_fbc(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_plane.c

1166

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/i9xx_plane.c

1179

drm_WARN_ON(display->drm, pipe != crtc->pipe);

sys/dev/pci/drm/i915/display/i9xx_plane.c

1183

drm_dbg_kms(display->drm, "failed to alloc fb\n");

sys/dev/pci/drm/i915/display/i9xx_plane.c

1189

fb->dev = display->drm;

sys/dev/pci/drm/i915/display/i9xx_plane.c

119

if (!HAS_FBC(display))

sys/dev/pci/drm/i915/display/i9xx_plane.c

1191

val = intel_de_read(display, DSPCNTR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

1193

if (DISPLAY_VER(display) >= 4) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

1203

if (display->platform.cherryview &&

sys/dev/pci/drm/i915/display/i9xx_plane.c

1211

if (display->platform.haswell || display->platform.broadwell) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

1212

offset = intel_de_read(display,

sys/dev/pci/drm/i915/display/i9xx_plane.c

1213

DSPOFFSET(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

1214

base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1215

} else if (DISPLAY_VER(display) >= 4) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

1217

offset = intel_de_read(display,

sys/dev/pci/drm/i915/display/i9xx_plane.c

1218

DSPTILEOFF(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

122

if (display->platform.broadwell || display->platform.haswell)

sys/dev/pci/drm/i915/display/i9xx_plane.c

1220

offset = intel_de_read(display,

sys/dev/pci/drm/i915/display/i9xx_plane.c

1221

DSPLINOFF(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

1222

base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1225

base = intel_de_read(display, DSPADDR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

1229

drm_WARN_ON(display->drm, offset != 0);

sys/dev/pci/drm/i915/display/i9xx_plane.c

1231

val = intel_de_read(display, PIPESRC(display, pipe));

sys/dev/pci/drm/i915/display/i9xx_plane.c

1235

val = intel_de_read(display, DSPSTRIDE(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

124

else if (display->platform.ivybridge)

sys/dev/pci/drm/i915/display/i9xx_plane.c

1242

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_plane.c

1255

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/i9xx_plane.c

127

else if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/i9xx_plane.c

1271

if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/i9xx_plane.c

1272

intel_de_write(display, DSPSURF(display, i9xx_plane), plane_state->surf);

sys/dev/pci/drm/i915/display/i9xx_plane.c

1274

intel_de_write(display, DSPADDR(display, i9xx_plane), plane_state->surf);

sys/dev/pci/drm/i915/display/i9xx_plane.c

133

static struct intel_fbc *i9xx_plane_fbc(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_plane.c

136

if (i9xx_plane_has_fbc(display, i9xx_plane))

sys/dev/pci/drm/i915/display/i9xx_plane.c

137

return display->fbc[INTEL_FBC_A];

sys/dev/pci/drm/i915/display/i9xx_plane.c

144

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

147

if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/i9xx_plane.c

149

else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

sys/dev/pci/drm/i915/display/i9xx_plane.c

151

else if (DISPLAY_VER(display) == 4)

sys/dev/pci/drm/i915/display/i9xx_plane.c

160

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/i9xx_plane.c

167

if (display->platform.g4x || display->platform.ironlake ||

sys/dev/pci/drm/i915/display/i9xx_plane.c

168

display->platform.sandybridge || display->platform.ivybridge)

sys/dev/pci/drm/i915/display/i9xx_plane.c

216

if (DISPLAY_VER(display) >= 4 &&

sys/dev/pci/drm/i915/display/i9xx_plane.c

231

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/i9xx_plane.c

250

if (HAS_GMCH(display) && fb->format->cpp[0] == 8 && src_w > 2048) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

251

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_plane.c

259

if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/i9xx_plane.c

276

if (DISPLAY_VER(display) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

282

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_plane.c

301

if (!display->platform.haswell && !display->platform.broadwell) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

314

if (display->platform.haswell || display->platform.broadwell) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

315

drm_WARN_ON(display->drm, src_x > 8191 || src_y > 4095);

sys/dev/pci/drm/i915/display/i9xx_plane.c

316

} else if (DISPLAY_VER(display) >= 4 &&

sys/dev/pci/drm/i915/display/i9xx_plane.c

318

drm_WARN_ON(display->drm, src_x > 4095 || src_y > 4095);

sys/dev/pci/drm/i915/display/i9xx_plane.c

377

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/i9xx_plane.c

387

if (DISPLAY_VER(display) < 5)

sys/dev/pci/drm/i915/display/i9xx_plane.c

445

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

448

intel_de_write_fw(display, DSPSTRIDE(display, i9xx_plane),

sys/dev/pci/drm/i915/display/i9xx_plane.c

451

if (DISPLAY_VER(display) < 4) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

462

intel_de_write_fw(display, DSPPOS(display, i9xx_plane),

sys/dev/pci/drm/i915/display/i9xx_plane.c

464

intel_de_write_fw(display, DSPSIZE(display, i9xx_plane),

sys/dev/pci/drm/i915/display/i9xx_plane.c

474

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

487

if (display->platform.cherryview && i9xx_plane == PLANE_B) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

493

intel_de_write_fw(display, PRIMPOS(display, i9xx_plane),

sys/dev/pci/drm/i915/display/i9xx_plane.c

495

intel_de_write_fw(display, PRIMSIZE(display, i9xx_plane),

sys/dev/pci/drm/i915/display/i9xx_plane.c

497

intel_de_write_fw(display,

sys/dev/pci/drm/i915/display/i9xx_plane.c

498

PRIMCNSTALPHA(display, i9xx_plane), 0);

sys/dev/pci/drm/i915/display/i9xx_plane.c

501

if (display->platform.haswell || display->platform.broadwell) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

502

intel_de_write_fw(display, DSPOFFSET(display, i9xx_plane),

sys/dev/pci/drm/i915/display/i9xx_plane.c

504

} else if (DISPLAY_VER(display) >= 4) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

505

intel_de_write_fw(display, DSPLINOFF(display, i9xx_plane),

sys/dev/pci/drm/i915/display/i9xx_plane.c

507

intel_de_write_fw(display, DSPTILEOFF(display, i9xx_plane),

sys/dev/pci/drm/i915/display/i9xx_plane.c

516

intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr);

sys/dev/pci/drm/i915/display/i9xx_plane.c

518

if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/i9xx_plane.c

519

intel_de_write_fw(display, DSPSURF(display, i9xx_plane), plane_state->surf);

sys/dev/pci/drm/i915/display/i9xx_plane.c

521

intel_de_write_fw(display, DSPADDR(display, i9xx_plane), plane_state->surf);

sys/dev/pci/drm/i915/display/i9xx_plane.c

543

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

559

intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr);

sys/dev/pci/drm/i915/display/i9xx_plane.c

561

if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/i9xx_plane.c

562

intel_de_write_fw(display, DSPSURF(display, i9xx_plane), 0);

sys/dev/pci/drm/i915/display/i9xx_plane.c

564

intel_de_write_fw(display, DSPADDR(display, i9xx_plane), 0);

sys/dev/pci/drm/i915/display/i9xx_plane.c

571

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

574

error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

575

error->surf = intel_de_read(display, DSPSURF(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

576

error->surflive = intel_de_read(display, DSPSURFLIVE(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

583

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

586

error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

587

error->surf = intel_de_read(display, DSPSURF(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

594

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

597

error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

598

error->surf = intel_de_read(display, DSPADDR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

608

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

615

intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr);

sys/dev/pci/drm/i915/display/i9xx_plane.c

616

intel_de_write_fw(display, DSPSURF(display, i9xx_plane), plane_state->surf);

sys/dev/pci/drm/i915/display/i9xx_plane.c

626

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

629

intel_de_write_fw(display, DSPADDR_VLV(display, i9xx_plane), plane_state->surf);

sys/dev/pci/drm/i915/display/i9xx_plane.c

635

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

638

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/i9xx_plane.c

639

bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);

sys/dev/pci/drm/i915/display/i9xx_plane.c

640

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/i9xx_plane.c

646

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

649

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/i9xx_plane.c

650

bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);

sys/dev/pci/drm/i915/display/i9xx_plane.c

651

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/i9xx_plane.c

657

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

659

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/i9xx_plane.c

660

ilk_enable_display_irq(display, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

661

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/i9xx_plane.c

667

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

669

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/i9xx_plane.c

670

ilk_disable_display_irq(display, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

671

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/i9xx_plane.c

677

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

679

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/i9xx_plane.c

680

ilk_enable_display_irq(display, DE_PLANE_FLIP_DONE(plane->i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

681

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/i9xx_plane.c

687

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

689

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/i9xx_plane.c

690

ilk_disable_display_irq(display, DE_PLANE_FLIP_DONE(plane->i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

691

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/i9xx_plane.c

697

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

700

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/i9xx_plane.c

701

i915_enable_pipestat(display, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);

sys/dev/pci/drm/i915/display/i9xx_plane.c

702

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/i9xx_plane.c

708

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

711

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/i9xx_plane.c

712

i915_disable_pipestat(display, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);

sys/dev/pci/drm/i915/display/i9xx_plane.c

713

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/i9xx_plane.c

724

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

737

wakeref = intel_display_power_get_if_enabled(display, power_domain);

sys/dev/pci/drm/i915/display/i9xx_plane.c

741

val = intel_de_read(display, DSPCNTR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

745

if (DISPLAY_VER(display) >= 5)

sys/dev/pci/drm/i915/display/i9xx_plane.c

750

intel_display_power_put(display, power_domain, wakeref);

sys/dev/pci/drm/i915/display/i9xx_plane.c

823

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

829

if (intel_scanout_needs_vtd_wa(display))

sys/dev/pci/drm/i915/display/i9xx_plane.c

847

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

852

if (intel_scanout_needs_vtd_wa(display))

sys/dev/pci/drm/i915/display/i9xx_plane.c

909

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

914

dspcntr = intel_de_read_fw(display, DSPCNTR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

916

intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr);

sys/dev/pci/drm/i915/display/i9xx_plane.c

918

if (DISPLAY_VER(display) >= 4) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

919

reg = intel_de_read_fw(display, DSPSURF(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

920

intel_de_write_fw(display, DSPSURF(display, i9xx_plane), reg);

sys/dev/pci/drm/i915/display/i9xx_plane.c

923

reg = intel_de_read_fw(display, DSPADDR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

924

intel_de_write_fw(display, DSPADDR(display, i9xx_plane), reg);

sys/dev/pci/drm/i915/display/i9xx_plane.c

929

intel_primary_plane_create(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/i9xx_plane.c

948

if (HAS_FBC(display) && DISPLAY_VER(display) < 4 &&

sys/dev/pci/drm/i915/display/i9xx_plane.c

949

INTEL_NUM_PIPES(display) == 2)

sys/dev/pci/drm/i915/display/i9xx_plane.c

956

intel_fbc_add_plane(i9xx_plane_fbc(display, plane->i9xx_plane), plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

958

if (display->platform.valleyview || display->platform.cherryview) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

961

} else if (DISPLAY_VER(display) >= 4) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

975

if (display->platform.ivybridge) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

987

if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/i9xx_plane.c

992

if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/i9xx_plane.c

994

else if (display->platform.broadwell || display->platform.haswell)

sys/dev/pci/drm/i915/display/i9xx_plane.c

996

else if (display->platform.ivybridge)

sys/dev/pci/drm/i915/display/i9xx_plane.h

30

intel_primary_plane_create(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/i9xx_plane.h

48

intel_primary_plane_create(struct intel_display *display, int pipe)

sys/dev/pci/drm/i915/display/i9xx_wm.c

1026

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1029

for (; level < display->wm.num_levels; level++) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

1042

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1048

for (; level < display->wm.num_levels; level++) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

1065

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/i9xx_wm.c

107

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

1078

for (level = 0; level < display->wm.num_levels; level++) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

1118

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

1126

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

1146

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1148

if (level >= display->wm.num_levels)

sys/dev/pci/drm/i915/display/i9xx_wm.c

115

static void chv_set_memory_dvfs(struct intel_display *display, bool enable)

sys/dev/pci/drm/i915/display/i9xx_wm.c

120

vlv_punit_get(display->drm);

sys/dev/pci/drm/i915/display/i9xx_wm.c

122

val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2);

sys/dev/pci/drm/i915/display/i9xx_wm.c

129

vlv_punit_write(display->drm, PUNIT_REG_DDR_SETUP2, val);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1290

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/i9xx_wm.c

131

ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2),

sys/dev/pci/drm/i915/display/i9xx_wm.c

1320

drm_WARN_ON(display->drm, intermediate->wm.plane[plane_id] >

sys/dev/pci/drm/i915/display/i9xx_wm.c

1338

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

1344

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

135

drm_err(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

1351

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

1354

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

138

vlv_punit_put(display->drm);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1385

static void g4x_merge_wm(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

1395

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

141

static void chv_set_memory_pm5(struct intel_display *display, bool enable)

sys/dev/pci/drm/i915/display/i9xx_wm.c

1417

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

1429

static void g4x_program_watermarks(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

1431

struct g4x_wm_values *old_wm = &display->wm.g4x;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1434

g4x_merge_wm(display, &new_wm);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1440

_intel_set_memory_cxsr(display, false);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1442

g4x_write_wm_values(display, &new_wm);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1445

_intel_set_memory_cxsr(display, true);

sys/dev/pci/drm/i915/display/i9xx_wm.c

145

vlv_punit_get(display->drm);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1453

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1457

mutex_lock(&display->wm.wm_mutex);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1459

g4x_program_watermarks(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1460

mutex_unlock(&display->wm.wm_mutex);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1466

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/i9xx_wm.c

147

val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1473

mutex_lock(&display->wm.wm_mutex);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1475

g4x_program_watermarks(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1476

mutex_unlock(&display->wm.wm_mutex);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1495

static void vlv_setup_wm_latency(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

1498

display->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1500

display->wm.num_levels = VLV_WM_LEVEL_PM2 + 1;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1502

if (display->platform.cherryview) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

1503

display->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1504

display->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1506

display->wm.num_levels = VLV_WM_LEVEL_DDR_DVFS + 1;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1514

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/i9xx_wm.c

152

vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1520

if (display->wm.pri_latency[level] == 0)

sys/dev/pci/drm/i915/display/i9xx_wm.c

154

vlv_punit_put(display->drm);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1541

display->wm.pri_latency[level] * 10);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1555

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/i9xx_wm.c

160

static bool _intel_set_memory_cxsr(struct intel_display *display, bool enable)

sys/dev/pci/drm/i915/display/i9xx_wm.c

1625

drm_WARN_ON(display->drm, active_planes != 0 && fifo_left != 0);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1629

drm_WARN_ON(display->drm, fifo_left != fifo_size);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1640

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1642

for (; level < display->wm.num_levels; level++) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

165

if (display->platform.valleyview || display->platform.cherryview) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

166

was_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1668

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/i9xx_wm.c

167

intel_de_write(display, FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1671

for (; level < display->wm.num_levels; level++) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

168

intel_de_posting_read(display, FW_BLC_SELF_VLV);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1684

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/i9xx_wm.c

169

} else if (display->platform.g4x || display->platform.i965gm) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

1695

for (level = 0; level < display->wm.num_levels; level++) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

170

was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;

sys/dev/pci/drm/i915/display/i9xx_wm.c

171

intel_de_write(display, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1712

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

172

intel_de_posting_read(display, FW_BLC_SELF);

sys/dev/pci/drm/i915/display/i9xx_wm.c

173

} else if (display->platform.pineview) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

174

val = intel_de_read(display, DSPFW3(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

1743

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1754

wm_state->num_levels = display->wm.num_levels;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1764

const int sr_fifo_size = INTEL_NUM_PIPES(display) * 512 - 1;

sys/dev/pci/drm/i915/display/i9xx_wm.c

180

intel_de_write(display, DSPFW3(display), val);

sys/dev/pci/drm/i915/display/i9xx_wm.c

181

intel_de_posting_read(display, DSPFW3(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

182

} else if (display->platform.i945g || display->platform.i945gm) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

183

was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;

sys/dev/pci/drm/i915/display/i9xx_wm.c

186

intel_de_write(display, FW_BLC_SELF, val);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1864

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/i9xx_wm.c

187

intel_de_posting_read(display, FW_BLC_SELF);

sys/dev/pci/drm/i915/display/i9xx_wm.c

188

} else if (display->platform.i915gm) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

1881

drm_WARN_ON(display->drm, fifo_state->plane[PLANE_CURSOR] != 63);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1882

drm_WARN_ON(display->drm, fifo_size != 511);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1899

dsparb = intel_de_read_fw(display, DSPARB(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

1900

dsparb2 = intel_de_read_fw(display, DSPARB2);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1912

intel_de_write_fw(display, DSPARB(display), dsparb);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1913

intel_de_write_fw(display, DSPARB2, dsparb2);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1916

dsparb = intel_de_read_fw(display, DSPARB(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

1917

dsparb2 = intel_de_read_fw(display, DSPARB2);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1929

intel_de_write_fw(display, DSPARB(display), dsparb);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1930

intel_de_write_fw(display, DSPARB2, dsparb2);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1933

dsparb3 = intel_de_read_fw(display, DSPARB3);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1934

dsparb2 = intel_de_read_fw(display, DSPARB2);

sys/dev/pci/drm/i915/display/i9xx_wm.c

194

was_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1946

intel_de_write_fw(display, DSPARB3, dsparb3);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1947

intel_de_write_fw(display, DSPARB2, dsparb2);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1953

intel_de_read_fw(display, DSPARB(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

197

intel_de_write(display, INSTPM, val);

sys/dev/pci/drm/i915/display/i9xx_wm.c

198

intel_de_posting_read(display, INSTPM);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2028

static void vlv_merge_wm(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

203

trace_intel_memory_cxsr(display, was_enabled, enable);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2034

wm->level = display->wm.num_levels - 1;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2037

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

205

drm_dbg_kms(display->drm, "memory self-refresh is %s (was %s)\n",

sys/dev/pci/drm/i915/display/i9xx_wm.c

2056

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

2071

static void vlv_program_watermarks(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2073

struct vlv_wm_values *old_wm = &display->wm.vlv;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2076

vlv_merge_wm(display, &new_wm);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2082

chv_set_memory_dvfs(display, false);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2085

chv_set_memory_pm5(display, false);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2088

_intel_set_memory_cxsr(display, false);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2090

vlv_write_wm_values(display, &new_wm);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2093

_intel_set_memory_cxsr(display, true);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2096

chv_set_memory_pm5(display, true);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2099

chv_set_memory_dvfs(display, true);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2107

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2111

mutex_lock(&display->wm.wm_mutex);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2113

vlv_program_watermarks(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2114

mutex_unlock(&display->wm.wm_mutex);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2120

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2127

mutex_lock(&display->wm.wm_mutex);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2129

vlv_program_watermarks(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2130

mutex_unlock(&display->wm.wm_mutex);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2133

static void i965_update_wm(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2141

crtc = single_enabled_crtc(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2162

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2177

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2185

intel_set_memory_cxsr(display, false);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2188

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2193

intel_de_write(display, DSPFW1(display),

sys/dev/pci/drm/i915/display/i9xx_wm.c

2198

intel_de_write(display, DSPFW2(display),

sys/dev/pci/drm/i915/display/i9xx_wm.c

2202

intel_de_write(display, DSPFW3(display),

sys/dev/pci/drm/i915/display/i9xx_wm.c

2206

intel_set_memory_cxsr(display, true);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2211

static struct intel_crtc *intel_crtc_for_plane(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2216

for_each_intel_plane(display->drm, plane) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

2219

return intel_crtc_for_pipe(display, plane->pipe);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2225

static void i9xx_update_wm(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2235

if (display->platform.i945gm)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2237

else if (DISPLAY_VER(display) != 2)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2242

if (DISPLAY_VER(display) == 2)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2243

fifo_size = i830_get_fifo_size(display, PLANE_A);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2245

fifo_size = i9xx_get_fifo_size(display, PLANE_A);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2246

crtc = intel_crtc_for_plane(display, PLANE_A);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2252

if (DISPLAY_VER(display) == 2)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2257

planea_wm = intel_calculate_wm(display, crtc->config->pixel_rate,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2266

if (DISPLAY_VER(display) == 2)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2269

if (DISPLAY_VER(display) == 2)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2270

fifo_size = i830_get_fifo_size(display, PLANE_B);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2272

fifo_size = i9xx_get_fifo_size(display, PLANE_B);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2273

crtc = intel_crtc_for_plane(display, PLANE_B);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2279

if (DISPLAY_VER(display) == 2)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2284

planeb_wm = intel_calculate_wm(display, crtc->config->pixel_rate,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2293

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2296

crtc = single_enabled_crtc(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2297

if (display->platform.i915gm && crtc) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

2313

intel_set_memory_cxsr(display, false);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2316

if (HAS_FW_BLC(display) && crtc) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

2329

if (display->platform.i915gm || display->platform.i945gm)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2337

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2343

if (display->platform.i945g || display->platform.i945gm)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2344

intel_de_write(display, FW_BLC_SELF,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2347

intel_de_write(display, FW_BLC_SELF, srwm & 0x3f);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2350

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2361

intel_de_write(display, FW_BLC, fwater_lo);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2362

intel_de_write(display, FW_BLC2, fwater_hi);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2365

intel_set_memory_cxsr(display, true);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2368

static void i845_update_wm(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2374

crtc = single_enabled_crtc(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2378

planea_wm = intel_calculate_wm(display, crtc->config->pixel_rate,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2380

i845_get_fifo_size(display, PLANE_A),

sys/dev/pci/drm/i915/display/i9xx_wm.c

2382

fwater_lo = intel_de_read(display, FW_BLC) & ~0xfff;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2385

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2388

intel_de_write(display, FW_BLC, fwater_lo);

sys/dev/pci/drm/i915/display/i9xx_wm.c

249

bool intel_set_memory_cxsr(struct intel_display *display, bool enable)

sys/dev/pci/drm/i915/display/i9xx_wm.c

253

mutex_lock(&display->wm.wm_mutex);

sys/dev/pci/drm/i915/display/i9xx_wm.c

254

ret = _intel_set_memory_cxsr(display, enable);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2543

ilk_display_fifo_size(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2545

if (DISPLAY_VER(display) >= 8)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2547

else if (DISPLAY_VER(display) >= 7)

sys/dev/pci/drm/i915/display/i9xx_wm.c

255

if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2554

ilk_plane_wm_reg_max(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2557

if (DISPLAY_VER(display) >= 8)

sys/dev/pci/drm/i915/display/i9xx_wm.c

256

display->wm.vlv.cxsr = enable;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2560

else if (DISPLAY_VER(display) >= 7)

sys/dev/pci/drm/i915/display/i9xx_wm.c

257

else if (display->platform.g4x)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2572

ilk_cursor_wm_reg_max(struct intel_display *display, int level)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2574

if (DISPLAY_VER(display) >= 7)

sys/dev/pci/drm/i915/display/i9xx_wm.c

258

display->wm.g4x.cxsr = enable;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2580

static unsigned int ilk_fbc_wm_reg_max(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2582

if (DISPLAY_VER(display) >= 8)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2589

static unsigned int ilk_plane_wm_max(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

259

mutex_unlock(&display->wm.wm_mutex);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2595

unsigned int fifo_size = ilk_display_fifo_size(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2603

fifo_size /= INTEL_NUM_PIPES(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2610

if (DISPLAY_VER(display) < 7)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2626

return min(fifo_size, ilk_plane_wm_reg_max(display, level, is_sprite));

sys/dev/pci/drm/i915/display/i9xx_wm.c

2630

static unsigned int ilk_cursor_wm_max(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2639

return ilk_cursor_wm_reg_max(display, level);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2642

static void ilk_compute_wm_maximums(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2648

max->pri = ilk_plane_wm_max(display, level, config, ddb_partitioning, false);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2649

max->spr = ilk_plane_wm_max(display, level, config, ddb_partitioning, true);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2650

max->cur = ilk_cursor_wm_max(display, level, config);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2651

max->fbc = ilk_fbc_wm_reg_max(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2654

static void ilk_compute_wm_reg_maximums(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2658

max->pri = ilk_plane_wm_reg_max(display, level, false);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2659

max->spr = ilk_plane_wm_reg_max(display, level, true);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2660

max->cur = ilk_cursor_wm_reg_max(display, level);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2661

max->fbc = ilk_fbc_wm_reg_max(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2664

static bool ilk_validate_wm_level(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2688

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2692

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2696

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2709

static void ilk_compute_wm_level(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2718

u16 pri_latency = display->wm.pri_latency[level];

sys/dev/pci/drm/i915/display/i9xx_wm.c

2719

u16 spr_latency = display->wm.spr_latency[level];

sys/dev/pci/drm/i915/display/i9xx_wm.c

2720

u16 cur_latency = display->wm.cur_latency[level];

sys/dev/pci/drm/i915/display/i9xx_wm.c

2744

static void hsw_read_wm_latency(struct intel_display *display, u16 wm[])

sys/dev/pci/drm/i915/display/i9xx_wm.c

2746

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2749

display->wm.num_levels = 5;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2762

static void snb_read_wm_latency(struct intel_display *display, u16 wm[])

sys/dev/pci/drm/i915/display/i9xx_wm.c

2764

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2767

display->wm.num_levels = 4;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2777

static void ilk_read_wm_latency(struct intel_display *display, u16 wm[])

sys/dev/pci/drm/i915/display/i9xx_wm.c

2779

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2782

display->wm.num_levels = 3;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2792

static void intel_fixup_spr_wm_latency(struct intel_display *display, u16 wm[5])

sys/dev/pci/drm/i915/display/i9xx_wm.c

2795

if (DISPLAY_VER(display) == 5)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2799

static void intel_fixup_cur_wm_latency(struct intel_display *display, u16 wm[5])

sys/dev/pci/drm/i915/display/i9xx_wm.c

2802

if (DISPLAY_VER(display) == 5)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2806

static bool ilk_increase_wm_latency(struct intel_display *display, u16 wm[5], u16 min)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2814

for (level = 1; level < display->wm.num_levels; level++)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2820

static void snb_wm_latency_quirk(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2828

changed = ilk_increase_wm_latency(display, display->wm.pri_latency, 12);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2829

changed |= ilk_increase_wm_latency(display, display->wm.spr_latency, 12);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2830

changed |= ilk_increase_wm_latency(display, display->wm.cur_latency, 12);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2835

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2837

intel_print_wm_latency(display, "Primary", display->wm.pri_latency);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2838

intel_print_wm_latency(display, "Sprite", display->wm.spr_latency);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2839

intel_print_wm_latency(display, "Cursor", display->wm.cur_latency);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2842

static void snb_wm_lp3_irq_quirk(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

285

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2855

if (display->wm.pri_latency[3] == 0 &&

sys/dev/pci/drm/i915/display/i9xx_wm.c

2856

display->wm.spr_latency[3] == 0 &&

sys/dev/pci/drm/i915/display/i9xx_wm.c

2857

display->wm.cur_latency[3] == 0)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2860

display->wm.pri_latency[3] = 0;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2861

display->wm.spr_latency[3] = 0;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2862

display->wm.cur_latency[3] = 0;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2864

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2866

intel_print_wm_latency(display, "Primary", display->wm.pri_latency);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2867

intel_print_wm_latency(display, "Sprite", display->wm.spr_latency);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2868

intel_print_wm_latency(display, "Cursor", display->wm.cur_latency);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2871

static void ilk_setup_wm_latency(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2873

if (display->platform.broadwell || display->platform.haswell)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2874

hsw_read_wm_latency(display, display->wm.pri_latency);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2875

else if (DISPLAY_VER(display) >= 6)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2876

snb_read_wm_latency(display, display->wm.pri_latency);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2878

ilk_read_wm_latency(display, display->wm.pri_latency);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2880

memcpy(display->wm.spr_latency, display->wm.pri_latency,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2881

sizeof(display->wm.pri_latency));

sys/dev/pci/drm/i915/display/i9xx_wm.c

2882

memcpy(display->wm.cur_latency, display->wm.pri_latency,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2883

sizeof(display->wm.pri_latency));

sys/dev/pci/drm/i915/display/i9xx_wm.c

2885

intel_fixup_spr_wm_latency(display, display->wm.spr_latency);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2886

intel_fixup_cur_wm_latency(display, display->wm.cur_latency);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2888

intel_print_wm_latency(display, "Primary", display->wm.pri_latency);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2889

intel_print_wm_latency(display, "Sprite", display->wm.spr_latency);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2890

intel_print_wm_latency(display, "Cursor", display->wm.cur_latency);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2892

if (DISPLAY_VER(display) == 6) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

2893

snb_wm_latency_quirk(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2894

snb_wm_lp3_irq_quirk(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2898

static bool ilk_validate_pipe_wm(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2910

ilk_compute_wm_maximums(display, 0, &config, INTEL_DDB_PART_1_2, &max);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2913

if (!ilk_validate_wm_level(display, 0, &max, &pipe_wm->wm[0])) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

2914

drm_dbg_kms(display->drm, "LP0 watermark invalid\n");

sys/dev/pci/drm/i915/display/i9xx_wm.c

2925

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/i9xx_wm.c

294

dsparb = intel_de_read(display, DSPARB(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

295

dsparb2 = intel_de_read(display, DSPARB2);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2952

usable_level = display->wm.num_levels - 1;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2955

if (DISPLAY_VER(display) < 7 && pipe_wm->sprites_enabled)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2963

ilk_compute_wm_level(display, crtc, 0, crtc_state,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2966

if (!ilk_validate_pipe_wm(display, pipe_wm))

sys/dev/pci/drm/i915/display/i9xx_wm.c

2969

ilk_compute_wm_reg_maximums(display, 1, &max);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2974

ilk_compute_wm_level(display, crtc, level, crtc_state,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2982

if (!ilk_validate_wm_level(display, level, &max, wm)) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

2999

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/i9xx_wm.c

300

dsparb = intel_de_read(display, DSPARB(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

301

dsparb2 = intel_de_read(display, DSPARB2);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3024

for (level = 0; level < display->wm.num_levels; level++) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

3045

if (!ilk_validate_pipe_wm(display, intermediate))

sys/dev/pci/drm/i915/display/i9xx_wm.c

306

dsparb2 = intel_de_read(display, DSPARB2);

sys/dev/pci/drm/i915/display/i9xx_wm.c

307

dsparb3 = intel_de_read(display, DSPARB3);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3077

static void ilk_merge_wm_level(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

3085

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

3110

static void ilk_wm_merge(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

3115

int level, num_levels = display->wm.num_levels;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3119

if ((DISPLAY_VER(display) < 7 || display->platform.ivybridge) &&

sys/dev/pci/drm/i915/display/i9xx_wm.c

3124

merged->fbc_wm_enabled = DISPLAY_VER(display) >= 6;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3130

ilk_merge_wm_level(display, level, wm);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3134

else if (!ilk_validate_wm_level(display, level, max, wm))

sys/dev/pci/drm/i915/display/i9xx_wm.c

3150

if (DISPLAY_VER(display) == 5 && HAS_FBC(display) &&

sys/dev/pci/drm/i915/display/i9xx_wm.c

3151

display->params.enable_fbc && !merged->fbc_wm_enabled) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

3167

static unsigned int ilk_wm_lp_latency(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

3170

if (display->platform.haswell || display->platform.broadwell)

sys/dev/pci/drm/i915/display/i9xx_wm.c

3173

return display->wm.pri_latency[level];

sys/dev/pci/drm/i915/display/i9xx_wm.c

3176

static void ilk_compute_wm_results(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

3200

WM_LP_LATENCY(ilk_wm_lp_latency(display, level)) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

3207

if (DISPLAY_VER(display) >= 8)

sys/dev/pci/drm/i915/display/i9xx_wm.c

3218

if (DISPLAY_VER(display) < 7 && r->spr_val) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

3219

drm_WARN_ON(display->drm, wm_lp != 1);

sys/dev/pci/drm/i915/display/i9xx_wm.c

322

static int i9xx_get_fifo_size(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

3225

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

3230

if (drm_WARN_ON(display->drm, !r->enable))

sys/dev/pci/drm/i915/display/i9xx_wm.c

3245

ilk_find_best_result(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

325

u32 dsparb = intel_de_read(display, DSPARB(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3251

for (level = 1; level < display->wm.num_levels; level++) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

3277

static unsigned int ilk_compute_wm_dirty(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

3285

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

332

drm_dbg_kms(display->drm, "FIFO size - (0x%08x) %c: %d\n",

sys/dev/pci/drm/i915/display/i9xx_wm.c

3323

static bool _ilk_disable_lp_wm(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

3326

struct ilk_wm_values *previous = &display->wm.hw;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3331

intel_de_write(display, WM3_LP_ILK, previous->wm_lp[2]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3336

intel_de_write(display, WM2_LP_ILK, previous->wm_lp[1]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3341

intel_de_write(display, WM1_LP_ILK, previous->wm_lp[0]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3357

static void ilk_write_wm_values(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

3360

struct ilk_wm_values *previous = &display->wm.hw;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3363

dirty = ilk_compute_wm_dirty(display, previous, results);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3367

_ilk_disable_lp_wm(display, dirty);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3370

intel_de_write(display, WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3372

intel_de_write(display, WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3374

intel_de_write(display, WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3377

if (display->platform.haswell || display->platform.broadwell)

sys/dev/pci/drm/i915/display/i9xx_wm.c

3378

intel_de_rmw(display, WM_MISC, WM_MISC_DATA_PARTITION_5_6,

sys/dev/pci/drm/i915/display/i9xx_wm.c

338

static int i830_get_fifo_size(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

3382

intel_de_rmw(display, DISP_ARB_CTL2, DISP_DATA_PARTITION_5_6,

sys/dev/pci/drm/i915/display/i9xx_wm.c

3388

intel_de_rmw(display, DISP_ARB_CTL, DISP_FBC_WM_DIS,

sys/dev/pci/drm/i915/display/i9xx_wm.c

3393

intel_de_write(display, WM1S_LP_ILK, results->wm_lp_spr[0]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3395

if (DISPLAY_VER(display) >= 7) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

3397

intel_de_write(display, WM2S_LP_IVB, results->wm_lp_spr[1]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3399

intel_de_write(display, WM3S_LP_IVB, results->wm_lp_spr[2]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3403

intel_de_write(display, WM1_LP_ILK, results->wm_lp[0]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3405

intel_de_write(display, WM2_LP_ILK, results->wm_lp[1]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3407

intel_de_write(display, WM3_LP_ILK, results->wm_lp[2]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3409

display->wm.hw = *results;

sys/dev/pci/drm/i915/display/i9xx_wm.c

341

u32 dsparb = intel_de_read(display, DSPARB(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3412

bool ilk_disable_cxsr(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

3414

return _ilk_disable_lp_wm(display, WM_DIRTY_LP_ALL);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3417

static void ilk_compute_wm_config(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

3423

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

3435

static void ilk_program_watermarks(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

3443

ilk_compute_wm_config(display, &config);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3445

ilk_compute_wm_maximums(display, 1, &config, INTEL_DDB_PART_1_2, &max);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3446

ilk_wm_merge(display, &config, &max, &lp_wm_1_2);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3449

if (DISPLAY_VER(display) >= 7 &&

sys/dev/pci/drm/i915/display/i9xx_wm.c

3451

ilk_compute_wm_maximums(display, 1, &config, INTEL_DDB_PART_5_6, &max);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3452

ilk_wm_merge(display, &config, &max, &lp_wm_5_6);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3454

best_lp_wm = ilk_find_best_result(display, &lp_wm_1_2, &lp_wm_5_6);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3462

ilk_compute_wm_results(display, best_lp_wm, partitioning, &results);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3464

ilk_write_wm_values(display, &results);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3470

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3474

mutex_lock(&display->wm.wm_mutex);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3476

ilk_program_watermarks(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3477

mutex_unlock(&display->wm.wm_mutex);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3483

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/i9xx_wm.c

349

drm_dbg_kms(display->drm, "FIFO size - (0x%08x) %c: %d\n",

sys/dev/pci/drm/i915/display/i9xx_wm.c

3490

mutex_lock(&display->wm.wm_mutex);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3492

ilk_program_watermarks(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3493

mutex_unlock(&display->wm.wm_mutex);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3498

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3499

struct ilk_wm_values *hw = &display->wm.hw;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3504

hw->wm_pipe[pipe] = intel_de_read(display, WM0_PIPE_ILK(pipe));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3531

for (level = 0; level < display->wm.num_levels; level++)

sys/dev/pci/drm/i915/display/i9xx_wm.c

355

static int i845_get_fifo_size(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

358

u32 dsparb = intel_de_read(display, DSPARB(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3580

void ilk_wm_sanitize(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

3591

if (!display->funcs.wm->optimize_watermarks)

sys/dev/pci/drm/i915/display/i9xx_wm.c

3594

if (drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 9))

sys/dev/pci/drm/i915/display/i9xx_wm.c

3597

state = drm_atomic_state_alloc(display->drm);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3598

if (drm_WARN_ON(display->drm, !state))

sys/dev/pci/drm/i915/display/i9xx_wm.c

3614

if (!HAS_GMCH(display))

sys/dev/pci/drm/i915/display/i9xx_wm.c

3621

ret = intel_atomic_check(display->drm, state);

sys/dev/pci/drm/i915/display/i9xx_wm.c

364

drm_dbg_kms(display->drm, "FIFO size - (0x%08x) %c: %d\n",

sys/dev/pci/drm/i915/display/i9xx_wm.c

3651

drm_WARN(display->drm, ret,

sys/dev/pci/drm/i915/display/i9xx_wm.c

3665

static void g4x_read_wm_values(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

3670

tmp = intel_de_read(display, DSPFW1(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3676

tmp = intel_de_read(display, DSPFW2(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3684

tmp = intel_de_read(display, DSPFW3(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3691

static void vlv_read_wm_values(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

3697

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

3698

tmp = intel_de_read(display, VLV_DDL(pipe));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3710

tmp = intel_de_read(display, DSPFW1(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3716

tmp = intel_de_read(display, DSPFW2(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3721

tmp = intel_de_read(display, DSPFW3(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3724

if (display->platform.cherryview) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

3725

tmp = intel_de_read(display, DSPFW7_CHV);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3729

tmp = intel_de_read(display, DSPFW8_CHV);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3733

tmp = intel_de_read(display, DSPFW9_CHV);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3737

tmp = intel_de_read(display, DSPHOWM);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3749

tmp = intel_de_read(display, DSPFW7);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3753

tmp = intel_de_read(display, DSPHOWM);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3767

static void g4x_wm_get_hw_state(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

3769

struct g4x_wm_values *wm = &display->wm.g4x;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3772

g4x_read_wm_values(display, wm);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3774

wm->cxsr = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3776

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

3841

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

3849

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

3852

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

3855

drm_dbg_kms(display->drm, "Initial SR=%s HPLL=%s FBC=%s\n",

sys/dev/pci/drm/i915/display/i9xx_wm.c

3860

static void g4x_wm_sanitize(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

3865

mutex_lock(&display->wm.wm_mutex);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3867

for_each_intel_plane(display->drm, plane) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

3869

intel_crtc_for_pipe(display, plane->pipe);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3880

for (level = 0; level < display->wm.num_levels; level++) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

3891

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

3897

drm_WARN_ON(display->drm, ret);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3904

g4x_program_watermarks(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3906

mutex_unlock(&display->wm.wm_mutex);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3909

static void vlv_wm_get_hw_state(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

3911

struct vlv_wm_values *wm = &display->wm.vlv;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3916

vlv_read_wm_values(display, wm);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3918

wm->cxsr = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3921

if (display->platform.cherryview) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

3922

vlv_punit_get(display->drm);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3924

val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3937

val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3939

vlv_punit_write(display->drm, PUNIT_REG_DDR_SETUP2, val);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3941

ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2),

sys/dev/pci/drm/i915/display/i9xx_wm.c

3945

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

3948

display->wm.num_levels = VLV_WM_LEVEL_PM5 + 1;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3950

val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3955

vlv_punit_put(display->drm);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3958

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

3998

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

4007

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

4012

static void vlv_wm_sanitize(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

4017

mutex_lock(&display->wm.wm_mutex);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4019

for_each_intel_plane(display->drm, plane) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

4021

intel_crtc_for_pipe(display, plane->pipe);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4032

for (level = 0; level < display->wm.num_levels; level++) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

4040

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

4046

drm_WARN_ON(display->drm, ret);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4053

vlv_program_watermarks(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4055

mutex_unlock(&display->wm.wm_mutex);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4062

static void ilk_init_lp_watermarks(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

4064

intel_de_rmw(display, WM3_LP_ILK, WM_LP_ENABLE, 0);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4065

intel_de_rmw(display, WM2_LP_ILK, WM_LP_ENABLE, 0);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4066

intel_de_rmw(display, WM1_LP_ILK, WM_LP_ENABLE, 0);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4074

static void ilk_wm_get_hw_state(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

4076

struct ilk_wm_values *hw = &display->wm.hw;

sys/dev/pci/drm/i915/display/i9xx_wm.c

4079

ilk_init_lp_watermarks(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4081

for_each_intel_crtc(display->drm, crtc)

sys/dev/pci/drm/i915/display/i9xx_wm.c

4084

hw->wm_lp[0] = intel_de_read(display, WM1_LP_ILK);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4085

hw->wm_lp[1] = intel_de_read(display, WM2_LP_ILK);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4086

hw->wm_lp[2] = intel_de_read(display, WM3_LP_ILK);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4088

hw->wm_lp_spr[0] = intel_de_read(display, WM1S_LP_ILK);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4089

if (DISPLAY_VER(display) >= 7) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

4090

hw->wm_lp_spr[1] = intel_de_read(display, WM2S_LP_IVB);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4091

hw->wm_lp_spr[2] = intel_de_read(display, WM3S_LP_IVB);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4094

if (display->platform.haswell || display->platform.broadwell)

sys/dev/pci/drm/i915/display/i9xx_wm.c

4095

hw->partitioning = (intel_de_read(display, WM_MISC) &

sys/dev/pci/drm/i915/display/i9xx_wm.c

4098

else if (display->platform.ivybridge)

sys/dev/pci/drm/i915/display/i9xx_wm.c

4099

hw->partitioning = (intel_de_read(display, DISP_ARB_CTL2) &

sys/dev/pci/drm/i915/display/i9xx_wm.c

4104

!(intel_de_read(display, DISP_ARB_CTL) & DISP_FBC_WM_DIS);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4154

void i9xx_wm_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

4157

if (HAS_PCH_SPLIT(display)) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

4158

ilk_setup_wm_latency(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4159

display->funcs.wm = &ilk_wm_funcs;

sys/dev/pci/drm/i915/display/i9xx_wm.c

4160

} else if (display->platform.valleyview || display->platform.cherryview) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

4161

vlv_setup_wm_latency(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4162

display->funcs.wm = &vlv_wm_funcs;

sys/dev/pci/drm/i915/display/i9xx_wm.c

4163

} else if (display->platform.g4x) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

4164

g4x_setup_wm_latency(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4165

display->funcs.wm = &g4x_wm_funcs;

sys/dev/pci/drm/i915/display/i9xx_wm.c

4166

} else if (display->platform.pineview) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

4167

if (!pnv_get_cxsr_latency(display)) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

4168

drm_info(display->drm, "Unknown FSB/MEM, disabling CxSR\n");

sys/dev/pci/drm/i915/display/i9xx_wm.c

4170

intel_set_memory_cxsr(display, false);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4171

display->funcs.wm = &nop_funcs;

sys/dev/pci/drm/i915/display/i9xx_wm.c

4173

display->funcs.wm = &pnv_wm_funcs;

sys/dev/pci/drm/i915/display/i9xx_wm.c

4175

} else if (DISPLAY_VER(display) == 4) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

4176

display->funcs.wm = &i965_wm_funcs;

sys/dev/pci/drm/i915/display/i9xx_wm.c

4177

} else if (DISPLAY_VER(display) == 3) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

4178

display->funcs.wm = &i9xx_wm_funcs;

sys/dev/pci/drm/i915/display/i9xx_wm.c

4179

} else if (DISPLAY_VER(display) == 2) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

4180

if (INTEL_NUM_PIPES(display) == 1)

sys/dev/pci/drm/i915/display/i9xx_wm.c

4181

display->funcs.wm = &i845_wm_funcs;

sys/dev/pci/drm/i915/display/i9xx_wm.c

4183

display->funcs.wm = &i9xx_wm_funcs;

sys/dev/pci/drm/i915/display/i9xx_wm.c

4185

drm_err(display->drm,

sys/dev/pci/drm/i915/display/i9xx_wm.c

4187

display->funcs.wm = &nop_funcs;

sys/dev/pci/drm/i915/display/i9xx_wm.c

567

static unsigned int intel_calculate_wm(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

585

drm_dbg_kms(display->drm, "FIFO entries required for mode: %d\n", entries);

sys/dev/pci/drm/i915/display/i9xx_wm.c

588

drm_dbg_kms(display->drm, "FIFO watermark level: %d\n", wm_size);

sys/dev/pci/drm/i915/display/i9xx_wm.c

638

static struct intel_crtc *single_enabled_crtc(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

642

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

653

static void pnv_update_wm(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

660

latency = pnv_get_cxsr_latency(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

662

drm_dbg_kms(display->drm, "Unknown FSB/MEM, disabling CxSR\n");

sys/dev/pci/drm/i915/display/i9xx_wm.c

663

intel_set_memory_cxsr(display, false);

sys/dev/pci/drm/i915/display/i9xx_wm.c

667

crtc = single_enabled_crtc(display);

sys/dev/pci/drm/i915/display/i9xx_wm.c

675

wm = intel_calculate_wm(display, pixel_rate,

sys/dev/pci/drm/i915/display/i9xx_wm.c

679

reg = intel_de_read(display, DSPFW1(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

682

intel_de_write(display, DSPFW1(display), reg);

sys/dev/pci/drm/i915/display/i9xx_wm.c

683

drm_dbg_kms(display->drm, "DSPFW1 register is %x\n", reg);

sys/dev/pci/drm/i915/display/i9xx_wm.c

686

wm = intel_calculate_wm(display, pixel_rate,

sys/dev/pci/drm/i915/display/i9xx_wm.c

690

intel_de_rmw(display, DSPFW3(display),

sys/dev/pci/drm/i915/display/i9xx_wm.c

694

wm = intel_calculate_wm(display, pixel_rate,

sys/dev/pci/drm/i915/display/i9xx_wm.c

698

intel_de_rmw(display, DSPFW3(display),

sys/dev/pci/drm/i915/display/i9xx_wm.c

702

wm = intel_calculate_wm(display, pixel_rate,

sys/dev/pci/drm/i915/display/i9xx_wm.c

706

reg = intel_de_read(display, DSPFW3(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

709

intel_de_write(display, DSPFW3(display), reg);

sys/dev/pci/drm/i915/display/i9xx_wm.c

710

drm_dbg_kms(display->drm, "DSPFW3 register is %x\n", reg);

sys/dev/pci/drm/i915/display/i9xx_wm.c

712

intel_set_memory_cxsr(display, true);

sys/dev/pci/drm/i915/display/i9xx_wm.c

714

intel_set_memory_cxsr(display, false);

sys/dev/pci/drm/i915/display/i9xx_wm.c

805

static void g4x_write_wm_values(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

810

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/i9xx_wm.c

811

trace_g4x_wm(intel_crtc_for_pipe(display, pipe), wm);

sys/dev/pci/drm/i915/display/i9xx_wm.c

813

intel_de_write(display, DSPFW1(display),

sys/dev/pci/drm/i915/display/i9xx_wm.c

818

intel_de_write(display, DSPFW2(display),

sys/dev/pci/drm/i915/display/i9xx_wm.c

825

intel_de_write(display, DSPFW3(display),

sys/dev/pci/drm/i915/display/i9xx_wm.c

831

intel_de_posting_read(display, DSPFW1(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

837

static void vlv_write_wm_values(struct intel_display *display,

sys/dev/pci/drm/i915/display/i9xx_wm.c

842

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

843

trace_vlv_wm(intel_crtc_for_pipe(display, pipe), wm);

sys/dev/pci/drm/i915/display/i9xx_wm.c

845

intel_de_write(display, VLV_DDL(pipe),

sys/dev/pci/drm/i915/display/i9xx_wm.c

857

intel_de_write(display, DSPHOWM, 0);

sys/dev/pci/drm/i915/display/i9xx_wm.c

858

intel_de_write(display, DSPHOWM1, 0);

sys/dev/pci/drm/i915/display/i9xx_wm.c

859

intel_de_write(display, DSPFW4, 0);

sys/dev/pci/drm/i915/display/i9xx_wm.c

860

intel_de_write(display, DSPFW5, 0);

sys/dev/pci/drm/i915/display/i9xx_wm.c

861

intel_de_write(display, DSPFW6, 0);

sys/dev/pci/drm/i915/display/i9xx_wm.c

863

intel_de_write(display, DSPFW1(display),

sys/dev/pci/drm/i915/display/i9xx_wm.c

868

intel_de_write(display, DSPFW2(display),

sys/dev/pci/drm/i915/display/i9xx_wm.c

872

intel_de_write(display, DSPFW3(display),

sys/dev/pci/drm/i915/display/i9xx_wm.c

875

if (display->platform.cherryview) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

876

intel_de_write(display, DSPFW7_CHV,

sys/dev/pci/drm/i915/display/i9xx_wm.c

879

intel_de_write(display, DSPFW8_CHV,

sys/dev/pci/drm/i915/display/i9xx_wm.c

882

intel_de_write(display, DSPFW9_CHV,

sys/dev/pci/drm/i915/display/i9xx_wm.c

885

intel_de_write(display, DSPHOWM,

sys/dev/pci/drm/i915/display/i9xx_wm.c

897

intel_de_write(display, DSPFW7,

sys/dev/pci/drm/i915/display/i9xx_wm.c

90

static const struct cxsr_latency *pnv_get_cxsr_latency(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

900

intel_de_write(display, DSPHOWM,

sys/dev/pci/drm/i915/display/i9xx_wm.c

910

intel_de_posting_read(display, DSPFW1(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

915

static void g4x_setup_wm_latency(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.c

918

display->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;

sys/dev/pci/drm/i915/display/i9xx_wm.c

919

display->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;

sys/dev/pci/drm/i915/display/i9xx_wm.c

92

const struct dram_info *dram_info = intel_dram_info(display->drm);

sys/dev/pci/drm/i915/display/i9xx_wm.c

920

display->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;

sys/dev/pci/drm/i915/display/i9xx_wm.c

922

display->wm.num_levels = G4X_WM_LEVEL_HPLL + 1;

sys/dev/pci/drm/i915/display/i9xx_wm.c

971

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/i9xx_wm.c

975

unsigned int latency = display->wm.pri_latency[level] * 10;

sys/dev/pci/drm/i915/display/i9xx_wm.c

98

bool is_desktop = !display->platform.mobile;

sys/dev/pci/drm/i915/display/i9xx_wm.h

16

bool ilk_disable_cxsr(struct intel_display *display);

sys/dev/pci/drm/i915/display/i9xx_wm.h

17

void ilk_wm_sanitize(struct intel_display *display);

sys/dev/pci/drm/i915/display/i9xx_wm.h

18

bool intel_set_memory_cxsr(struct intel_display *display, bool enable);

sys/dev/pci/drm/i915/display/i9xx_wm.h

19

void i9xx_wm_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/i9xx_wm.h

21

static inline bool ilk_disable_cxsr(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.h

25

static inline void ilk_wm_sanitize(struct intel_display *display)

sys/dev/pci/drm/i915/display/i9xx_wm.h

28

static inline bool intel_set_memory_cxsr(struct intel_display *display, bool enable)

sys/dev/pci/drm/i915/display/i9xx_wm.h

32

static inline void i9xx_wm_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/icl_dsi.c

1001

intel_de_write(display,

sys/dev/pci/drm/i915/display/icl_dsi.c

1002

TRANS_VSYNC(display, dsi_trans),

sys/dev/pci/drm/i915/display/icl_dsi.c

1016

intel_de_write(display,

sys/dev/pci/drm/i915/display/icl_dsi.c

1017

TRANS_VSYNCSHIFT(display, dsi_trans),

sys/dev/pci/drm/i915/display/icl_dsi.c

1028

if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/icl_dsi.c

1031

intel_de_write(display,

sys/dev/pci/drm/i915/display/icl_dsi.c

1032

TRANS_VBLANK(display, dsi_trans),

sys/dev/pci/drm/i915/display/icl_dsi.c

1040

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

1047

intel_de_rmw(display, TRANSCONF(display, dsi_trans), 0,

sys/dev/pci/drm/i915/display/icl_dsi.c

1051

if (intel_de_wait_for_set(display, TRANSCONF(display, dsi_trans),

sys/dev/pci/drm/i915/display/icl_dsi.c

1053

drm_err(display->drm,

sys/dev/pci/drm/i915/display/icl_dsi.c

1061

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

1085

intel_de_rmw(display, DSI_HSTX_TO(dsi_trans),

sys/dev/pci/drm/i915/display/icl_dsi.c

1092

intel_de_rmw(display, DSI_LPRX_HOST_TO(dsi_trans),

sys/dev/pci/drm/i915/display/icl_dsi.c

1099

intel_de_rmw(display, DSI_TA_TO(dsi_trans),

sys/dev/pci/drm/i915/display/icl_dsi.c

1108

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

1120

tmp = intel_de_read(display, UTIL_PIN_CTL);

sys/dev/pci/drm/i915/display/icl_dsi.c

1128

intel_de_write(display, UTIL_PIN_CTL, tmp);

sys/dev/pci/drm/i915/display/icl_dsi.c

116

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

1166

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

1182

tmp = intel_de_read(display, DSI_CMD_RXCTL(dsi_trans));

sys/dev/pci/drm/i915/display/icl_dsi.c

1189

drm_err(display->drm,

sys/dev/pci/drm/i915/display/icl_dsi.c

1249

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

1251

if (DISPLAY_VER(display) == 11 && pipe == PIPE_B)

sys/dev/pci/drm/i915/display/icl_dsi.c

1252

intel_de_rmw(display, CHICKEN_PAR1_1,

sys/dev/pci/drm/i915/display/icl_dsi.c

126

wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);

sys/dev/pci/drm/i915/display/icl_dsi.c

1265

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

1269

if (DISPLAY_VER(display) == 13) {

sys/dev/pci/drm/i915/display/icl_dsi.c

127

wait_for_payload_credits(display, dsi_trans, MAX_PLOAD_CREDIT);

sys/dev/pci/drm/i915/display/icl_dsi.c

1271

intel_de_rmw(display, TGL_DSI_CHKN_REG(port),

sys/dev/pci/drm/i915/display/icl_dsi.c

1307

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

1316

intel_de_rmw(display, TRANSCONF(display, dsi_trans),

sys/dev/pci/drm/i915/display/icl_dsi.c

1320

if (intel_de_wait_for_clear(display, TRANSCONF(display, dsi_trans),

sys/dev/pci/drm/i915/display/icl_dsi.c

1322

drm_err(display->drm,

sys/dev/pci/drm/i915/display/icl_dsi.c

1339

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

1349

intel_de_rmw(display, DSI_CMD_FRMCTL(port),

sys/dev/pci/drm/i915/display/icl_dsi.c

1356

tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans));

sys/dev/pci/drm/i915/display/icl_dsi.c

1359

intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp);

sys/dev/pci/drm/i915/display/icl_dsi.c

1361

ret = intel_de_wait_custom(display, DSI_LP_MSG(dsi_trans),

sys/dev/pci/drm/i915/display/icl_dsi.c

1365

drm_err(display->drm, "DSI link not in ULPS\n");

sys/dev/pci/drm/i915/display/icl_dsi.c

137

drm_err(display->drm,

sys/dev/pci/drm/i915/display/icl_dsi.c

1371

intel_de_rmw(display,

sys/dev/pci/drm/i915/display/icl_dsi.c

1372

TRANS_DDI_FUNC_CTL(display, dsi_trans),

sys/dev/pci/drm/i915/display/icl_dsi.c

1380

intel_de_rmw(display,

sys/dev/pci/drm/i915/display/icl_dsi.c

1381

TRANS_DDI_FUNC_CTL2(display, dsi_trans),

sys/dev/pci/drm/i915/display/icl_dsi.c

1389

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

1396

intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);

sys/dev/pci/drm/i915/display/icl_dsi.c

1398

ret = intel_de_wait_custom(display, DDI_BUF_CTL(port),

sys/dev/pci/drm/i915/display/icl_dsi.c

1403

drm_err(display->drm,

sys/dev/pci/drm/i915/display/icl_dsi.c

1412

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

1420

intel_display_power_put(display,

sys/dev/pci/drm/i915/display/icl_dsi.c

1429

intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),

sys/dev/pci/drm/i915/display/icl_dsi.c

144

wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);

sys/dev/pci/drm/i915/display/icl_dsi.c

1491

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/icl_dsi.c

1494

status = intel_cpu_transcoder_mode_valid(display, mode);

sys/dev/pci/drm/i915/display/icl_dsi.c

151

ret = intel_de_wait_custom(display, DSI_LP_MSG(dsi_trans),

sys/dev/pci/drm/i915/display/icl_dsi.c

1543

struct intel_display *display = to_intel_display(&intel_dsi->base);

sys/dev/pci/drm/i915/display/icl_dsi.c

155

drm_err(display->drm, "LPTX bit not cleared\n");

sys/dev/pci/drm/i915/display/icl_dsi.c

1552

val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));

sys/dev/pci/drm/i915/display/icl_dsi.c

1595

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

1606

if (DISPLAY_VER(display) == 11 && pipe == PIPE_B &&

sys/dev/pci/drm/i915/display/icl_dsi.c

1607

!(intel_de_read(display, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))

sys/dev/pci/drm/i915/display/icl_dsi.c

1608

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/icl_dsi.c

1617

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

1619

int dsc_max_bpc = DISPLAY_VER(display) >= 12 ? 12 : 10;

sys/dev/pci/drm/i915/display/icl_dsi.c

163

struct intel_display *display = to_intel_display(&intel_dsi->base);

sys/dev/pci/drm/i915/display/icl_dsi.c

1646

drm_WARN_ON(display->drm, vdsc_cfg->vbr_enable);

sys/dev/pci/drm/i915/display/icl_dsi.c

1647

drm_WARN_ON(display->drm, vdsc_cfg->simple_422);

sys/dev/pci/drm/i915/display/icl_dsi.c

1648

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/icl_dsi.c

1650

drm_WARN_ON(display->drm, vdsc_cfg->slice_height < 8);

sys/dev/pci/drm/i915/display/icl_dsi.c

1651

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/icl_dsi.c

1667

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

1701

drm_dbg_kms(display->drm, "Attempting to use DSC failed\n");

sys/dev/pci/drm/i915/display/icl_dsi.c

171

drm_err(display->drm, "payload size exceeds max queue limit\n");

sys/dev/pci/drm/i915/display/icl_dsi.c

1725

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

1733

wakeref = intel_display_power_get_if_enabled(display,

sys/dev/pci/drm/i915/display/icl_dsi.c

1740

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/icl_dsi.c

1741

TRANS_DDI_FUNC_CTL(display, dsi_trans));

sys/dev/pci/drm/i915/display/icl_dsi.c

1756

drm_err(display->drm, "Invalid PIPE input\n");

sys/dev/pci/drm/i915/display/icl_dsi.c

1760

tmp = intel_de_read(display, TRANSCONF(display, dsi_trans));

sys/dev/pci/drm/i915/display/icl_dsi.c

1764

intel_display_power_put(display, encoder->power_domain, wakeref);

sys/dev/pci/drm/i915/display/icl_dsi.c

178

if (!wait_for_payload_credits(display, dsi_trans, 1))

sys/dev/pci/drm/i915/display/icl_dsi.c

184

intel_de_write(display, DSI_CMD_TXPYLD(dsi_trans), tmp);

sys/dev/pci/drm/i915/display/icl_dsi.c

1927

void icl_dsi_init(struct intel_display *display,

sys/dev/pci/drm/i915/display/icl_dsi.c

195

struct intel_display *display = to_intel_display(&intel_dsi->base);

sys/dev/pci/drm/i915/display/icl_dsi.c

1957

drm_encoder_init(display->drm, &encoder->base,

sys/dev/pci/drm/i915/display/icl_dsi.c

1983

drm_connector_init(display->drm, connector,

sys/dev/pci/drm/i915/display/icl_dsi.c

199

if (!wait_for_header_credits(display, dsi_trans, 1))

sys/dev/pci/drm/i915/display/icl_dsi.c

1995

intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, NULL);

sys/dev/pci/drm/i915/display/icl_dsi.c

1997

mutex_lock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/icl_dsi.c

1999

mutex_unlock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/icl_dsi.c

2002

drm_err(display->drm, "DSI fixed mode info missing\n");

sys/dev/pci/drm/i915/display/icl_dsi.c

2015

if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))

sys/dev/pci/drm/i915/display/icl_dsi.c

2018

if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))

sys/dev/pci/drm/i915/display/icl_dsi.c

202

tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans));

sys/dev/pci/drm/i915/display/icl_dsi.c

2032

drm_dbg_kms(display->drm, "no device found\n");

sys/dev/pci/drm/i915/display/icl_dsi.c

221

intel_de_write(display, DSI_CMD_TXHDR(dsi_trans), tmp);

sys/dev/pci/drm/i915/display/icl_dsi.c

228

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/icl_dsi.c

246

intel_de_rmw(display, DSI_CMD_FRMCTL(port), 0,

sys/dev/pci/drm/i915/display/icl_dsi.c

252

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

266

tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

sys/dev/pci/drm/i915/display/icl_dsi.c

269

intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);

sys/dev/pci/drm/i915/display/icl_dsi.c

270

intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), mask, val);

sys/dev/pci/drm/i915/display/icl_dsi.c

276

tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));

sys/dev/pci/drm/i915/display/icl_dsi.c

279

intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);

sys/dev/pci/drm/i915/display/icl_dsi.c

280

intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), mask, val);

sys/dev/pci/drm/i915/display/icl_dsi.c

286

intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), mask, val);

sys/dev/pci/drm/i915/display/icl_dsi.c

290

intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),

sys/dev/pci/drm/i915/display/icl_dsi.c

298

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

304

if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/icl_dsi.c

314

dss_ctl1 = intel_de_read(display, dss_ctl1_reg);

sys/dev/pci/drm/i915/display/icl_dsi.c

329

drm_err(display->drm,

sys/dev/pci/drm/i915/display/icl_dsi.c

334

intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,

sys/dev/pci/drm/i915/display/icl_dsi.c

341

intel_de_write(display, dss_ctl1_reg, dss_ctl1);

sys/dev/pci/drm/i915/display/icl_dsi.c

362

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

371

if (display->platform.alderlake_s || display->platform.alderlake_p) {

sys/dev/pci/drm/i915/display/icl_dsi.c

381

intel_de_write(display, ICL_DSI_ESC_CLK_DIV(port),

sys/dev/pci/drm/i915/display/icl_dsi.c

383

intel_de_posting_read(display, ICL_DSI_ESC_CLK_DIV(port));

sys/dev/pci/drm/i915/display/icl_dsi.c

387

intel_de_write(display, ICL_DPHY_ESC_CLK_DIV(port),

sys/dev/pci/drm/i915/display/icl_dsi.c

389

intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port));

sys/dev/pci/drm/i915/display/icl_dsi.c

392

if (display->platform.alderlake_s || display->platform.alderlake_p) {

sys/dev/pci/drm/i915/display/icl_dsi.c

394

intel_de_write(display, ADL_MIPIO_DW(port, 8),

sys/dev/pci/drm/i915/display/icl_dsi.c

396

intel_de_posting_read(display, ADL_MIPIO_DW(port, 8));

sys/dev/pci/drm/i915/display/icl_dsi.c

403

struct intel_display *display = to_intel_display(&intel_dsi->base);

sys/dev/pci/drm/i915/display/icl_dsi.c

407

drm_WARN_ON(display->drm, intel_dsi->io_wakeref[port]);

sys/dev/pci/drm/i915/display/icl_dsi.c

409

intel_display_power_get(display,

sys/dev/pci/drm/i915/display/icl_dsi.c

418

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

423

intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),

sys/dev/pci/drm/i915/display/icl_dsi.c

431

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

436

intel_combo_phy_power_up_lanes(display, phy, true,

sys/dev/pci/drm/i915/display/icl_dsi.c

442

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

450

intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy),

sys/dev/pci/drm/i915/display/icl_dsi.c

453

intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),

sys/dev/pci/drm/i915/display/icl_dsi.c

459

intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy),

sys/dev/pci/drm/i915/display/icl_dsi.c

461

tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));

sys/dev/pci/drm/i915/display/icl_dsi.c

464

intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);

sys/dev/pci/drm/i915/display/icl_dsi.c

467

if (display->platform.jasperlake || display->platform.elkhartlake ||

sys/dev/pci/drm/i915/display/icl_dsi.c

468

(DISPLAY_VER(display) >= 12)) {

sys/dev/pci/drm/i915/display/icl_dsi.c

469

intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy),

sys/dev/pci/drm/i915/display/icl_dsi.c

472

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/icl_dsi.c

476

intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy),

sys/dev/pci/drm/i915/display/icl_dsi.c

485

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

492

tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));

sys/dev/pci/drm/i915/display/icl_dsi.c

494

intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), tmp);

sys/dev/pci/drm/i915/display/icl_dsi.c

495

intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0);

sys/dev/pci/drm/i915/display/icl_dsi.c

504

intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 0,

sys/dev/pci/drm/i915/display/icl_dsi.c

509

tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

sys/dev/pci/drm/i915/display/icl_dsi.c

511

intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);

sys/dev/pci/drm/i915/display/icl_dsi.c

512

intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0);

sys/dev/pci/drm/i915/display/icl_dsi.c

520

tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

sys/dev/pci/drm/i915/display/icl_dsi.c

522

intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);

sys/dev/pci/drm/i915/display/icl_dsi.c

523

intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN);

sys/dev/pci/drm/i915/display/icl_dsi.c

529

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

535

intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);

sys/dev/pci/drm/i915/display/icl_dsi.c

537

ret = intel_de_wait_custom(display, DDI_BUF_CTL(port),

sys/dev/pci/drm/i915/display/icl_dsi.c

541

drm_err(display->drm, "DDI port:%c buffer idle\n",

sys/dev/pci/drm/i915/display/icl_dsi.c

550

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

557

intel_de_write(display, DPHY_CLK_TIMING_PARAM(port),

sys/dev/pci/drm/i915/display/icl_dsi.c

562

intel_de_write(display, DPHY_DATA_TIMING_PARAM(port),

sys/dev/pci/drm/i915/display/icl_dsi.c

571

if (DISPLAY_VER(display) == 11) {

sys/dev/pci/drm/i915/display/icl_dsi.c

574

intel_de_rmw(display, DPHY_TA_TIMING_PARAM(port),

sys/dev/pci/drm/i915/display/icl_dsi.c

580

if (display->platform.jasperlake || display->platform.elkhartlake) {

sys/dev/pci/drm/i915/display/icl_dsi.c

582

intel_de_rmw(display, ICL_DPHY_CHKN(phy),

sys/dev/pci/drm/i915/display/icl_dsi.c

591

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

597

intel_de_rmw(display, ICL_DSI_T_INIT_MASTER(port),

sys/dev/pci/drm/i915/display/icl_dsi.c

60

static int header_credits_available(struct intel_display *display,

sys/dev/pci/drm/i915/display/icl_dsi.c

602

intel_de_write(display, DSI_CLK_TIMING_PARAM(port),

sys/dev/pci/drm/i915/display/icl_dsi.c

607

intel_de_write(display, DSI_DATA_TIMING_PARAM(port),

sys/dev/pci/drm/i915/display/icl_dsi.c

611

if (DISPLAY_VER(display) == 11) {

sys/dev/pci/drm/i915/display/icl_dsi.c

614

intel_de_rmw(display, DSI_TA_TIMING_PARAM(port),

sys/dev/pci/drm/i915/display/icl_dsi.c

624

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

629

mutex_lock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/icl_dsi.c

63

return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)

sys/dev/pci/drm/i915/display/icl_dsi.c

630

tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);

sys/dev/pci/drm/i915/display/icl_dsi.c

634

intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);

sys/dev/pci/drm/i915/display/icl_dsi.c

635

mutex_unlock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/icl_dsi.c

640

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

645

mutex_lock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/icl_dsi.c

646

tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);

sys/dev/pci/drm/i915/display/icl_dsi.c

650

intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);

sys/dev/pci/drm/i915/display/icl_dsi.c

651

mutex_unlock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/icl_dsi.c

656

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

662

tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);

sys/dev/pci/drm/i915/display/icl_dsi.c

67

static int payload_credits_available(struct intel_display *display,

sys/dev/pci/drm/i915/display/icl_dsi.c

675

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

681

mutex_lock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/icl_dsi.c

683

val = intel_de_read(display, ICL_DPCLKA_CFGCR0);

sys/dev/pci/drm/i915/display/icl_dsi.c

688

intel_de_write(display, ICL_DPCLKA_CFGCR0, val);

sys/dev/pci/drm/i915/display/icl_dsi.c

693

intel_de_write(display, ICL_DPCLKA_CFGCR0, val);

sys/dev/pci/drm/i915/display/icl_dsi.c

695

intel_de_posting_read(display, ICL_DPCLKA_CFGCR0);

sys/dev/pci/drm/i915/display/icl_dsi.c

697

mutex_unlock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/icl_dsi.c

70

return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)

sys/dev/pci/drm/i915/display/icl_dsi.c

704

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

714

tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));

sys/dev/pci/drm/i915/display/icl_dsi.c

74

static bool wait_for_header_credits(struct intel_display *display,

sys/dev/pci/drm/i915/display/icl_dsi.c

770

if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/icl_dsi.c

79

ret = poll_timeout_us(available = header_credits_available(display, dsi_trans),

sys/dev/pci/drm/i915/display/icl_dsi.c

803

intel_de_write(display, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);

sys/dev/pci/drm/i915/display/icl_dsi.c

810

intel_de_rmw(display,

sys/dev/pci/drm/i915/display/icl_dsi.c

811

TRANS_DDI_FUNC_CTL2(display, dsi_trans),

sys/dev/pci/drm/i915/display/icl_dsi.c

823

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/icl_dsi.c

824

TRANS_DDI_FUNC_CTL(display, dsi_trans));

sys/dev/pci/drm/i915/display/icl_dsi.c

83

drm_err(display->drm, "DSI header credits not released\n");

sys/dev/pci/drm/i915/display/icl_dsi.c

850

intel_de_write(display,

sys/dev/pci/drm/i915/display/icl_dsi.c

851

TRANS_DDI_FUNC_CTL(display, dsi_trans), tmp);

sys/dev/pci/drm/i915/display/icl_dsi.c

860

ret = intel_de_wait_custom(display, DSI_TRANS_FUNC_CONF(dsi_trans),

sys/dev/pci/drm/i915/display/icl_dsi.c

864

drm_err(display->drm, "DSI link not ready\n");

sys/dev/pci/drm/i915/display/icl_dsi.c

872

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/icl_dsi.c

90

static bool wait_for_payload_credits(struct intel_display *display,

sys/dev/pci/drm/i915/display/icl_dsi.c

939

drm_err(display->drm, "hactive is less then 256 pixels\n");

sys/dev/pci/drm/i915/display/icl_dsi.c

943

drm_err(display->drm,

sys/dev/pci/drm/i915/display/icl_dsi.c

949

intel_de_write(display, TRANS_HTOTAL(display, dsi_trans),

sys/dev/pci/drm/i915/display/icl_dsi.c

95

ret = poll_timeout_us(available = payload_credits_available(display, dsi_trans),

sys/dev/pci/drm/i915/display/icl_dsi.c

958

drm_err(display->drm,

sys/dev/pci/drm/i915/display/icl_dsi.c

963

drm_err(display->drm, "hback porch < 16 pixels\n");

sys/dev/pci/drm/i915/display/icl_dsi.c

972

intel_de_write(display,

sys/dev/pci/drm/i915/display/icl_dsi.c

973

TRANS_HSYNC(display, dsi_trans),

sys/dev/pci/drm/i915/display/icl_dsi.c

987

intel_de_write(display, TRANS_VTOTAL(display, dsi_trans),

sys/dev/pci/drm/i915/display/icl_dsi.c

99

drm_err(display->drm, "DSI payload credits not released\n");

sys/dev/pci/drm/i915/display/icl_dsi.c

992

drm_err(display->drm, "Invalid vsync_end value\n");

sys/dev/pci/drm/i915/display/icl_dsi.c

995

drm_err(display->drm, "vsync_start less than vactive\n");

sys/dev/pci/drm/i915/display/icl_dsi.h

13

void icl_dsi_init(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_acpi.h

14

void intel_dsm_get_bios_data_funcs_supported(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_acpi.h

15

void intel_acpi_device_id_update(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_acpi.h

16

void intel_acpi_assign_connector_fwnodes(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_acpi.h

17

void intel_acpi_video_register(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_acpi.h

22

void intel_dsm_get_bios_data_funcs_supported(struct intel_display *display) { return; }

sys/dev/pci/drm/i915/display/intel_acpi.h

24

void intel_acpi_device_id_update(struct intel_display *display) { return; }

sys/dev/pci/drm/i915/display/intel_acpi.h

26

void intel_acpi_assign_connector_fwnodes(struct intel_display *display) { return; }

sys/dev/pci/drm/i915/display/intel_acpi.h

28

void intel_acpi_video_register(struct intel_display *display) { return; }

sys/dev/pci/drm/i915/display/intel_alpm.c

138

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_alpm.c

157

if (display->params.psr_safest_params)

sys/dev/pci/drm/i915/display/intel_alpm.c

170

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_alpm.c

173

if (DISPLAY_VER(display) < 20)

sys/dev/pci/drm/i915/display/intel_alpm.c

186

if (display->params.psr_safest_params)

sys/dev/pci/drm/i915/display/intel_alpm.c

211

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_alpm.c

213

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_alpm.c

222

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_alpm.c

235

if (DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/intel_alpm.c

237

else if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_alpm.c

254

if (display->params.psr_safest_params)

sys/dev/pci/drm/i915/display/intel_alpm.c

268

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_alpm.c

274

drm_dbg_kms(display->drm, "LOBF is disabled by debug flag\n");

sys/dev/pci/drm/i915/display/intel_alpm.c

284

if (DISPLAY_VER(display) < 20)

sys/dev/pci/drm/i915/display/intel_alpm.c

320

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_alpm.c

324

if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&

sys/dev/pci/drm/i915/display/intel_alpm.c

349

intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_alpm.c

360

drm_dbg_kms(display->drm, "Link off between frames (LOBF) enabled\n");

sys/dev/pci/drm/i915/display/intel_alpm.c

365

intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl);

sys/dev/pci/drm/i915/display/intel_alpm.c

379

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_alpm.c

383

if (DISPLAY_VER(display) < 20)

sys/dev/pci/drm/i915/display/intel_alpm.c

401

intel_de_write(display, PORT_ALPM_CTL(port), alpm_ctl_val);

sys/dev/pci/drm/i915/display/intel_alpm.c

403

intel_de_write(display, PORT_ALPM_LFPS_CTL(port), lfps_ctl_val);

sys/dev/pci/drm/i915/display/intel_alpm.c

409

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_alpm.c

417

if (DISPLAY_VER(display) < 20)

sys/dev/pci/drm/i915/display/intel_alpm.c

423

for_each_intel_encoder_mask(display->drm, encoder,

sys/dev/pci/drm/i915/display/intel_alpm.c

437

intel_de_write(display, ALPM_CTL(display, cpu_transcoder), 0);

sys/dev/pci/drm/i915/display/intel_alpm.c

438

drm_dbg_kms(display->drm, "Link off between frames (LOBF) disabled\n");

sys/dev/pci/drm/i915/display/intel_alpm.c

464

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_alpm.c

475

for_each_intel_encoder_mask(display->drm, encoder,

sys/dev/pci/drm/i915/display/intel_alpm.c

494

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_alpm.c

501

ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_alpm.c

513

alpm_ctl = intel_de_read(display, ALPM_CTL(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_alpm.c

520

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_alpm.c

555

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_alpm.c

558

if (DISPLAY_VER(display) < 20 ||

sys/dev/pci/drm/i915/display/intel_alpm.c

571

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_alpm.c

574

if (DISPLAY_VER(display) < 20 || !intel_dp->alpm_dpcd)

sys/dev/pci/drm/i915/display/intel_alpm.c

579

intel_de_rmw(display, ALPM_CTL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_alpm.c

582

drm_dbg_kms(display->drm, "Disabling ALPM\n");

sys/dev/pci/drm/i915/display/intel_alpm.c

588

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_alpm.c

595

drm_err(display->drm, "Error reading ALPM status\n");

sys/dev/pci/drm/i915/display/intel_alpm.c

600

drm_dbg_kms(display->drm, "ALPM lock timeout error\n");

sys/dev/pci/drm/i915/display/intel_atomic.c

104

if (property == display->properties.broadcast_rgb) {

sys/dev/pci/drm/i915/display/intel_atomic.c

109

drm_dbg_atomic(display->drm, "Unknown property [PROP:%d:%s]\n",

sys/dev/pci/drm/i915/display/intel_atomic.c

63

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_atomic.c

67

if (property == display->properties.force_audio)

sys/dev/pci/drm/i915/display/intel_atomic.c

69

else if (property == display->properties.broadcast_rgb)

sys/dev/pci/drm/i915/display/intel_atomic.c

72

drm_dbg_atomic(display->drm,

sys/dev/pci/drm/i915/display/intel_atomic.c

95

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_atomic.c

99

if (property == display->properties.force_audio) {

sys/dev/pci/drm/i915/display/intel_audio.c

1012

if (DISPLAY_VER(display) == 10) {

sys/dev/pci/drm/i915/display/intel_audio.c

1015

} else if (DISPLAY_VER(display) == 9 || display->platform.broadwell) {

sys/dev/pci/drm/i915/display/intel_audio.c

1025

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_audio.c

1035

if ((display->platform.valleyview || display->platform.cherryview) &&

sys/dev/pci/drm/i915/display/intel_audio.c

1044

struct intel_display *display = to_intel_display(kdev);

sys/dev/pci/drm/i915/display/intel_audio.c

1050

wakeref = intel_display_power_get(display, POWER_DOMAIN_AUDIO_PLAYBACK);

sys/dev/pci/drm/i915/display/intel_audio.c

1052

if (display->audio.power_refcount++ == 0) {

sys/dev/pci/drm/i915/display/intel_audio.c

1053

if (DISPLAY_VER(display) >= 9) {

sys/dev/pci/drm/i915/display/intel_audio.c

1054

intel_de_write(display, AUD_FREQ_CNTRL,

sys/dev/pci/drm/i915/display/intel_audio.c

1055

display->audio.freq_cntrl);

sys/dev/pci/drm/i915/display/intel_audio.c

1056

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_audio.c

1058

display->audio.freq_cntrl);

sys/dev/pci/drm/i915/display/intel_audio.c

1062

if (display->platform.geminilake)

sys/dev/pci/drm/i915/display/intel_audio.c

1063

glk_force_audio_cdclk(display, true);

sys/dev/pci/drm/i915/display/intel_audio.c

1065

if (DISPLAY_VER(display) >= 10)

sys/dev/pci/drm/i915/display/intel_audio.c

1066

intel_de_rmw(display, AUD_PIN_BUF_CTL,

sys/dev/pci/drm/i915/display/intel_audio.c

1076

struct intel_display *display = to_intel_display(kdev);

sys/dev/pci/drm/i915/display/intel_audio.c

1080

if (--display->audio.power_refcount == 0)

sys/dev/pci/drm/i915/display/intel_audio.c

1081

if (display->platform.geminilake)

sys/dev/pci/drm/i915/display/intel_audio.c

1082

glk_force_audio_cdclk(display, false);

sys/dev/pci/drm/i915/display/intel_audio.c

1084

intel_display_power_put(display, POWER_DOMAIN_AUDIO_PLAYBACK, wakeref);

sys/dev/pci/drm/i915/display/intel_audio.c

1090

struct intel_display *display = to_intel_display(kdev);

sys/dev/pci/drm/i915/display/intel_audio.c

1093

if (DISPLAY_VER(display) < 9)

sys/dev/pci/drm/i915/display/intel_audio.c

1102

intel_de_rmw(display, HSW_AUD_CHICKENBIT,

sys/dev/pci/drm/i915/display/intel_audio.c

1107

intel_de_rmw(display, HSW_AUD_CHICKENBIT,

sys/dev/pci/drm/i915/display/intel_audio.c

1118

struct intel_display *display = to_intel_display(kdev);

sys/dev/pci/drm/i915/display/intel_audio.c

1120

if (drm_WARN_ON_ONCE(display->drm, !HAS_DDI(display)))

sys/dev/pci/drm/i915/display/intel_audio.c

1123

return display->cdclk.hw.cdclk;

sys/dev/pci/drm/i915/display/intel_audio.c

1135

static struct intel_audio_state *find_audio_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_audio.c

1143

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_audio.c

1144

cpu_transcoder >= ARRAY_SIZE(display->audio.state)))

sys/dev/pci/drm/i915/display/intel_audio.c

1147

audio_state = &display->audio.state[cpu_transcoder];

sys/dev/pci/drm/i915/display/intel_audio.c

1159

for_each_cpu_transcoder(display, cpu_transcoder) {

sys/dev/pci/drm/i915/display/intel_audio.c

1163

audio_state = &display->audio.state[cpu_transcoder];

sys/dev/pci/drm/i915/display/intel_audio.c

1177

struct intel_display *display = to_intel_display(kdev);

sys/dev/pci/drm/i915/display/intel_audio.c

1178

struct i915_audio_component *acomp = display->audio.component;

sys/dev/pci/drm/i915/display/intel_audio.c

1185

if (!HAS_DDI(display))

sys/dev/pci/drm/i915/display/intel_audio.c

1189

mutex_lock(&display->audio.mutex);

sys/dev/pci/drm/i915/display/intel_audio.c

1191

audio_state = find_audio_state(display, port, cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_audio.c

1193

drm_dbg_kms(display->drm, "Not valid for port %c\n",

sys/dev/pci/drm/i915/display/intel_audio.c

1211

mutex_unlock(&display->audio.mutex);

sys/dev/pci/drm/i915/display/intel_audio.c

1220

struct intel_display *display = to_intel_display(kdev);

sys/dev/pci/drm/i915/display/intel_audio.c

1224

mutex_lock(&display->audio.mutex);

sys/dev/pci/drm/i915/display/intel_audio.c

1226

audio_state = find_audio_state(display, port, cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_audio.c

1228

drm_dbg_kms(display->drm, "Not valid for port %c\n",

sys/dev/pci/drm/i915/display/intel_audio.c

1230

mutex_unlock(&display->audio.mutex);

sys/dev/pci/drm/i915/display/intel_audio.c

1242

mutex_unlock(&display->audio.mutex);

sys/dev/pci/drm/i915/display/intel_audio.c

1261

struct intel_display *display = to_intel_display(drv_kdev);

sys/dev/pci/drm/i915/display/intel_audio.c

1265

if (drm_WARN_ON(display->drm, acomp->base.ops || acomp->base.dev))

sys/dev/pci/drm/i915/display/intel_audio.c

1268

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_audio.c

1273

drm_modeset_lock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_audio.c

1279

display->audio.component = acomp;

sys/dev/pci/drm/i915/display/intel_audio.c

1280

drm_modeset_unlock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_audio.c

1288

struct intel_display *display = to_intel_display(drv_kdev);

sys/dev/pci/drm/i915/display/intel_audio.c

1291

drm_modeset_lock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_audio.c

1294

display->audio.component = NULL;

sys/dev/pci/drm/i915/display/intel_audio.c

1295

drm_modeset_unlock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_audio.c

1299

if (display->audio.power_refcount)

sys/dev/pci/drm/i915/display/intel_audio.c

1300

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_audio.c

1302

display->audio.power_refcount);

sys/dev/pci/drm/i915/display/intel_audio.c

1337

static void intel_audio_component_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_audio.c

1342

if (DISPLAY_VER(display) >= 9) {

sys/dev/pci/drm/i915/display/intel_audio.c

1343

aud_freq_init = intel_de_read(display, AUD_FREQ_CNTRL);

sys/dev/pci/drm/i915/display/intel_audio.c

1345

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_audio.c

1351

if ((display->platform.tigerlake || display->platform.rocketlake) &&

sys/dev/pci/drm/i915/display/intel_audio.c

1355

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_audio.c

1359

display->audio.freq_cntrl = aud_freq;

sys/dev/pci/drm/i915/display/intel_audio.c

1363

intel_audio_cdclk_change_post(display);

sys/dev/pci/drm/i915/display/intel_audio.c

1367

static void intel_audio_component_register(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_audio.c

1372

ret = component_add_typed(display->drm->dev,

sys/dev/pci/drm/i915/display/intel_audio.c

1376

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_audio.c

1382

display->audio.component_registered = true;

sys/dev/pci/drm/i915/display/intel_audio.c

1393

static void intel_audio_component_cleanup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_audio.c

1395

if (!display->audio.component_registered)

sys/dev/pci/drm/i915/display/intel_audio.c

1398

component_del(display->drm->dev, &intel_audio_component_bind_ops);

sys/dev/pci/drm/i915/display/intel_audio.c

1399

display->audio.component_registered = false;

sys/dev/pci/drm/i915/display/intel_audio.c

1408

void intel_audio_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_audio.c

1410

if (intel_lpe_audio_init(display) < 0)

sys/dev/pci/drm/i915/display/intel_audio.c

1411

intel_audio_component_init(display);

sys/dev/pci/drm/i915/display/intel_audio.c

1414

void intel_audio_register(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_audio.c

1416

if (!display->audio.lpe.platdev)

sys/dev/pci/drm/i915/display/intel_audio.c

1417

intel_audio_component_register(display);

sys/dev/pci/drm/i915/display/intel_audio.c

1424

void intel_audio_deinit(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_audio.c

1426

if (display->audio.lpe.platdev)

sys/dev/pci/drm/i915/display/intel_audio.c

1427

intel_lpe_audio_teardown(display);

sys/dev/pci/drm/i915/display/intel_audio.c

1429

intel_audio_component_cleanup(display);

sys/dev/pci/drm/i915/display/intel_audio.c

191

static bool needs_wa_14020863754(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_audio.c

193

return DISPLAY_VERx100(display) == 3000 ||

sys/dev/pci/drm/i915/display/intel_audio.c

194

DISPLAY_VERx100(display) == 2000 ||

sys/dev/pci/drm/i915/display/intel_audio.c

195

DISPLAY_VERx100(display) == 1401;

sys/dev/pci/drm/i915/display/intel_audio.c

201

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_audio.c

211

if (DISPLAY_VER(display) < 12 && adjusted_mode->crtc_clock > 148500)

sys/dev/pci/drm/i915/display/intel_audio.c

215

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_audio.c

221

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_audio.c

256

static int g4x_eld_buffer_size(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_audio.c

260

tmp = intel_de_read(display, G4X_AUD_CNTL_ST);

sys/dev/pci/drm/i915/display/intel_audio.c

268

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_audio.c

273

tmp = intel_de_read(display, G4X_AUD_CNTL_ST);

sys/dev/pci/drm/i915/display/intel_audio.c

277

intel_de_rmw(display, G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK, 0);

sys/dev/pci/drm/i915/display/intel_audio.c

279

eld_buffer_size = g4x_eld_buffer_size(display);

sys/dev/pci/drm/i915/display/intel_audio.c

283

eld[i] = intel_de_read(display, G4X_HDMIW_HDMIEDID);

sys/dev/pci/drm/i915/display/intel_audio.c

290

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_audio.c

294

intel_de_rmw(display, G4X_AUD_CNTL_ST,

sys/dev/pci/drm/i915/display/intel_audio.c

305

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_audio.c

312

intel_de_rmw(display, G4X_AUD_CNTL_ST,

sys/dev/pci/drm/i915/display/intel_audio.c

315

eld_buffer_size = g4x_eld_buffer_size(display);

sys/dev/pci/drm/i915/display/intel_audio.c

319

intel_de_write(display, G4X_HDMIW_HDMIEDID, eld[i]);

sys/dev/pci/drm/i915/display/intel_audio.c

321

intel_de_write(display, G4X_HDMIW_HDMIEDID, 0);

sys/dev/pci/drm/i915/display/intel_audio.c

323

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_audio.c

324

(intel_de_read(display, G4X_AUD_CNTL_ST) & G4X_ELD_ADDRESS_MASK) != 0);

sys/dev/pci/drm/i915/display/intel_audio.c

326

intel_de_rmw(display, G4X_AUD_CNTL_ST,

sys/dev/pci/drm/i915/display/intel_audio.c

334

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_audio.c

338

intel_de_rmw(display, HSW_AUD_CFG(cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_audio.c

352

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_audio.c

353

struct i915_audio_component *acomp = display->audio.component;

sys/dev/pci/drm/i915/display/intel_audio.c

361

tmp = intel_de_read(display, HSW_AUD_CFG(cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_audio.c

369

drm_dbg_kms(display->drm, "using N %d\n", n);

sys/dev/pci/drm/i915/display/intel_audio.c

375

drm_dbg_kms(display->drm, "using automatic N\n");

sys/dev/pci/drm/i915/display/intel_audio.c

378

intel_de_write(display, HSW_AUD_CFG(cpu_transcoder), tmp);

sys/dev/pci/drm/i915/display/intel_audio.c

384

tmp = intel_de_read(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_audio.c

387

intel_de_write(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);

sys/dev/pci/drm/i915/display/intel_audio.c

403

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_audio.c

406

if (!HAS_DP20(display))

sys/dev/pci/drm/i915/display/intel_audio.c

409

intel_de_rmw(display, AUD_DP_2DOT0_CTRL(trans), AUD_ENABLE_SDP_SPLIT,

sys/dev/pci/drm/i915/display/intel_audio.c

417

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_audio.c

421

mutex_lock(&display->audio.mutex);

sys/dev/pci/drm/i915/display/intel_audio.c

424

intel_de_rmw(display, HSW_AUD_CFG(cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_audio.c

433

intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD,

sys/dev/pci/drm/i915/display/intel_audio.c

440

intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD,

sys/dev/pci/drm/i915/display/intel_audio.c

443

if (needs_wa_14020863754(display))

sys/dev/pci/drm/i915/display/intel_audio.c

444

intel_de_rmw(display, AUD_CHICKENBIT_REG3, DACBE_DISABLE_MIN_HBLANK_FIX, 0);

sys/dev/pci/drm/i915/display/intel_audio.c

448

mutex_unlock(&display->audio.mutex);

sys/dev/pci/drm/i915/display/intel_audio.c

454

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_audio.c

466

cdclk = display->cdclk.hw.cdclk;

sys/dev/pci/drm/i915/display/intel_audio.c

472

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_audio.c

517

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_audio.c

522

if (DISPLAY_VER(display) < 11)

sys/dev/pci/drm/i915/display/intel_audio.c

525

val = intel_de_read(display, AUD_CONFIG_BE);

sys/dev/pci/drm/i915/display/intel_audio.c

527

if (DISPLAY_VER(display) == 11)

sys/dev/pci/drm/i915/display/intel_audio.c

529

else if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_audio.c

556

intel_de_write(display, AUD_CONFIG_BE, val);

sys/dev/pci/drm/i915/display/intel_audio.c

563

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_audio.c

567

mutex_lock(&display->audio.mutex);

sys/dev/pci/drm/i915/display/intel_audio.c

575

if (needs_wa_14020863754(display))

sys/dev/pci/drm/i915/display/intel_audio.c

576

intel_de_rmw(display, AUD_CHICKENBIT_REG3, 0, DACBE_DISABLE_MIN_HBLANK_FIX);

sys/dev/pci/drm/i915/display/intel_audio.c

579

intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD,

sys/dev/pci/drm/i915/display/intel_audio.c

585

intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD,

sys/dev/pci/drm/i915/display/intel_audio.c

596

mutex_unlock(&display->audio.mutex);

sys/dev/pci/drm/i915/display/intel_audio.c

603

static void ibx_audio_regs_init(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_audio.c

607

if (display->platform.valleyview || display->platform.cherryview) {

sys/dev/pci/drm/i915/display/intel_audio.c

612

} else if (HAS_PCH_CPT(display)) {

sys/dev/pci/drm/i915/display/intel_audio.c

617

} else if (HAS_PCH_IBX(display)) {

sys/dev/pci/drm/i915/display/intel_audio.c

629

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_audio.c

635

if (drm_WARN_ON(display->drm, port == PORT_A))

sys/dev/pci/drm/i915/display/intel_audio.c

638

ibx_audio_regs_init(display, pipe, &regs);

sys/dev/pci/drm/i915/display/intel_audio.c

640

mutex_lock(&display->audio.mutex);

sys/dev/pci/drm/i915/display/intel_audio.c

643

intel_de_rmw(display, regs.aud_config,

sys/dev/pci/drm/i915/display/intel_audio.c

652

intel_de_rmw(display, regs.aud_cntrl_st2,

sys/dev/pci/drm/i915/display/intel_audio.c

655

mutex_unlock(&display->audio.mutex);

sys/dev/pci/drm/i915/display/intel_audio.c

665

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_audio.c

671

if (drm_WARN_ON(display->drm, port == PORT_A))

sys/dev/pci/drm/i915/display/intel_audio.c

676

ibx_audio_regs_init(display, pipe, &regs);

sys/dev/pci/drm/i915/display/intel_audio.c

678

mutex_lock(&display->audio.mutex);

sys/dev/pci/drm/i915/display/intel_audio.c

681

intel_de_rmw(display, regs.aud_cntrl_st2,

sys/dev/pci/drm/i915/display/intel_audio.c

690

intel_de_rmw(display, regs.aud_config,

sys/dev/pci/drm/i915/display/intel_audio.c

698

mutex_unlock(&display->audio.mutex);

sys/dev/pci/drm/i915/display/intel_audio.c

705

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_audio.c

712

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_audio.c

741

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_audio.c

742

struct i915_audio_component *acomp = display->audio.component;

sys/dev/pci/drm/i915/display/intel_audio.c

752

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_audio.c

759

if (display->funcs.audio)

sys/dev/pci/drm/i915/display/intel_audio.c

760

display->funcs.audio->audio_codec_enable(encoder,

sys/dev/pci/drm/i915/display/intel_audio.c

764

mutex_lock(&display->audio.mutex);

sys/dev/pci/drm/i915/display/intel_audio.c

766

audio_state = &display->audio.state[cpu_transcoder];

sys/dev/pci/drm/i915/display/intel_audio.c

772

mutex_unlock(&display->audio.mutex);

sys/dev/pci/drm/i915/display/intel_audio.c

783

intel_lpe_audio_notify(display, cpu_transcoder, port, crtc_state->eld,

sys/dev/pci/drm/i915/display/intel_audio.c

801

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_audio.c

802

struct i915_audio_component *acomp = display->audio.component;

sys/dev/pci/drm/i915/display/intel_audio.c

812

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_audio.c

818

if (display->funcs.audio)

sys/dev/pci/drm/i915/display/intel_audio.c

819

display->funcs.audio->audio_codec_disable(encoder,

sys/dev/pci/drm/i915/display/intel_audio.c

823

mutex_lock(&display->audio.mutex);

sys/dev/pci/drm/i915/display/intel_audio.c

825

audio_state = &display->audio.state[cpu_transcoder];

sys/dev/pci/drm/i915/display/intel_audio.c

830

mutex_unlock(&display->audio.mutex);

sys/dev/pci/drm/i915/display/intel_audio.c

841

intel_lpe_audio_notify(display, cpu_transcoder, port, NULL, 0, false);

sys/dev/pci/drm/i915/display/intel_audio.c

847

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_audio.c

851

mutex_lock(&display->audio.mutex);

sys/dev/pci/drm/i915/display/intel_audio.c

853

audio_state = &display->audio.state[cpu_transcoder];

sys/dev/pci/drm/i915/display/intel_audio.c

858

mutex_unlock(&display->audio.mutex);

sys/dev/pci/drm/i915/display/intel_audio.c

864

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_audio.c

869

if (display->funcs.audio)

sys/dev/pci/drm/i915/display/intel_audio.c

870

display->funcs.audio->audio_codec_get_config(encoder, crtc_state);

sys/dev/pci/drm/i915/display/intel_audio.c

895

void intel_audio_hooks_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_audio.c

897

if (display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_audio.c

898

display->funcs.audio = &g4x_audio_funcs;

sys/dev/pci/drm/i915/display/intel_audio.c

899

else if (display->platform.valleyview || display->platform.cherryview ||

sys/dev/pci/drm/i915/display/intel_audio.c

900

HAS_PCH_CPT(display) || HAS_PCH_IBX(display))

sys/dev/pci/drm/i915/display/intel_audio.c

901

display->funcs.audio = &ibx_audio_funcs;

sys/dev/pci/drm/i915/display/intel_audio.c

902

else if (display->platform.haswell || DISPLAY_VER(display) >= 8)

sys/dev/pci/drm/i915/display/intel_audio.c

903

display->funcs.audio = &hsw_audio_funcs;

sys/dev/pci/drm/i915/display/intel_audio.c

911

void intel_audio_cdclk_change_pre(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_audio.c

913

if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/intel_audio.c

914

intel_de_rmw(display, AUD_TS_CDCLK_M, AUD_TS_CDCLK_M_EN, 0);

sys/dev/pci/drm/i915/display/intel_audio.c

923

void intel_audio_cdclk_change_post(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_audio.c

927

if (DISPLAY_VER(display) >= 13) {

sys/dev/pci/drm/i915/display/intel_audio.c

928

get_aud_ts_cdclk_m_n(display->cdclk.hw.ref,

sys/dev/pci/drm/i915/display/intel_audio.c

929

display->cdclk.hw.cdclk, &aud_ts);

sys/dev/pci/drm/i915/display/intel_audio.c

931

intel_de_write(display, AUD_TS_CDCLK_N, aud_ts.n);

sys/dev/pci/drm/i915/display/intel_audio.c

932

intel_de_write(display, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN);

sys/dev/pci/drm/i915/display/intel_audio.c

933

drm_dbg_kms(display->drm, "aud_ts_cdclk set to M=%u, N=%u\n",

sys/dev/pci/drm/i915/display/intel_audio.c

959

static void glk_force_audio_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_audio.c

967

crtc = intel_first_crtc(display);

sys/dev/pci/drm/i915/display/intel_audio.c

972

state = drm_atomic_state_alloc(display->drm);

sys/dev/pci/drm/i915/display/intel_audio.c

973

if (drm_WARN_ON(display->drm, !state))

sys/dev/pci/drm/i915/display/intel_audio.c

988

drm_WARN_ON(display->drm, ret);

sys/dev/pci/drm/i915/display/intel_audio.c

998

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_audio.h

16

void intel_audio_hooks_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_audio.h

28

void intel_audio_cdclk_change_pre(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_audio.h

29

void intel_audio_cdclk_change_post(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_audio.h

31

void intel_audio_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_audio.h

32

void intel_audio_register(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_audio.h

33

void intel_audio_deinit(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_backlight.c

100

if (display->params.invert_brightness > 0 ||

sys/dev/pci/drm/i915/display/intel_backlight.c

1001

display->drm->primary->index,

sys/dev/pci/drm/i915/display/intel_backlight.c

101

intel_has_quirk(display, QUIRK_INVERT_BRIGHTNESS)) {

sys/dev/pci/drm/i915/display/intel_backlight.c

1010

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

1019

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

1046

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1048

return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq),

sys/dev/pci/drm/i915/display/intel_backlight.c

1085

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1094

if (HAS_PCH_LPT_H(display))

sys/dev/pci/drm/i915/display/intel_backlight.c

1108

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

111

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1110

return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq),

sys/dev/pci/drm/i915/display/intel_backlight.c

1124

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1127

if (display->platform.pineview)

sys/dev/pci/drm/i915/display/intel_backlight.c

1128

clock = KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq);

sys/dev/pci/drm/i915/display/intel_backlight.c

1130

clock = KHz(display->cdclk.hw.cdclk);

sys/dev/pci/drm/i915/display/intel_backlight.c

114

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] set backlight PWM = %d\n",

sys/dev/pci/drm/i915/display/intel_backlight.c

1142

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1145

if (display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_backlight.c

1146

clock = KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq);

sys/dev/pci/drm/i915/display/intel_backlight.c

1148

clock = KHz(display->cdclk.hw.cdclk);

sys/dev/pci/drm/i915/display/intel_backlight.c

1160

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1163

if ((intel_de_read(display, CBR1_VLV) & CBR_PWM_CLOCK_MUX_SELECT) == 0) {

sys/dev/pci/drm/i915/display/intel_backlight.c

1164

if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_backlight.c

1170

clock = KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq);

sys/dev/pci/drm/i915/display/intel_backlight.c

1179

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1183

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

1188

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

1198

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1204

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

121

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1211

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

1224

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1228

drm_WARN_ON(display->drm, panel->backlight.pwm_level_max == 0);

sys/dev/pci/drm/i915/display/intel_backlight.c

1239

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

124

drm_WARN_ON_ONCE(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

1250

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1255

if (HAS_PCH_LPT(display))

sys/dev/pci/drm/i915/display/intel_backlight.c

1256

alt = intel_de_read(display, SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY;

sys/dev/pci/drm/i915/display/intel_backlight.c

1258

alt = intel_de_read(display, SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY;

sys/dev/pci/drm/i915/display/intel_backlight.c

1261

pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);

sys/dev/pci/drm/i915/display/intel_backlight.c

1264

pch_ctl2 = intel_de_read(display, BLC_PWM_PCH_CTL2);

sys/dev/pci/drm/i915/display/intel_backlight.c

1267

cpu_ctl2 = intel_de_read(display, BLC_PWM_CPU_CTL2);

sys/dev/pci/drm/i915/display/intel_backlight.c

1279

cpu_mode = panel->backlight.pwm_enabled && HAS_PCH_LPT(display) &&

sys/dev/pci/drm/i915/display/intel_backlight.c

1286

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

1291

intel_de_write(display, BLC_PWM_PCH_CTL1,

sys/dev/pci/drm/i915/display/intel_backlight.c

1294

intel_de_write(display, BLC_PWM_CPU_CTL2,

sys/dev/pci/drm/i915/display/intel_backlight.c

1298

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

1307

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1311

pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);

sys/dev/pci/drm/i915/display/intel_backlight.c

1314

pch_ctl2 = intel_de_read(display, BLC_PWM_PCH_CTL2);

sys/dev/pci/drm/i915/display/intel_backlight.c

1325

cpu_ctl2 = intel_de_read(display, BLC_PWM_CPU_CTL2);

sys/dev/pci/drm/i915/display/intel_backlight.c

1329

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

1338

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1342

ctl = intel_de_read(display, BLC_PWM_CTL);

sys/dev/pci/drm/i915/display/intel_backlight.c

1344

if (DISPLAY_VER(display) == 2 || display->platform.i915gm || display->platform.i945gm)

sys/dev/pci/drm/i915/display/intel_backlight.c

1347

if (display->platform.pineview)

sys/dev/pci/drm/i915/display/intel_backlight.c

135

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1371

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

138

drm_WARN_ON_ONCE(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

1380

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1384

ctl2 = intel_de_read(display, BLC_PWM_CTL2);

sys/dev/pci/drm/i915/display/intel_backlight.c

1388

ctl = intel_de_read(display, BLC_PWM_CTL);

sys/dev/pci/drm/i915/display/intel_backlight.c

1404

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

141

if (display->params.invert_brightness > 0 ||

sys/dev/pci/drm/i915/display/intel_backlight.c

1413

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1417

if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))

sys/dev/pci/drm/i915/display/intel_backlight.c

142

(display->params.invert_brightness == 0 &&

sys/dev/pci/drm/i915/display/intel_backlight.c

1420

ctl2 = intel_de_read(display, VLV_BLC_PWM_CTL2(pipe));

sys/dev/pci/drm/i915/display/intel_backlight.c

1423

ctl = intel_de_read(display, VLV_BLC_PWM_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_backlight.c

143

intel_has_quirk(display, QUIRK_INVERT_BRIGHTNESS)))

sys/dev/pci/drm/i915/display/intel_backlight.c

1436

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

1446

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1452

pwm_ctl = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_backlight.c

1457

val = intel_de_read(display, UTIL_PIN_CTL);

sys/dev/pci/drm/i915/display/intel_backlight.c

1464

intel_de_read(display, BXT_BLC_PWM_FREQ(panel->backlight.controller));

sys/dev/pci/drm/i915/display/intel_backlight.c

1476

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

1484

static int cnp_num_backlight_controllers(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_backlight.c

1486

if (INTEL_PCH_TYPE(display) >= PCH_MTL)

sys/dev/pci/drm/i915/display/intel_backlight.c

1489

if (INTEL_PCH_TYPE(display) >= PCH_DG1)

sys/dev/pci/drm/i915/display/intel_backlight.c

1492

if (INTEL_PCH_TYPE(display) >= PCH_ICP)

sys/dev/pci/drm/i915/display/intel_backlight.c

1498

static bool cnp_backlight_controller_is_valid(struct intel_display *display, int controller)

sys/dev/pci/drm/i915/display/intel_backlight.c

1500

if (controller < 0 || controller >= cnp_num_backlight_controllers(display))

sys/dev/pci/drm/i915/display/intel_backlight.c

1504

INTEL_PCH_TYPE(display) >= PCH_ICP &&

sys/dev/pci/drm/i915/display/intel_backlight.c

1505

INTEL_PCH_TYPE(display) <= PCH_ADP)

sys/dev/pci/drm/i915/display/intel_backlight.c

1506

return intel_de_read(display, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;

sys/dev/pci/drm/i915/display/intel_backlight.c

1514

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

152

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1523

if (!cnp_backlight_controller_is_valid(display, panel->backlight.controller)) {

sys/dev/pci/drm/i915/display/intel_backlight.c

1524

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

1531

pwm_ctl = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_backlight.c

1536

intel_de_read(display, BXT_BLC_PWM_FREQ(panel->backlight.controller));

sys/dev/pci/drm/i915/display/intel_backlight.c

154

return intel_de_read(display, BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK;

sys/dev/pci/drm/i915/display/intel_backlight.c

1548

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

1559

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1566

panel->backlight.pwm = pwm_get(display->drm->dev,

sys/dev/pci/drm/i915/display/intel_backlight.c

1570

panel->backlight.pwm = pwm_get(display->drm->dev,

sys/dev/pci/drm/i915/display/intel_backlight.c

1576

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

159

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1596

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

161

return intel_de_read(display, BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;

sys/dev/pci/drm/i915/display/intel_backlight.c

1610

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

166

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1676

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1682

mutex_lock(&display->backlight.lock);

sys/dev/pci/drm/i915/display/intel_backlight.c

1686

mutex_unlock(&display->backlight.lock);

sys/dev/pci/drm/i915/display/intel_backlight.c

1691

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1696

if (intel_has_quirk(display, QUIRK_BACKLIGHT_PRESENT)) {

sys/dev/pci/drm/i915/display/intel_backlight.c

1697

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

170

val = intel_de_read(display, BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;

sys/dev/pci/drm/i915/display/intel_backlight.c

1701

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

1709

if (drm_WARN_ON(display->drm, !panel->backlight.funcs))

sys/dev/pci/drm/i915/display/intel_backlight.c

171

if (DISPLAY_VER(display) < 4)

sys/dev/pci/drm/i915/display/intel_backlight.c

1713

mutex_lock(&display->backlight.lock);

sys/dev/pci/drm/i915/display/intel_backlight.c

1715

mutex_unlock(&display->backlight.lock);

sys/dev/pci/drm/i915/display/intel_backlight.c

1718

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

1726

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

175

struct pci_dev *pdev = display->drm->pdev;

sys/dev/pci/drm/i915/display/intel_backlight.c

1837

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1843

if (display->platform.geminilake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/intel_backlight.c

1845

} else if (INTEL_PCH_TYPE(display) >= PCH_CNP) {

sys/dev/pci/drm/i915/display/intel_backlight.c

1847

} else if (INTEL_PCH_TYPE(display) >= PCH_LPT_H) {

sys/dev/pci/drm/i915/display/intel_backlight.c

1848

if (HAS_PCH_LPT(display))

sys/dev/pci/drm/i915/display/intel_backlight.c

1852

} else if (HAS_PCH_SPLIT(display)) {

sys/dev/pci/drm/i915/display/intel_backlight.c

1854

} else if (display->platform.valleyview || display->platform.cherryview) {

sys/dev/pci/drm/i915/display/intel_backlight.c

1860

} else if (DISPLAY_VER(display) == 4) {

sys/dev/pci/drm/i915/display/intel_backlight.c

187

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

1870

if (!intel_has_quirk(display, QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK))

sys/dev/pci/drm/i915/display/intel_backlight.c

189

if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))

sys/dev/pci/drm/i915/display/intel_backlight.c

192

return intel_de_read(display, VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK;

sys/dev/pci/drm/i915/display/intel_backlight.c

197

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

200

return intel_de_read(display, BXT_BLC_PWM_DUTY(panel->backlight.controller));

sys/dev/pci/drm/i915/display/intel_backlight.c

219

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

222

val = intel_de_read(display, BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK;

sys/dev/pci/drm/i915/display/intel_backlight.c

223

intel_de_write(display, BLC_PWM_PCH_CTL2, val | level);

sys/dev/pci/drm/i915/display/intel_backlight.c

229

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

232

tmp = intel_de_read(display, BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;

sys/dev/pci/drm/i915/display/intel_backlight.c

233

intel_de_write(display, BLC_PWM_CPU_CTL, tmp | level);

sys/dev/pci/drm/i915/display/intel_backlight.c

239

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

243

if (drm_WARN_ON(display->drm, panel->backlight.pwm_level_max == 0))

sys/dev/pci/drm/i915/display/intel_backlight.c

247

struct pci_dev *pdev = display->drm->pdev;

sys/dev/pci/drm/i915/display/intel_backlight.c

255

if (DISPLAY_VER(display) == 4) {

sys/dev/pci/drm/i915/display/intel_backlight.c

262

tmp = intel_de_read(display, BLC_PWM_CTL) & ~mask;

sys/dev/pci/drm/i915/display/intel_backlight.c

263

intel_de_write(display, BLC_PWM_CTL, tmp | level);

sys/dev/pci/drm/i915/display/intel_backlight.c

269

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

273

tmp = intel_de_read(display, VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK;

sys/dev/pci/drm/i915/display/intel_backlight.c

274

intel_de_write(display, VLV_BLC_PWM_CTL(pipe), tmp | level);

sys/dev/pci/drm/i915/display/intel_backlight.c

280

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

283

intel_de_write(display, BXT_BLC_PWM_DUTY(panel->backlight.controller), level);

sys/dev/pci/drm/i915/display/intel_backlight.c

301

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

304

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] set backlight level = %d\n",

sys/dev/pci/drm/i915/display/intel_backlight.c

317

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

330

mutex_lock(&display->backlight.lock);

sys/dev/pci/drm/i915/display/intel_backlight.c

332

drm_WARN_ON(display->drm, panel->backlight.max == 0);

sys/dev/pci/drm/i915/display/intel_backlight.c

346

mutex_unlock(&display->backlight.lock);

sys/dev/pci/drm/i915/display/intel_backlight.c

352

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

365

tmp = intel_de_read(display, BLC_PWM_CPU_CTL2);

sys/dev/pci/drm/i915/display/intel_backlight.c

367

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] CPU backlight was enabled, disabling\n",

sys/dev/pci/drm/i915/display/intel_backlight.c

369

intel_de_write(display, BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE);

sys/dev/pci/drm/i915/display/intel_backlight.c

372

intel_de_rmw(display, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_backlight.c

378

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

382

intel_de_rmw(display, BLC_PWM_CPU_CTL2, BLM_PWM_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_backlight.c

384

intel_de_rmw(display, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_backlight.c

395

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

399

intel_de_rmw(display, BLC_PWM_CTL2, BLM_PWM_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_backlight.c

405

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

410

intel_de_rmw(display, VLV_BLC_PWM_CTL2(pipe), BLM_PWM_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_backlight.c

416

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

421

intel_de_rmw(display, BXT_BLC_PWM_CTL(panel->backlight.controller),

sys/dev/pci/drm/i915/display/intel_backlight.c

425

intel_de_rmw(display, UTIL_PIN_CTL, UTIL_PIN_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_backlight.c

431

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

436

intel_de_rmw(display, BXT_BLC_PWM_CTL(panel->backlight.controller),

sys/dev/pci/drm/i915/display/intel_backlight.c

457

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

469

if (display->drm->switch_power_state == DRM_SWITCH_POWER_CHANGING) {

sys/dev/pci/drm/i915/display/intel_backlight.c

470

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Skipping backlight disable on vga switch\n",

sys/dev/pci/drm/i915/display/intel_backlight.c

475

mutex_lock(&display->backlight.lock);

sys/dev/pci/drm/i915/display/intel_backlight.c

482

mutex_unlock(&display->backlight.lock);

sys/dev/pci/drm/i915/display/intel_backlight.c

489

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

493

pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);

sys/dev/pci/drm/i915/display/intel_backlight.c

495

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

499

intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1);

sys/dev/pci/drm/i915/display/intel_backlight.c

502

if (HAS_PCH_LPT(display))

sys/dev/pci/drm/i915/display/intel_backlight.c

503

intel_de_rmw(display, SOUTH_CHICKEN2, LPT_PWM_GRANULARITY,

sys/dev/pci/drm/i915/display/intel_backlight.c

507

intel_de_rmw(display, SOUTH_CHICKEN1, SPT_PWM_GRANULARITY,

sys/dev/pci/drm/i915/display/intel_backlight.c

512

intel_de_write(display, BLC_PWM_PCH_CTL2, pch_ctl2);

sys/dev/pci/drm/i915/display/intel_backlight.c

519

if (HAS_PCH_LPT(display))

sys/dev/pci/drm/i915/display/intel_backlight.c

522

intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1);

sys/dev/pci/drm/i915/display/intel_backlight.c

523

intel_de_posting_read(display, BLC_PWM_PCH_CTL1);

sys/dev/pci/drm/i915/display/intel_backlight.c

524

intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE);

sys/dev/pci/drm/i915/display/intel_backlight.c

534

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

539

cpu_ctl2 = intel_de_read(display, BLC_PWM_CPU_CTL2);

sys/dev/pci/drm/i915/display/intel_backlight.c

541

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

545

intel_de_write(display, BLC_PWM_CPU_CTL2, cpu_ctl2);

sys/dev/pci/drm/i915/display/intel_backlight.c

548

pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);

sys/dev/pci/drm/i915/display/intel_backlight.c

550

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

554

intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1);

sys/dev/pci/drm/i915/display/intel_backlight.c

561

intel_de_write(display, BLC_PWM_CPU_CTL2, cpu_ctl2);

sys/dev/pci/drm/i915/display/intel_backlight.c

562

intel_de_posting_read(display, BLC_PWM_CPU_CTL2);

sys/dev/pci/drm/i915/display/intel_backlight.c

563

intel_de_write(display, BLC_PWM_CPU_CTL2, cpu_ctl2 | BLM_PWM_ENABLE);

sys/dev/pci/drm/i915/display/intel_backlight.c

569

intel_de_write(display, BLC_PWM_PCH_CTL2, pch_ctl2);

sys/dev/pci/drm/i915/display/intel_backlight.c

575

intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1);

sys/dev/pci/drm/i915/display/intel_backlight.c

576

intel_de_posting_read(display, BLC_PWM_PCH_CTL1);

sys/dev/pci/drm/i915/display/intel_backlight.c

577

intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE);

sys/dev/pci/drm/i915/display/intel_backlight.c

584

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

588

ctl = intel_de_read(display, BLC_PWM_CTL);

sys/dev/pci/drm/i915/display/intel_backlight.c

590

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

593

intel_de_write(display, BLC_PWM_CTL, 0);

sys/dev/pci/drm/i915/display/intel_backlight.c

603

if (display->platform.pineview && panel->backlight.active_low_pwm)

sys/dev/pci/drm/i915/display/intel_backlight.c

606

intel_de_write(display, BLC_PWM_CTL, ctl);

sys/dev/pci/drm/i915/display/intel_backlight.c

607

intel_de_posting_read(display, BLC_PWM_CTL);

sys/dev/pci/drm/i915/display/intel_backlight.c

617

if (DISPLAY_VER(display) == 2)

sys/dev/pci/drm/i915/display/intel_backlight.c

618

intel_de_write(display, BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE);

sys/dev/pci/drm/i915/display/intel_backlight.c

625

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

630

ctl2 = intel_de_read(display, BLC_PWM_CTL2);

sys/dev/pci/drm/i915/display/intel_backlight.c

632

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

636

intel_de_write(display, BLC_PWM_CTL2, ctl2);

sys/dev/pci/drm/i915/display/intel_backlight.c

644

intel_de_write(display, BLC_PWM_CTL, ctl);

sys/dev/pci/drm/i915/display/intel_backlight.c

651

intel_de_write(display, BLC_PWM_CTL2, ctl2);

sys/dev/pci/drm/i915/display/intel_backlight.c

652

intel_de_posting_read(display, BLC_PWM_CTL2);

sys/dev/pci/drm/i915/display/intel_backlight.c

653

intel_de_write(display, BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE);

sys/dev/pci/drm/i915/display/intel_backlight.c

662

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

667

ctl2 = intel_de_read(display, VLV_BLC_PWM_CTL2(pipe));

sys/dev/pci/drm/i915/display/intel_backlight.c

669

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

673

intel_de_write(display, VLV_BLC_PWM_CTL2(pipe), ctl2);

sys/dev/pci/drm/i915/display/intel_backlight.c

677

intel_de_write(display, VLV_BLC_PWM_CTL(pipe), ctl);

sys/dev/pci/drm/i915/display/intel_backlight.c

685

intel_de_write(display, VLV_BLC_PWM_CTL2(pipe), ctl2);

sys/dev/pci/drm/i915/display/intel_backlight.c

686

intel_de_posting_read(display, VLV_BLC_PWM_CTL2(pipe));

sys/dev/pci/drm/i915/display/intel_backlight.c

687

intel_de_write(display, VLV_BLC_PWM_CTL2(pipe), ctl2 | BLM_PWM_ENABLE);

sys/dev/pci/drm/i915/display/intel_backlight.c

694

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

701

val = intel_de_read(display, UTIL_PIN_CTL);

sys/dev/pci/drm/i915/display/intel_backlight.c

703

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

707

intel_de_write(display, UTIL_PIN_CTL, val);

sys/dev/pci/drm/i915/display/intel_backlight.c

713

intel_de_write(display, UTIL_PIN_CTL,

sys/dev/pci/drm/i915/display/intel_backlight.c

717

pwm_ctl = intel_de_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller));

sys/dev/pci/drm/i915/display/intel_backlight.c

719

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

723

intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller),

sys/dev/pci/drm/i915/display/intel_backlight.c

727

intel_de_write(display, BXT_BLC_PWM_FREQ(panel->backlight.controller),

sys/dev/pci/drm/i915/display/intel_backlight.c

736

intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);

sys/dev/pci/drm/i915/display/intel_backlight.c

737

intel_de_posting_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller));

sys/dev/pci/drm/i915/display/intel_backlight.c

738

intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller),

sys/dev/pci/drm/i915/display/intel_backlight.c

746

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

750

pwm_ctl = intel_de_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller));

sys/dev/pci/drm/i915/display/intel_backlight.c

752

drm_dbg_kms(display->drm, "backlight already enabled\n");

sys/dev/pci/drm/i915/display/intel_backlight.c

754

intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller),

sys/dev/pci/drm/i915/display/intel_backlight.c

758

intel_de_write(display, BXT_BLC_PWM_FREQ(panel->backlight.controller),

sys/dev/pci/drm/i915/display/intel_backlight.c

767

intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);

sys/dev/pci/drm/i915/display/intel_backlight.c

768

intel_de_posting_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller));

sys/dev/pci/drm/i915/display/intel_backlight.c

769

intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller),

sys/dev/pci/drm/i915/display/intel_backlight.c

814

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

821

drm_dbg_kms(display->drm, "pipe %c\n", pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_backlight.c

823

mutex_lock(&display->backlight.lock);

sys/dev/pci/drm/i915/display/intel_backlight.c

827

mutex_unlock(&display->backlight.lock);

sys/dev/pci/drm/i915/display/intel_backlight.c

833

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

837

mutex_lock(&display->backlight.lock);

sys/dev/pci/drm/i915/display/intel_backlight.c

842

mutex_unlock(&display->backlight.lock);

sys/dev/pci/drm/i915/display/intel_backlight.c

844

drm_dbg_kms(display->drm, "get backlight PWM = %d\n", val);

sys/dev/pci/drm/i915/display/intel_backlight.c

863

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

870

mutex_lock(&display->backlight.lock);

sys/dev/pci/drm/i915/display/intel_backlight.c

872

drm_WARN_ON(display->drm, panel->backlight.max == 0);

sys/dev/pci/drm/i915/display/intel_backlight.c

880

mutex_unlock(&display->backlight.lock);

sys/dev/pci/drm/i915/display/intel_backlight.c

886

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

889

drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL);

sys/dev/pci/drm/i915/display/intel_backlight.c

891

drm_dbg_kms(display->drm, "updating intel_backlight, brightness=%d/%d\n",

sys/dev/pci/drm/i915/display/intel_backlight.c

912

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_backlight.c

92

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

920

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

923

with_intel_display_rpm(display) {

sys/dev/pci/drm/i915/display/intel_backlight.c

926

drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL);

sys/dev/pci/drm/i915/display/intel_backlight.c

932

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_backlight.c

945

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_backlight.c

95

drm_WARN_ON(display->drm, panel->backlight.pwm_level_max == 0);

sys/dev/pci/drm/i915/display/intel_backlight.c

961

drm_info(display->drm,

sys/dev/pci/drm/i915/display/intel_backlight.c

97

if (display->params.invert_brightness < 0)

sys/dev/pci/drm/i915/display/intel_bios.c

1009

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1017

parse_lfp_backlight(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

1025

backlight_data = bdb_find_section(display, BDB_LFP_BACKLIGHT);

sys/dev/pci/drm/i915/display/intel_bios.c

1030

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1040

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1048

if (display->vbt.version >= 191) {

sys/dev/pci/drm/i915/display/intel_bios.c

1059

if (display->vbt.version >= 234) {

sys/dev/pci/drm/i915/display/intel_bios.c

1066

if (display->vbt.version >= 236)

sys/dev/pci/drm/i915/display/intel_bios.c

1075

drm_warn(display->drm, "Brightness min level > 255\n");

sys/dev/pci/drm/i915/display/intel_bios.c

1087

if (display->vbt.version >= 239)

sys/dev/pci/drm/i915/display/intel_bios.c

1093

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1104

parse_sdvo_lvds_data(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

1111

index = display->params.vbt_sdvo_panel_type;

sys/dev/pci/drm/i915/display/intel_bios.c

1113

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1121

sdvo_lvds_options = bdb_find_section(display, BDB_SDVO_LVDS_OPTIONS);

sys/dev/pci/drm/i915/display/intel_bios.c

1128

dtd = bdb_find_section(display, BDB_SDVO_LVDS_DTD);

sys/dev/pci/drm/i915/display/intel_bios.c

1139

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1149

fill_detail_timing_data(display, panel_fixed_mode, &dtd->dtd[index]);

sys/dev/pci/drm/i915/display/intel_bios.c

1153

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1158

static int intel_bios_ssc_frequency(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

1161

switch (DISPLAY_VER(display)) {

sys/dev/pci/drm/i915/display/intel_bios.c

1173

parse_general_features(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_bios.c

1177

general = bdb_find_section(display, BDB_GENERAL_FEATURES);

sys/dev/pci/drm/i915/display/intel_bios.c

1181

display->vbt.int_tv_support = general->int_tv_support;

sys/dev/pci/drm/i915/display/intel_bios.c

1183

if (display->vbt.version >= 155 &&

sys/dev/pci/drm/i915/display/intel_bios.c

1184

(HAS_DDI(display) || display->platform.valleyview))

sys/dev/pci/drm/i915/display/intel_bios.c

1185

display->vbt.int_crt_support = general->int_crt_support;

sys/dev/pci/drm/i915/display/intel_bios.c

1186

display->vbt.lvds_use_ssc = general->enable_ssc;

sys/dev/pci/drm/i915/display/intel_bios.c

1187

display->vbt.lvds_ssc_freq =

sys/dev/pci/drm/i915/display/intel_bios.c

1188

intel_bios_ssc_frequency(display, general->ssc_freq);

sys/dev/pci/drm/i915/display/intel_bios.c

1189

display->vbt.display_clock_mode = general->display_clock_mode;

sys/dev/pci/drm/i915/display/intel_bios.c

1190

display->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;

sys/dev/pci/drm/i915/display/intel_bios.c

1191

if (display->vbt.version >= 181) {

sys/dev/pci/drm/i915/display/intel_bios.c

1192

display->vbt.orientation = general->rotate_180 ?

sys/dev/pci/drm/i915/display/intel_bios.c

1196

display->vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;

sys/dev/pci/drm/i915/display/intel_bios.c

1199

if (display->vbt.version >= 249 && general->afc_startup_config) {

sys/dev/pci/drm/i915/display/intel_bios.c

1200

display->vbt.override_afc_startup = true;

sys/dev/pci/drm/i915/display/intel_bios.c

1201

display->vbt.override_afc_startup_val = general->afc_startup_config == 1 ? 0 : 7;

sys/dev/pci/drm/i915/display/intel_bios.c

1204

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1206

display->vbt.int_tv_support,

sys/dev/pci/drm/i915/display/intel_bios.c

1207

display->vbt.int_crt_support,

sys/dev/pci/drm/i915/display/intel_bios.c

1208

display->vbt.lvds_use_ssc,

sys/dev/pci/drm/i915/display/intel_bios.c

1209

display->vbt.lvds_ssc_freq,

sys/dev/pci/drm/i915/display/intel_bios.c

1210

display->vbt.display_clock_mode,

sys/dev/pci/drm/i915/display/intel_bios.c

1211

display->vbt.fdi_rx_polarity_inverted);

sys/dev/pci/drm/i915/display/intel_bios.c

1221

parse_sdvo_device_mapping(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_bios.c

1230

if (!IS_DISPLAY_VER(display, 3, 7)) {

sys/dev/pci/drm/i915/display/intel_bios.c

1231

drm_dbg_kms(display->drm, "Skipping SDVO device mapping\n");

sys/dev/pci/drm/i915/display/intel_bios.c

1235

list_for_each_entry(devdata, &display->vbt.display_devices, node) {

sys/dev/pci/drm/i915/display/intel_bios.c

1250

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1254

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1260

mapping = &display->vbt.sdvo_mappings[child->dvo_port - 1];

sys/dev/pci/drm/i915/display/intel_bios.c

1268

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1274

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1281

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1290

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1296

parse_driver_features(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_bios.c

1300

driver = bdb_find_section(display, BDB_DRIVER_FEATURES);

sys/dev/pci/drm/i915/display/intel_bios.c

1304

if (DISPLAY_VER(display) >= 5) {

sys/dev/pci/drm/i915/display/intel_bios.c

1311

display->vbt.int_lvds_support = 0;

sys/dev/pci/drm/i915/display/intel_bios.c

1324

if (display->vbt.version >= 134 &&

sys/dev/pci/drm/i915/display/intel_bios.c

1327

display->vbt.int_lvds_support = 0;

sys/dev/pci/drm/i915/display/intel_bios.c

1332

parse_panel_driver_features(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

1337

driver = bdb_find_section(display, BDB_DRIVER_FEATURES);

sys/dev/pci/drm/i915/display/intel_bios.c

1341

if (display->vbt.version < 228) {

sys/dev/pci/drm/i915/display/intel_bios.c

1342

drm_dbg_kms(display->drm, "DRRS State Enabled:%d\n",

sys/dev/pci/drm/i915/display/intel_bios.c

1366

parse_power_conservation_features(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

1374

if (display->vbt.version < 228)

sys/dev/pci/drm/i915/display/intel_bios.c

1377

power = bdb_find_section(display, BDB_LFP_POWER);

sys/dev/pci/drm/i915/display/intel_bios.c

1400

if (display->vbt.version >= 232)

sys/dev/pci/drm/i915/display/intel_bios.c

1403

if (display->vbt.version >= 233)

sys/dev/pci/drm/i915/display/intel_bios.c

1419

parse_edp(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

1426

edp = bdb_find_section(display, BDB_EDP);

sys/dev/pci/drm/i915/display/intel_bios.c

1448

if (display->vbt.version >= 224) {

sys/dev/pci/drm/i915/display/intel_bios.c

1463

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1481

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1501

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

152

bdb_find_section(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

1521

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1527

if (display->vbt.version >= 173) {

sys/dev/pci/drm/i915/display/intel_bios.c

1531

if (display->params.edp_vswing) {

sys/dev/pci/drm/i915/display/intel_bios.c

1533

display->params.edp_vswing == 1;

sys/dev/pci/drm/i915/display/intel_bios.c

1543

if (display->vbt.version >= 244)

sys/dev/pci/drm/i915/display/intel_bios.c

1547

if (display->vbt.version >= 251)

sys/dev/pci/drm/i915/display/intel_bios.c

1553

parse_psr(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

1560

psr = bdb_find_section(display, BDB_PSR);

sys/dev/pci/drm/i915/display/intel_bios.c

1562

drm_dbg_kms(display->drm, "No PSR BDB found.\n");

sys/dev/pci/drm/i915/display/intel_bios.c

157

list_for_each_entry(entry, &display->vbt.bdb_blocks, node) {

sys/dev/pci/drm/i915/display/intel_bios.c

1576

if (display->vbt.version >= 205 &&

sys/dev/pci/drm/i915/display/intel_bios.c

1577

(DISPLAY_VER(display) >= 9 && !display->platform.broxton)) {

sys/dev/pci/drm/i915/display/intel_bios.c

1589

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1609

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1622

if (display->vbt.version >= 226) {

sys/dev/pci/drm/i915/display/intel_bios.c

1648

static void parse_dsi_backlight_ports(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

1652

enum port port_bc = DISPLAY_VER(display) >= 11 ? PORT_B : PORT_C;

sys/dev/pci/drm/i915/display/intel_bios.c

1654

if (!panel->vbt.dsi.config->dual_link || display->vbt.version < 197) {

sys/dev/pci/drm/i915/display/intel_bios.c

1694

parse_mipi_config(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

1704

if (!intel_bios_is_dsi_present(display, &port))

sys/dev/pci/drm/i915/display/intel_bios.c

1710

start = bdb_find_section(display, BDB_MIPI_CONFIG);

sys/dev/pci/drm/i915/display/intel_bios.c

1712

drm_dbg_kms(display->drm, "No MIPI config BDB found");

sys/dev/pci/drm/i915/display/intel_bios.c

1716

drm_dbg_kms(display->drm, "Found MIPI Config block, panel index = %d\n",

sys/dev/pci/drm/i915/display/intel_bios.c

1737

parse_dsi_backlight_ports(display, panel, port);

sys/dev/pci/drm/i915/display/intel_bios.c

1769

find_panel_sequence_block(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

1787

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1801

drm_err(display->drm, "Invalid sequence block\n");

sys/dev/pci/drm/i915/display/intel_bios.c

1813

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1819

static int goto_next_sequence(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

1850

drm_err(display->drm, "Unknown operation byte\n");

sys/dev/pci/drm/i915/display/intel_bios.c

1858

static int goto_next_sequence_v3(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

1870

drm_err(display->drm, "Too small sequence size\n");

sys/dev/pci/drm/i915/display/intel_bios.c

1887

drm_err(display->drm, "Invalid sequence size\n");

sys/dev/pci/drm/i915/display/intel_bios.c

1897

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1920

drm_err(display->drm, "Unknown operation byte %u\n",

sys/dev/pci/drm/i915/display/intel_bios.c

1933

static int get_init_otp_deassert_fragment_len(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

1939

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

1968

static void vlv_fixup_mipi_sequences(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

1986

len = get_init_otp_deassert_fragment_len(display, panel);

sys/dev/pci/drm/i915/display/intel_bios.c

1990

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2023

static void icl_fixup_mipi_sequences(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

2028

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2036

static void fixup_mipi_sequences(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

2039

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_bios.c

2040

icl_fixup_mipi_sequences(display, panel);

sys/dev/pci/drm/i915/display/intel_bios.c

2041

else if (display->platform.valleyview)

sys/dev/pci/drm/i915/display/intel_bios.c

2042

vlv_fixup_mipi_sequences(display, panel);

sys/dev/pci/drm/i915/display/intel_bios.c

2046

parse_mipi_sequence(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

2060

sequence = bdb_find_section(display, BDB_MIPI_SEQUENCE);

sys/dev/pci/drm/i915/display/intel_bios.c

2062

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2069

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

207

static size_t lfp_data_min_size(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_bios.c

2075

drm_dbg_kms(display->drm, "Found MIPI sequence block v%u\n",

sys/dev/pci/drm/i915/display/intel_bios.c

2078

seq_data = find_panel_sequence_block(display, sequence, panel_type, &seq_size);

sys/dev/pci/drm/i915/display/intel_bios.c

2093

drm_err(display->drm, "Unknown sequence %u\n",

sys/dev/pci/drm/i915/display/intel_bios.c

2100

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2106

index = goto_next_sequence_v3(display, data, index, seq_size);

sys/dev/pci/drm/i915/display/intel_bios.c

2108

index = goto_next_sequence(display, data, index, seq_size);

sys/dev/pci/drm/i915/display/intel_bios.c

2110

drm_err(display->drm, "Invalid sequence %u\n",

sys/dev/pci/drm/i915/display/intel_bios.c

212

ptrs = bdb_find_section(display, BDB_LFP_DATA_PTRS);

sys/dev/pci/drm/i915/display/intel_bios.c

2120

fixup_mipi_sequences(display, panel);

sys/dev/pci/drm/i915/display/intel_bios.c

2122

drm_dbg_kms(display->drm, "MIPI related VBT parsing complete\n");

sys/dev/pci/drm/i915/display/intel_bios.c

2131

parse_compression_parameters(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_bios.c

2138

if (display->vbt.version < 198)

sys/dev/pci/drm/i915/display/intel_bios.c

2141

params = bdb_find_section(display, BDB_COMPRESSION_PARAMETERS);

sys/dev/pci/drm/i915/display/intel_bios.c

2145

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2152

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2158

list_for_each_entry(devdata, &display->vbt.display_devices, node) {

sys/dev/pci/drm/i915/display/intel_bios.c

2165

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2171

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2183

static u8 translate_iboost(struct intel_display *display, u8 val)

sys/dev/pci/drm/i915/display/intel_bios.c

2188

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2245

static u8 map_ddc_pin(struct intel_display *display, u8 vbt_pin)

sys/dev/pci/drm/i915/display/intel_bios.c

2250

if (INTEL_PCH_TYPE(display) >= PCH_MTL || display->platform.alderlake_p) {

sys/dev/pci/drm/i915/display/intel_bios.c

2253

} else if (display->platform.alderlake_s) {

sys/dev/pci/drm/i915/display/intel_bios.c

2256

} else if (INTEL_PCH_TYPE(display) >= PCH_DG1) {

sys/dev/pci/drm/i915/display/intel_bios.c

2258

} else if (display->platform.rocketlake && INTEL_PCH_TYPE(display) == PCH_TGP) {

sys/dev/pci/drm/i915/display/intel_bios.c

2261

} else if (HAS_PCH_TGP(display) && DISPLAY_VER(display) == 9) {

sys/dev/pci/drm/i915/display/intel_bios.c

2264

} else if (INTEL_PCH_TYPE(display) >= PCH_ICP) {

sys/dev/pci/drm/i915/display/intel_bios.c

2267

} else if (HAS_PCH_CNP(display)) {

sys/dev/pci/drm/i915/display/intel_bios.c

2280

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2338

static enum port dvo_port_to_port(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

2392

if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/intel_bios.c

2397

else if (display->platform.alderlake_s)

sys/dev/pci/drm/i915/display/intel_bios.c

2402

else if (display->platform.dg1 || display->platform.rocketlake)

sys/dev/pci/drm/i915/display/intel_bios.c

2415

dsi_dvo_port_to_port(struct intel_display *display, u8 dvo_port)

sys/dev/pci/drm/i915/display/intel_bios.c

2421

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_bios.c

2432

struct intel_display *display = devdata->display;

sys/dev/pci/drm/i915/display/intel_bios.c

2436

port = dvo_port_to_port(display, child->dvo_port);

sys/dev/pci/drm/i915/display/intel_bios.c

2437

if (port == PORT_NONE && DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_bios.c

2438

port = dsi_dvo_port_to_port(display, child->dvo_port);

sys/dev/pci/drm/i915/display/intel_bios.c

2502

if (!devdata || devdata->display->vbt.version < 216)

sys/dev/pci/drm/i915/display/intel_bios.c

2505

if (devdata->display->vbt.version >= 230)

sys/dev/pci/drm/i915/display/intel_bios.c

2513

if (!devdata || devdata->display->vbt.version < 244)

sys/dev/pci/drm/i915/display/intel_bios.c

2523

if (!devdata || devdata->display->vbt.version < 263)

sys/dev/pci/drm/i915/display/intel_bios.c

2535

struct intel_display *display = devdata->display;

sys/dev/pci/drm/i915/display/intel_bios.c

2538

if (port != PORT_A || DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_bios.c

2546

drm_dbg_kms(display->drm, "VBT claims port A supports DVI%s, ignoring\n",

sys/dev/pci/drm/i915/display/intel_bios.c

2556

struct intel_display *display = devdata->display;

sys/dev/pci/drm/i915/display/intel_bios.c

2566

if (display->platform.broadwell && devdata->child.hdmi_level_shifter_value > 9) {

sys/dev/pci/drm/i915/display/intel_bios.c

2567

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2616

return devdata && HAS_LSPCON(devdata->display) && devdata->child.lspcon;

sys/dev/pci/drm/i915/display/intel_bios.c

2622

if (!devdata || devdata->display->vbt.version < 158 ||

sys/dev/pci/drm/i915/display/intel_bios.c

2623

DISPLAY_VER(devdata->display) >= 14)

sys/dev/pci/drm/i915/display/intel_bios.c

2631

if (!devdata || devdata->display->vbt.version < 204)

sys/dev/pci/drm/i915/display/intel_bios.c

2653

static bool is_port_valid(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_bios.c

2660

if (port == PORT_F && display->platform.icelake)

sys/dev/pci/drm/i915/display/intel_bios.c

2661

return display->platform.icelake_port_f;

sys/dev/pci/drm/i915/display/intel_bios.c

2668

struct intel_display *display = devdata->display;

sys/dev/pci/drm/i915/display/intel_bios.c

2688

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2698

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2705

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2712

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2718

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2724

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2732

drm_WARN(display->drm, child->use_vbt_vswing,

sys/dev/pci/drm/i915/display/intel_bios.c

2739

struct intel_display *display = devdata->display;

sys/dev/pci/drm/i915/display/intel_bios.c

2746

if (!is_port_valid(display, port)) {

sys/dev/pci/drm/i915/display/intel_bios.c

2747

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2757

static bool has_ddi_port_info(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_bios.c

2759

return DISPLAY_VER(display) >= 5 || display->platform.g4x;

sys/dev/pci/drm/i915/display/intel_bios.c

2762

static void parse_ddi_ports(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_bios.c

2766

if (!has_ddi_port_info(display))

sys/dev/pci/drm/i915/display/intel_bios.c

2769

list_for_each_entry(devdata, &display->vbt.display_devices, node)

sys/dev/pci/drm/i915/display/intel_bios.c

2772

list_for_each_entry(devdata, &display->vbt.display_devices, node)

sys/dev/pci/drm/i915/display/intel_bios.c

2800

static bool child_device_size_valid(struct intel_display *display, int size)

sys/dev/pci/drm/i915/display/intel_bios.c

2804

expected_size = child_device_expected_size(display->vbt.version);

sys/dev/pci/drm/i915/display/intel_bios.c

2807

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2809

display->vbt.version, expected_size);

sys/dev/pci/drm/i915/display/intel_bios.c

2814

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2816

size, expected_size, display->vbt.version);

sys/dev/pci/drm/i915/display/intel_bios.c

2820

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2830

parse_general_definitions(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_bios.c

2839

defs = bdb_find_section(display, BDB_GENERAL_DEFINITIONS);

sys/dev/pci/drm/i915/display/intel_bios.c

2841

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2848

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2855

drm_dbg_kms(display->drm, "crt_ddc_bus_pin: %d\n", bus_pin);

sys/dev/pci/drm/i915/display/intel_bios.c

2856

if (intel_gmbus_is_valid_pin(display, bus_pin))

sys/dev/pci/drm/i915/display/intel_bios.c

2857

display->vbt.crt_ddc_pin = bus_pin;

sys/dev/pci/drm/i915/display/intel_bios.c

2859

if (!child_device_size_valid(display, defs->child_dev_size))

sys/dev/pci/drm/i915/display/intel_bios.c

2870

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2878

devdata->display = display;

sys/dev/pci/drm/i915/display/intel_bios.c

2888

list_add_tail(&devdata->node, &display->vbt.display_devices);

sys/dev/pci/drm/i915/display/intel_bios.c

2891

if (list_empty(&display->vbt.display_devices))

sys/dev/pci/drm/i915/display/intel_bios.c

2892

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2898

init_vbt_defaults(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_bios.c

2900

display->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC;

sys/dev/pci/drm/i915/display/intel_bios.c

2903

display->vbt.int_tv_support = 1;

sys/dev/pci/drm/i915/display/intel_bios.c

2904

display->vbt.int_crt_support = 1;

sys/dev/pci/drm/i915/display/intel_bios.c

2907

display->vbt.int_lvds_support = 1;

sys/dev/pci/drm/i915/display/intel_bios.c

2910

display->vbt.lvds_use_ssc = 1;

sys/dev/pci/drm/i915/display/intel_bios.c

2915

display->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(display,

sys/dev/pci/drm/i915/display/intel_bios.c

2916

!HAS_PCH_SPLIT(display));

sys/dev/pci/drm/i915/display/intel_bios.c

2917

drm_dbg_kms(display->drm, "Set default to SSC at %d kHz\n",

sys/dev/pci/drm/i915/display/intel_bios.c

2918

display->vbt.lvds_ssc_freq);

sys/dev/pci/drm/i915/display/intel_bios.c

2934

init_vbt_missing_defaults(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_bios.c

2936

unsigned int ports = DISPLAY_RUNTIME_INFO(display)->port_mask;

sys/dev/pci/drm/i915/display/intel_bios.c

2939

if (!HAS_DDI(display) && !display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_bios.c

2945

enum phy phy = intel_port_to_phy(display, port);

sys/dev/pci/drm/i915/display/intel_bios.c

2951

if (intel_phy_is_tc(display, phy))

sys/dev/pci/drm/i915/display/intel_bios.c

2959

devdata->display = display;

sys/dev/pci/drm/i915/display/intel_bios.c

2978

list_add_tail(&devdata->node, &display->vbt.display_devices);

sys/dev/pci/drm/i915/display/intel_bios.c

2980

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

2986

display->vbt.version = 155;

sys/dev/pci/drm/i915/display/intel_bios.c

3013

bool intel_bios_is_valid_vbt(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

3023

drm_dbg_kms(display->drm, "VBT header incomplete\n");

sys/dev/pci/drm/i915/display/intel_bios.c

3028

drm_dbg_kms(display->drm, "VBT invalid signature\n");

sys/dev/pci/drm/i915/display/intel_bios.c

3033

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

3044

drm_dbg_kms(display->drm, "BDB header incomplete\n");

sys/dev/pci/drm/i915/display/intel_bios.c

3050

drm_dbg_kms(display->drm, "BDB incomplete\n");

sys/dev/pci/drm/i915/display/intel_bios.c

3057

static struct vbt_header *firmware_get_vbt(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

3062

const char *name = display->params.vbt_firmware;

sys/dev/pci/drm/i915/display/intel_bios.c

3068

ret = request_firmware(&fw, name, display->drm->dev);

sys/dev/pci/drm/i915/display/intel_bios.c

3070

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

3076

if (intel_bios_is_valid_vbt(display, fw->data, fw->size)) {

sys/dev/pci/drm/i915/display/intel_bios.c

3079

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

3085

drm_dbg_kms(display->drm, "Invalid VBT firmware \"%s\"\n",

sys/dev/pci/drm/i915/display/intel_bios.c

3094

static struct vbt_header *oprom_get_vbt(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

3113

drm_dbg_kms(display->drm, "VBT header incomplete\n");

sys/dev/pci/drm/i915/display/intel_bios.c

3121

drm_dbg_kms(display->drm, "VBT incomplete (vbt_size overflows)\n");

sys/dev/pci/drm/i915/display/intel_bios.c

3131

if (!intel_bios_is_valid_vbt(display, vbt, vbt_size))

sys/dev/pci/drm/i915/display/intel_bios.c

3134

drm_dbg_kms(display->drm, "Found valid VBT in %s\n", type);

sys/dev/pci/drm/i915/display/intel_bios.c

3150

static const struct vbt_header *intel_bios_get_vbt(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

3153

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_bios.c

3156

vbt = firmware_get_vbt(display, sizep);

sys/dev/pci/drm/i915/display/intel_bios.c

3159

vbt = intel_opregion_get_vbt(display, sizep);

sys/dev/pci/drm/i915/display/intel_bios.c

3165

if (!vbt && display->platform.dgfx)

sys/dev/pci/drm/i915/display/intel_bios.c

3166

with_intel_display_rpm(display)

sys/dev/pci/drm/i915/display/intel_bios.c

3167

vbt = oprom_get_vbt(display, intel_rom_spi(i915), sizep, "SPI flash");

sys/dev/pci/drm/i915/display/intel_bios.c

3170

with_intel_display_rpm(display)

sys/dev/pci/drm/i915/display/intel_bios.c

3171

vbt = oprom_get_vbt(display, intel_rom_pci(i915), sizep, "PCI ROM");

sys/dev/pci/drm/i915/display/intel_bios.c

3184

void intel_bios_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_bios.c

3189

INIT_LIST_HEAD(&display->vbt.display_devices);

sys/dev/pci/drm/i915/display/intel_bios.c

3190

INIT_LIST_HEAD(&display->vbt.bdb_blocks);

sys/dev/pci/drm/i915/display/intel_bios.c

3192

if (!HAS_DISPLAY(display)) {

sys/dev/pci/drm/i915/display/intel_bios.c

3193

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

3198

init_vbt_defaults(display);

sys/dev/pci/drm/i915/display/intel_bios.c

3200

vbt = intel_bios_get_vbt(display, NULL);

sys/dev/pci/drm/i915/display/intel_bios.c

3206

display->vbt.version = bdb->version;

sys/dev/pci/drm/i915/display/intel_bios.c

3208

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

3211

display->vbt.version);

sys/dev/pci/drm/i915/display/intel_bios.c

3213

init_bdb_blocks(display, bdb);

sys/dev/pci/drm/i915/display/intel_bios.c

3216

parse_general_features(display);

sys/dev/pci/drm/i915/display/intel_bios.c

3217

parse_general_definitions(display);

sys/dev/pci/drm/i915/display/intel_bios.c

3218

parse_driver_features(display);

sys/dev/pci/drm/i915/display/intel_bios.c

3221

parse_compression_parameters(display);

sys/dev/pci/drm/i915/display/intel_bios.c

3225

drm_info(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

3227

init_vbt_missing_defaults(display);

sys/dev/pci/drm/i915/display/intel_bios.c

3231

parse_sdvo_device_mapping(display);

sys/dev/pci/drm/i915/display/intel_bios.c

3232

parse_ddi_ports(display);

sys/dev/pci/drm/i915/display/intel_bios.c

3237

static void intel_bios_init_panel(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

3245

drm_WARN_ON(display->drm, !use_fallback);

sys/dev/pci/drm/i915/display/intel_bios.c

3249

panel->vbt.panel_type = get_panel_type(display, devdata,

sys/dev/pci/drm/i915/display/intel_bios.c

3252

drm_WARN_ON(display->drm, use_fallback);

sys/dev/pci/drm/i915/display/intel_bios.c

3258

parse_panel_options(display, panel);

sys/dev/pci/drm/i915/display/intel_bios.c

3259

parse_generic_dtd(display, panel);

sys/dev/pci/drm/i915/display/intel_bios.c

3260

parse_lfp_data(display, panel);

sys/dev/pci/drm/i915/display/intel_bios.c

3261

parse_lfp_backlight(display, panel);

sys/dev/pci/drm/i915/display/intel_bios.c

3262

parse_sdvo_lvds_data(display, panel);

sys/dev/pci/drm/i915/display/intel_bios.c

3263

parse_panel_driver_features(display, panel);

sys/dev/pci/drm/i915/display/intel_bios.c

3264

parse_power_conservation_features(display, panel);

sys/dev/pci/drm/i915/display/intel_bios.c

3265

parse_edp(display, panel);

sys/dev/pci/drm/i915/display/intel_bios.c

3266

parse_psr(display, panel);

sys/dev/pci/drm/i915/display/intel_bios.c

3267

parse_mipi_config(display, panel);

sys/dev/pci/drm/i915/display/intel_bios.c

3268

parse_mipi_sequence(display, panel);

sys/dev/pci/drm/i915/display/intel_bios.c

3271

void intel_bios_init_panel_early(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

3275

intel_bios_init_panel(display, panel, devdata, NULL, false);

sys/dev/pci/drm/i915/display/intel_bios.c

3278

void intel_bios_init_panel_late(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

3283

intel_bios_init_panel(display, panel, devdata, drm_edid, true);

sys/dev/pci/drm/i915/display/intel_bios.c

3290

void intel_bios_driver_remove(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_bios.c

3295

list_for_each_entry_safe(devdata, nd, &display->vbt.display_devices,

sys/dev/pci/drm/i915/display/intel_bios.c

3302

list_for_each_entry_safe(entry, ne, &display->vbt.bdb_blocks, node) {

sys/dev/pci/drm/i915/display/intel_bios.c

3331

bool intel_bios_is_tv_present(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_bios.c

3335

if (!display->vbt.int_tv_support)

sys/dev/pci/drm/i915/display/intel_bios.c

3338

if (list_empty(&display->vbt.display_devices))

sys/dev/pci/drm/i915/display/intel_bios.c

3341

list_for_each_entry(devdata, &display->vbt.display_devices, node) {

sys/dev/pci/drm/i915/display/intel_bios.c

3373

bool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin)

sys/dev/pci/drm/i915/display/intel_bios.c

3377

if (list_empty(&display->vbt.display_devices))

sys/dev/pci/drm/i915/display/intel_bios.c

3380

list_for_each_entry(devdata, &display->vbt.display_devices, node) {

sys/dev/pci/drm/i915/display/intel_bios.c

3391

if (intel_gmbus_is_valid_pin(display, child->i2c_pin))

sys/dev/pci/drm/i915/display/intel_bios.c

3407

return intel_opregion_vbt_present(display);

sys/dev/pci/drm/i915/display/intel_bios.c

3420

bool intel_bios_is_port_present(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_bios.c

3424

if (WARN_ON(!has_ddi_port_info(display)))

sys/dev/pci/drm/i915/display/intel_bios.c

3427

if (!is_port_valid(display, port))

sys/dev/pci/drm/i915/display/intel_bios.c

3430

list_for_each_entry(devdata, &display->vbt.display_devices, node) {

sys/dev/pci/drm/i915/display/intel_bios.c

3433

if (dvo_port_to_port(display, child->dvo_port) == port)

sys/dev/pci/drm/i915/display/intel_bios.c

3469

bool intel_bios_is_dsi_present(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

3474

list_for_each_entry(devdata, &display->vbt.display_devices, node) {

sys/dev/pci/drm/i915/display/intel_bios.c

3481

if (dsi_dvo_port_to_port(display, dvo_port) == PORT_NONE) {

sys/dev/pci/drm/i915/display/intel_bios.c

3482

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

3489

*port = dsi_dvo_port_to_port(display, dvo_port);

sys/dev/pci/drm/i915/display/intel_bios.c

3500

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_bios.c

3514

drm_dbg_kms(display->drm, "VBT: Unsupported BPC %d for DCS\n",

sys/dev/pci/drm/i915/display/intel_bios.c

3535

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

3543

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

3568

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_bios.c

3571

list_for_each_entry(devdata, &display->vbt.display_devices, node) {

sys/dev/pci/drm/i915/display/intel_bios.c

3577

if (dsi_dvo_port_to_port(display, child->dvo_port) == encoder->port) {

sys/dev/pci/drm/i915/display/intel_bios.c

3637

static enum aux_ch map_aux_ch(struct intel_display *display, u8 aux_channel)

sys/dev/pci/drm/i915/display/intel_bios.c

3642

if (DISPLAY_VER(display) >= 13) {

sys/dev/pci/drm/i915/display/intel_bios.c

3645

} else if (display->platform.alderlake_s) {

sys/dev/pci/drm/i915/display/intel_bios.c

3648

} else if (display->platform.dg1 || display->platform.rocketlake) {

sys/dev/pci/drm/i915/display/intel_bios.c

3661

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

367

static void *generate_lfp_data_ptrs(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

3673

return map_aux_ch(devdata->display, devdata->child.aux_channel);

sys/dev/pci/drm/i915/display/intel_bios.c

3678

struct intel_display *display;

sys/dev/pci/drm/i915/display/intel_bios.c

3685

display = devdata->display;

sys/dev/pci/drm/i915/display/intel_bios.c

3688

list_for_each_entry(devdata, &display->vbt.display_devices, node) {

sys/dev/pci/drm/i915/display/intel_bios.c

3699

if (!devdata || devdata->display->vbt.version < 196 || !devdata->child.iboost)

sys/dev/pci/drm/i915/display/intel_bios.c

3702

return translate_iboost(devdata->display, devdata->child.dp_iboost_level);

sys/dev/pci/drm/i915/display/intel_bios.c

3707

if (!devdata || devdata->display->vbt.version < 196 || !devdata->child.iboost)

sys/dev/pci/drm/i915/display/intel_bios.c

3710

return translate_iboost(devdata->display, devdata->child.hdmi_iboost_level);

sys/dev/pci/drm/i915/display/intel_bios.c

3718

return map_ddc_pin(devdata->display, devdata->child.ddc_pin);

sys/dev/pci/drm/i915/display/intel_bios.c

3723

return devdata->display->vbt.version >= 195 && devdata->child.dp_usb_type_c;

sys/dev/pci/drm/i915/display/intel_bios.c

3728

return devdata->display->vbt.version >= 209 && devdata->child.tbt;

sys/dev/pci/drm/i915/display/intel_bios.c

3742

intel_bios_encoder_data_lookup(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_bios.c

3746

list_for_each_entry(devdata, &display->vbt.display_devices, node) {

sys/dev/pci/drm/i915/display/intel_bios.c

3754

void intel_bios_for_each_encoder(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

3755

void (*func)(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

3760

list_for_each_entry(devdata, &display->vbt.display_devices, node)

sys/dev/pci/drm/i915/display/intel_bios.c

3761

func(display, devdata);

sys/dev/pci/drm/i915/display/intel_bios.c

3766

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/intel_bios.c

3770

vbt = intel_bios_get_vbt(display, &vbt_size);

sys/dev/pci/drm/i915/display/intel_bios.c

3782

void intel_bios_debugfs_register(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_bios.c

3784

debugfs_create_file("i915_vbt", 0444, display->drm->debugfs_root,

sys/dev/pci/drm/i915/display/intel_bios.c

3785

display, &intel_bios_vbt_fops);

sys/dev/pci/drm/i915/display/intel_bios.c

381

if (display->vbt.version < 155)

sys/dev/pci/drm/i915/display/intel_bios.c

390

drm_dbg_kms(display->drm, "Generating LFP data table pointers\n");

sys/dev/pci/drm/i915/display/intel_bios.c

458

init_bdb_block(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

471

temp_block = generate_lfp_data_ptrs(display, bdb);

sys/dev/pci/drm/i915/display/intel_bios.c

478

drm_WARN(display->drm, min_size == 0,

sys/dev/pci/drm/i915/display/intel_bios.c

502

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

508

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

514

list_add_tail(&entry->node, &display->vbt.bdb_blocks);

sys/dev/pci/drm/i915/display/intel_bios.c

517

static void init_bdb_blocks(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

527

min_size = lfp_data_min_size(display);

sys/dev/pci/drm/i915/display/intel_bios.c

529

init_bdb_block(display, bdb, section_id, min_size);

sys/dev/pci/drm/i915/display/intel_bios.c

534

fill_detail_timing_data(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

577

drm_dbg_kms(display->drm, "reducing hsync_end %d->%d\n",

sys/dev/pci/drm/i915/display/intel_bios.c

582

drm_dbg_kms(display->drm, "reducing vsync_end %d->%d\n",

sys/dev/pci/drm/i915/display/intel_bios.c

627

static int opregion_get_panel_type(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

631

return intel_opregion_get_panel_type(display);

sys/dev/pci/drm/i915/display/intel_bios.c

634

static int vbt_get_panel_type(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

640

lfp_options = bdb_find_section(display, BDB_LFP_OPTIONS);

sys/dev/pci/drm/i915/display/intel_bios.c

646

drm_dbg_kms(display->drm, "Invalid VBT panel type 0x%x\n",

sys/dev/pci/drm/i915/display/intel_bios.c

654

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

660

static int pnpid_get_panel_type(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

679

p = drm_dbg_printer(display->drm, DRM_UT_KMS, "EDID");

sys/dev/pci/drm/i915/display/intel_bios.c

682

ptrs = bdb_find_section(display, BDB_LFP_DATA_PTRS);

sys/dev/pci/drm/i915/display/intel_bios.c

686

data = bdb_find_section(display, BDB_LFP_DATA);

sys/dev/pci/drm/i915/display/intel_bios.c

710

static int fallback_get_panel_type(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

724

static int get_panel_type(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

73

struct intel_display *display;

sys/dev/pci/drm/i915/display/intel_bios.c

730

int (*get_panel_type)(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

755

panel_types[i].panel_type = panel_types[i].get_panel_type(display, devdata,

sys/dev/pci/drm/i915/display/intel_bios.c

758

drm_WARN_ON(display->drm, panel_types[i].panel_type > 0xf &&

sys/dev/pci/drm/i915/display/intel_bios.c

762

drm_dbg_kms(display->drm, "Panel type (%s): %d\n",

sys/dev/pci/drm/i915/display/intel_bios.c

777

drm_dbg_kms(display->drm, "Selected panel type (%s): %d\n",

sys/dev/pci/drm/i915/display/intel_bios.c

795

parse_panel_options(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

802

lfp_options = bdb_find_section(display, BDB_LFP_OPTIONS);

sys/dev/pci/drm/i915/display/intel_bios.c

826

drm_dbg_kms(display->drm, "DRRS supported mode is static\n");

sys/dev/pci/drm/i915/display/intel_bios.c

830

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

835

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

842

parse_lfp_panel_dtd(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

860

fill_detail_timing_data(display, panel_fixed_mode, panel_dvo_timing);

sys/dev/pci/drm/i915/display/intel_bios.c

864

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

876

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

883

parse_lfp_data(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

893

ptrs = bdb_find_section(display, BDB_LFP_DATA_PTRS);

sys/dev/pci/drm/i915/display/intel_bios.c

897

data = bdb_find_section(display, BDB_LFP_DATA);

sys/dev/pci/drm/i915/display/intel_bios.c

902

parse_lfp_panel_dtd(display, panel, data, ptrs);

sys/dev/pci/drm/i915/display/intel_bios.c

906

p = drm_dbg_printer(display->drm, DRM_UT_KMS, "Panel");

sys/dev/pci/drm/i915/display/intel_bios.c

913

drm_dbg_kms(display->drm, "Panel name: %.*s\n",

sys/dev/pci/drm/i915/display/intel_bios.c

917

if (display->vbt.version >= 188) {

sys/dev/pci/drm/i915/display/intel_bios.c

920

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.c

927

parse_generic_dtd(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.c

943

if (display->vbt.version < 229)

sys/dev/pci/drm/i915/display/intel_bios.c

946

generic_dtd = bdb_find_section(display, BDB_GENERIC_DTD);

sys/dev/pci/drm/i915/display/intel_bios.c

951

drm_err(display->drm, "GDTD size %u is too small.\n",

sys/dev/pci/drm/i915/display/intel_bios.c

956

drm_err(display->drm, "Unexpected GDTD size %u\n",

sys/dev/pci/drm/i915/display/intel_bios.c

964

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_bios.h

100

void intel_bios_for_each_encoder(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.h

101

void (*func)(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.h

104

void intel_bios_debugfs_register(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_bios.h

53

void intel_bios_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_bios.h

54

void intel_bios_init_panel_early(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.h

57

void intel_bios_init_panel_late(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.h

62

void intel_bios_driver_remove(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_bios.h

63

bool intel_bios_is_valid_vbt(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bios.h

65

bool intel_bios_is_tv_present(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_bios.h

66

bool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin);

sys/dev/pci/drm/i915/display/intel_bios.h

67

bool intel_bios_is_port_present(struct intel_display *display, enum port port);

sys/dev/pci/drm/i915/display/intel_bios.h

68

bool intel_bios_is_dsi_present(struct intel_display *display, enum port *port);

sys/dev/pci/drm/i915/display/intel_bios.h

74

intel_bios_encoder_data_lookup(struct intel_display *display, enum port port);

sys/dev/pci/drm/i915/display/intel_bw.c

1008

static void icl_force_disable_sagv(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

1011

unsigned int qgv_points = icl_max_bw_qgv_point_mask(display, 0);

sys/dev/pci/drm/i915/display/intel_bw.c

1012

unsigned int psf_points = icl_max_bw_psf_gv_point_mask(display);

sys/dev/pci/drm/i915/display/intel_bw.c

1014

bw_state->qgv_points_mask = icl_prepare_qgv_points_mask(display,

sys/dev/pci/drm/i915/display/intel_bw.c

1018

drm_dbg_kms(display->drm, "Forcing SAGV disable: mask 0x%x\n",

sys/dev/pci/drm/i915/display/intel_bw.c

1021

icl_pcode_restrict_qgv_points(display, bw_state->qgv_points_mask);

sys/dev/pci/drm/i915/display/intel_bw.c

1026

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_bw.c

1044

drm_dbg_kms(display->drm, "Restricting QGV points: 0x%x -> 0x%x\n",

sys/dev/pci/drm/i915/display/intel_bw.c

1053

icl_pcode_restrict_qgv_points(display, new_mask);

sys/dev/pci/drm/i915/display/intel_bw.c

1058

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_bw.c

1076

drm_dbg_kms(display->drm, "Relaxing QGV points: 0x%x -> 0x%x\n",

sys/dev/pci/drm/i915/display/intel_bw.c

1085

icl_pcode_restrict_qgv_points(display, new_mask);

sys/dev/pci/drm/i915/display/intel_bw.c

1088

static int mtl_find_qgv_points(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

1094

unsigned int num_qgv_points = display->bw.max[0].num_qgv_points;

sys/dev/pci/drm/i915/display/intel_bw.c

1108

if (!intel_bw_can_enable_sagv(display, new_bw_state)) {

sys/dev/pci/drm/i915/display/intel_bw.c

1110

drm_dbg_kms(display->drm, "No SAGV, use UINT_MAX as peak bw.");

sys/dev/pci/drm/i915/display/intel_bw.c

1120

tgl_max_bw_index(display, num_active_planes, i);

sys/dev/pci/drm/i915/display/intel_bw.c

1123

if (bw_index >= ARRAY_SIZE(display->bw.max))

sys/dev/pci/drm/i915/display/intel_bw.c

1126

max_data_rate = display->bw.max[bw_index].deratedbw[i];

sys/dev/pci/drm/i915/display/intel_bw.c

1133

qgv_peak_bw = display->bw.max[bw_index].peakbw[i];

sys/dev/pci/drm/i915/display/intel_bw.c

1136

drm_dbg_kms(display->drm, "QGV point %d: max bw %d required %d qgv_peak_bw: %d\n",

sys/dev/pci/drm/i915/display/intel_bw.c

1140

drm_dbg_kms(display->drm, "Matching peaks QGV bw: %d for required data rate: %d\n",

sys/dev/pci/drm/i915/display/intel_bw.c

1148

drm_dbg_kms(display->drm, "No QGV points for bw %d for display configuration(%d active planes).\n",

sys/dev/pci/drm/i915/display/intel_bw.c

1159

static int icl_find_qgv_points(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

1165

unsigned int num_psf_gv_points = display->bw.max[0].num_psf_gv_points;

sys/dev/pci/drm/i915/display/intel_bw.c

1166

unsigned int num_qgv_points = display->bw.max[0].num_qgv_points;

sys/dev/pci/drm/i915/display/intel_bw.c

117

static int icl_pcode_read_qgv_point_info(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

1177

unsigned int max_data_rate = icl_qgv_bw(display,

sys/dev/pci/drm/i915/display/intel_bw.c

1182

drm_dbg_kms(display->drm, "QGV point %d: max bw %d required %d\n",

sys/dev/pci/drm/i915/display/intel_bw.c

1187

unsigned int max_data_rate = adl_psf_bw(display, i);

sys/dev/pci/drm/i915/display/intel_bw.c

1192

drm_dbg_kms(display->drm, "PSF GV point %d: max bw %d"

sys/dev/pci/drm/i915/display/intel_bw.c

1203

drm_dbg_kms(display->drm, "No QGV points provide sufficient memory"

sys/dev/pci/drm/i915/display/intel_bw.c

1210

drm_dbg_kms(display->drm, "No PSF GV points provide sufficient memory"

sys/dev/pci/drm/i915/display/intel_bw.c

1221

if (!intel_bw_can_enable_sagv(display, new_bw_state)) {

sys/dev/pci/drm/i915/display/intel_bw.c

1222

qgv_points = icl_max_bw_qgv_point_mask(display, num_active_planes);

sys/dev/pci/drm/i915/display/intel_bw.c

1223

drm_dbg_kms(display->drm, "No SAGV, using single QGV point mask 0x%x\n",

sys/dev/pci/drm/i915/display/intel_bw.c

1231

new_bw_state->qgv_points_mask = icl_prepare_qgv_points_mask(display,

sys/dev/pci/drm/i915/display/intel_bw.c

1247

static int intel_bw_check_qgv_points(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

125

ret = intel_pcode_read(display->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |

sys/dev/pci/drm/i915/display/intel_bw.c

1251

unsigned int data_rate = intel_bw_data_rate(display, new_bw_state);

sys/dev/pci/drm/i915/display/intel_bw.c

1253

intel_bw_num_active_planes(display, new_bw_state);

sys/dev/pci/drm/i915/display/intel_bw.c

1257

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_bw.c

1258

return mtl_find_qgv_points(display, data_rate, num_active_planes,

sys/dev/pci/drm/i915/display/intel_bw.c

1261

return icl_find_qgv_points(display, data_rate, num_active_planes,

sys/dev/pci/drm/i915/display/intel_bw.c

1265

static bool intel_dbuf_bw_changed(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

1271

for_each_dbuf_slice(display, slice) {

sys/dev/pci/drm/i915/display/intel_bw.c

1280

static bool intel_bw_state_changed(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

1286

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_bw.c

1292

if (intel_dbuf_bw_changed(display, old_dbuf_bw, new_dbuf_bw))

sys/dev/pci/drm/i915/display/intel_bw.c

1295

if (intel_bw_crtc_min_cdclk(display, old_bw_state->data_rate[pipe]) !=

sys/dev/pci/drm/i915/display/intel_bw.c

1296

intel_bw_crtc_min_cdclk(display, new_bw_state->data_rate[pipe]))

sys/dev/pci/drm/i915/display/intel_bw.c

1309

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_bw.c

1310

unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(display, ddb);

sys/dev/pci/drm/i915/display/intel_bw.c

1317

for_each_dbuf_slice_in_mask(display, slice, dbuf_mask) {

sys/dev/pci/drm/i915/display/intel_bw.c

132

sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(display) >= 12 ? 500 : 0),

sys/dev/pci/drm/i915/display/intel_bw.c

1326

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_bw.c

1347

if (DISPLAY_VER(display) < 11)

sys/dev/pci/drm/i915/display/intel_bw.c

1356

intel_bw_dbuf_min_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

1362

for_each_dbuf_slice(display, slice) {

sys/dev/pci/drm/i915/display/intel_bw.c

1371

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_bw.c

1385

int intel_bw_min_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

1391

min_cdclk = intel_bw_dbuf_min_cdclk(display, bw_state);

sys/dev/pci/drm/i915/display/intel_bw.c

1393

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_bw.c

1395

intel_bw_crtc_min_cdclk(display,

sys/dev/pci/drm/i915/display/intel_bw.c

1404

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_bw.c

1414

if (DISPLAY_VER(display) < 9)

sys/dev/pci/drm/i915/display/intel_bw.c

1424

if (!intel_dbuf_bw_changed(display, &old_dbuf_bw, &new_dbuf_bw))

sys/dev/pci/drm/i915/display/intel_bw.c

1439

if (intel_bw_state_changed(display, old_bw_state, new_bw_state)) {

sys/dev/pci/drm/i915/display/intel_bw.c

1445

old_min_cdclk = intel_bw_min_cdclk(display, old_bw_state);

sys/dev/pci/drm/i915/display/intel_bw.c

1446

new_min_cdclk = intel_bw_min_cdclk(display, new_bw_state);

sys/dev/pci/drm/i915/display/intel_bw.c

145

static int adls_pcode_read_psf_gv_point_info(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

1474

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bw.c

1484

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_bw.c

1518

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bw.c

152

ret = intel_pcode_read(display->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |

sys/dev/pci/drm/i915/display/intel_bw.c

1530

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_bw.c

1534

if (DISPLAY_VER(display) < 9)

sys/dev/pci/drm/i915/display/intel_bw.c

1559

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_bw.c

1588

if (intel_bw_can_enable_sagv(display, new_bw_state) !=

sys/dev/pci/drm/i915/display/intel_bw.c

1589

intel_bw_can_enable_sagv(display, old_bw_state)) {

sys/dev/pci/drm/i915/display/intel_bw.c

1604

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_bw.c

1610

if (DISPLAY_VER(display) < 9)

sys/dev/pci/drm/i915/display/intel_bw.c

1624

if (DISPLAY_VER(display) < 11)

sys/dev/pci/drm/i915/display/intel_bw.c

1635

intel_bw_can_enable_sagv(display, old_bw_state) !=

sys/dev/pci/drm/i915/display/intel_bw.c

1636

intel_bw_can_enable_sagv(display, new_bw_state))

sys/dev/pci/drm/i915/display/intel_bw.c

1646

ret = intel_bw_check_qgv_points(display, old_bw_state, new_bw_state);

sys/dev/pci/drm/i915/display/intel_bw.c

165

static u16 icl_qgv_points_mask(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_bw.c

1656

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_bw.c

1664

drm_dbg_kms(display->drm, "pipe %c data rate %u num active planes %u\n",

sys/dev/pci/drm/i915/display/intel_bw.c

167

unsigned int num_psf_gv_points = display->bw.max[0].num_psf_gv_points;

sys/dev/pci/drm/i915/display/intel_bw.c

1670

void intel_bw_update_hw_state(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_bw.c

1673

to_intel_bw_state(display->bw.obj.state);

sys/dev/pci/drm/i915/display/intel_bw.c

1676

if (DISPLAY_VER(display) < 9)

sys/dev/pci/drm/i915/display/intel_bw.c

168

unsigned int num_qgv_points = display->bw.max[0].num_qgv_points;

sys/dev/pci/drm/i915/display/intel_bw.c

1682

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_bw.c

1690

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_bw.c

1702

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_bw.c

1704

to_intel_bw_state(display->bw.obj.state);

sys/dev/pci/drm/i915/display/intel_bw.c

1707

if (DISPLAY_VER(display) < 9)

sys/dev/pci/drm/i915/display/intel_bw.c

1738

int intel_bw_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_bw.c

1746

intel_atomic_global_obj_init(display, &display->bw.obj,

sys/dev/pci/drm/i915/display/intel_bw.c

1753

if (intel_has_sagv(display) && IS_DISPLAY_VER(display, 11, 13))

sys/dev/pci/drm/i915/display/intel_bw.c

1754

icl_force_disable_sagv(display, state);

sys/dev/pci/drm/i915/display/intel_bw.c

1773

bool intel_bw_can_enable_sagv(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

1776

if (DISPLAY_VER(display) < 11 &&

sys/dev/pci/drm/i915/display/intel_bw.c

185

static bool is_sagv_enabled(struct intel_display *display, u16 points_mask)

sys/dev/pci/drm/i915/display/intel_bw.c

187

return !is_power_of_2(~points_mask & icl_qgv_points_mask(display) &

sys/dev/pci/drm/i915/display/intel_bw.c

191

static int icl_pcode_restrict_qgv_points(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

196

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_bw.c

200

ret = intel_pcode_request(display->drm, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,

sys/dev/pci/drm/i915/display/intel_bw.c

207

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_bw.c

213

display->sagv.status = is_sagv_enabled(display, points_mask) ?

sys/dev/pci/drm/i915/display/intel_bw.c

219

static int mtl_read_qgv_point_info(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

222

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_bw.c

244

intel_read_qgv_point_info(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

248

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_bw.c

249

return mtl_read_qgv_point_info(display, sp, point);

sys/dev/pci/drm/i915/display/intel_bw.c

250

else if (display->platform.dg1)

sys/dev/pci/drm/i915/display/intel_bw.c

251

return dg1_mchbar_read_qgv_point_info(display, sp, point);

sys/dev/pci/drm/i915/display/intel_bw.c

253

return icl_pcode_read_qgv_point_info(display, sp, point);

sys/dev/pci/drm/i915/display/intel_bw.c

256

static int icl_get_qgv_points(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

266

if (DISPLAY_VER(display) >= 14) {

sys/dev/pci/drm/i915/display/intel_bw.c

295

} else if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_bw.c

310

if (display->platform.rocketlake) {

sys/dev/pci/drm/i915/display/intel_bw.c

329

} else if (DISPLAY_VER(display) == 11) {

sys/dev/pci/drm/i915/display/intel_bw.c

334

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_bw.c

341

ret = intel_read_qgv_point_info(display, sp, i);

sys/dev/pci/drm/i915/display/intel_bw.c

343

drm_dbg_kms(display->drm, "Could not read QGV %d info\n", i);

sys/dev/pci/drm/i915/display/intel_bw.c

347

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bw.c

354

ret = adls_pcode_read_psf_gv_point_info(display, qi->psf_points);

sys/dev/pci/drm/i915/display/intel_bw.c

356

drm_err(display->drm, "Failed to read PSF point data; PSF points will not be considered in bandwidth calculations.\n");

sys/dev/pci/drm/i915/display/intel_bw.c

361

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bw.c

463

static int icl_get_bw_info(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

473

int num_groups = ARRAY_SIZE(display->bw.max);

sys/dev/pci/drm/i915/display/intel_bw.c

476

ret = icl_get_qgv_points(display, dram_info, &qi, is_y_tile);

sys/dev/pci/drm/i915/display/intel_bw.c

478

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bw.c

489

struct intel_bw_info *bi = &display->bw.max[i];

sys/dev/pci/drm/i915/display/intel_bw.c

516

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bw.c

527

display->sagv.status = I915_SAGV_NOT_CONTROLLED;

sys/dev/pci/drm/i915/display/intel_bw.c

529

display->sagv.status = I915_SAGV_ENABLED;

sys/dev/pci/drm/i915/display/intel_bw.c

534

static int tgl_get_bw_info(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

545

int num_groups = ARRAY_SIZE(display->bw.max);

sys/dev/pci/drm/i915/display/intel_bw.c

548

ret = icl_get_qgv_points(display, dram_info, &qi, is_y_tile);

sys/dev/pci/drm/i915/display/intel_bw.c

550

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bw.c

555

if (DISPLAY_VER(display) < 14 &&

sys/dev/pci/drm/i915/display/intel_bw.c

561

if (num_channels < qi.max_numchannels && DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_bw.c

564

if (DISPLAY_VER(display) >= 12 && num_channels > qi.max_numchannels)

sys/dev/pci/drm/i915/display/intel_bw.c

565

drm_warn(display->drm, "Number of channels exceeds max number of channels.");

sys/dev/pci/drm/i915/display/intel_bw.c

582

struct intel_bw_info *bi = &display->bw.max[i];

sys/dev/pci/drm/i915/display/intel_bw.c

590

bi_next = &display->bw.max[i + 1];

sys/dev/pci/drm/i915/display/intel_bw.c

622

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bw.c

633

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bw.c

645

display->sagv.status = I915_SAGV_NOT_CONTROLLED;

sys/dev/pci/drm/i915/display/intel_bw.c

647

display->sagv.status = I915_SAGV_ENABLED;

sys/dev/pci/drm/i915/display/intel_bw.c

652

static void dg2_get_bw_info(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_bw.c

654

unsigned int deratedbw = display->platform.dg2_g11 ? 38000 : 50000;

sys/dev/pci/drm/i915/display/intel_bw.c

655

int num_groups = ARRAY_SIZE(display->bw.max);

sys/dev/pci/drm/i915/display/intel_bw.c

666

struct intel_bw_info *bi = &display->bw.max[i];

sys/dev/pci/drm/i915/display/intel_bw.c

674

display->sagv.status = I915_SAGV_NOT_CONTROLLED;

sys/dev/pci/drm/i915/display/intel_bw.c

677

static int xe2_hpd_get_bw_info(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

686

ret = icl_get_qgv_points(display, dram_info, &qi, true);

sys/dev/pci/drm/i915/display/intel_bw.c

688

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_bw.c

700

display->bw.max[0].deratedbw[i] =

sys/dev/pci/drm/i915/display/intel_bw.c

702

display->bw.max[0].peakbw[i] = bw;

sys/dev/pci/drm/i915/display/intel_bw.c

704

drm_dbg_kms(display->drm, "QGV %d: deratedbw=%u peakbw: %u\n",

sys/dev/pci/drm/i915/display/intel_bw.c

705

i, display->bw.max[0].deratedbw[i],

sys/dev/pci/drm/i915/display/intel_bw.c

706

display->bw.max[0].peakbw[i]);

sys/dev/pci/drm/i915/display/intel_bw.c

710

display->bw.max[0].num_planes = 1;

sys/dev/pci/drm/i915/display/intel_bw.c

711

display->bw.max[0].num_qgv_points = qi.num_points;

sys/dev/pci/drm/i915/display/intel_bw.c

712

for (i = 1; i < ARRAY_SIZE(display->bw.max); i++)

sys/dev/pci/drm/i915/display/intel_bw.c

713

memcpy(&display->bw.max[i], &display->bw.max[0],

sys/dev/pci/drm/i915/display/intel_bw.c

714

sizeof(display->bw.max[0]));

sys/dev/pci/drm/i915/display/intel_bw.c

720

drm_WARN_ON(display->drm, qi.num_points != 2);

sys/dev/pci/drm/i915/display/intel_bw.c

721

display->sagv.status = I915_SAGV_ENABLED;

sys/dev/pci/drm/i915/display/intel_bw.c

726

static unsigned int icl_max_bw_index(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

736

for (i = 0; i < ARRAY_SIZE(display->bw.max); i++) {

sys/dev/pci/drm/i915/display/intel_bw.c

738

&display->bw.max[i];

sys/dev/pci/drm/i915/display/intel_bw.c

754

static unsigned int tgl_max_bw_index(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

764

for (i = ARRAY_SIZE(display->bw.max) - 1; i >= 0; i--) {

sys/dev/pci/drm/i915/display/intel_bw.c

766

&display->bw.max[i];

sys/dev/pci/drm/i915/display/intel_bw.c

782

static unsigned int adl_psf_bw(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

786

&display->bw.max[0];

sys/dev/pci/drm/i915/display/intel_bw.c

791

static unsigned int icl_qgv_bw(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

796

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_bw.c

797

idx = tgl_max_bw_index(display, num_active_planes, qgv_point);

sys/dev/pci/drm/i915/display/intel_bw.c

799

idx = icl_max_bw_index(display, num_active_planes, qgv_point);

sys/dev/pci/drm/i915/display/intel_bw.c

801

if (idx >= ARRAY_SIZE(display->bw.max))

sys/dev/pci/drm/i915/display/intel_bw.c

804

return display->bw.max[idx].deratedbw[qgv_point];

sys/dev/pci/drm/i915/display/intel_bw.c

807

void intel_bw_init_hw(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_bw.c

809

const struct dram_info *dram_info = intel_dram_info(display->drm);

sys/dev/pci/drm/i915/display/intel_bw.c

81

static int dg1_mchbar_read_qgv_point_info(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

811

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_bw.c

814

if (DISPLAY_VERx100(display) >= 3002)

sys/dev/pci/drm/i915/display/intel_bw.c

815

tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);

sys/dev/pci/drm/i915/display/intel_bw.c

816

else if (DISPLAY_VER(display) >= 30)

sys/dev/pci/drm/i915/display/intel_bw.c

817

tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);

sys/dev/pci/drm/i915/display/intel_bw.c

818

else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx &&

sys/dev/pci/drm/i915/display/intel_bw.c

820

xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);

sys/dev/pci/drm/i915/display/intel_bw.c

821

else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx)

sys/dev/pci/drm/i915/display/intel_bw.c

822

xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);

sys/dev/pci/drm/i915/display/intel_bw.c

823

else if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_bw.c

824

tgl_get_bw_info(display, dram_info, &mtl_sa_info);

sys/dev/pci/drm/i915/display/intel_bw.c

825

else if (display->platform.dg2)

sys/dev/pci/drm/i915/display/intel_bw.c

826

dg2_get_bw_info(display);

sys/dev/pci/drm/i915/display/intel_bw.c

827

else if (display->platform.alderlake_p)

sys/dev/pci/drm/i915/display/intel_bw.c

828

tgl_get_bw_info(display, dram_info, &adlp_sa_info);

sys/dev/pci/drm/i915/display/intel_bw.c

829

else if (display->platform.alderlake_s)

sys/dev/pci/drm/i915/display/intel_bw.c

830

tgl_get_bw_info(display, dram_info, &adls_sa_info);

sys/dev/pci/drm/i915/display/intel_bw.c

831

else if (display->platform.rocketlake)

sys/dev/pci/drm/i915/display/intel_bw.c

832

tgl_get_bw_info(display, dram_info, &rkl_sa_info);

sys/dev/pci/drm/i915/display/intel_bw.c

833

else if (DISPLAY_VER(display) == 12)

sys/dev/pci/drm/i915/display/intel_bw.c

834

tgl_get_bw_info(display, dram_info, &tgl_sa_info);

sys/dev/pci/drm/i915/display/intel_bw.c

835

else if (DISPLAY_VER(display) == 11)

sys/dev/pci/drm/i915/display/intel_bw.c

836

icl_get_bw_info(display, dram_info, &icl_sa_info);

sys/dev/pci/drm/i915/display/intel_bw.c

85

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_bw.c

850

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_bw.c

865

if (DISPLAY_VER(display) < 11)

sys/dev/pci/drm/i915/display/intel_bw.c

873

static int intel_bw_crtc_min_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

876

if (DISPLAY_VER(display) < 12)

sys/dev/pci/drm/i915/display/intel_bw.c

882

static unsigned int intel_bw_num_active_planes(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

888

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_bw.c

894

static unsigned int intel_bw_data_rate(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

897

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_bw.c

901

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_bw.c

904

if (DISPLAY_VER(display) >= 13 && i915_vtd_active(i915))

sys/dev/pci/drm/i915/display/intel_bw.c

918

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_bw.c

921

bw_state = intel_atomic_get_old_global_obj_state(state, &display->bw.obj);

sys/dev/pci/drm/i915/display/intel_bw.c

929

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_bw.c

932

bw_state = intel_atomic_get_new_global_obj_state(state, &display->bw.obj);

sys/dev/pci/drm/i915/display/intel_bw.c

940

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_bw.c

943

bw_state = intel_atomic_get_global_obj_state(state, &display->bw.obj);

sys/dev/pci/drm/i915/display/intel_bw.c

950

static unsigned int icl_max_bw_qgv_point_mask(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

953

unsigned int num_qgv_points = display->bw.max[0].num_qgv_points;

sys/dev/pci/drm/i915/display/intel_bw.c

960

icl_qgv_bw(display, num_active_planes, i);

sys/dev/pci/drm/i915/display/intel_bw.c

979

static u16 icl_prepare_qgv_points_mask(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.c

984

ADLS_PCODE_REQ_PSF_PT(psf_points)) & icl_qgv_points_mask(display);

sys/dev/pci/drm/i915/display/intel_bw.c

987

static unsigned int icl_max_bw_psf_gv_point_mask(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_bw.c

989

unsigned int num_psf_gv_points = display->bw.max[0].num_psf_gv_points;

sys/dev/pci/drm/i915/display/intel_bw.c

995

unsigned int max_data_rate = adl_psf_bw(display, i);

sys/dev/pci/drm/i915/display/intel_bw.h

29

void intel_bw_init_hw(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_bw.h

30

int intel_bw_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_bw.h

34

int intel_bw_min_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_bw.h

36

void intel_bw_update_hw_state(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_bw.h

40

bool intel_bw_can_enable_sagv(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1013

static void skl_get_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1018

skl_dpll0_update(display, cdclk_config);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1025

cdctl = intel_de_read(display, CDCLK_CTL);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1080

static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1082

bool changed = display->cdclk.skl_preferred_vco_freq != vco;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1084

display->cdclk.skl_preferred_vco_freq = vco;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1087

intel_update_max_cdclk(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1090

static u32 skl_dpll0_link_rate(struct intel_display *display, int vco)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1092

drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1109

static void skl_dpll0_enable(struct intel_display *display, int vco)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1111

intel_de_rmw(display, DPLL_CTRL1,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1116

skl_dpll0_link_rate(display, vco));

sys/dev/pci/drm/i915/display/intel_cdclk.c

1117

intel_de_posting_read(display, DPLL_CTRL1);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1119

intel_de_rmw(display, LCPLL1_CTL,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1122

if (intel_de_wait_for_set(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))

sys/dev/pci/drm/i915/display/intel_cdclk.c

1123

drm_err(display->drm, "DPLL0 not locked\n");

sys/dev/pci/drm/i915/display/intel_cdclk.c

1125

display->cdclk.hw.vco = vco;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1128

skl_set_preferred_cdclk_vco(display, vco);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1131

static void skl_dpll0_disable(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1133

intel_de_rmw(display, LCPLL1_CTL,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1136

if (intel_de_wait_for_clear(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))

sys/dev/pci/drm/i915/display/intel_cdclk.c

1137

drm_err(display->drm, "Couldn't disable DPLL0\n");

sys/dev/pci/drm/i915/display/intel_cdclk.c

1139

display->cdclk.hw.vco = 0;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1142

static u32 skl_cdclk_freq_sel(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1147

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1148

cdclk != display->cdclk.hw.bypass);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1149

drm_WARN_ON(display->drm, vco != 0);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1165

static void skl_set_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1182

drm_WARN_ON_ONCE(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1183

display->platform.skylake && vco == 8640000);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1185

ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1190

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1195

freq_select = skl_cdclk_freq_sel(display, cdclk, vco);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1197

if (display->cdclk.hw.vco != 0 &&

sys/dev/pci/drm/i915/display/intel_cdclk.c

1198

display->cdclk.hw.vco != vco)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1199

skl_dpll0_disable(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1201

cdclk_ctl = intel_de_read(display, CDCLK_CTL);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1203

if (display->cdclk.hw.vco != vco) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

1207

intel_de_write(display, CDCLK_CTL, cdclk_ctl);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1212

intel_de_write(display, CDCLK_CTL, cdclk_ctl);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1213

intel_de_posting_read(display, CDCLK_CTL);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1215

if (display->cdclk.hw.vco != vco)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1216

skl_dpll0_enable(display, vco);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1220

intel_de_write(display, CDCLK_CTL, cdclk_ctl);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1223

intel_de_write(display, CDCLK_CTL, cdclk_ctl);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1227

intel_de_write(display, CDCLK_CTL, cdclk_ctl);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1228

intel_de_posting_read(display, CDCLK_CTL);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1231

intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1234

intel_update_cdclk(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1237

static void skl_sanitize_cdclk(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1246

if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1249

intel_update_cdclk(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1250

intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");

sys/dev/pci/drm/i915/display/intel_cdclk.c

1253

if (display->cdclk.hw.vco == 0 ||

sys/dev/pci/drm/i915/display/intel_cdclk.c

1254

display->cdclk.hw.cdclk == display->cdclk.hw.bypass)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1263

cdctl = intel_de_read(display, CDCLK_CTL);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1265

skl_cdclk_decimal(display->cdclk.hw.cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1271

drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");

sys/dev/pci/drm/i915/display/intel_cdclk.c

1274

display->cdclk.hw.cdclk = 0;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1276

display->cdclk.hw.vco = ~0;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1279

static void skl_cdclk_init_hw(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1283

skl_sanitize_cdclk(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1285

if (display->cdclk.hw.cdclk != 0 &&

sys/dev/pci/drm/i915/display/intel_cdclk.c

1286

display->cdclk.hw.vco != 0) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

1291

if (display->cdclk.skl_preferred_vco_freq == 0)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1292

skl_set_preferred_cdclk_vco(display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1293

display->cdclk.hw.vco);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1297

cdclk_config = display->cdclk.hw;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1299

cdclk_config.vco = display->cdclk.skl_preferred_vco_freq;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1305

skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1308

static void skl_cdclk_uninit_hw(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1310

struct intel_cdclk_config cdclk_config = display->cdclk.hw;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1316

skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1557

static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1559

const struct intel_cdclk_vals *table = display->cdclk.table;

sys/dev/pci/drm/i915/display/intel_cdclk.c

156

void (*get_cdclk)(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1563

if (table[i].refclk == display->cdclk.hw.ref &&

sys/dev/pci/drm/i915/display/intel_cdclk.c

1567

drm_WARN(display->drm, 1,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1569

min_cdclk, display->cdclk.hw.ref);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1573

static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1575

const struct intel_cdclk_vals *table = display->cdclk.table;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1578

if (cdclk == display->cdclk.hw.bypass)

sys/dev/pci/drm/i915/display/intel_cdclk.c

158

void (*set_cdclk)(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1582

if (table[i].refclk == display->cdclk.hw.ref &&

sys/dev/pci/drm/i915/display/intel_cdclk.c

1584

return display->cdclk.hw.ref * table[i].ratio;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1586

drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",

sys/dev/pci/drm/i915/display/intel_cdclk.c

1587

cdclk, display->cdclk.hw.ref);

sys/dev/pci/drm/i915/display/intel_cdclk.c

165

void intel_cdclk_get_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1679

static void icl_readout_refclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

168

display->funcs.cdclk->get_cdclk(display, cdclk_config);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1682

u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1700

static void bxt_de_pll_readout(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1705

if (display->platform.dg2)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1707

else if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1708

icl_readout_refclk(display, cdclk_config);

sys/dev/pci/drm/i915/display/intel_cdclk.c

171

static void intel_cdclk_set_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1712

val = intel_de_read(display, BXT_DE_PLL_ENABLE);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1727

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1730

ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1735

static void bxt_get_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1742

bxt_de_pll_readout(display, cdclk_config);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1744

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1746

else if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_cdclk.c

175

display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1756

divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1776

if (HAS_CDCLK_SQUASH(display))

sys/dev/pci/drm/i915/display/intel_cdclk.c

1777

squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1793

if (DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1794

cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN;

sys/dev/pci/drm/i915/display/intel_cdclk.c

180

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1800

intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1803

static void bxt_de_pll_disable(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1805

intel_de_write(display, BXT_DE_PLL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1808

if (intel_de_wait_for_clear(display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1810

drm_err(display->drm, "timeout waiting for DE PLL unlock\n");

sys/dev/pci/drm/i915/display/intel_cdclk.c

1812

display->cdclk.hw.vco = 0;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1815

static void bxt_de_pll_enable(struct intel_display *display, int vco)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1817

int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1819

intel_de_rmw(display, BXT_DE_PLL_CTL,

sys/dev/pci/drm/i915/display/intel_cdclk.c

182

return display->funcs.cdclk->modeset_calc_cdclk(state);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1822

intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1825

if (intel_de_wait_for_set(display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1827

drm_err(display->drm, "timeout waiting for DE PLL lock\n");

sys/dev/pci/drm/i915/display/intel_cdclk.c

1829

display->cdclk.hw.vco = vco;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1832

static void icl_cdclk_pll_disable(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1834

intel_de_rmw(display, BXT_DE_PLL_ENABLE,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1838

if (intel_de_wait_for_clear(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))

sys/dev/pci/drm/i915/display/intel_cdclk.c

1839

drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n");

sys/dev/pci/drm/i915/display/intel_cdclk.c

1841

display->cdclk.hw.vco = 0;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1844

static void icl_cdclk_pll_enable(struct intel_display *display, int vco)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1846

int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);

sys/dev/pci/drm/i915/display/intel_cdclk.c

185

static u8 intel_cdclk_calc_voltage_level(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1850

intel_de_write(display, BXT_DE_PLL_ENABLE, val);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1853

intel_de_write(display, BXT_DE_PLL_ENABLE, val);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1856

if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))

sys/dev/pci/drm/i915/display/intel_cdclk.c

1857

drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n");

sys/dev/pci/drm/i915/display/intel_cdclk.c

1859

display->cdclk.hw.vco = vco;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1862

static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1864

int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1869

intel_de_write(display, BXT_DE_PLL_ENABLE, val);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1873

intel_de_write(display, BXT_DE_PLL_ENABLE, val);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1876

if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1878

drm_err(display->drm, "timeout waiting for FREQ change request ack\n");

sys/dev/pci/drm/i915/display/intel_cdclk.c

188

return display->funcs.cdclk->calc_voltage_level(cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1881

intel_de_write(display, BXT_DE_PLL_ENABLE, val);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1883

display->cdclk.hw.vco = vco;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1886

static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1888

if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

1893

} else if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

1906

static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

191

static void fixed_133mhz_get_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1912

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1913

cdclk != display->cdclk.hw.bypass);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1914

drm_WARN_ON(display->drm, vco != 0);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1927

static u16 cdclk_squash_waveform(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1930

const struct intel_cdclk_vals *table = display->cdclk.table;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1933

if (cdclk == display->cdclk.hw.bypass)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1937

if (table[i].refclk == display->cdclk.hw.ref &&

sys/dev/pci/drm/i915/display/intel_cdclk.c

1941

drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",

sys/dev/pci/drm/i915/display/intel_cdclk.c

1942

cdclk, display->cdclk.hw.ref);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1947

static void icl_cdclk_pll_update(struct intel_display *display, int vco)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1949

if (display->cdclk.hw.vco != 0 &&

sys/dev/pci/drm/i915/display/intel_cdclk.c

1950

display->cdclk.hw.vco != vco)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1951

icl_cdclk_pll_disable(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1953

if (display->cdclk.hw.vco != vco)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1954

icl_cdclk_pll_enable(display, vco);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1957

static void bxt_cdclk_pll_update(struct intel_display *display, int vco)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1959

if (display->cdclk.hw.vco != 0 &&

sys/dev/pci/drm/i915/display/intel_cdclk.c

1960

display->cdclk.hw.vco != vco)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1961

bxt_de_pll_disable(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1963

if (display->cdclk.hw.vco != vco)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1964

bxt_de_pll_enable(display, vco);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1967

static void dg2_cdclk_squash_program(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

197

static void fixed_200mhz_get_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1976

intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1989

static bool mdclk_source_is_cdclk_pll(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1991

return DISPLAY_VER(display) >= 20;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1994

static u32 xe2lpd_mdclk_source_sel(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1996

if (mdclk_source_is_cdclk_pll(display))

sys/dev/pci/drm/i915/display/intel_cdclk.c

2002

int intel_mdclk_cdclk_ratio(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2005

if (mdclk_source_is_cdclk_pll(display))

sys/dev/pci/drm/i915/display/intel_cdclk.c

2012

static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2015

intel_dbuf_mdclk_cdclk_ratio_update(display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2016

intel_mdclk_cdclk_ratio(display, cdclk_config),

sys/dev/pci/drm/i915/display/intel_cdclk.c

2020

static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

203

static void fixed_266mhz_get_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2033

if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display))

sys/dev/pci/drm/i915/display/intel_cdclk.c

2036

old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2037

new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2054

if (drm_WARN_ON(display->drm, old_div != new_div))

sys/dev/pci/drm/i915/display/intel_cdclk.c

2083

drm_WARN_ON(display->drm, mid_cdclk_config->cdclk <

sys/dev/pci/drm/i915/display/intel_cdclk.c

2085

drm_WARN_ON(display->drm, mid_cdclk_config->cdclk >

sys/dev/pci/drm/i915/display/intel_cdclk.c

2086

display->cdclk.max_cdclk_freq);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2087

drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) !=

sys/dev/pci/drm/i915/display/intel_cdclk.c

209

static void fixed_333mhz_get_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2093

static bool pll_enable_wa_needed(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2095

return (DISPLAY_VERx100(display) == 2000 ||

sys/dev/pci/drm/i915/display/intel_cdclk.c

2096

DISPLAY_VERx100(display) == 1400 ||

sys/dev/pci/drm/i915/display/intel_cdclk.c

2097

display->platform.dg2) &&

sys/dev/pci/drm/i915/display/intel_cdclk.c

2098

display->cdclk.hw.vco > 0;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2101

static u32 bxt_cdclk_ctl(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2110

waveform = cdclk_squash_waveform(display, cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2112

val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) |

sys/dev/pci/drm/i915/display/intel_cdclk.c

2113

bxt_cdclk_cd2x_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2119

if ((display->platform.geminilake || display->platform.broxton) &&

sys/dev/pci/drm/i915/display/intel_cdclk.c

2123

if (DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2124

val |= xe2lpd_mdclk_source_sel(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2131

static void _bxt_set_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2138

if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 &&

sys/dev/pci/drm/i915/display/intel_cdclk.c

2139

!cdclk_pll_is_unknown(display->cdclk.hw.vco)) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

2140

if (display->cdclk.hw.vco != vco)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2141

adlp_cdclk_pll_crawl(display, vco);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2142

} else if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

2144

if (pll_enable_wa_needed(display))

sys/dev/pci/drm/i915/display/intel_cdclk.c

2145

dg2_cdclk_squash_program(display, 0);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2147

icl_cdclk_pll_update(display, vco);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2149

bxt_cdclk_pll_update(display, vco);

sys/dev/pci/drm/i915/display/intel_cdclk.c

215

static void fixed_400mhz_get_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2152

if (HAS_CDCLK_SQUASH(display)) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

2153

u16 waveform = cdclk_squash_waveform(display, cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2155

dg2_cdclk_squash_program(display, waveform);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2158

intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe));

sys/dev/pci/drm/i915/display/intel_cdclk.c

2161

intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));

sys/dev/pci/drm/i915/display/intel_cdclk.c

2164

static void bxt_set_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2178

if (DISPLAY_VER(display) >= 14 || display->platform.dg2)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2180

else if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2181

ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2190

ret = intel_pcode_write_timeout(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2195

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2201

if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2202

xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2204

if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2206

_bxt_set_cdclk(display, &mid_cdclk_config, pipe);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2207

_bxt_set_cdclk(display, cdclk_config, pipe);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2209

_bxt_set_cdclk(display, cdclk_config, pipe);

sys/dev/pci/drm/i915/display/intel_cdclk.c

221

static void fixed_450mhz_get_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2212

if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2213

xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2215

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2220

else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2221

ret = intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2223

if (DISPLAY_VER(display) < 11) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

2230

ret = intel_pcode_write_timeout(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2235

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2241

intel_update_cdclk(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2243

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2248

display->cdclk.hw.voltage_level = cdclk_config->voltage_level;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2251

static void bxt_sanitize_cdclk(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2256

intel_update_cdclk(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2257

intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");

sys/dev/pci/drm/i915/display/intel_cdclk.c

2259

if (display->cdclk.hw.vco == 0 ||

sys/dev/pci/drm/i915/display/intel_cdclk.c

2260

display->cdclk.hw.cdclk == display->cdclk.hw.bypass)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2264

cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2265

if (cdclk != display->cdclk.hw.cdclk)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2269

vco = bxt_calc_cdclk_pll_vco(display, cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

227

static void i85x_get_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2270

if (vco != display->cdclk.hw.vco)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2278

cdctl = intel_de_read(display, CDCLK_CTL);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2279

expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2286

cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2287

expected &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2294

drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");

sys/dev/pci/drm/i915/display/intel_cdclk.c

2297

display->cdclk.hw.cdclk = 0;

sys/dev/pci/drm/i915/display/intel_cdclk.c

230

struct pci_dev *pdev = display->drm->pdev;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2300

display->cdclk.hw.vco = ~0;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2303

static void bxt_cdclk_init_hw(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2307

bxt_sanitize_cdclk(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2309

if (display->cdclk.hw.cdclk != 0 &&

sys/dev/pci/drm/i915/display/intel_cdclk.c

2310

display->cdclk.hw.vco != 0)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2313

cdclk_config = display->cdclk.hw;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2320

cdclk_config.cdclk = bxt_calc_cdclk(display, 0);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2321

cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2323

intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2325

bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2328

static void bxt_cdclk_uninit_hw(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2330

struct intel_cdclk_config cdclk_config = display->cdclk.hw;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2335

intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2337

bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2349

void intel_cdclk_init_hw(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2351

if (DISPLAY_VER(display) >= 10 || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2352

bxt_cdclk_init_hw(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2353

else if (DISPLAY_VER(display) == 9)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2354

skl_cdclk_init_hw(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2364

void intel_cdclk_uninit_hw(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2366

if (DISPLAY_VER(display) >= 10 || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2367

bxt_cdclk_uninit_hw(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2368

else if (DISPLAY_VER(display) == 9)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2369

skl_cdclk_uninit_hw(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2372

static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2379

drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco));

sys/dev/pci/drm/i915/display/intel_cdclk.c

2384

if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display))

sys/dev/pci/drm/i915/display/intel_cdclk.c

2387

old_waveform = cdclk_squash_waveform(display, a->cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2388

new_waveform = cdclk_squash_waveform(display, b->cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2394

static bool intel_cdclk_can_crawl(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2400

if (!HAS_CDCLK_CRAWL(display))

sys/dev/pci/drm/i915/display/intel_cdclk.c

2416

static bool intel_cdclk_can_squash(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2426

if (!HAS_CDCLK_SQUASH(display))

sys/dev/pci/drm/i915/display/intel_cdclk.c

2463

static bool intel_cdclk_can_cd2x_update(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2468

if (DISPLAY_VER(display) < 10 && !display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2477

if (HAS_CDCLK_SQUASH(display))

sys/dev/pci/drm/i915/display/intel_cdclk.c

2501

void intel_cdclk_dump_config(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2505

drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",

sys/dev/pci/drm/i915/display/intel_cdclk.c

2511

static void intel_pcode_notify(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2521

if (!display->platform.dg2)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2532

ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2538

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2543

static void intel_set_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2549

if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config))

sys/dev/pci/drm/i915/display/intel_cdclk.c

2552

if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk))

sys/dev/pci/drm/i915/display/intel_cdclk.c

2555

intel_cdclk_dump_config(display, cdclk_config, context);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2557

for_each_intel_encoder_with_psr(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

2563

intel_audio_cdclk_change_pre(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2570

mutex_lock(&display->gmbus.mutex);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2571

for_each_intel_dp(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

2575

&display->gmbus.mutex);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2578

intel_cdclk_set_cdclk(display, cdclk_config, pipe);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2580

for_each_intel_dp(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

2585

mutex_unlock(&display->gmbus.mutex);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2587

for_each_intel_encoder_with_psr(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

2593

intel_audio_cdclk_change_post(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2595

if (drm_WARN(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2596

intel_cdclk_changed(&display->cdclk.hw, cdclk_config),

sys/dev/pci/drm/i915/display/intel_cdclk.c

2598

intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]");

sys/dev/pci/drm/i915/display/intel_cdclk.c

2599

intel_cdclk_dump_config(display, cdclk_config, "[sw state]");

sys/dev/pci/drm/i915/display/intel_cdclk.c

2605

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2644

intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2650

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2681

intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,

sys/dev/pci/drm/i915/display/intel_cdclk.c

269

static void i915gm_get_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2706

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2718

if (display->platform.dg2)

sys/dev/pci/drm/i915/display/intel_cdclk.c

272

struct pci_dev *pdev = display->drm->pdev;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2743

drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2745

intel_set_cdclk(display, &cdclk_config, pipe,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2759

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2770

if (display->platform.dg2)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2779

drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2781

intel_set_cdclk(display, &new_cdclk_state->actual, pipe,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2786

static int intel_cdclk_ppc(struct intel_display *display, bool double_wide)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2788

return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2792

static int intel_cdclk_guardband(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2794

if (DISPLAY_VER(display) >= 9 ||

sys/dev/pci/drm/i915/display/intel_cdclk.c

2795

display->platform.broadwell || display->platform.haswell)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2797

else if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2805

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2806

int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2807

int guardband = intel_cdclk_guardband(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2816

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2820

for_each_intel_plane_on_crtc(display->drm, crtc, plane)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2845

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2873

min_cdclk = intel_bw_min_cdclk(display, bw_state);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2888

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2899

if (display->platform.geminilake && cdclk_state->active_pipes &&

sys/dev/pci/drm/i915/display/intel_cdclk.c

2903

if (min_cdclk > display->cdclk.max_cdclk_freq) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

2904

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2906

min_cdclk, display->cdclk.max_cdclk_freq);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2928

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_cdclk.c

293

static void i945gm_get_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2956

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_cdclk.c

296

struct pci_dev *pdev = display->drm->pdev;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2965

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2974

cdclk = vlv_calc_cdclk(display, min_cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2978

vlv_calc_voltage_level(display, cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2981

cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2985

vlv_calc_voltage_level(display, cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3024

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3033

vco = display->cdclk.skl_preferred_vco_freq;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3095

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3108

cdclk = bxt_calc_cdclk(display, min_cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3109

vco = bxt_calc_cdclk_pll_vco(display, cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3115

intel_cdclk_calc_voltage_level(display, cdclk));

sys/dev/pci/drm/i915/display/intel_cdclk.c

3118

cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3119

vco = bxt_calc_cdclk_pll_vco(display, cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3124

intel_cdclk_calc_voltage_level(display, cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

317

static unsigned int intel_hpll_vco(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3176

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3179

cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3235

int intel_cdclk_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3243

intel_atomic_global_obj_init(display, &display->cdclk.obj,

sys/dev/pci/drm/i915/display/intel_cdclk.c

3249

static bool intel_cdclk_need_serialize(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

3261

return cdclk_changed || (display->platform.dg2 && power_well_cnt_changed);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3266

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3285

if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3305

intel_cdclk_can_cd2x_update(display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

3312

crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3322

if (intel_cdclk_can_crawl_and_squash(display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

3325

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

3327

} else if (intel_cdclk_can_squash(display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

3330

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

3332

} else if (intel_cdclk_can_crawl(display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

3335

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

3340

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

3352

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

3356

if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) !=

sys/dev/pci/drm/i915/display/intel_cdclk.c

3357

intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3358

int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3365

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

3369

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

3377

void intel_cdclk_update_hw_state(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3380

to_intel_bw_state(display->bw.obj.state);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3382

to_intel_cdclk_state(display->cdclk.obj.state);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3387

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3399

cdclk_state->bw_min_cdclk = intel_bw_min_cdclk(display, bw_state);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3404

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3406

intel_cdclk_update_hw_state(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3409

static int intel_compute_max_dotclk(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3411

int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display));

sys/dev/pci/drm/i915/display/intel_cdclk.c

3412

int guardband = intel_cdclk_guardband(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3413

int max_cdclk_freq = display->cdclk.max_cdclk_freq;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3426

void intel_update_max_cdclk(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3428

if (DISPLAY_VERx100(display) >= 3002) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3429

display->cdclk.max_cdclk_freq = 480000;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3430

} else if (DISPLAY_VER(display) >= 30) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3431

display->cdclk.max_cdclk_freq = 691200;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3432

} else if (display->platform.jasperlake || display->platform.elkhartlake) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3433

if (display->cdclk.hw.ref == 24000)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3434

display->cdclk.max_cdclk_freq = 552000;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3436

display->cdclk.max_cdclk_freq = 556800;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3437

} else if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3438

if (display->cdclk.hw.ref == 24000)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3439

display->cdclk.max_cdclk_freq = 648000;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3441

display->cdclk.max_cdclk_freq = 652800;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3442

} else if (display->platform.geminilake) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3443

display->cdclk.max_cdclk_freq = 316800;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3444

} else if (display->platform.broxton) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3445

display->cdclk.max_cdclk_freq = 624000;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3446

} else if (DISPLAY_VER(display) == 9) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3447

u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3450

vco = display->cdclk.skl_preferred_vco_freq;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3451

drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3467

display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3468

} else if (display->platform.broadwell) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3475

if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3476

display->cdclk.max_cdclk_freq = 450000;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3477

else if (display->platform.broadwell_ulx)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3478

display->cdclk.max_cdclk_freq = 450000;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3479

else if (display->platform.broadwell_ult)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3480

display->cdclk.max_cdclk_freq = 540000;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3482

display->cdclk.max_cdclk_freq = 675000;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3483

} else if (display->platform.cherryview) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3484

display->cdclk.max_cdclk_freq = 320000;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3485

} else if (display->platform.valleyview) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3486

display->cdclk.max_cdclk_freq = 400000;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3489

display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3492

display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3494

drm_dbg(display->drm, "Max CD clock rate: %d kHz\n",

sys/dev/pci/drm/i915/display/intel_cdclk.c

3495

display->cdclk.max_cdclk_freq);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3497

drm_dbg(display->drm, "Max dotclock rate: %d kHz\n",

sys/dev/pci/drm/i915/display/intel_cdclk.c

3498

display->cdclk.max_dotclk_freq);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3507

void intel_update_cdclk(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3509

intel_cdclk_get_cdclk(display, &display->cdclk.hw);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3517

if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3518

intel_de_write(display, GMBUSFREQ_VLV,

sys/dev/pci/drm/i915/display/intel_cdclk.c

3519

DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000));

sys/dev/pci/drm/i915/display/intel_cdclk.c

3522

static int dg1_rawclk(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3528

intel_de_write(display, PCH_RAWCLK_FREQ,

sys/dev/pci/drm/i915/display/intel_cdclk.c

3534

static int cnp_rawclk(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3539

if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3555

if (INTEL_PCH_TYPE(display) >= PCH_ICP)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3559

intel_de_write(display, PCH_RAWCLK_FREQ, rawclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3563

static int pch_rawclk(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3565

return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3568

static int vlv_hrawclk(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3571

return vlv_get_cck_clock_hpll(display->drm, "hrawclk",

sys/dev/pci/drm/i915/display/intel_cdclk.c

3575

static int i9xx_hrawclk(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3577

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3590

u32 intel_read_rawclk(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3594

if (INTEL_PCH_TYPE(display) >= PCH_MTL)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3601

else if (INTEL_PCH_TYPE(display) >= PCH_DG1)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3602

freq = dg1_rawclk(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3603

else if (INTEL_PCH_TYPE(display) >= PCH_CNP)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3604

freq = cnp_rawclk(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3605

else if (HAS_PCH_SPLIT(display))

sys/dev/pci/drm/i915/display/intel_cdclk.c

3606

freq = pch_rawclk(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3607

else if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3608

freq = vlv_hrawclk(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3609

else if (DISPLAY_VER(display) >= 3)

sys/dev/pci/drm/i915/display/intel_cdclk.c

361

if (display->platform.gm45)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3610

freq = i9xx_hrawclk(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3620

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3622

seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3623

seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3624

seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq);

sys/dev/pci/drm/i915/display/intel_cdclk.c

363

else if (display->platform.g45)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3631

void intel_cdclk_debugfs_register(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3633

debugfs_create_file("i915_cdclk_info", 0444, display->drm->debugfs_root,

sys/dev/pci/drm/i915/display/intel_cdclk.c

3634

display, &i915_cdclk_info_fops);

sys/dev/pci/drm/i915/display/intel_cdclk.c

365

else if (display->platform.i965gm)

sys/dev/pci/drm/i915/display/intel_cdclk.c

367

else if (display->platform.pineview)

sys/dev/pci/drm/i915/display/intel_cdclk.c

369

else if (display->platform.g33)

sys/dev/pci/drm/i915/display/intel_cdclk.c

374

tmp = intel_de_read(display, display->platform.pineview ||

sys/dev/pci/drm/i915/display/intel_cdclk.c

375

display->platform.mobile ? HPLLVCO_MOBILE : HPLLVCO);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3784

void intel_init_cdclk_hooks(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3786

if (DISPLAY_VER(display) >= 30) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3787

display->funcs.cdclk = &xe3lpd_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3788

display->cdclk.table = xe3lpd_cdclk_table;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3789

} else if (DISPLAY_VER(display) >= 20) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

379

drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",

sys/dev/pci/drm/i915/display/intel_cdclk.c

3790

display->funcs.cdclk = &rplu_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3791

display->cdclk.table = xe2lpd_cdclk_table;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3792

} else if (DISPLAY_VERx100(display) >= 1401) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3793

display->funcs.cdclk = &rplu_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3794

display->cdclk.table = xe2hpd_cdclk_table;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3795

} else if (DISPLAY_VER(display) >= 14) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3796

display->funcs.cdclk = &rplu_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3797

display->cdclk.table = mtl_cdclk_table;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3798

} else if (display->platform.dg2) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3799

display->funcs.cdclk = &tgl_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3800

display->cdclk.table = dg2_cdclk_table;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3801

} else if (display->platform.alderlake_p) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3803

if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3804

display->cdclk.table = adlp_a_step_cdclk_table;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3805

display->funcs.cdclk = &tgl_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3806

} else if (display->platform.alderlake_p_raptorlake_u) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3807

display->cdclk.table = rplu_cdclk_table;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3808

display->funcs.cdclk = &rplu_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3810

display->cdclk.table = adlp_cdclk_table;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3811

display->funcs.cdclk = &tgl_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3813

} else if (display->platform.rocketlake) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3814

display->funcs.cdclk = &tgl_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3815

display->cdclk.table = rkl_cdclk_table;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3816

} else if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3817

display->funcs.cdclk = &tgl_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3818

display->cdclk.table = icl_cdclk_table;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3819

} else if (display->platform.jasperlake || display->platform.elkhartlake) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

382

drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3820

display->funcs.cdclk = &ehl_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3821

display->cdclk.table = icl_cdclk_table;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3822

} else if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3823

display->funcs.cdclk = &icl_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3824

display->cdclk.table = icl_cdclk_table;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3825

} else if (display->platform.geminilake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3826

display->funcs.cdclk = &bxt_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3827

if (display->platform.geminilake)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3828

display->cdclk.table = glk_cdclk_table;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3830

display->cdclk.table = bxt_cdclk_table;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3831

} else if (DISPLAY_VER(display) == 9) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3832

display->funcs.cdclk = &skl_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3833

} else if (display->platform.broadwell) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3834

display->funcs.cdclk = &bdw_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3835

} else if (display->platform.haswell) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3836

display->funcs.cdclk = &hsw_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3837

} else if (display->platform.cherryview) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3838

display->funcs.cdclk = &chv_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3839

} else if (display->platform.valleyview) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3840

display->funcs.cdclk = &vlv_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3841

} else if (display->platform.sandybridge || display->platform.ivybridge) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3842

display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3843

} else if (display->platform.ironlake) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3844

display->funcs.cdclk = &ilk_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3845

} else if (display->platform.gm45) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3846

display->funcs.cdclk = &gm45_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3847

} else if (display->platform.g45) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3848

display->funcs.cdclk = &g33_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3849

} else if (display->platform.i965gm) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3850

display->funcs.cdclk = &i965gm_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3851

} else if (display->platform.i965g) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3852

display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3853

} else if (display->platform.pineview) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3854

display->funcs.cdclk = &pnv_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3855

} else if (display->platform.g33) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3856

display->funcs.cdclk = &g33_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3857

} else if (display->platform.i945gm) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3858

display->funcs.cdclk = &i945gm_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3859

} else if (display->platform.i945g) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3860

display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3861

} else if (display->platform.i915gm) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3862

display->funcs.cdclk = &i915gm_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3863

} else if (display->platform.i915g) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3864

display->funcs.cdclk = &i915g_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3865

} else if (display->platform.i865g) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3866

display->funcs.cdclk = &i865g_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3867

} else if (display->platform.i85x) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3868

display->funcs.cdclk = &i85x_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3869

} else if (display->platform.i845g) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

387

static void g33_get_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

3870

display->funcs.cdclk = &i845g_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3871

} else if (display->platform.i830) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3872

display->funcs.cdclk = &i830_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3875

if (drm_WARN(display->drm, !display->funcs.cdclk,

sys/dev/pci/drm/i915/display/intel_cdclk.c

3877

display->funcs.cdclk = &i830_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

390

struct pci_dev *pdev = display->drm->pdev;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3925

void intel_cdclk_read_hw(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3929

cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3931

intel_update_cdclk(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3932

intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");

sys/dev/pci/drm/i915/display/intel_cdclk.c

3933

cdclk_state->actual = display->cdclk.hw;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3934

cdclk_state->logical = display->cdclk.hw;

sys/dev/pci/drm/i915/display/intel_cdclk.c

399

cdclk_config->vco = intel_hpll_vco(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

430

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

436

static void pnv_get_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

439

struct pci_dev *pdev = display->drm->pdev;

sys/dev/pci/drm/i915/display/intel_cdclk.c

458

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

470

static void i965gm_get_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

473

struct pci_dev *pdev = display->drm->pdev;

sys/dev/pci/drm/i915/display/intel_cdclk.c

481

cdclk_config->vco = intel_hpll_vco(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

509

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

515

static void gm45_get_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

518

struct pci_dev *pdev = display->drm->pdev;

sys/dev/pci/drm/i915/display/intel_cdclk.c

522

cdclk_config->vco = intel_hpll_vco(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

538

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

546

static void hsw_get_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

549

u32 lcpll = intel_de_read(display, LCPLL_CTL);

sys/dev/pci/drm/i915/display/intel_cdclk.c

554

else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)

sys/dev/pci/drm/i915/display/intel_cdclk.c

558

else if (display->platform.haswell_ult)

sys/dev/pci/drm/i915/display/intel_cdclk.c

564

static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk)

sys/dev/pci/drm/i915/display/intel_cdclk.c

566

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_cdclk.c

575

if (display->platform.valleyview && min_cdclk > freq_320)

sys/dev/pci/drm/i915/display/intel_cdclk.c

585

static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk)

sys/dev/pci/drm/i915/display/intel_cdclk.c

587

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_cdclk.c

589

if (display->platform.valleyview) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

606

static void vlv_get_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

611

vlv_iosf_sb_get(display->drm, BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));

sys/dev/pci/drm/i915/display/intel_cdclk.c

613

cdclk_config->vco = vlv_get_hpll_vco(display->drm);

sys/dev/pci/drm/i915/display/intel_cdclk.c

614

cdclk_config->cdclk = vlv_get_cck_clock(display->drm, "cdclk",

sys/dev/pci/drm/i915/display/intel_cdclk.c

618

val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);

sys/dev/pci/drm/i915/display/intel_cdclk.c

620

vlv_iosf_sb_put(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

623

if (display->platform.valleyview)

sys/dev/pci/drm/i915/display/intel_cdclk.c

631

static void vlv_program_pfi_credits(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cdclk.c

633

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_cdclk.c

636

if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_cdclk.c

641

if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

643

if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_cdclk.c

655

intel_de_write(display, GCI_CONTROL,

sys/dev/pci/drm/i915/display/intel_cdclk.c

658

intel_de_write(display, GCI_CONTROL,

sys/dev/pci/drm/i915/display/intel_cdclk.c

665

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

666

intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND);

sys/dev/pci/drm/i915/display/intel_cdclk.c

669

static void vlv_set_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

673

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_cdclk.c

697

wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE);

sys/dev/pci/drm/i915/display/intel_cdclk.c

699

vlv_iosf_sb_get(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

704

val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);

sys/dev/pci/drm/i915/display/intel_cdclk.c

707

vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val);

sys/dev/pci/drm/i915/display/intel_cdclk.c

709

ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),

sys/dev/pci/drm/i915/display/intel_cdclk.c

713

drm_err(display->drm, "timed out waiting for CDCLK change\n");

sys/dev/pci/drm/i915/display/intel_cdclk.c

722

val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL);

sys/dev/pci/drm/i915/display/intel_cdclk.c

725

vlv_cck_write(display->drm, CCK_DISPLAY_CLOCK_CONTROL, val);

sys/dev/pci/drm/i915/display/intel_cdclk.c

727

ret = poll_timeout_us(val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL),

sys/dev/pci/drm/i915/display/intel_cdclk.c

731

drm_err(display->drm, "timed out waiting for CDCLK change\n");

sys/dev/pci/drm/i915/display/intel_cdclk.c

735

val = vlv_bunit_read(display->drm, BUNIT_REG_BISOC);

sys/dev/pci/drm/i915/display/intel_cdclk.c

746

vlv_bunit_write(display->drm, BUNIT_REG_BISOC, val);

sys/dev/pci/drm/i915/display/intel_cdclk.c

748

vlv_iosf_sb_put(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

753

intel_update_cdclk(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

755

vlv_program_pfi_credits(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

757

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

sys/dev/pci/drm/i915/display/intel_cdclk.c

760

static void chv_set_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

786

wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE);

sys/dev/pci/drm/i915/display/intel_cdclk.c

788

vlv_punit_get(display->drm);

sys/dev/pci/drm/i915/display/intel_cdclk.c

789

val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);

sys/dev/pci/drm/i915/display/intel_cdclk.c

792

vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val);

sys/dev/pci/drm/i915/display/intel_cdclk.c

794

ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),

sys/dev/pci/drm/i915/display/intel_cdclk.c

798

drm_err(display->drm, "timed out waiting for CDCLK change\n");

sys/dev/pci/drm/i915/display/intel_cdclk.c

800

vlv_punit_put(display->drm);

sys/dev/pci/drm/i915/display/intel_cdclk.c

802

intel_update_cdclk(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

804

vlv_program_pfi_credits(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

806

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

sys/dev/pci/drm/i915/display/intel_cdclk.c

836

static void bdw_get_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

839

u32 lcpll = intel_de_read(display, LCPLL_CTL);

sys/dev/pci/drm/i915/display/intel_cdclk.c

844

else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)

sys/dev/pci/drm/i915/display/intel_cdclk.c

880

static void bdw_set_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

887

if (drm_WARN(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

888

(intel_de_read(display, LCPLL_CTL) &

sys/dev/pci/drm/i915/display/intel_cdclk.c

896

ret = intel_pcode_write(display->drm, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);

sys/dev/pci/drm/i915/display/intel_cdclk.c

898

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.c

903

intel_de_rmw(display, LCPLL_CTL,

sys/dev/pci/drm/i915/display/intel_cdclk.c

910

ret = intel_de_wait_custom(display, LCPLL_CTL,

sys/dev/pci/drm/i915/display/intel_cdclk.c

914

drm_err(display->drm, "Switching to FCLK failed\n");

sys/dev/pci/drm/i915/display/intel_cdclk.c

916

intel_de_rmw(display, LCPLL_CTL,

sys/dev/pci/drm/i915/display/intel_cdclk.c

919

intel_de_rmw(display, LCPLL_CTL,

sys/dev/pci/drm/i915/display/intel_cdclk.c

922

ret = intel_de_wait_custom(display, LCPLL_CTL,

sys/dev/pci/drm/i915/display/intel_cdclk.c

926

drm_err(display->drm, "Switching back to LCPLL failed\n");

sys/dev/pci/drm/i915/display/intel_cdclk.c

928

intel_pcode_write(display->drm, HSW_PCODE_DE_WRITE_FREQ_REQ,

sys/dev/pci/drm/i915/display/intel_cdclk.c

931

intel_de_write(display, CDCLK_FREQ,

sys/dev/pci/drm/i915/display/intel_cdclk.c

934

intel_update_cdclk(display);

sys/dev/pci/drm/i915/display/intel_cdclk.c

972

static void skl_dpll0_update(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

980

val = intel_de_read(display, LCPLL1_CTL);

sys/dev/pci/drm/i915/display/intel_cdclk.c

984

if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0))

sys/dev/pci/drm/i915/display/intel_cdclk.c

987

val = intel_de_read(display, DPLL_CTRL1);

sys/dev/pci/drm/i915/display/intel_cdclk.c

989

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_cdclk.h

25

void intel_cdclk_init_hw(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_cdclk.h

26

void intel_cdclk_uninit_hw(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_cdclk.h

27

void intel_init_cdclk_hooks(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_cdclk.h

28

void intel_update_max_cdclk(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_cdclk.h

29

void intel_update_cdclk(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_cdclk.h

30

u32 intel_read_rawclk(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_cdclk.h

33

int intel_mdclk_cdclk_ratio(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.h

38

void intel_cdclk_dump_config(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.h

42

void intel_cdclk_get_cdclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.h

49

void intel_cdclk_update_hw_state(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_cdclk.h

60

int intel_cdclk_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_cdclk.h

61

void intel_cdclk_debugfs_register(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_cdclk.h

70

void intel_cdclk_read_hw(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_cmtg.c

102

static void intel_cmtg_get_config(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cmtg.c

107

val = intel_de_read(display, TRANS_CMTG_CTL_A);

sys/dev/pci/drm/i915/display/intel_cmtg.c

110

if (intel_cmtg_has_cmtg_b(display)) {

sys/dev/pci/drm/i915/display/intel_cmtg.c

111

val = intel_de_read(display, TRANS_CMTG_CTL_B);

sys/dev/pci/drm/i915/display/intel_cmtg.c

115

cmtg_config->trans_a_secondary = intel_cmtg_transcoder_is_secondary(display, TRANSCODER_A);

sys/dev/pci/drm/i915/display/intel_cmtg.c

116

cmtg_config->trans_b_secondary = intel_cmtg_transcoder_is_secondary(display, TRANSCODER_B);

sys/dev/pci/drm/i915/display/intel_cmtg.c

119

static bool intel_cmtg_disable_requires_modeset(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cmtg.c

122

if (DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/intel_cmtg.c

128

static void intel_cmtg_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cmtg.c

135

intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_A),

sys/dev/pci/drm/i915/display/intel_cmtg.c

139

intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_B),

sys/dev/pci/drm/i915/display/intel_cmtg.c

143

drm_dbg_kms(display->drm, "Disabling CMTG A\n");

sys/dev/pci/drm/i915/display/intel_cmtg.c

144

intel_de_rmw(display, TRANS_CMTG_CTL_A, CMTG_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_cmtg.c

150

drm_dbg_kms(display->drm, "Disabling CMTG B\n");

sys/dev/pci/drm/i915/display/intel_cmtg.c

151

intel_de_rmw(display, TRANS_CMTG_CTL_B, CMTG_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_cmtg.c

156

if (intel_cmtg_has_clock_sel(display) && clk_sel_clr)

sys/dev/pci/drm/i915/display/intel_cmtg.c

157

intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);

sys/dev/pci/drm/i915/display/intel_cmtg.c

168

void intel_cmtg_sanitize(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cmtg.c

172

if (!HAS_CMTG(display))

sys/dev/pci/drm/i915/display/intel_cmtg.c

175

intel_cmtg_get_config(display, &cmtg_config);

sys/dev/pci/drm/i915/display/intel_cmtg.c

176

intel_cmtg_dump_config(display, &cmtg_config);

sys/dev/pci/drm/i915/display/intel_cmtg.c

184

if (intel_cmtg_disable_requires_modeset(display, &cmtg_config))

sys/dev/pci/drm/i915/display/intel_cmtg.c

187

intel_cmtg_disable(display, &cmtg_config);

sys/dev/pci/drm/i915/display/intel_cmtg.c

63

static bool intel_cmtg_has_cmtg_b(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cmtg.c

65

return DISPLAY_VER(display) >= 20;

sys/dev/pci/drm/i915/display/intel_cmtg.c

68

static bool intel_cmtg_has_clock_sel(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cmtg.c

70

return DISPLAY_VER(display) >= 14;

sys/dev/pci/drm/i915/display/intel_cmtg.c

73

static void intel_cmtg_dump_config(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cmtg.c

76

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cmtg.c

79

intel_cmtg_has_cmtg_b(display) ? str_enabled_disabled(cmtg_config->cmtg_b_enable) : "n/a",

sys/dev/pci/drm/i915/display/intel_cmtg.c

84

static bool intel_cmtg_transcoder_is_secondary(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cmtg.c

91

if (!HAS_TRANSCODER(display, trans))

sys/dev/pci/drm/i915/display/intel_cmtg.c

96

with_intel_display_power_if_enabled(display, power_domain, wakeref)

sys/dev/pci/drm/i915/display/intel_cmtg.c

97

val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, trans));

sys/dev/pci/drm/i915/display/intel_cmtg.h

11

void intel_cmtg_sanitize(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_color.c

1026

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

1031

intel_de_write_fw(display, PIPE_CSC_MODE(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1039

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

1041

intel_de_write(display, GAMMA_MODE(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1044

intel_de_write_fw(display, PIPE_CSC_MODE(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1050

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

1052

return intel_de_read(display, GAMMA_MODE(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_color.c

1057

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

1059

return intel_de_read(display, PIPE_CSC_MODE(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_color.c

1064

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1070

tmp = intel_de_read(display, DSPCNTR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/intel_color.c

1075

if (!HAS_GMCH(display) && tmp & DISP_PIPE_CSC_ENABLE)

sys/dev/pci/drm/i915/display/intel_color.c

1091

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1098

tmp = intel_de_read(display, SKL_BOTTOM_COLOR(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_color.c

1110

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1127

intel_de_write_dsb(display, dsb, SKL_BOTTOM_COLOR(pipe), val);

sys/dev/pci/drm/i915/display/intel_color.c

1129

intel_de_write_dsb(display, dsb, GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);

sys/dev/pci/drm/i915/display/intel_color.c

1131

intel_de_write_dsb(display, dsb, PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);

sys/dev/pci/drm/i915/display/intel_color.c

1137

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1145

intel_de_write_dsb(display, dsb, SKL_BOTTOM_COLOR(pipe), 0);

sys/dev/pci/drm/i915/display/intel_color.c

1147

intel_de_write_dsb(display, dsb, GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);

sys/dev/pci/drm/i915/display/intel_color.c

1149

intel_de_write_dsb(display, dsb, PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);

sys/dev/pci/drm/i915/display/intel_color.c

1154

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1171

intel_de_read_fw(display, PIPE_CSC_PREOFF_HI(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_color.c

1175

create_linear_lut(struct intel_display *display, int lut_size)

sys/dev/pci/drm/i915/display/intel_color.c

1181

blob = drm_property_create_blob(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

1209

create_resized_lut(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_color.c

1218

blob_out = drm_property_create_blob(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

1246

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

1257

intel_de_write_fw(display, PALETTE(display, pipe, i),

sys/dev/pci/drm/i915/display/intel_color.c

1264

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

1270

intel_de_write_fw(display,

sys/dev/pci/drm/i915/display/intel_color.c

1271

PALETTE(display, pipe, 2 * i + 0),

sys/dev/pci/drm/i915/display/intel_color.c

1273

intel_de_write_fw(display,

sys/dev/pci/drm/i915/display/intel_color.c

1274

PALETTE(display, pipe, 2 * i + 1),

sys/dev/pci/drm/i915/display/intel_color.c

1300

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

1306

intel_de_write_fw(display,

sys/dev/pci/drm/i915/display/intel_color.c

1307

PALETTE(display, pipe, 2 * i + 0),

sys/dev/pci/drm/i915/display/intel_color.c

1309

intel_de_write_fw(display,

sys/dev/pci/drm/i915/display/intel_color.c

1310

PALETTE(display, pipe, 2 * i + 1),

sys/dev/pci/drm/i915/display/intel_color.c

1314

intel_de_write_fw(display, PIPEGCMAX(display, pipe, 0), lut[i].red);

sys/dev/pci/drm/i915/display/intel_color.c

1315

intel_de_write_fw(display, PIPEGCMAX(display, pipe, 1), lut[i].green);

sys/dev/pci/drm/i915/display/intel_color.c

1316

intel_de_write_fw(display, PIPEGCMAX(display, pipe, 2), lut[i].blue);

sys/dev/pci/drm/i915/display/intel_color.c

1340

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1345

intel_de_write_fw(display, reg, val);

sys/dev/pci/drm/i915/display/intel_color.c

1351

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1356

intel_de_write_fw(display, reg, val);

sys/dev/pci/drm/i915/display/intel_color.c

1573

static int glk_degamma_lut_size(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_color.c

1575

if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/intel_color.c

1607

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1639

DISPLAY_VER(display) >= 14 ?

sys/dev/pci/drm/i915/display/intel_color.c

1644

while (i++ < glk_degamma_lut_size(display))

sys/dev/pci/drm/i915/display/intel_color.c

1646

DISPLAY_VER(display) >= 14 ?

sys/dev/pci/drm/i915/display/intel_color.c

1847

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

1853

intel_de_write_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 0),

sys/dev/pci/drm/i915/display/intel_color.c

1855

intel_de_write_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 1),

sys/dev/pci/drm/i915/display/intel_color.c

1881

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

1887

intel_de_write_fw(display, CGM_PIPE_GAMMA(pipe, i, 0),

sys/dev/pci/drm/i915/display/intel_color.c

1889

intel_de_write_fw(display, CGM_PIPE_GAMMA(pipe, i, 1),

sys/dev/pci/drm/i915/display/intel_color.c

1896

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1912

intel_de_write_fw(display, CGM_PIPE_MODE(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1918

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1923

display->funcs.color->load_luts(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1929

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1931

if (display->funcs.color->color_commit_noarm)

sys/dev/pci/drm/i915/display/intel_color.c

1932

display->funcs.color->color_commit_noarm(dsb, crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1938

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1940

display->funcs.color->color_commit_arm(dsb, crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1945

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1947

if (display->funcs.color->color_post_update)

sys/dev/pci/drm/i915/display/intel_color.c

1948

display->funcs.color->color_post_update(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1953

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1959

if (DISPLAY_VER(display) < 9) {

sys/dev/pci/drm/i915/display/intel_color.c

1975

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1977

return crtc_state->dsb_color && !HAS_DOUBLE_BUFFERED_LUT(display);

sys/dev/pci/drm/i915/display/intel_color.c

1982

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1984

return crtc_state->dsb_color && HAS_DOUBLE_BUFFERED_LUT(display);

sys/dev/pci/drm/i915/display/intel_color.c

1990

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_color.c

2004

if (HAS_DOUBLE_BUFFERED_LUT(display))

sys/dev/pci/drm/i915/display/intel_color.c

2012

display->funcs.color->load_luts(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2044

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_color.c

2048

if (HAS_DOUBLE_BUFFERED_LUT(display))

sys/dev/pci/drm/i915/display/intel_color.c

2087

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_color.c

2103

return display->funcs.color->color_check(state, crtc);

sys/dev/pci/drm/i915/display/intel_color.c

2108

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2110

display->funcs.color->get_config(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2112

display->funcs.color->read_luts(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2114

if (display->funcs.color->read_csc)

sys/dev/pci/drm/i915/display/intel_color.c

2115

display->funcs.color->read_csc(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2123

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2132

return display->funcs.color->lut_equal(crtc_state, blob1, blob2,

sys/dev/pci/drm/i915/display/intel_color.c

2139

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_color.c

2147

(DISPLAY_VER(display) < 9 && plane->id == PLANE_PRIMARY);

sys/dev/pci/drm/i915/display/intel_color.c

2154

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_color.c

2169

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/intel_color.c

218

struct intel_display *display = to_intel_display(crtc->base.dev);

sys/dev/pci/drm/i915/display/intel_color.c

2184

if (HAS_GMCH(display))

sys/dev/pci/drm/i915/display/intel_color.c

2193

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2199

return DISPLAY_INFO(display)->color.gamma_lut_tests;

sys/dev/pci/drm/i915/display/intel_color.c

2204

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2206

return DISPLAY_INFO(display)->color.degamma_lut_tests;

sys/dev/pci/drm/i915/display/intel_color.c

221

intel_de_write_dsb(display, dsb, PIPE_CSC_PREOFF_HI(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

2211

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2217

return DISPLAY_INFO(display)->color.gamma_lut_size;

sys/dev/pci/drm/i915/display/intel_color.c

2222

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2224

return DISPLAY_INFO(display)->color.degamma_lut_size;

sys/dev/pci/drm/i915/display/intel_color.c

223

intel_de_write_dsb(display, dsb, PIPE_CSC_PREOFF_ME(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

2230

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

2238

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

225

intel_de_write_dsb(display, dsb, PIPE_CSC_PREOFF_LO(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

2250

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2258

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

228

intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_RY_GY(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

230

intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_BY(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

2303

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

2312

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

2323

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2326

if (DISPLAY_VER(display) >= 11 || HAS_GMCH(display)) {

sys/dev/pci/drm/i915/display/intel_color.c

2327

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

2329

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

233

intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_RU_GU(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

2331

} else if (DISPLAY_VER(display) == 10) {

sys/dev/pci/drm/i915/display/intel_color.c

2332

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

2335

crtc_state->pre_csc_lut != display->color.glk_linear_degamma_lut);

sys/dev/pci/drm/i915/display/intel_color.c

2336

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

2341

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

2344

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

235

intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_BU(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

2362

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_color.c

2377

if (DISPLAY_VER(display) < 4 &&

sys/dev/pci/drm/i915/display/intel_color.c

238

intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_RV_GV(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

240

intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_BV(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

243

if (DISPLAY_VER(display) < 7)

sys/dev/pci/drm/i915/display/intel_color.c

246

intel_de_write_dsb(display, dsb, PIPE_CSC_POSTOFF_HI(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

248

intel_de_write_dsb(display, dsb, PIPE_CSC_POSTOFF_ME(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

250

intel_de_write_dsb(display, dsb, PIPE_CSC_POSTOFF_LO(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

2546

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2551

gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut,

sys/dev/pci/drm/i915/display/intel_color.c

257

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

2585

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_color.c

2595

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

2603

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

261

csc->preoff[0] = intel_de_read_fw(display, PIPE_CSC_PREOFF_HI(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

262

csc->preoff[1] = intel_de_read_fw(display, PIPE_CSC_PREOFF_ME(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

263

csc->preoff[2] = intel_de_read_fw(display, PIPE_CSC_PREOFF_LO(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

265

tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_RY_GY(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

2658

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2664

drm_WARN_ON(display->drm, drm_color_lut_size(crtc_state->hw.degamma_lut) != 1024);

sys/dev/pci/drm/i915/display/intel_color.c

2665

drm_WARN_ON(display->drm, drm_color_lut_size(crtc_state->hw.gamma_lut) != 1024);

sys/dev/pci/drm/i915/display/intel_color.c

2667

degamma_lut = create_resized_lut(display, crtc_state->hw.degamma_lut, 512,

sys/dev/pci/drm/i915/display/intel_color.c

2672

gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut, 512,

sys/dev/pci/drm/i915/display/intel_color.c

268

tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_BY(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

2691

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_color.c

2701

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

2709

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

271

tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_RU_GU(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

2717

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

274

tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_BU(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

2764

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2769

gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut,

sys/dev/pci/drm/i915/display/intel_color.c

277

tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_RV_GV(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

2770

DISPLAY_INFO(display)->color.degamma_lut_size,

sys/dev/pci/drm/i915/display/intel_color.c

2786

gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut,

sys/dev/pci/drm/i915/display/intel_color.c

280

tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_BV(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

2809

display->color.glk_linear_degamma_lut);

sys/dev/pci/drm/i915/display/intel_color.c

2828

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_color.c

283

if (DISPLAY_VER(display) < 7)

sys/dev/pci/drm/i915/display/intel_color.c

2839

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

2847

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

286

csc->postoff[0] = intel_de_read_fw(display, PIPE_CSC_POSTOFF_HI(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

287

csc->postoff[1] = intel_de_read_fw(display, PIPE_CSC_POSTOFF_ME(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

288

csc->postoff[2] = intel_de_read_fw(display, PIPE_CSC_POSTOFF_LO(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

2886

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2904

else if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/intel_color.c

324

struct intel_display *display = to_intel_display(crtc->base.dev);

sys/dev/pci/drm/i915/display/intel_color.c

327

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_PREOFF_HI(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3285

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

329

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_PREOFF_ME(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3291

blob = drm_property_create_blob(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

3300

u32 val = intel_de_read_fw(display,

sys/dev/pci/drm/i915/display/intel_color.c

3301

PALETTE(display, pipe, i));

sys/dev/pci/drm/i915/display/intel_color.c

331

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_PREOFF_LO(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3311

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

3312

u32 lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;

sys/dev/pci/drm/i915/display/intel_color.c

3319

blob = drm_property_create_blob(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

3327

ldw = intel_de_read_fw(display,

sys/dev/pci/drm/i915/display/intel_color.c

3328

PALETTE(display, pipe, 2 * i + 0));

sys/dev/pci/drm/i915/display/intel_color.c

3329

udw = intel_de_read_fw(display,

sys/dev/pci/drm/i915/display/intel_color.c

3330

PALETTE(display, pipe, 2 * i + 1));

sys/dev/pci/drm/i915/display/intel_color.c

334

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

336

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_BY(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3362

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

3363

int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;

sys/dev/pci/drm/i915/display/intel_color.c

3368

blob = drm_property_create_blob(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

3377

u32 ldw = intel_de_read_fw(display,

sys/dev/pci/drm/i915/display/intel_color.c

3378

PALETTE(display, pipe, 2 * i + 0));

sys/dev/pci/drm/i915/display/intel_color.c

3379

u32 udw = intel_de_read_fw(display,

sys/dev/pci/drm/i915/display/intel_color.c

3380

PALETTE(display, pipe, 2 * i + 1));

sys/dev/pci/drm/i915/display/intel_color.c

3385

lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(display, PIPEGCMAX(display, pipe, 0)));

sys/dev/pci/drm/i915/display/intel_color.c

3386

lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(display, PIPEGCMAX(display, pipe, 1)));

sys/dev/pci/drm/i915/display/intel_color.c

3387

lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(display, PIPEGCMAX(display, pipe, 2)));

sys/dev/pci/drm/i915/display/intel_color.c

339

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

341

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_BU(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3414

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

3415

int i, lut_size = DISPLAY_INFO(display)->color.degamma_lut_size;

sys/dev/pci/drm/i915/display/intel_color.c

3420

blob = drm_property_create_blob(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

3429

u32 ldw = intel_de_read_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 0));

sys/dev/pci/drm/i915/display/intel_color.c

3430

u32 udw = intel_de_read_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 1));

sys/dev/pci/drm/i915/display/intel_color.c

344

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3440

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

3441

int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;

sys/dev/pci/drm/i915/display/intel_color.c

3446

blob = drm_property_create_blob(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

3455

u32 ldw = intel_de_read_fw(display, CGM_PIPE_GAMMA(pipe, i, 0));

sys/dev/pci/drm/i915/display/intel_color.c

3456

u32 udw = intel_de_read_fw(display, CGM_PIPE_GAMMA(pipe, i, 1));

sys/dev/pci/drm/i915/display/intel_color.c

346

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_BV(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3466

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

3469

crtc_state->cgm_mode = intel_de_read(display, CGM_PIPE_MODE(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3489

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

349

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3495

blob = drm_property_create_blob(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

3504

u32 val = intel_de_read_fw(display, LGC_PALETTE(pipe, i));

sys/dev/pci/drm/i915/display/intel_color.c

351

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3514

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

3515

int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;

sys/dev/pci/drm/i915/display/intel_color.c

3520

blob = drm_property_create_blob(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

3529

u32 val = intel_de_read_fw(display, PREC_PALETTE(pipe, i));

sys/dev/pci/drm/i915/display/intel_color.c

353

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3577

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

3583

blob = drm_property_create_blob(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

3594

intel_de_write_fw(display, PREC_PAL_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3596

val = intel_de_read_fw(display, PREC_PAL_DATA(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

360

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

3601

intel_de_write_fw(display, PREC_PAL_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

364

csc->preoff[0] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_PREOFF_HI(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3642

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

3648

blob = drm_property_create_blob(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

365

csc->preoff[1] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_PREOFF_ME(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3656

intel_de_write_fw(display, PREC_PAL_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3658

intel_de_write_fw(display, PREC_PAL_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

366

csc->preoff[2] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_PREOFF_LO(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3663

u32 val = intel_de_read_fw(display, PREC_PAL_DATA(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3668

intel_de_write_fw(display, PREC_PAL_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

368

tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3707

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

3708

int i, lut_size = DISPLAY_INFO(display)->color.degamma_lut_size;

sys/dev/pci/drm/i915/display/intel_color.c

371

tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_BY(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3713

blob = drm_property_create_blob(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

3726

intel_de_write_fw(display, PRE_CSC_GAMC_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3728

intel_de_write_fw(display, PRE_CSC_GAMC_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3733

u32 val = intel_de_read_fw(display, PRE_CSC_GAMC_DATA(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3735

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_color.c

374

tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3741

intel_de_write_fw(display, PRE_CSC_GAMC_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

377

tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_BU(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3773

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

3774

int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;

sys/dev/pci/drm/i915/display/intel_color.c

3779

blob = drm_property_create_blob(display->drm,

sys/dev/pci/drm/i915/display/intel_color.c

3787

intel_de_write_fw(display, PREC_PAL_MULTI_SEG_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3789

intel_de_write_fw(display, PREC_PAL_MULTI_SEG_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3794

u32 ldw = intel_de_read_fw(display, PREC_PAL_MULTI_SEG_DATA(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3795

u32 udw = intel_de_read_fw(display, PREC_PAL_MULTI_SEG_DATA(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

380

tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3800

intel_de_write_fw(display, PREC_PAL_MULTI_SEG_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

383

tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_BV(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

386

csc->postoff[0] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

387

csc->postoff[1] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

388

csc->postoff[2] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3967

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

3973

gamma_lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;

sys/dev/pci/drm/i915/display/intel_color.c

3974

degamma_lut_size = DISPLAY_INFO(display)->color.degamma_lut_size;

sys/dev/pci/drm/i915/display/intel_color.c

3975

has_ctm = DISPLAY_VER(display) >= 5;

sys/dev/pci/drm/i915/display/intel_color.c

3985

if (DISPLAY_VER(display) == 3 && crtc->pipe == PIPE_A)

sys/dev/pci/drm/i915/display/intel_color.c

3992

int intel_color_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_color.c

3996

if (DISPLAY_VER(display) != 10)

sys/dev/pci/drm/i915/display/intel_color.c

3999

blob = create_linear_lut(display,

sys/dev/pci/drm/i915/display/intel_color.c

4000

DISPLAY_INFO(display)->color.degamma_lut_size);

sys/dev/pci/drm/i915/display/intel_color.c

4004

display->color.glk_linear_degamma_lut = blob;

sys/dev/pci/drm/i915/display/intel_color.c

4009

void intel_color_init_hooks(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_color.c

4011

if (HAS_GMCH(display)) {

sys/dev/pci/drm/i915/display/intel_color.c

4012

if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_color.c

4013

display->funcs.color = &chv_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

4014

else if (display->platform.valleyview)

sys/dev/pci/drm/i915/display/intel_color.c

4015

display->funcs.color = &vlv_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

4016

else if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/intel_color.c

4017

display->funcs.color = &i965_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

4019

display->funcs.color = &i9xx_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

4021

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_color.c

4022

display->funcs.color = &tgl_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

4023

else if (DISPLAY_VER(display) == 11)

sys/dev/pci/drm/i915/display/intel_color.c

4024

display->funcs.color = &icl_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

4025

else if (DISPLAY_VER(display) == 10)

sys/dev/pci/drm/i915/display/intel_color.c

4026

display->funcs.color = &glk_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

4027

else if (DISPLAY_VER(display) == 9)

sys/dev/pci/drm/i915/display/intel_color.c

4028

display->funcs.color = &skl_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

4029

else if (DISPLAY_VER(display) == 8)

sys/dev/pci/drm/i915/display/intel_color.c

4030

display->funcs.color = &bdw_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

4031

else if (display->platform.haswell)

sys/dev/pci/drm/i915/display/intel_color.c

4032

display->funcs.color = &hsw_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

4033

else if (DISPLAY_VER(display) == 7)

sys/dev/pci/drm/i915/display/intel_color.c

4034

display->funcs.color = &ivb_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

4036

display->funcs.color = &ilk_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

409

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

412

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_color.c

416

if (DISPLAY_VER(display) < 7 || display->platform.ivybridge)

sys/dev/pci/drm/i915/display/intel_color.c

424

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

432

if (DISPLAY_VER(display) == 10)

sys/dev/pci/drm/i915/display/intel_color.c

447

static void ilk_csc_copy(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_color.c

453

if (DISPLAY_VER(display) < 7)

sys/dev/pci/drm/i915/display/intel_color.c

461

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

469

ilk_csc_copy(display, csc, &ilk_csc_matrix_limited_range);

sys/dev/pci/drm/i915/display/intel_color.c

471

ilk_csc_copy(display, csc, &ilk_csc_matrix_identity);

sys/dev/pci/drm/i915/display/intel_color.c

519

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

523

drm_WARN_ON(display->drm, !crtc_state->csc_enable);

sys/dev/pci/drm/i915/display/intel_color.c

527

drm_WARN_ON(display->drm, !crtc_state->csc_enable);

sys/dev/pci/drm/i915/display/intel_color.c

529

ilk_csc_copy(display, &crtc_state->csc, &ilk_csc_matrix_rgb_to_ycbcr);

sys/dev/pci/drm/i915/display/intel_color.c

531

drm_WARN_ON(display->drm, !crtc_state->csc_enable);

sys/dev/pci/drm/i915/display/intel_color.c

533

ilk_csc_copy(display, &crtc_state->csc, &ilk_csc_matrix_limited_range);

sys/dev/pci/drm/i915/display/intel_color.c

541

drm_WARN_ON(display->drm, !display->platform.geminilake);

sys/dev/pci/drm/i915/display/intel_color.c

543

ilk_csc_copy(display, &crtc_state->csc, &ilk_csc_matrix_identity);

sys/dev/pci/drm/i915/display/intel_color.c

560

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

563

drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_CSC_ENABLE) == 0);

sys/dev/pci/drm/i915/display/intel_color.c

567

drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_CSC_ENABLE) != 0);

sys/dev/pci/drm/i915/display/intel_color.c

573

drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) == 0);

sys/dev/pci/drm/i915/display/intel_color.c

575

ilk_csc_copy(display, &crtc_state->output_csc, &ilk_csc_matrix_rgb_to_ycbcr);

sys/dev/pci/drm/i915/display/intel_color.c

577

drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) == 0);

sys/dev/pci/drm/i915/display/intel_color.c

579

ilk_csc_copy(display, &crtc_state->output_csc, &ilk_csc_matrix_limited_range);

sys/dev/pci/drm/i915/display/intel_color.c

581

drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) != 0);

sys/dev/pci/drm/i915/display/intel_color.c

639

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

642

intel_de_write_fw(display, PIPE_WGC_C01_C00(display, pipe),

sys/dev/pci/drm/i915/display/intel_color.c

644

intel_de_write_fw(display, PIPE_WGC_C02(display, pipe),

sys/dev/pci/drm/i915/display/intel_color.c

647

intel_de_write_fw(display, PIPE_WGC_C11_C10(display, pipe),

sys/dev/pci/drm/i915/display/intel_color.c

649

intel_de_write_fw(display, PIPE_WGC_C12(display, pipe),

sys/dev/pci/drm/i915/display/intel_color.c

652

intel_de_write_fw(display, PIPE_WGC_C21_C20(display, pipe),

sys/dev/pci/drm/i915/display/intel_color.c

654

intel_de_write_fw(display, PIPE_WGC_C22(display, pipe),

sys/dev/pci/drm/i915/display/intel_color.c

661

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

665

tmp = intel_de_read_fw(display, PIPE_WGC_C01_C00(display, pipe));

sys/dev/pci/drm/i915/display/intel_color.c

669

tmp = intel_de_read_fw(display, PIPE_WGC_C02(display, pipe));

sys/dev/pci/drm/i915/display/intel_color.c

672

tmp = intel_de_read_fw(display, PIPE_WGC_C11_C10(display, pipe));

sys/dev/pci/drm/i915/display/intel_color.c

676

tmp = intel_de_read_fw(display, PIPE_WGC_C12(display, pipe));

sys/dev/pci/drm/i915/display/intel_color.c

679

tmp = intel_de_read_fw(display, PIPE_WGC_C21_C20(display, pipe));

sys/dev/pci/drm/i915/display/intel_color.c

683

tmp = intel_de_read_fw(display, PIPE_WGC_C22(display, pipe));

sys/dev/pci/drm/i915/display/intel_color.c

697

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

700

drm_WARN_ON(display->drm, !crtc_state->wgc_enable);

sys/dev/pci/drm/i915/display/intel_color.c

704

drm_WARN_ON(display->drm, crtc_state->wgc_enable);

sys/dev/pci/drm/i915/display/intel_color.c

741

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

744

intel_de_write_fw(display, CGM_PIPE_CSC_COEFF01(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

746

intel_de_write_fw(display, CGM_PIPE_CSC_COEFF23(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

748

intel_de_write_fw(display, CGM_PIPE_CSC_COEFF45(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

750

intel_de_write_fw(display, CGM_PIPE_CSC_COEFF67(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

752

intel_de_write_fw(display, CGM_PIPE_CSC_COEFF8(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

759

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_color.c

763

tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF01(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

767

tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF23(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

771

tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF45(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

775

tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF67(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

779

tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF8(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

793

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

795

drm_WARN_ON(display->drm, crtc_state->wgc_enable);

sys/dev/pci/drm/i915/display/intel_color.c

798

drm_WARN_ON(display->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) == 0);

sys/dev/pci/drm/i915/display/intel_color.c

802

drm_WARN_ON(display->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) == 0);

sys/dev/pci/drm/i915/display/intel_color.h

18

void intel_color_init_hooks(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_color.h

19

int intel_color_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

101

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_combo_phy.c

112

static bool icl_verify_procmon_ref_values(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_combo_phy.c

118

procmon = icl_get_procmon_ref_values(display, phy);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

120

ret = check_phy_reg(display, phy, ICL_PORT_COMP_DW1(phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

122

ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW9(phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

124

ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW10(phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

130

static bool has_phy_misc(struct intel_display *display, enum phy phy)

sys/dev/pci/drm/i915/display/intel_combo_phy.c

141

if (display->platform.alderlake_s)

sys/dev/pci/drm/i915/display/intel_combo_phy.c

143

else if ((display->platform.jasperlake || display->platform.elkhartlake) ||

sys/dev/pci/drm/i915/display/intel_combo_phy.c

144

display->platform.rocketlake ||

sys/dev/pci/drm/i915/display/intel_combo_phy.c

145

display->platform.dg1)

sys/dev/pci/drm/i915/display/intel_combo_phy.c

151

static bool icl_combo_phy_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_combo_phy.c

155

if (!has_phy_misc(display, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy.c

156

return intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT;

sys/dev/pci/drm/i915/display/intel_combo_phy.c

158

return !(intel_de_read(display, ICL_PHY_MISC(phy)) &

sys/dev/pci/drm/i915/display/intel_combo_phy.c

160

(intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

163

static bool ehl_vbt_ddi_d_present(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_combo_phy.c

165

bool ddi_a_present = intel_bios_is_port_present(display, PORT_A);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

166

bool ddi_d_present = intel_bios_is_port_present(display, PORT_D);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

167

bool dsi_present = intel_bios_is_dsi_present(display, NULL);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

184

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_combo_phy.c

190

static bool phy_is_master(struct intel_display *display, enum phy phy)

sys/dev/pci/drm/i915/display/intel_combo_phy.c

210

else if (display->platform.alderlake_s)

sys/dev/pci/drm/i915/display/intel_combo_phy.c

212

else if (display->platform.dg1 || display->platform.rocketlake)

sys/dev/pci/drm/i915/display/intel_combo_phy.c

218

static bool icl_combo_phy_verify_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_combo_phy.c

224

if (!icl_combo_phy_enabled(display, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy.c

227

if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_combo_phy.c

228

ret &= check_phy_reg(display, phy, ICL_PORT_TX_DW8_LN(0, phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

234

ret &= check_phy_reg(display, phy, ICL_PORT_PCS_DW1_LN(0, phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

238

ret &= icl_verify_procmon_ref_values(display, phy);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

240

if (phy_is_master(display, phy)) {

sys/dev/pci/drm/i915/display/intel_combo_phy.c

241

ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW8(phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

244

if (display->platform.jasperlake || display->platform.elkhartlake) {

sys/dev/pci/drm/i915/display/intel_combo_phy.c

245

if (ehl_vbt_ddi_d_present(display))

sys/dev/pci/drm/i915/display/intel_combo_phy.c

248

ret &= check_phy_reg(display, phy, ICL_PHY_MISC(phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

254

ret &= check_phy_reg(display, phy, ICL_PORT_CL_DW5(phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

260

void intel_combo_phy_power_up_lanes(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_combo_phy.c

267

drm_WARN_ON(display->drm, lane_reversal);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

305

intel_de_rmw(display, ICL_PORT_CL_DW10(phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

309

static void icl_combo_phys_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_combo_phy.c

313

for_each_combo_phy(display, phy) {

sys/dev/pci/drm/i915/display/intel_combo_phy.c

317

if (icl_combo_phy_verify_state(display, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy.c

320

procmon = icl_get_procmon_ref_values(display, phy);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

322

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_combo_phy.c

326

if (!has_phy_misc(display, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy.c

337

val = intel_de_read(display, ICL_PHY_MISC(phy));

sys/dev/pci/drm/i915/display/intel_combo_phy.c

338

if ((display->platform.jasperlake || display->platform.elkhartlake) &&

sys/dev/pci/drm/i915/display/intel_combo_phy.c

342

if (ehl_vbt_ddi_d_present(display))

sys/dev/pci/drm/i915/display/intel_combo_phy.c

347

intel_de_write(display, ICL_PHY_MISC(phy), val);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

350

if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_combo_phy.c

351

val = intel_de_read(display, ICL_PORT_TX_DW8_LN(0, phy));

sys/dev/pci/drm/i915/display/intel_combo_phy.c

355

intel_de_write(display, ICL_PORT_TX_DW8_GRP(phy), val);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

357

val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));

sys/dev/pci/drm/i915/display/intel_combo_phy.c

360

intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

363

icl_set_procmon_ref_values(display, phy);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

365

if (phy_is_master(display, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy.c

366

intel_de_rmw(display, ICL_PORT_COMP_DW8(phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

369

intel_de_rmw(display, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

370

intel_de_rmw(display, ICL_PORT_CL_DW5(phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

375

static void icl_combo_phys_uninit(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_combo_phy.c

379

for_each_combo_phy_reverse(display, phy) {

sys/dev/pci/drm/i915/display/intel_combo_phy.c

381

!icl_combo_phy_verify_state(display, phy)) {

sys/dev/pci/drm/i915/display/intel_combo_phy.c

382

if (display->platform.tigerlake || display->platform.dg1) {

sys/dev/pci/drm/i915/display/intel_combo_phy.c

388

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_combo_phy.c

392

drm_warn(display->drm,

sys/dev/pci/drm/i915/display/intel_combo_phy.c

398

if (!has_phy_misc(display, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy.c

401

intel_de_rmw(display, ICL_PHY_MISC(phy), 0,

sys/dev/pci/drm/i915/display/intel_combo_phy.c

405

intel_de_rmw(display, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

409

void intel_combo_phy_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_combo_phy.c

411

icl_combo_phys_init(display);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

414

void intel_combo_phy_uninit(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_combo_phy.c

416

icl_combo_phys_uninit(display);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

58

icl_get_procmon_ref_values(struct intel_display *display, enum phy phy)

sys/dev/pci/drm/i915/display/intel_combo_phy.c

62

val = intel_de_read(display, ICL_PORT_COMP_DW3(phy));

sys/dev/pci/drm/i915/display/intel_combo_phy.c

80

static void icl_set_procmon_ref_values(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_combo_phy.c

85

procmon = icl_get_procmon_ref_values(display, phy);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

87

intel_de_rmw(display, ICL_PORT_COMP_DW1(phy),

sys/dev/pci/drm/i915/display/intel_combo_phy.c

90

intel_de_write(display, ICL_PORT_COMP_DW9(phy), procmon->dw9);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

91

intel_de_write(display, ICL_PORT_COMP_DW10(phy), procmon->dw10);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

94

static bool check_phy_reg(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_combo_phy.c

98

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_combo_phy.h

14

void intel_combo_phy_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_combo_phy.h

15

void intel_combo_phy_uninit(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_combo_phy.h

16

void intel_combo_phy_power_up_lanes(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_connector.c

209

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_connector.c

211

drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_connector.c

268

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_connector.c

271

prop = display->properties.force_audio;

sys/dev/pci/drm/i915/display/intel_connector.c

273

prop = drm_property_create_enum(display->drm, 0,

sys/dev/pci/drm/i915/display/intel_connector.c

280

display->properties.force_audio = prop;

sys/dev/pci/drm/i915/display/intel_connector.c

294

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_connector.c

297

prop = display->properties.broadcast_rgb;

sys/dev/pci/drm/i915/display/intel_connector.c

299

prop = drm_property_create_enum(display->drm, DRM_MODE_PROP_ENUM,

sys/dev/pci/drm/i915/display/intel_connector.c

306

display->properties.broadcast_rgb = prop;

sys/dev/pci/drm/i915/display/intel_connector.c

338

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_connector.c

345

if (!HAS_GMCH(display) || connector->connector_type == DRM_MODE_CONNECTOR_LVDS)

sys/dev/pci/drm/i915/display/intel_connector.c

46

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_connector.c

48

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", connector->base.base.id,

sys/dev/pci/drm/i915/display/intel_connector.c

52

mutex_lock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/intel_connector.c

58

mutex_unlock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/intel_connector.c

67

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_connector.c

70

if (!queue_work(display->wq.unordered, &connector->modeset_retry_work))

sys/dev/pci/drm/i915/display/intel_crt.c

1006

void intel_crt_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_crt.c

1014

if (HAS_PCH_SPLIT(display))

sys/dev/pci/drm/i915/display/intel_crt.c

1016

else if (display->platform.valleyview)

sys/dev/pci/drm/i915/display/intel_crt.c

1021

adpa = intel_de_read(display, adpa_reg);

sys/dev/pci/drm/i915/display/intel_crt.c

1031

intel_de_write(display, adpa_reg,

sys/dev/pci/drm/i915/display/intel_crt.c

1035

if ((intel_de_read(display, adpa_reg) & ADPA_DAC_ENABLE) == 0)

sys/dev/pci/drm/i915/display/intel_crt.c

1037

intel_de_write(display, adpa_reg, adpa);

sys/dev/pci/drm/i915/display/intel_crt.c

1050

ddc_pin = display->vbt.crt_ddc_pin;

sys/dev/pci/drm/i915/display/intel_crt.c

1052

drm_connector_init_with_ddc(display->drm, &connector->base,

sys/dev/pci/drm/i915/display/intel_crt.c

1055

intel_gmbus_get_adapter(display, ddc_pin));

sys/dev/pci/drm/i915/display/intel_crt.c

1057

drm_encoder_init(display->drm, &crt->base.base, &intel_crt_enc_funcs,

sys/dev/pci/drm/i915/display/intel_crt.c

1064

if (display->platform.i830)

sys/dev/pci/drm/i915/display/intel_crt.c

1069

if (DISPLAY_VER(display) != 2)

sys/dev/pci/drm/i915/display/intel_crt.c

1076

if (HAS_HOTPLUG(display) &&

sys/dev/pci/drm/i915/display/intel_crt.c

1086

if (HAS_DDI(display)) {

sys/dev/pci/drm/i915/display/intel_crt.c

1087

assert_port_valid(display, PORT_E);

sys/dev/pci/drm/i915/display/intel_crt.c

110

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_crt.c

1104

if (HAS_PCH_SPLIT(display)) {

sys/dev/pci/drm/i915/display/intel_crt.c

1126

if (HAS_PCH_LPT(display)) {

sys/dev/pci/drm/i915/display/intel_crt.c

1130

display->fdi.rx_config = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_crt.c

115

wakeref = intel_display_power_get_if_enabled(display,

sys/dev/pci/drm/i915/display/intel_crt.c

120

ret = intel_crt_port_enabled(display, crt->adpa_reg, pipe);

sys/dev/pci/drm/i915/display/intel_crt.c

122

intel_display_power_put(display, encoder->power_domain, wakeref);

sys/dev/pci/drm/i915/display/intel_crt.c

129

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_crt.c

133

tmp = intel_de_read(display, crt->adpa_reg);

sys/dev/pci/drm/i915/display/intel_crt.c

178

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_crt.c

184

if (DISPLAY_VER(display) >= 5)

sys/dev/pci/drm/i915/display/intel_crt.c

195

if (HAS_PCH_LPT(display))

sys/dev/pci/drm/i915/display/intel_crt.c

197

else if (HAS_PCH_CPT(display))

sys/dev/pci/drm/i915/display/intel_crt.c

202

if (!HAS_PCH_SPLIT(display))

sys/dev/pci/drm/i915/display/intel_crt.c

203

intel_de_write(display, BCLRPAT(display, crtc->pipe), 0);

sys/dev/pci/drm/i915/display/intel_crt.c

220

intel_de_write(display, crt->adpa_reg, adpa);

sys/dev/pci/drm/i915/display/intel_crt.c

251

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_crt.c

253

drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);

sys/dev/pci/drm/i915/display/intel_crt.c

255

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);

sys/dev/pci/drm/i915/display/intel_crt.c

263

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_crt.c

282

drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);

sys/dev/pci/drm/i915/display/intel_crt.c

284

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

sys/dev/pci/drm/i915/display/intel_crt.c

292

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_crt.c

294

drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);

sys/dev/pci/drm/i915/display/intel_crt.c

296

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);

sys/dev/pci/drm/i915/display/intel_crt.c

304

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_crt.c

308

drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);

sys/dev/pci/drm/i915/display/intel_crt.c

310

intel_set_cpu_fifo_underrun_reporting(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_crt.c

322

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_crt.c

326

drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);

sys/dev/pci/drm/i915/display/intel_crt.c

340

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_crt.c

341

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

sys/dev/pci/drm/i915/display/intel_crt.c

356

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_crt.c

357

int max_dotclk = display->cdclk.max_dotclk_freq;

sys/dev/pci/drm/i915/display/intel_crt.c

361

status = intel_cpu_transcoder_mode_valid(display, mode);

sys/dev/pci/drm/i915/display/intel_crt.c

368

if (HAS_PCH_LPT(display))

sys/dev/pci/drm/i915/display/intel_crt.c

370

else if (display->platform.valleyview)

sys/dev/pci/drm/i915/display/intel_crt.c

376

else if (IS_DISPLAY_VER(display, 3, 4))

sys/dev/pci/drm/i915/display/intel_crt.c

387

if (HAS_PCH_LPT(display) &&

sys/dev/pci/drm/i915/display/intel_crt.c

437

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_crt.c

456

if (HAS_PCH_LPT(display)) {

sys/dev/pci/drm/i915/display/intel_crt.c

459

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_crt.c

479

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_crt.c

486

bool turn_off_dac = HAS_PCH_SPLIT(display);

sys/dev/pci/drm/i915/display/intel_crt.c

491

save_adpa = adpa = intel_de_read(display, crt->adpa_reg);

sys/dev/pci/drm/i915/display/intel_crt.c

492

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_crt.c

499

intel_de_write(display, crt->adpa_reg, adpa);

sys/dev/pci/drm/i915/display/intel_crt.c

501

if (intel_de_wait_for_clear(display,

sys/dev/pci/drm/i915/display/intel_crt.c

505

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_crt.c

509

intel_de_write(display, crt->adpa_reg, save_adpa);

sys/dev/pci/drm/i915/display/intel_crt.c

510

intel_de_posting_read(display, crt->adpa_reg);

sys/dev/pci/drm/i915/display/intel_crt.c

515

adpa = intel_de_read(display, crt->adpa_reg);

sys/dev/pci/drm/i915/display/intel_crt.c

520

drm_dbg_kms(display->drm, "ironlake hotplug adpa=0x%x, result %d\n",

sys/dev/pci/drm/i915/display/intel_crt.c

528

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_crt.c

548

save_adpa = adpa = intel_de_read(display, crt->adpa_reg);

sys/dev/pci/drm/i915/display/intel_crt.c

549

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_crt.c

554

intel_de_write(display, crt->adpa_reg, adpa);

sys/dev/pci/drm/i915/display/intel_crt.c

556

if (intel_de_wait_for_clear(display, crt->adpa_reg,

sys/dev/pci/drm/i915/display/intel_crt.c

558

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_crt.c

560

intel_de_write(display, crt->adpa_reg, save_adpa);

sys/dev/pci/drm/i915/display/intel_crt.c

564

adpa = intel_de_read(display, crt->adpa_reg);

sys/dev/pci/drm/i915/display/intel_crt.c

570

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_crt.c

580

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_crt.c

585

if (HAS_PCH_SPLIT(display))

sys/dev/pci/drm/i915/display/intel_crt.c

588

if (display->platform.valleyview)

sys/dev/pci/drm/i915/display/intel_crt.c

596

if (display->platform.g45)

sys/dev/pci/drm/i915/display/intel_crt.c

603

i915_hotplug_interrupt_update(display,

sys/dev/pci/drm/i915/display/intel_crt.c

607

if (intel_de_wait_for_clear(display, PORT_HOTPLUG_EN(display),

sys/dev/pci/drm/i915/display/intel_crt.c

609

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_crt.c

613

stat = intel_de_read(display, PORT_HOTPLUG_STAT(display));

sys/dev/pci/drm/i915/display/intel_crt.c

618

intel_de_write(display, PORT_HOTPLUG_STAT(display),

sys/dev/pci/drm/i915/display/intel_crt.c

621

i915_hotplug_interrupt_update(display, CRT_HOTPLUG_FORCE_DETECT, 0);

sys/dev/pci/drm/i915/display/intel_crt.c

664

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_crt.c

677

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_crt.c

680

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_crt.c

685

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_crt.c

697

struct intel_display *display = to_intel_display(&crt->base);

sys/dev/pci/drm/i915/display/intel_crt.c

708

drm_dbg_kms(display->drm, "starting load-detect on CRT\n");

sys/dev/pci/drm/i915/display/intel_crt.c

710

save_bclrpat = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_crt.c

711

BCLRPAT(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_crt.c

712

save_vtotal = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_crt.c

713

TRANS_VTOTAL(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_crt.c

714

vblank = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_crt.c

715

TRANS_VBLANK(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_crt.c

724

intel_de_write(display, BCLRPAT(display, cpu_transcoder), 0x500050);

sys/dev/pci/drm/i915/display/intel_crt.c

726

if (DISPLAY_VER(display) != 2) {

sys/dev/pci/drm/i915/display/intel_crt.c

727

u32 transconf = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_crt.c

728

TRANSCONF(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_crt.c

730

intel_de_write(display, TRANSCONF(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_crt.c

732

intel_de_posting_read(display,

sys/dev/pci/drm/i915/display/intel_crt.c

733

TRANSCONF(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_crt.c

738

intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));

sys/dev/pci/drm/i915/display/intel_crt.c

739

st00 = intel_de_read8(display, _VGA_MSR_WRITE);

sys/dev/pci/drm/i915/display/intel_crt.c

744

intel_de_write(display, TRANSCONF(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_crt.c

755

u32 vsync = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_crt.c

756

TRANS_VSYNC(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_crt.c

760

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_crt.c

761

TRANS_VBLANK(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_crt.c

775

while (intel_de_read(display, PIPEDSL(display, pipe)) >= vactive)

sys/dev/pci/drm/i915/display/intel_crt.c

777

while ((dsl = intel_de_read(display, PIPEDSL(display, pipe))) <= vsample)

sys/dev/pci/drm/i915/display/intel_crt.c

787

st00 = intel_de_read8(display, _VGA_MSR_WRITE);

sys/dev/pci/drm/i915/display/intel_crt.c

790

} while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl));

sys/dev/pci/drm/i915/display/intel_crt.c

794

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_crt.c

795

TRANS_VBLANK(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_crt.c

809

intel_de_write(display, BCLRPAT(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_crt.c

846

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_crt.c

853

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n",

sys/dev/pci/drm/i915/display/intel_crt.c

857

if (!intel_display_device_enabled(display))

sys/dev/pci/drm/i915/display/intel_crt.c

860

if (!intel_display_driver_check_access(display))

sys/dev/pci/drm/i915/display/intel_crt.c

863

if (display->params.load_detect_test) {

sys/dev/pci/drm/i915/display/intel_crt.c

864

wakeref = intel_display_power_get(display, encoder->power_domain);

sys/dev/pci/drm/i915/display/intel_crt.c

872

wakeref = intel_display_power_get(display, encoder->power_domain);

sys/dev/pci/drm/i915/display/intel_crt.c

874

if (HAS_HOTPLUG(display)) {

sys/dev/pci/drm/i915/display/intel_crt.c

880

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_crt.c

885

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_crt.c

898

if (HAS_HOTPLUG(display)) {

sys/dev/pci/drm/i915/display/intel_crt.c

91

bool intel_crt_port_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_crt.c

918

else if (DISPLAY_VER(display) < 4)

sys/dev/pci/drm/i915/display/intel_crt.c

921

else if (display->params.load_detect_test)

sys/dev/pci/drm/i915/display/intel_crt.c

929

intel_display_power_put(display, encoder->power_domain, wakeref);

sys/dev/pci/drm/i915/display/intel_crt.c

936

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_crt.c

943

if (!intel_display_driver_check_access(display))

sys/dev/pci/drm/i915/display/intel_crt.c

946

wakeref = intel_display_power_get(display, encoder->power_domain);

sys/dev/pci/drm/i915/display/intel_crt.c

949

if (ret || !display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_crt.c

953

ddc = intel_gmbus_get_adapter(display, GMBUS_PIN_DPB);

sys/dev/pci/drm/i915/display/intel_crt.c

957

intel_display_power_put(display, encoder->power_domain, wakeref);

sys/dev/pci/drm/i915/display/intel_crt.c

96

val = intel_de_read(display, adpa_reg);

sys/dev/pci/drm/i915/display/intel_crt.c

964

struct intel_display *display = to_intel_display(encoder->dev);

sys/dev/pci/drm/i915/display/intel_crt.c

967

if (DISPLAY_VER(display) >= 5) {

sys/dev/pci/drm/i915/display/intel_crt.c

970

adpa = intel_de_read(display, crt->adpa_reg);

sys/dev/pci/drm/i915/display/intel_crt.c

973

intel_de_write(display, crt->adpa_reg, adpa);

sys/dev/pci/drm/i915/display/intel_crt.c

974

intel_de_posting_read(display, crt->adpa_reg);

sys/dev/pci/drm/i915/display/intel_crt.c

976

drm_dbg_kms(display->drm, "crt adpa set to 0x%x\n", adpa);

sys/dev/pci/drm/i915/display/intel_crt.c

99

if (HAS_PCH_CPT(display))

sys/dev/pci/drm/i915/display/intel_crt.h

16

bool intel_crt_port_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_crt.h

18

void intel_crt_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_crt.h

21

static inline bool intel_crt_port_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_crt.h

26

static inline void intel_crt_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_crtc.c

111

if (display->platform.i965gm &&

sys/dev/pci/drm/i915/display/intel_crtc.c

115

if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_crtc.c

117

else if (DISPLAY_VER(display) >= 3)

sys/dev/pci/drm/i915/display/intel_crtc.c

144

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_crtc.c

159

flush_work(&display->irq.vblank_notify_work);

sys/dev/pci/drm/i915/display/intel_crtc.c

306

int intel_crtc_init(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_crtc.c

318

crtc->num_scalers = DISPLAY_RUNTIME_INFO(display)->num_scalers[pipe];

sys/dev/pci/drm/i915/display/intel_crtc.c

320

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_crtc.c

321

primary = skl_universal_plane_create(display, pipe, PLANE_1);

sys/dev/pci/drm/i915/display/intel_crtc.c

323

primary = intel_primary_plane_create(display, pipe);

sys/dev/pci/drm/i915/display/intel_crtc.c

330

intel_init_fifo_underrun_reporting(display, crtc, false);

sys/dev/pci/drm/i915/display/intel_crtc.c

332

for_each_sprite(display, pipe, sprite) {

sys/dev/pci/drm/i915/display/intel_crtc.c

335

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_crtc.c

336

plane = skl_universal_plane_create(display, pipe, PLANE_2 + sprite);

sys/dev/pci/drm/i915/display/intel_crtc.c

338

plane = intel_sprite_plane_create(display, pipe, sprite);

sys/dev/pci/drm/i915/display/intel_crtc.c

346

cursor = intel_cursor_plane_create(display, pipe);

sys/dev/pci/drm/i915/display/intel_crtc.c

353

if (HAS_GMCH(display)) {

sys/dev/pci/drm/i915/display/intel_crtc.c

354

if (display->platform.cherryview ||

sys/dev/pci/drm/i915/display/intel_crtc.c

355

display->platform.valleyview ||

sys/dev/pci/drm/i915/display/intel_crtc.c

356

display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_crtc.c

358

else if (DISPLAY_VER(display) == 4)

sys/dev/pci/drm/i915/display/intel_crtc.c

360

else if (display->platform.i945gm ||

sys/dev/pci/drm/i915/display/intel_crtc.c

361

display->platform.i915gm)

sys/dev/pci/drm/i915/display/intel_crtc.c

363

else if (DISPLAY_VER(display) == 3)

sys/dev/pci/drm/i915/display/intel_crtc.c

368

if (DISPLAY_VER(display) >= 8)

sys/dev/pci/drm/i915/display/intel_crtc.c

374

ret = drm_crtc_init_with_planes(display->drm, &crtc->base,

sys/dev/pci/drm/i915/display/intel_crtc.c

380

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_crtc.c

391

drm_WARN_ON(display->drm, drm_crtc_index(&crtc->base) != crtc->pipe);

sys/dev/pci/drm/i915/display/intel_crtc.c

40

struct intel_display *display = to_intel_display(crtc->dev);

sys/dev/pci/drm/i915/display/intel_crtc.c

42

if (INTEL_DISPLAY_STATE_WARN(display, drm_crtc_vblank_get(crtc) == 0,

sys/dev/pci/drm/i915/display/intel_crtc.c

420

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_crtc.c

426

!HAS_DOUBLE_BUFFERED_LUT(display)) &&

sys/dev/pci/drm/i915/display/intel_crtc.c

48

struct intel_crtc *intel_first_crtc(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_crtc.c

50

return to_intel_crtc(drm_crtc_from_index(display->drm, 0));

sys/dev/pci/drm/i915/display/intel_crtc.c

519

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_crtc.c

527

drm_WARN_ON(display->drm, new_crtc_state->use_dsb);

sys/dev/pci/drm/i915/display/intel_crtc.c

53

struct intel_crtc *intel_crtc_for_pipe(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_crtc.c

555

if (drm_WARN_ON(display->drm, drm_crtc_vblank_get(&crtc->base)))

sys/dev/pci/drm/i915/display/intel_crtc.c

58

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_crtc.c

658

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_crtc.c

667

drm_WARN_ON(display->drm, new_crtc_state->use_dsb);

sys/dev/pci/drm/i915/display/intel_crtc.c

678

if (DISPLAY_VER(display) >= 11 &&

sys/dev/pci/drm/i915/display/intel_crtc.c

71

void intel_wait_for_vblank_if_active(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_crtc.c

736

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_crtc.c

74

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_crtc.c

95

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_crtc.h

41

int intel_crtc_init(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_crtc.h

55

struct intel_crtc *intel_first_crtc(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_crtc.h

56

struct intel_crtc *intel_crtc_for_pipe(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_crtc.h

58

void intel_wait_for_vblank_if_active(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

140

ilk_dump_csc(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

156

if (DISPLAY_VER(display) < 7)

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

180

struct intel_display *display = to_intel_display(pipe_config);

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

191

p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

265

intel_dump_infoframe(display, &pipe_config->infoframes.avi);

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

268

intel_dump_infoframe(display, &pipe_config->infoframes.spd);

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

271

intel_dump_infoframe(display, &pipe_config->infoframes.hdmi);

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

274

intel_dump_infoframe(display, &pipe_config->infoframes.drm);

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

277

intel_dump_infoframe(display, &pipe_config->infoframes.drm);

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

323

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

330

if (HAS_GMCH(display))

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

345

intel_dpll_dump_hw_state(display, &p, &pipe_config->dpll_hw_state);

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

347

if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

358

display->color.glk_linear_degamma_lut ? "(linear) " : "",

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

364

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

365

ilk_dump_csc(display, &p, "output csc", &pipe_config->output_csc);

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

367

if (!HAS_GMCH(display))

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

368

ilk_dump_csc(display, &p, "pipe csc", &pipe_config->csc);

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

369

else if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

371

else if (display->platform.valleyview)

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

46

intel_dump_infoframe(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

52

hdmi_infoframe_log(KERN_DEBUG, display->drm->dev, frame);

sys/dev/pci/drm/i915/display/intel_cursor.c

1002

intel_cursor_plane_create(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cursor.c

1018

if (display->platform.i845g || display->platform.i865g) {

sys/dev/pci/drm/i915/display/intel_cursor.c

1028

if (display->platform.i830)

sys/dev/pci/drm/i915/display/intel_cursor.c

1030

else if (display->platform.i85x)

sys/dev/pci/drm/i915/display/intel_cursor.c

1035

if (intel_scanout_needs_vtd_wa(display))

sys/dev/pci/drm/i915/display/intel_cursor.c

1046

if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_cursor.c

1054

if (display->platform.i845g || display->platform.i865g || HAS_CUR_FBC(display))

sys/dev/pci/drm/i915/display/intel_cursor.c

1057

modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_NONE);

sys/dev/pci/drm/i915/display/intel_cursor.c

1059

ret = drm_universal_plane_init(display->drm, &cursor->base,

sys/dev/pci/drm/i915/display/intel_cursor.c

1072

if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/intel_cursor.c

108

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cursor.c

1080

zpos = DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + 1;

sys/dev/pci/drm/i915/display/intel_cursor.c

1083

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_cursor.c

122

if (HAS_GMCH(display) && rotation & DRM_MODE_ROTATE_180) {

sys/dev/pci/drm/i915/display/intel_cursor.c

140

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_cursor.c

148

drm_dbg_kms(display->drm, "[PLANE:%d:%s] cursor cannot be tiled\n",

sys/dev/pci/drm/i915/display/intel_cursor.c

229

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_cursor.c

244

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cursor.c

252

drm_WARN_ON(display->drm, plane_state->uapi.visible &&

sys/dev/pci/drm/i915/display/intel_cursor.c

262

drm_dbg_kms(display->drm, "[PLANE:%d:%s] invalid cursor stride (%u)\n",

sys/dev/pci/drm/i915/display/intel_cursor.c

279

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

301

intel_de_write_fw(display, CURCNTR(display, PIPE_A), 0);

sys/dev/pci/drm/i915/display/intel_cursor.c

302

intel_de_write_fw(display, CURBASE(display, PIPE_A), base);

sys/dev/pci/drm/i915/display/intel_cursor.c

303

intel_de_write_fw(display, CURSIZE(display, PIPE_A), size);

sys/dev/pci/drm/i915/display/intel_cursor.c

304

intel_de_write_fw(display, CURPOS(display, PIPE_A), pos);

sys/dev/pci/drm/i915/display/intel_cursor.c

305

intel_de_write_fw(display, CURCNTR(display, PIPE_A), cntl);

sys/dev/pci/drm/i915/display/intel_cursor.c

311

intel_de_write_fw(display, CURPOS(display, PIPE_A), pos);

sys/dev/pci/drm/i915/display/intel_cursor.c

325

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

331

wakeref = intel_display_power_get_if_enabled(display, power_domain);

sys/dev/pci/drm/i915/display/intel_cursor.c

335

ret = intel_de_read(display, CURCNTR(display, PIPE_A)) & CURSOR_ENABLE;

sys/dev/pci/drm/i915/display/intel_cursor.c

339

intel_display_power_put(display, power_domain, wakeref);

sys/dev/pci/drm/i915/display/intel_cursor.c

371

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

373

if (intel_scanout_needs_vtd_wa(display))

sys/dev/pci/drm/i915/display/intel_cursor.c

381

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_cursor.c

385

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_cursor.c

394

if (DISPLAY_VER(display) < 5 && !display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_cursor.c

402

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_cursor.c

405

if (display->platform.sandybridge || display->platform.ivybridge)

sys/dev/pci/drm/i915/display/intel_cursor.c

427

if (DISPLAY_VER(display) == 13)

sys/dev/pci/drm/i915/display/intel_cursor.c

435

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_cursor.c

458

if (HAS_CUR_FBC(display) &&

sys/dev/pci/drm/i915/display/intel_cursor.c

473

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_cursor.c

489

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cursor.c

497

drm_WARN_ON(display->drm, plane_state->uapi.visible &&

sys/dev/pci/drm/i915/display/intel_cursor.c

502

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cursor.c

519

if (display->platform.cherryview && pipe == PIPE_C &&

sys/dev/pci/drm/i915/display/intel_cursor.c

521

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cursor.c

536

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

542

intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), 0);

sys/dev/pci/drm/i915/display/intel_cursor.c

550

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

558

intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), ctl);

sys/dev/pci/drm/i915/display/intel_cursor.c

560

intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(display, pipe),

sys/dev/pci/drm/i915/display/intel_cursor.c

569

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

580

intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(display, pipe), val);

sys/dev/pci/drm/i915/display/intel_cursor.c

583

intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), plane_state->ctl);

sys/dev/pci/drm/i915/display/intel_cursor.c

620

struct intel_display *display = to_intel_display(plane->base.dev);

sys/dev/pci/drm/i915/display/intel_cursor.c

628

for (level = 0; level < display->wm.num_levels; level++)

sys/dev/pci/drm/i915/display/intel_cursor.c

629

intel_de_write_dsb(display, dsb, CUR_WM(pipe, level),

sys/dev/pci/drm/i915/display/intel_cursor.c

632

intel_de_write_dsb(display, dsb, CUR_WM_TRANS(pipe),

sys/dev/pci/drm/i915/display/intel_cursor.c

635

if (HAS_HW_SAGV_WM(display)) {

sys/dev/pci/drm/i915/display/intel_cursor.c

638

intel_de_write_dsb(display, dsb, CUR_WM_SAGV(pipe),

sys/dev/pci/drm/i915/display/intel_cursor.c

640

intel_de_write_dsb(display, dsb, CUR_WM_SAGV_TRANS(pipe),

sys/dev/pci/drm/i915/display/intel_cursor.c

644

intel_de_write_dsb(display, dsb, CUR_BUF_CFG(pipe),

sys/dev/pci/drm/i915/display/intel_cursor.c

654

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

692

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_cursor.c

703

if (HAS_CUR_FBC(display))

sys/dev/pci/drm/i915/display/intel_cursor.c

704

intel_de_write_dsb(display, dsb, CUR_FBC_CTL(display, pipe), fbc_ctl);

sys/dev/pci/drm/i915/display/intel_cursor.c

705

intel_de_write_dsb(display, dsb, CURCNTR(display, pipe), cntl);

sys/dev/pci/drm/i915/display/intel_cursor.c

706

intel_de_write_dsb(display, dsb, CURPOS(display, pipe), pos);

sys/dev/pci/drm/i915/display/intel_cursor.c

707

intel_de_write_dsb(display, dsb, CURBASE(display, pipe), base);

sys/dev/pci/drm/i915/display/intel_cursor.c

713

intel_de_write_dsb(display, dsb, CURPOS(display, pipe), pos);

sys/dev/pci/drm/i915/display/intel_cursor.c

714

intel_de_write_dsb(display, dsb, CURBASE(display, pipe), base);

sys/dev/pci/drm/i915/display/intel_cursor.c

728

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

740

wakeref = intel_display_power_get_if_enabled(display, power_domain);

sys/dev/pci/drm/i915/display/intel_cursor.c

744

val = intel_de_read(display, CURCNTR(display, plane->pipe));

sys/dev/pci/drm/i915/display/intel_cursor.c

748

if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_cursor.c

753

intel_display_power_put(display, power_domain, wakeref);

sys/dev/pci/drm/i915/display/intel_cursor.c

762

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

764

error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_cursor.c

765

error->surf = intel_de_read(display, CURBASE(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_cursor.c

766

error->surflive = intel_de_read(display, CURSURFLIVE(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_cursor.c

773

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

775

error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_cursor.c

776

error->surf = intel_de_read(display, CURBASE(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_cursor.c

811

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

86

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_cursor.c

915

if (!drm_WARN_ON(display->drm, drm_crtc_vblank_get(&crtc->base))) {

sys/dev/pci/drm/i915/display/intel_cursor.c

981

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

982

const struct drm_mode_config *config = &display->drm->mode_config;

sys/dev/pci/drm/i915/display/intel_cursor.c

990

if (drm_WARN_ON(display->drm, num_hints >= ARRAY_SIZE(hints)))

sys/dev/pci/drm/i915/display/intel_cursor.h

15

intel_cursor_plane_create(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

111

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

116

wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

124

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

128

intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

134

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

136

intel_de_rmw(display,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

137

XELPDP_PORT_P2M_MSGBUS_STATUS(display, encoder->port, lane),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

143

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

147

intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

150

if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

153

drm_err_once(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

165

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

169

if (intel_de_wait_custom(display,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

170

XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

175

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

179

if (!(intel_de_read(display, XELPDP_PORT_MSGBUS_TIMER(display, port, lane)) &

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

181

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

190

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

199

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2032

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2035

if (intel_panel_use_ssc(display)) {

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2046

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2052

drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) < 9);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

213

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2132

static void intel_c10_pll_program(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2160

static void intel_c10pll_dump_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2169

drm_dbg_kms(display->drm, "c10pll_hw_state: fracen: %s, ",

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2176

drm_dbg_kms(display->drm, "quot: %u, rem: %u, den: %u,\n",

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2183

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2186

drm_dbg_kms(display->drm, "c10pll_rawhw_state:");

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2187

drm_dbg_kms(display->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

219

if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2192

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

222

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2225

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2230

if (DISPLAY_VER(display) >= 20) {

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2233

} else if (display->platform.battlemage) {

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2235

} else if (display->platform.meteorlake_u ||

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

228

intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2320

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2324

if (DISPLAY_RUNTIME_INFO(display)->edp_typec_support)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2326

if (DISPLAY_VERx100(display) == 1401)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2330

if (DISPLAY_VER(display) >= 30)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2332

else if (DISPLAY_VERx100(display) == 1401)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2436

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

244

if (DISPLAY_VER(display) < 30)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2451

PHY_C20_B_TX_CNTX_CFG(display, i));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2455

PHY_C20_A_TX_CNTX_CFG(display, i));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2463

PHY_C20_B_CMN_CNTX_CFG(display, i));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2467

PHY_C20_A_CMN_CNTX_CFG(display, i));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2476

PHY_C20_B_MPLLB_CNTX_CFG(display, i));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2480

PHY_C20_A_MPLLB_CNTX_CFG(display, i));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2488

PHY_C20_B_MPLLA_CNTX_CFG(display, i));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2492

PHY_C20_A_MPLLA_CNTX_CFG(display, i));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2501

static void intel_c20pll_dump_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2506

drm_dbg_kms(display->drm, "c20pll_hw_state:\n");

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2507

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2510

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2516

drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2520

drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2525

void intel_cx0pll_dump_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2529

intel_c10pll_dump_hw_state(display, &hw_state->c10);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

253

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2531

intel_c20pll_dump_hw_state(display, &hw_state->c20);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

257

assert_dc_off(display);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2631

static void intel_c20_pll_program(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2659

PHY_C20_A_TX_CNTX_CFG(display, i),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2663

PHY_C20_B_TX_CNTX_CFG(display, i),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

267

drm_err_once(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2671

PHY_C20_A_CMN_CNTX_CFG(display, i),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2675

PHY_C20_B_CMN_CNTX_CFG(display, i),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2684

PHY_C20_A_MPLLB_CNTX_CFG(display, i),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2688

PHY_C20_B_MPLLB_CNTX_CFG(display, i),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2695

PHY_C20_A_MPLLA_CNTX_CFG(display, i),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2699

PHY_C20_B_MPLLA_CNTX_CFG(display, i),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2767

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2770

intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2780

val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2782

val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2791

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2793

XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_SSC_ENABLE_PLLA |

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2822

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2825

i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(display, port);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2828

intel_de_rmw(display, buf_ctl2_reg,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2834

if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2837

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2843

intel_de_rmw(display, buf_ctl2_reg,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2848

if (intel_de_wait_custom(display, buf_ctl2_reg,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

285

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2851

drm_warn(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2858

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2861

intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2864

intel_de_rmw(display, XELPDP_PORT_BUF_CTL3(display, port),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2896

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2909

if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL1(display, port),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

291

if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2913

drm_warn(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2917

intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2920

if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2923

drm_warn(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2927

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2931

if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2935

drm_warn(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

294

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2943

intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset, 0);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2945

if (intel_de_wait_for_clear(display, XELPDP_PORT_BUF_CTL2(display, port),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2948

drm_warn(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

300

intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3023

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3055

intel_c10_pll_program(display, encoder, &pll_state->c10);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3057

intel_c20_pll_program(display, encoder, &pll_state->c20, is_dp, port_clock);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

307

if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3074

intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3080

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3085

if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3089

drm_warn(display->drm, "Port %c PLL not locked after %dus.\n",

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

310

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3111

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3114

val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3116

clock = XELPDP_DDI_CLOCK_SELECT_GET(display, val);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3118

drm_WARN_ON(display->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3119

drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_REQUEST));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3120

drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_ACK));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3141

static int intel_mtl_tbt_clock_select(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3154

if (DISPLAY_VER(display) < 30) {

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3155

drm_WARN_ON(display->drm, "UHBR10 not supported for the platform\n");

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3160

if (DISPLAY_VER(display) < 30) {

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3161

drm_WARN_ON(display->drm, "UHBR20 not supported for the platform\n");

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3174

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3184

mask = XELPDP_DDI_CLOCK_SELECT_MASK(display);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3185

val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3186

intel_mtl_tbt_clock_select(display, crtc_state->port_clock));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3191

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3195

val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

320

} else if ((intel_de_read(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane)) &

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3206

intel_de_write(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), val);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3209

if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3213

drm_warn(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

322

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3226

intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3249

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3254

if (DISPLAY_VER(display) < 20 ||

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3283

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3288

if ((display->platform.battlemage && encoder->port == PORT_A) ||

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3289

(DISPLAY_VER(display) >= 30 && encoder->type == INTEL_OUTPUT_EDP))

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3297

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3314

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3319

intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3324

if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3328

drm_warn(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3338

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3339

XELPDP_DDI_CLOCK_SELECT_MASK(display), 0);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3340

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3348

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

335

if (DISPLAY_VER(display) < 30)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3352

return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) &

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3358

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3369

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3373

if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3375

drm_warn(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3387

intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3388

XELPDP_DDI_CLOCK_SELECT_MASK(display) |

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3392

intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3409

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3416

val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3417

clock = XELPDP_DDI_CLOCK_SELECT_GET(display, val);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3431

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3438

INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->pll[i] != expected,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

344

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3444

INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->tx != mpllb_sw_state->tx,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3449

INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->cmn != mpllb_sw_state->cmn,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

348

assert_dc_off(display);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3538

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3545

INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->clock != clock,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3550

INTEL_DISPLAY_STATE_WARN(display, sw_use_mpllb != hw_use_mpllb,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3557

INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->mpllb[i] != mpll_sw_state->mpllb[i],

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3564

INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i],

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3572

INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->tx[i] != mpll_sw_state->tx[i],

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3579

INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->cmn[i] != mpll_sw_state->cmn[i],

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

358

drm_err_once(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3589

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3595

if (DISPLAY_VER(display) < 14)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3631

void intel_cx0_pll_power_save_wa(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3635

if (DISPLAY_VER(display) != 30)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3638

for_each_intel_encoder(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3655

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3660

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

374

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

376

assert_dc_off(display);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

388

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

39

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

391

assert_dc_off(display);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

42

if (display->platform.pantherlake) {

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

43

if (display->platform.pantherlake_wildcatlake)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

455

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

470

if (drm_WARN_ON_ONCE(display->drm, !trans)) {

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

49

if ((display->platform.lunarlake || display->platform.meteorlake) && phy < PHY_C)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

80

assert_dc_off(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

84

enabled = intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

85

drm_WARN_ON(display->drm, !enabled);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

90

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

94

intel_de_rmw(display,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

95

XELPDP_PORT_MSGBUS_TIMER(display, encoder->port, lane),

sys/dev/pci/drm/i915/display/intel_cx0_phy.h

36

void intel_cx0pll_dump_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cx0_phy.h

45

void intel_cx0_pll_power_save_wa(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

197

#define XELPDP_DDI_CLOCK_SELECT_MASK(display) (DISPLAY_VER(display) >= 30 ? \

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

199

#define XELPDP_DDI_CLOCK_SELECT_PREP(display, val) (DISPLAY_VER(display) >= 30 ? \

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

202

#define XELPDP_DDI_CLOCK_SELECT_GET(display, val) (DISPLAY_VER(display) >= 30 ? \

sys/dev/pci/drm/i915/display/intel_ddi.c

1008

intel_display_power_put(display, domain, wf);

sys/dev/pci/drm/i915/display/intel_ddi.c

1014

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1022

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

1029

drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);

sys/dev/pci/drm/i915/display/intel_ddi.c

1030

dig_port->ddi_io_wakeref = intel_display_power_get(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

1040

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_ddi.c

1048

if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/intel_ddi.c

1050

else if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_ddi.c

1055

intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val);

sys/dev/pci/drm/i915/display/intel_ddi.c

1060

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_ddi.c

1067

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_ddi.c

1072

intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val);

sys/dev/pci/drm/i915/display/intel_ddi.c

1075

static void _skl_ddi_set_iboost(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_ddi.c

1080

tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0);

sys/dev/pci/drm/i915/display/intel_ddi.c

1086

intel_de_write(display, DISPIO_CR_TX_BMU_CR0, tmp);

sys/dev/pci/drm/i915/display/intel_ddi.c

1093

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1107

if (drm_WARN_ON_ONCE(display->drm, !trans))

sys/dev/pci/drm/i915/display/intel_ddi.c

1115

drm_err(display->drm, "Invalid I_boost value %u\n", iboost);

sys/dev/pci/drm/i915/display/intel_ddi.c

1119

_skl_ddi_set_iboost(display, encoder->port, iboost);

sys/dev/pci/drm/i915/display/intel_ddi.c

1122

_skl_ddi_set_iboost(display, PORT_E, iboost);

sys/dev/pci/drm/i915/display/intel_ddi.c

1128

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_ddi.c

1134

if (drm_WARN_ON(display->drm, n_entries < 1))

sys/dev/pci/drm/i915/display/intel_ddi.c

1136

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

116

static bool has_buf_trans_select(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_ddi.c

1169

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1176

if (drm_WARN_ON_ONCE(display->drm, !trans))

sys/dev/pci/drm/i915/display/intel_ddi.c

118

return DISPLAY_VER(display) < 10 && !display->platform.broxton;

sys/dev/pci/drm/i915/display/intel_ddi.c

1184

intel_de_rmw(display, ICL_PORT_CL_DW10(phy), val,

sys/dev/pci/drm/i915/display/intel_ddi.c

1189

val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1196

intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);

sys/dev/pci/drm/i915/display/intel_ddi.c

1202

intel_de_rmw(display, ICL_PORT_TX_DW2_LN(ln, phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

121

static bool has_iboost(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_ddi.c

1214

intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1225

intel_de_rmw(display, ICL_PORT_TX_DW7_LN(ln, phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

123

return DISPLAY_VER(display) == 9 && !display->platform.broxton;

sys/dev/pci/drm/i915/display/intel_ddi.c

1234

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1244

val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1249

intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val);

sys/dev/pci/drm/i915/display/intel_ddi.c

1259

intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1265

intel_de_rmw(display, ICL_PORT_CL_DW5(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1269

val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1271

intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);

sys/dev/pci/drm/i915/display/intel_ddi.c

1277

val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1279

intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);

sys/dev/pci/drm/i915/display/intel_ddi.c

1285

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1294

if (drm_WARN_ON_ONCE(display->drm, !trans))

sys/dev/pci/drm/i915/display/intel_ddi.c

1298

intel_de_rmw(display, MG_TX1_LINK_PARAMS(ln, tc_port),

sys/dev/pci/drm/i915/display/intel_ddi.c

1300

intel_de_rmw(display, MG_TX2_LINK_PARAMS(ln, tc_port),

sys/dev/pci/drm/i915/display/intel_ddi.c

1310

intel_de_rmw(display, MG_TX1_SWINGCTRL(ln, tc_port),

sys/dev/pci/drm/i915/display/intel_ddi.c

1316

intel_de_rmw(display, MG_TX2_SWINGCTRL(ln, tc_port),

sys/dev/pci/drm/i915/display/intel_ddi.c

1327

intel_de_rmw(display, MG_TX1_DRVCTRL(ln, tc_port),

sys/dev/pci/drm/i915/display/intel_ddi.c

1336

intel_de_rmw(display, MG_TX2_DRVCTRL(ln, tc_port),

sys/dev/pci/drm/i915/display/intel_ddi.c

134

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1352

intel_de_rmw(display, MG_CLKHUB(ln, tc_port),

sys/dev/pci/drm/i915/display/intel_ddi.c

1359

intel_de_rmw(display, MG_TX1_DCC(ln, tc_port),

sys/dev/pci/drm/i915/display/intel_ddi.c

1366

intel_de_rmw(display, MG_TX2_DCC(ln, tc_port),

sys/dev/pci/drm/i915/display/intel_ddi.c

1376

intel_de_rmw(display, MG_TX1_PISO_READLOAD(ln, tc_port),

sys/dev/pci/drm/i915/display/intel_ddi.c

1378

intel_de_rmw(display, MG_TX2_PISO_READLOAD(ln, tc_port),

sys/dev/pci/drm/i915/display/intel_ddi.c

1386

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1395

if (drm_WARN_ON_ONCE(display->drm, !trans))

sys/dev/pci/drm/i915/display/intel_ddi.c

1402

if (display->platform.alderlake_p &&

sys/dev/pci/drm/i915/display/intel_ddi.c

1403

IS_DISPLAY_STEP(display, STEP_A0, STEP_D0)) {

sys/dev/pci/drm/i915/display/intel_ddi.c

1408

intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),

sys/dev/pci/drm/i915/display/intel_ddi.c

141

if (drm_WARN_ON_ONCE(display->drm, !trans))

sys/dev/pci/drm/i915/display/intel_ddi.c

1411

intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),

sys/dev/pci/drm/i915/display/intel_ddi.c

1416

intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);

sys/dev/pci/drm/i915/display/intel_ddi.c

1420

intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln),

sys/dev/pci/drm/i915/display/intel_ddi.c

1430

intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln),

sys/dev/pci/drm/i915/display/intel_ddi.c

1438

intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),

sys/dev/pci/drm/i915/display/intel_ddi.c

1441

if (display->platform.alderlake_p) {

sys/dev/pci/drm/i915/display/intel_ddi.c

145

if (has_iboost(display) &&

sys/dev/pci/drm/i915/display/intel_ddi.c

1457

intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),

sys/dev/pci/drm/i915/display/intel_ddi.c

1468

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_ddi.c

1476

drm_WARN(display->drm, 1,

sys/dev/pci/drm/i915/display/intel_ddi.c

150

intel_de_write(display, DDI_BUF_TRANS_LO(port, i),

sys/dev/pci/drm/i915/display/intel_ddi.c

1503

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1508

if (drm_WARN_ON_ONCE(display->drm, !trans))

sys/dev/pci/drm/i915/display/intel_ddi.c

1517

if (drm_WARN_ON_ONCE(display->drm, level >= n_entries))

sys/dev/pci/drm/i915/display/intel_ddi.c

152

intel_de_write(display, DDI_BUF_TRANS_HI(port, i),

sys/dev/pci/drm/i915/display/intel_ddi.c

1527

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1533

if (has_iboost(display))

sys/dev/pci/drm/i915/display/intel_ddi.c

1542

drm_dbg_kms(display->drm, "Using signal levels %08x\n",

sys/dev/pci/drm/i915/display/intel_ddi.c

1548

intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP);

sys/dev/pci/drm/i915/display/intel_ddi.c

1549

intel_de_posting_read(display, DDI_BUF_CTL(port));

sys/dev/pci/drm/i915/display/intel_ddi.c

1552

static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg,

sys/dev/pci/drm/i915/display/intel_ddi.c

1555

mutex_lock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1557

intel_de_rmw(display, reg, clk_sel_mask, clk_sel);

sys/dev/pci/drm/i915/display/intel_ddi.c

1563

intel_de_rmw(display, reg, clk_off, 0);

sys/dev/pci/drm/i915/display/intel_ddi.c

1565

mutex_unlock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1568

static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg,

sys/dev/pci/drm/i915/display/intel_ddi.c

1571

mutex_lock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1573

intel_de_rmw(display, reg, 0, clk_off);

sys/dev/pci/drm/i915/display/intel_ddi.c

1575

mutex_unlock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1578

static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg,

sys/dev/pci/drm/i915/display/intel_ddi.c

1581

return !(intel_de_read(display, reg) & clk_off);

sys/dev/pci/drm/i915/display/intel_ddi.c

1585

_icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,

sys/dev/pci/drm/i915/display/intel_ddi.c

1590

id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;

sys/dev/pci/drm/i915/display/intel_ddi.c

1592

return intel_get_dpll_by_id(display, id);

sys/dev/pci/drm/i915/display/intel_ddi.c

1598

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1602

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

1605

_icl_ddi_enable_clock(display, ADLS_DPCLKA_CFGCR(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1613

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1616

_icl_ddi_disable_clock(display, ADLS_DPCLKA_CFGCR(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1622

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1625

return _icl_ddi_is_clock_enabled(display, ADLS_DPCLKA_CFGCR(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1631

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1634

return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1642

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1646

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

1649

_icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0,

sys/dev/pci/drm/i915/display/intel_ddi.c

165

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1657

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1660

_icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0,

sys/dev/pci/drm/i915/display/intel_ddi.c

1666

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1669

return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0,

sys/dev/pci/drm/i915/display/intel_ddi.c

1675

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1678

return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0,

sys/dev/pci/drm/i915/display/intel_ddi.c

1686

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1690

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

1697

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

1702

_icl_ddi_enable_clock(display, DG1_DPCLKA_CFGCR0(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1710

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1713

_icl_ddi_disable_clock(display, DG1_DPCLKA_CFGCR0(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1719

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1722

return _icl_ddi_is_clock_enabled(display, DG1_DPCLKA_CFGCR0(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1728

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

173

if (drm_WARN_ON_ONCE(display->drm, !trans))

sys/dev/pci/drm/i915/display/intel_ddi.c

1733

val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1746

return intel_get_dpll_by_id(display, id);

sys/dev/pci/drm/i915/display/intel_ddi.c

1752

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1756

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

1759

_icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0,

sys/dev/pci/drm/i915/display/intel_ddi.c

1767

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

177

if (has_iboost(display) &&

sys/dev/pci/drm/i915/display/intel_ddi.c

1770

_icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0,

sys/dev/pci/drm/i915/display/intel_ddi.c

1776

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1779

return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0,

sys/dev/pci/drm/i915/display/intel_ddi.c

1785

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1788

return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0,

sys/dev/pci/drm/i915/display/intel_ddi.c

1796

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1800

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

1807

intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);

sys/dev/pci/drm/i915/display/intel_ddi.c

1814

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1819

intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);

sys/dev/pci/drm/i915/display/intel_ddi.c

182

intel_de_write(display, DDI_BUF_TRANS_LO(port, 9),

sys/dev/pci/drm/i915/display/intel_ddi.c

1824

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1828

tmp = intel_de_read(display, DDI_CLK_SEL(port));

sys/dev/pci/drm/i915/display/intel_ddi.c

1839

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

184

intel_de_write(display, DDI_BUF_TRANS_HI(port, 9),

sys/dev/pci/drm/i915/display/intel_ddi.c

1844

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

1847

intel_de_write(display, DDI_CLK_SEL(port),

sys/dev/pci/drm/i915/display/intel_ddi.c

1850

mutex_lock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1852

intel_de_rmw(display, ICL_DPCLKA_CFGCR0,

sys/dev/pci/drm/i915/display/intel_ddi.c

1855

mutex_unlock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1860

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1864

mutex_lock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1866

intel_de_rmw(display, ICL_DPCLKA_CFGCR0,

sys/dev/pci/drm/i915/display/intel_ddi.c

1869

mutex_unlock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1871

intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);

sys/dev/pci/drm/i915/display/intel_ddi.c

1876

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

188

static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_ddi.c

1881

tmp = intel_de_read(display, DDI_CLK_SEL(port));

sys/dev/pci/drm/i915/display/intel_ddi.c

1886

tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);

sys/dev/pci/drm/i915/display/intel_ddi.c

1893

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1899

tmp = intel_de_read(display, DDI_CLK_SEL(port));

sys/dev/pci/drm/i915/display/intel_ddi.c

190

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_ddi.c

191

return XELPDP_PORT_BUF_CTL1(display, port);

sys/dev/pci/drm/i915/display/intel_ddi.c

1918

return intel_get_dpll_by_id(display, id);

sys/dev/pci/drm/i915/display/intel_ddi.c

1923

struct intel_display *display = to_intel_display(encoder->base.dev);

sys/dev/pci/drm/i915/display/intel_ddi.c

1941

return intel_get_dpll_by_id(display, id);

sys/dev/pci/drm/i915/display/intel_ddi.c

1947

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1951

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

1954

mutex_lock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1956

intel_de_rmw(display, DPLL_CTRL2,

sys/dev/pci/drm/i915/display/intel_ddi.c

196

void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_ddi.c

1962

mutex_unlock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1967

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1970

mutex_lock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1972

intel_de_rmw(display, DPLL_CTRL2,

sys/dev/pci/drm/i915/display/intel_ddi.c

1975

mutex_unlock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1980

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1987

return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));

sys/dev/pci/drm/i915/display/intel_ddi.c

1992

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

1997

tmp = intel_de_read(display, DPLL_CTRL2);

sys/dev/pci/drm/i915/display/intel_ddi.c

2009

return intel_get_dpll_by_id(display, id);

sys/dev/pci/drm/i915/display/intel_ddi.c

2015

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

2019

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

2022

intel_de_write(display, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));

sys/dev/pci/drm/i915/display/intel_ddi.c

2027

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

2030

intel_de_write(display, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);

sys/dev/pci/drm/i915/display/intel_ddi.c

2035

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

2038

return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;

sys/dev/pci/drm/i915/display/intel_ddi.c

2043

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

2048

tmp = intel_de_read(display, PORT_CLK_SEL(port));

sys/dev/pci/drm/i915/display/intel_ddi.c

206

if (display->platform.broxton) {

sys/dev/pci/drm/i915/display/intel_ddi.c

2076

return intel_get_dpll_by_id(display, id);

sys/dev/pci/drm/i915/display/intel_ddi.c

2094

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

2114

if (drm_WARN_ON(display->drm, is_mst))

sys/dev/pci/drm/i915/display/intel_ddi.c

212

if (intel_de_wait_for_set(display, intel_ddi_buf_status_reg(display, port),

sys/dev/pci/drm/i915/display/intel_ddi.c

2129

for_each_intel_encoder(display->drm, other_encoder) {

sys/dev/pci/drm/i915/display/intel_ddi.c

2133

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

214

drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n",

sys/dev/pci/drm/i915/display/intel_ddi.c

2148

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

2156

tgl_dkl_phy_check_and_rewrite(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_ddi.c

2159

if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)))

sys/dev/pci/drm/i915/display/intel_ddi.c

2160

intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0);

sys/dev/pci/drm/i915/display/intel_ddi.c

2161

if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)))

sys/dev/pci/drm/i915/display/intel_ddi.c

2162

intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1);

sys/dev/pci/drm/i915/display/intel_ddi.c

2169

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_ddi.c

2175

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_ddi.c

2182

if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_ddi.c

2183

ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0));

sys/dev/pci/drm/i915/display/intel_ddi.c

2184

ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1));

sys/dev/pci/drm/i915/display/intel_ddi.c

2186

ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port));

sys/dev/pci/drm/i915/display/intel_ddi.c

2187

ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port));

sys/dev/pci/drm/i915/display/intel_ddi.c

2199

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

220

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

2244

if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_ddi.c

2245

intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0);

sys/dev/pci/drm/i915/display/intel_ddi.c

2246

intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1);

sys/dev/pci/drm/i915/display/intel_ddi.c

2248

if (IS_DISPLAY_VER(display, 12, 13))

sys/dev/pci/drm/i915/display/intel_ddi.c

2249

tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1);

sys/dev/pci/drm/i915/display/intel_ddi.c

2252

intel_de_write(display, MG_DP_MODE(0, tc_port), ln0);

sys/dev/pci/drm/i915/display/intel_ddi.c

2253

intel_de_write(display, MG_DP_MODE(1, tc_port), ln1);

sys/dev/pci/drm/i915/display/intel_ddi.c

2269

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

2271

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_ddi.c

2272

return TGL_DP_TP_CTL(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

2281

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

2283

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_ddi.c

2284

return TGL_DP_TP_STATUS(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

2293

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

2295

intel_de_write(display, dp_tp_status_reg(encoder, crtc_state),

sys/dev/pci/drm/i915/display/intel_ddi.c

2302

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

2304

if (intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state),

sys/dev/pci/drm/i915/display/intel_ddi.c

2306

drm_err(display->drm, "Timed out waiting for ACT sent\n");

sys/dev/pci/drm/i915/display/intel_ddi.c

231

if (DISPLAY_VER(display) < 10) {

sys/dev/pci/drm/i915/display/intel_ddi.c

2313

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_ddi.c

2320

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

2329

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_ddi.c

2336

drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n",

sys/dev/pci/drm/i915/display/intel_ddi.c

2342

drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n");

sys/dev/pci/drm/i915/display/intel_ddi.c

2347

struct intel_display *display = to_intel_display(aux->drm_dev);

sys/dev/pci/drm/i915/display/intel_ddi.c

2359

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

237

if (intel_de_wait_for_clear(display, intel_ddi_buf_status_reg(display, port),

sys/dev/pci/drm/i915/display/intel_ddi.c

2372

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

2380

ret = intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state),

sys/dev/pci/drm/i915/display/intel_ddi.c

2383

ret = intel_de_wait_for_clear(display, dp_tp_status_reg(encoder, crtc_state),

sys/dev/pci/drm/i915/display/intel_ddi.c

2387

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

239

drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n",

sys/dev/pci/drm/i915/display/intel_ddi.c

2408

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

2415

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

sys/dev/pci/drm/i915/display/intel_ddi.c

2418

if (DISPLAY_VER(display) < 30)

sys/dev/pci/drm/i915/display/intel_ddi.c

2426

drm_dbg_kms(display->drm, "Retry FEC enabling\n");

sys/dev/pci/drm/i915/display/intel_ddi.c

2428

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

sys/dev/pci/drm/i915/display/intel_ddi.c

2435

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

sys/dev/pci/drm/i915/display/intel_ddi.c

2443

drm_err(display->drm, "Failed to enable FEC after retries\n");

sys/dev/pci/drm/i915/display/intel_ddi.c

2449

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

2454

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

sys/dev/pci/drm/i915/display/intel_ddi.c

2456

intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));

sys/dev/pci/drm/i915/display/intel_ddi.c

2462

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

2468

intel_combo_phy_power_up_lanes(display, phy, false,

sys/dev/pci/drm/i915/display/intel_ddi.c

2478

static u8 intel_ddi_splitter_pipe_mask(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_ddi.c

2480

if (DISPLAY_VER(display) > 20)

sys/dev/pci/drm/i915/display/intel_ddi.c

2482

else if (display->platform.alderlake_p)

sys/dev/pci/drm/i915/display/intel_ddi.c

2491

struct intel_display *display = to_intel_display(pipe_config);

sys/dev/pci/drm/i915/display/intel_ddi.c

2496

if (!HAS_MSO(display))

sys/dev/pci/drm/i915/display/intel_ddi.c

2499

dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

sys/dev/pci/drm/i915/display/intel_ddi.c

2505

if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) {

sys/dev/pci/drm/i915/display/intel_ddi.c

2512

drm_WARN(display->drm, true,

sys/dev/pci/drm/i915/display/intel_ddi.c

2528

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_ddi.c

2533

if (!HAS_MSO(display))

sys/dev/pci/drm/i915/display/intel_ddi.c

2545

intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe),

sys/dev/pci/drm/i915/display/intel_ddi.c

2553

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

2559

if (DISPLAY_VER(display) < 14)

sys/dev/pci/drm/i915/display/intel_ddi.c

2562

if (DISPLAY_VER(display) >= 20) {

sys/dev/pci/drm/i915/display/intel_ddi.c

2567

reg = XELPDP_PORT_BUF_CTL1(display, port);

sys/dev/pci/drm/i915/display/intel_ddi.c

2572

intel_de_rmw(display, reg, 0, set_bits);

sys/dev/pci/drm/i915/display/intel_ddi.c

2574

ret = intel_de_wait_custom(display, reg,

sys/dev/pci/drm/i915/display/intel_ddi.c

2578

drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n",

sys/dev/pci/drm/i915/display/intel_ddi.c

2586

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

2601

intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port),

sys/dev/pci/drm/i915/display/intel_ddi.c

2608

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

2614

intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),

sys/dev/pci/drm/i915/display/intel_ddi.c

2741

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

2786

drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);

sys/dev/pci/drm/i915/display/intel_ddi.c

2787

dig_port->ddi_io_wakeref = intel_display_power_get(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

2888

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

2894

if (DISPLAY_VER(display) < 11)

sys/dev/pci/drm/i915/display/intel_ddi.c

2895

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

2898

drm_WARN_ON(display->drm, is_mst && port == PORT_A);

sys/dev/pci/drm/i915/display/intel_ddi.c

2915

drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);

sys/dev/pci/drm/i915/display/intel_ddi.c

2916

dig_port->ddi_io_wakeref = intel_display_power_get(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

2922

if (has_buf_trans_select(display))

sys/dev/pci/drm/i915/display/intel_ddi.c

2938

if ((port != PORT_A || DISPLAY_VER(display) >= 9) &&

sys/dev/pci/drm/i915/display/intel_ddi.c

2955

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

2957

if (HAS_DP20(display))

sys/dev/pci/drm/i915/display/intel_ddi.c

2964

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_ddi.c

2966

else if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_ddi.c

2983

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

2990

drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);

sys/dev/pci/drm/i915/display/intel_ddi.c

2991

dig_port->ddi_io_wakeref = intel_display_power_get(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

3026

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_ddi.c

3030

drm_WARN_ON(display->drm, crtc_state->has_pch_encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

3032

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_ddi.c

3055

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

3061

if (DISPLAY_VER(display) < 14)

sys/dev/pci/drm/i915/display/intel_ddi.c

3064

if (DISPLAY_VER(display) >= 20) {

sys/dev/pci/drm/i915/display/intel_ddi.c

3069

reg = XELPDP_PORT_BUF_CTL1(display, port);

sys/dev/pci/drm/i915/display/intel_ddi.c

3074

intel_de_rmw(display, reg, clr_bits, 0);

sys/dev/pci/drm/i915/display/intel_ddi.c

3076

ret = intel_de_wait_custom(display, reg,

sys/dev/pci/drm/i915/display/intel_ddi.c

3080

drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n",

sys/dev/pci/drm/i915/display/intel_ddi.c

3086

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

3089

intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE);

sys/dev/pci/drm/i915/display/intel_ddi.c

3090

intel_de_posting_read(display, DDI_BUF_CTL(port));

sys/dev/pci/drm/i915/display/intel_ddi.c

3098

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

3101

intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_ddi.c

3103

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_ddi.c

3104

intel_wait_ddi_buf_idle(display, port);

sys/dev/pci/drm/i915/display/intel_ddi.c

3109

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

sys/dev/pci/drm/i915/display/intel_ddi.c

3115

if (DISPLAY_VER(display) < 14)

sys/dev/pci/drm/i915/display/intel_ddi.c

3116

intel_wait_ddi_buf_idle(display, port);

sys/dev/pci/drm/i915/display/intel_ddi.c

3126

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

3143

if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_ddi.c

3147

intel_de_rmw(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

3148

TRANS_DDI_FUNC_CTL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_ddi.c

3168

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_ddi.c

3177

intel_display_power_put(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

3184

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_ddi.c

3185

intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),

sys/dev/pci/drm/i915/display/intel_ddi.c

3194

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

3202

if (DISPLAY_VER(display) < 12)

sys/dev/pci/drm/i915/display/intel_ddi.c

3207

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_ddi.c

3212

intel_display_power_put(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

3226

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

3232

for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {

sys/dev/pci/drm/i915/display/intel_ddi.c

3248

intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_ddi.c

3259

for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {

sys/dev/pci/drm/i915/display/intel_ddi.c

3265

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_ddi.c

3367

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

3372

if (port == PORT_A && DISPLAY_VER(display) < 9)

sys/dev/pci/drm/i915/display/intel_ddi.c

3387

gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_ddi.c

3397

drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9);

sys/dev/pci/drm/i915/display/intel_ddi.c

3399

if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E))

sys/dev/pci/drm/i915/display/intel_ddi.c

3402

return CHICKEN_TRANS(display, trans[port]);

sys/dev/pci/drm/i915/display/intel_ddi.c

3410

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

3419

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

3423

if (has_buf_trans_select(display))

sys/dev/pci/drm/i915/display/intel_ddi.c

3432

if (DISPLAY_VER(display) == 9 && !display->platform.broxton) {

sys/dev/pci/drm/i915/display/intel_ddi.c

3439

i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port);

sys/dev/pci/drm/i915/display/intel_ddi.c

3442

val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_ddi.c

3451

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_ddi.c

3452

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_ddi.c

3463

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_ddi.c

3484

if (DISPLAY_VER(display) >= 14) {

sys/dev/pci/drm/i915/display/intel_ddi.c

3492

intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port),

sys/dev/pci/drm/i915/display/intel_ddi.c

3497

if (DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/intel_ddi.c

3499

} else if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) {

sys/dev/pci/drm/i915/display/intel_ddi.c

3500

drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port));

sys/dev/pci/drm/i915/display/intel_ddi.c

3512

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

3523

intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_ddi.c

3525

intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_ddi.c

353

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

3539

intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0,

sys/dev/pci/drm/i915/display/intel_ddi.c

3550

for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state, i) {

sys/dev/pci/drm/i915/display/intel_ddi.c

3594

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

3599

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

366

if (DISPLAY_VER(display) >= 14) {

sys/dev/pci/drm/i915/display/intel_ddi.c

3663

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

3669

if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder))

sys/dev/pci/drm/i915/display/intel_ddi.c

3672

for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,

sys/dev/pci/drm/i915/display/intel_ddi.c

3688

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

3707

else if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_ddi.c

3714

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

3719

intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln),

sys/dev/pci/drm/i915/display/intel_ddi.c

3726

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_ddi.c

373

if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) {

sys/dev/pci/drm/i915/display/intel_ddi.c

3735

dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));

sys/dev/pci/drm/i915/display/intel_ddi.c

3737

drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE);

sys/dev/pci/drm/i915/display/intel_ddi.c

3749

intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);

sys/dev/pci/drm/i915/display/intel_ddi.c

3750

intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));

sys/dev/pci/drm/i915/display/intel_ddi.c

3762

if (DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/intel_ddi.c

3784

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_ddi.c

3789

dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));

sys/dev/pci/drm/i915/display/intel_ddi.c

379

if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) {

sys/dev/pci/drm/i915/display/intel_ddi.c

3791

drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE);

sys/dev/pci/drm/i915/display/intel_ddi.c

3802

intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);

sys/dev/pci/drm/i915/display/intel_ddi.c

3803

intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));

sys/dev/pci/drm/i915/display/intel_ddi.c

3805

if (display->platform.alderlake_p &&

sys/dev/pci/drm/i915/display/intel_ddi.c

3817

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_ddi.c

3821

temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));

sys/dev/pci/drm/i915/display/intel_ddi.c

3842

intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), temp);

sys/dev/pci/drm/i915/display/intel_ddi.c

3848

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_ddi.c

3852

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

sys/dev/pci/drm/i915/display/intel_ddi.c

386

static int icl_calc_tbt_pll_link(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_ddi.c

3862

if (port == PORT_A && DISPLAY_VER(display) < 12)

sys/dev/pci/drm/i915/display/intel_ddi.c

3865

if (intel_de_wait_for_set(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

3868

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

3872

static bool intel_ddi_is_audio_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_ddi.c

3878

if (!intel_display_power_is_enabled(display, POWER_DOMAIN_AUDIO_MMIO))

sys/dev/pci/drm/i915/display/intel_ddi.c

388

u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;

sys/dev/pci/drm/i915/display/intel_ddi.c

3881

return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) &

sys/dev/pci/drm/i915/display/intel_ddi.c

3911

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_ddi.c

3913

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_ddi.c

3915

else if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_ddi.c

3917

else if (display->platform.jasperlake || display->platform.elkhartlake)

sys/dev/pci/drm/i915/display/intel_ddi.c

3919

else if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_ddi.c

3923

static enum transcoder bdw_transcoder_master_readout(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_ddi.c

3928

if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/intel_ddi.c

3929

u32 ctl2 = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

3930

TRANS_DDI_FUNC_CTL2(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_ddi.c

3937

u32 ctl = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

3938

TRANS_DDI_FUNC_CTL(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_ddi.c

3954

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_ddi.c

3960

bdw_transcoder_master_readout(display, crtc_state->cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

3962

for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) {

sys/dev/pci/drm/i915/display/intel_ddi.c

3967

trans_wakeref = intel_display_power_get_if_enabled(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

3973

if (bdw_transcoder_master_readout(display, cpu_transcoder) ==

sys/dev/pci/drm/i915/display/intel_ddi.c

3977

intel_display_power_put(display, power_domain, trans_wakeref);

sys/dev/pci/drm/i915/display/intel_ddi.c

3980

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

3989

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

3992

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_ddi.c

4023

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

4027

intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &

sys/dev/pci/drm/i915/display/intel_ddi.c

4035

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

4047

if (DISPLAY_VER(display) >= 12 &&

sys/dev/pci/drm/i915/display/intel_ddi.c

4056

intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &

sys/dev/pci/drm/i915/display/intel_ddi.c

4059

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_ddi.c

4061

intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

4076

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

4084

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_ddi.c

4090

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_ddi.c

4092

intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

4102

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

4106

ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_ddi.c

4141

} else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) {

sys/dev/pci/drm/i915/display/intel_ddi.c

4147

} else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) {

sys/dev/pci/drm/i915/display/intel_ddi.c

4169

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

4173

if (drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)))

sys/dev/pci/drm/i915/display/intel_ddi.c

4181

intel_ddi_is_audio_enabled(display, cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

4188

if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_ddi.c

420

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_ddi.c

4209

if (DISPLAY_VER(display) >= 8)

sys/dev/pci/drm/i915/display/intel_ddi.c

4225

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

4230

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

4234

pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);

sys/dev/pci/drm/i915/display/intel_ddi.c

4235

drm_WARN_ON(display->drm, !pll_active);

sys/dev/pci/drm/i915/display/intel_ddi.c

4239

crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,

sys/dev/pci/drm/i915/display/intel_ddi.c

427

drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_ddi.c

4302

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

4305

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

4328

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

4333

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

4344

pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);

sys/dev/pci/drm/i915/display/intel_ddi.c

4345

drm_WARN_ON(display->drm, !pll_active);

sys/dev/pci/drm/i915/display/intel_ddi.c

4350

crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port);

sys/dev/pci/drm/i915/display/intel_ddi.c

4352

crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,

sys/dev/pci/drm/i915/display/intel_ddi.c

4399

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

4403

drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n",

sys/dev/pci/drm/i915/display/intel_ddi.c

4438

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

4443

if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A)

sys/dev/pci/drm/i915/display/intel_ddi.c

4458

if (display->platform.haswell && crtc->pipe == PIPE_A &&

sys/dev/pci/drm/i915/display/intel_ddi.c

4464

if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_ddi.c

450

drm_WARN_ON(display->drm, crtc_state->limited_color_range &&

sys/dev/pci/drm/i915/display/intel_ddi.c

4515

struct intel_display *display = to_intel_display(ref_crtc_state);

sys/dev/pci/drm/i915/display/intel_ddi.c

4527

if (DISPLAY_VER(display) < 9)

sys/dev/pci/drm/i915/display/intel_ddi.c

4559

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

4563

drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n",

sys/dev/pci/drm/i915/display/intel_ddi.c

4591

struct intel_display *display = to_intel_display(encoder->dev);

sys/dev/pci/drm/i915/display/intel_ddi.c

4597

intel_display_power_flush_work(display);

sys/dev/pci/drm/i915/display/intel_ddi.c

4635

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_ddi.c

4644

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_ddi.c

4662

privacy_screen = drm_privacy_screen_get(display->drm->dev, NULL);

sys/dev/pci/drm/i915/display/intel_ddi.c

4667

drm_warn(display->drm, "Error getting privacy-screen\n");

sys/dev/pci/drm/i915/display/intel_ddi.c

4677

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

4690

ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,

sys/dev/pci/drm/i915/display/intel_ddi.c

4707

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

4723

drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n",

sys/dev/pci/drm/i915/display/intel_ddi.c

473

intel_de_write(display, TRANS_MSA_MISC(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_ddi.c

4743

return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx);

sys/dev/pci/drm/i915/display/intel_ddi.c

4748

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

4752

drm_WARN_ON(display->drm, !dig_port->dp.attached_connector);

sys/dev/pci/drm/i915/display/intel_ddi.c

4815

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

4816

u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin];

sys/dev/pci/drm/i915/display/intel_ddi.c

4818

return intel_de_read(display, SDEISR) & bit;

sys/dev/pci/drm/i915/display/intel_ddi.c

4823

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

4824

u32 bit = display->hotplug.hpd[encoder->hpd_pin];

sys/dev/pci/drm/i915/display/intel_ddi.c

4826

return intel_de_read(display, DEISR) & bit;

sys/dev/pci/drm/i915/display/intel_ddi.c

4831

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

4832

u32 bit = display->hotplug.hpd[encoder->hpd_pin];

sys/dev/pci/drm/i915/display/intel_ddi.c

4834

return intel_de_read(display, GEN8_DE_PORT_ISR) & bit;

sys/dev/pci/drm/i915/display/intel_ddi.c

4863

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_ddi.c

4874

if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_ddi.c

4883

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_ddi.c

4887

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_ddi.c

489

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_ddi.c

4891

if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)

sys/dev/pci/drm/i915/display/intel_ddi.c

4904

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

4913

static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_ddi.c

4923

static enum hpd_pin dg1_hpd_pin(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_ddi.c

493

if (!HAS_DP20(display))

sys/dev/pci/drm/i915/display/intel_ddi.c

4931

static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_ddi.c

4939

static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_ddi.c

4941

if (HAS_PCH_TGP(display))

sys/dev/pci/drm/i915/display/intel_ddi.c

4942

return tgl_hpd_pin(display, port);

sys/dev/pci/drm/i915/display/intel_ddi.c

4950

static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_ddi.c

4958

static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_ddi.c

4963

if (HAS_PCH_TGP(display))

sys/dev/pci/drm/i915/display/intel_ddi.c

4964

return icl_hpd_pin(display, port);

sys/dev/pci/drm/i915/display/intel_ddi.c

4969

static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_ddi.c

4971

if (HAS_PCH_TGP(display))

sys/dev/pci/drm/i915/display/intel_ddi.c

4972

return icl_hpd_pin(display, port);

sys/dev/pci/drm/i915/display/intel_ddi.c

4977

static bool intel_ddi_is_tc(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_ddi.c

4979

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_ddi.c

4981

else if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_ddi.c

499

intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val);

sys/dev/pci/drm/i915/display/intel_ddi.c

5024

static bool port_strap_detected(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_ddi.c

5027

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_ddi.c

5032

return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;

sys/dev/pci/drm/i915/display/intel_ddi.c

5034

return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED;

sys/dev/pci/drm/i915/display/intel_ddi.c

5036

return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED;

sys/dev/pci/drm/i915/display/intel_ddi.c

5038

return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED;

sys/dev/pci/drm/i915/display/intel_ddi.c

5052

static bool assert_has_icl_dsi(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_ddi.c

5054

return !drm_WARN(display->drm, !display->platform.alderlake_p &&

sys/dev/pci/drm/i915/display/intel_ddi.c

5055

!display->platform.tigerlake && DISPLAY_VER(display) != 11,

sys/dev/pci/drm/i915/display/intel_ddi.c

5059

static bool port_in_use(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_ddi.c

5063

for_each_intel_encoder(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5072

static const char *intel_ddi_encoder_name(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_ddi.c

5076

if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5080

} else if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5081

enum tc_port tc_port = intel_port_to_tc(display, port);

sys/dev/pci/drm/i915/display/intel_ddi.c

5088

} else if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5089

enum tc_port tc_port = intel_port_to_tc(display, port);

sys/dev/pci/drm/i915/display/intel_ddi.c

5100

drm_WARN_ON(display->drm, seq_buf_has_overflowed(s));

sys/dev/pci/drm/i915/display/intel_ddi.c

5105

void intel_ddi_init(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_ddi.c

512

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_ddi.c

5120

if (!port_strap_detected(display, port)) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5121

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

5126

if (!assert_port_valid(display, port))

sys/dev/pci/drm/i915/display/intel_ddi.c

5129

if (port_in_use(display, port)) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5130

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

5137

if (!assert_has_icl_dsi(display))

sys/dev/pci/drm/i915/display/intel_ddi.c

5140

icl_dsi_init(display, devdata);

sys/dev/pci/drm/i915/display/intel_ddi.c

5144

phy = intel_port_to_phy(display, port);

sys/dev/pci/drm/i915/display/intel_ddi.c

5152

if (intel_hti_uses_phy(display, phy)) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5153

drm_dbg_kms(display->drm, "PORT %c / PHY %c reserved by HTI\n",

sys/dev/pci/drm/i915/display/intel_ddi.c

5170

drm_dbg_kms(display->drm, "VBT says port %c has lspcon\n",

sys/dev/pci/drm/i915/display/intel_ddi.c

5175

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

5181

if (intel_phy_is_snps(display, phy) &&

sys/dev/pci/drm/i915/display/intel_ddi.c

5182

display->snps.phy_failed_calibration & BIT(phy)) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5183

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

5195

drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs,

sys/dev/pci/drm/i915/display/intel_ddi.c

5197

intel_ddi_encoder_name(display, port, phy, &encoder_name));

sys/dev/pci/drm/i915/display/intel_ddi.c

521

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_ddi.c

5222

encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port);

sys/dev/pci/drm/i915/display/intel_ddi.c

5227

if (DISPLAY_VER(display) >= 14) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5232

} else if (display->platform.dg2) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5236

} else if (display->platform.alderlake_s) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5241

} else if (display->platform.rocketlake) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5246

} else if (display->platform.dg1) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5251

} else if (display->platform.jasperlake || display->platform.elkhartlake) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5252

if (intel_ddi_is_tc(display, port)) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5264

} else if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5265

if (intel_ddi_is_tc(display, port)) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5277

} else if (display->platform.geminilake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5280

} else if (DISPLAY_VER(display) == 9) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5285

} else if (display->platform.broadwell || display->platform.haswell) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5292

if (DISPLAY_VER(display) >= 14) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5294

} else if (display->platform.dg2) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5296

} else if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5301

} else if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5306

} else if (display->platform.geminilake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5314

if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/intel_ddi.c

5315

encoder->hpd_pin = xelpd_hpd_pin(display, port);

sys/dev/pci/drm/i915/display/intel_ddi.c

5316

else if (display->platform.dg1)

sys/dev/pci/drm/i915/display/intel_ddi.c

5317

encoder->hpd_pin = dg1_hpd_pin(display, port);

sys/dev/pci/drm/i915/display/intel_ddi.c

5318

else if (display->platform.rocketlake)

sys/dev/pci/drm/i915/display/intel_ddi.c

5319

encoder->hpd_pin = rkl_hpd_pin(display, port);

sys/dev/pci/drm/i915/display/intel_ddi.c

5320

else if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_ddi.c

5321

encoder->hpd_pin = tgl_hpd_pin(display, port);

sys/dev/pci/drm/i915/display/intel_ddi.c

5322

else if (display->platform.jasperlake || display->platform.elkhartlake)

sys/dev/pci/drm/i915/display/intel_ddi.c

5323

encoder->hpd_pin = ehl_hpd_pin(display, port);

sys/dev/pci/drm/i915/display/intel_ddi.c

5324

else if (DISPLAY_VER(display) == 11)

sys/dev/pci/drm/i915/display/intel_ddi.c

5325

encoder->hpd_pin = icl_hpd_pin(display, port);

sys/dev/pci/drm/i915/display/intel_ddi.c

5326

else if (DISPLAY_VER(display) == 9 && !display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_ddi.c

5327

encoder->hpd_pin = skl_hpd_pin(display, port);

sys/dev/pci/drm/i915/display/intel_ddi.c

5331

ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port));

sys/dev/pci/drm/i915/display/intel_ddi.c

5336

dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES;

sys/dev/pci/drm/i915/display/intel_ddi.c

5354

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

5371

drm_WARN_ON(display->drm, port > PORT_I);

sys/dev/pci/drm/i915/display/intel_ddi.c

5372

dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port);

sys/dev/pci/drm/i915/display/intel_ddi.c

5374

if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5379

} else if (display->platform.geminilake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5381

} else if (DISPLAY_VER(display) == 9) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5383

} else if (display->platform.broadwell) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5388

} else if (display->platform.haswell) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5404

encoder->pipe_mask = intel_ddi_splitter_pipe_mask(display);

sys/dev/pci/drm/i915/display/intel_ddi.c

583

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_ddi.c

596

if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_ddi.c

600

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

610

if (IS_DISPLAY_VER(display, 8, 10) &&

sys/dev/pci/drm/i915/display/intel_ddi.c

625

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_ddi.c

628

if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/intel_ddi.c

640

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

641

TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_ddi.c

645

intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_ddi.c

659

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_ddi.c

667

intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_ddi.c

679

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_ddi.c

684

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_ddi.c

685

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

686

TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_ddi.c

689

ctl = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

690

TRANS_DDI_FUNC_CTL(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_ddi.c

696

if (IS_DISPLAY_VER(display, 8, 10))

sys/dev/pci/drm/i915/display/intel_ddi.c

700

if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_ddi.c

709

intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_ddi.c

715

if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) &&

sys/dev/pci/drm/i915/display/intel_ddi.c

717

drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n");

sys/dev/pci/drm/i915/display/intel_ddi.c

727

struct intel_display *display = to_intel_display(intel_encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

731

wakeref = intel_display_power_get_if_enabled(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

733

if (drm_WARN_ON(display->drm, !wakeref))

sys/dev/pci/drm/i915/display/intel_ddi.c

736

intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_ddi.c

738

intel_display_power_put(display, intel_encoder->power_domain, wakeref);

sys/dev/pci/drm/i915/display/intel_ddi.c

744

struct intel_display *display = to_intel_display(intel_connector);

sys/dev/pci/drm/i915/display/intel_ddi.c

754

wakeref = intel_display_power_get_if_enabled(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

765

if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A)

sys/dev/pci/drm/i915/display/intel_ddi.c

770

ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) &

sys/dev/pci/drm/i915/display/intel_ddi.c

776

} else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) {

sys/dev/pci/drm/i915/display/intel_ddi.c

781

} else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) {

sys/dev/pci/drm/i915/display/intel_ddi.c

787

} else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) {

sys/dev/pci/drm/i915/display/intel_ddi.c

795

intel_display_power_put(display, encoder->power_domain, wakeref);

sys/dev/pci/drm/i915/display/intel_ddi.c

803

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi.c

813

wakeref = intel_display_power_get_if_enabled(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

818

tmp = intel_de_read(display, DDI_BUF_CTL(port));

sys/dev/pci/drm/i915/display/intel_ddi.c

822

if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) {

sys/dev/pci/drm/i915/display/intel_ddi.c

823

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

824

TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP));

sys/dev/pci/drm/i915/display/intel_ddi.c

845

for_each_pipe(display, p) {

sys/dev/pci/drm/i915/display/intel_ddi.c

850

trans_wakeref = intel_display_power_get_if_enabled(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

855

if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_ddi.c

863

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

864

TRANS_DDI_FUNC_CTL(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_ddi.c

865

intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_ddi.c

875

else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display))

sys/dev/pci/drm/i915/display/intel_ddi.c

882

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

905

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

913

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

921

if (*pipe_mask && (display->platform.geminilake || display->platform.broxton)) {

sys/dev/pci/drm/i915/display/intel_ddi.c

922

tmp = intel_de_read(display, BXT_PHY_CTL(port));

sys/dev/pci/drm/i915/display/intel_ddi.c

926

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_ddi.c

931

intel_display_power_put(display, encoder->power_domain, wakeref);

sys/dev/pci/drm/i915/display/intel_ddi.c

954

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_ddi.c

970

return intel_display_power_aux_io_domain(display, dig_port->aux_ch);

sys/dev/pci/drm/i915/display/intel_ddi.c

971

else if (DISPLAY_VER(display) < 14 &&

sys/dev/pci/drm/i915/display/intel_ddi.c

983

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_ddi.c

987

drm_WARN_ON(display->drm, dig_port->aux_wakeref);

sys/dev/pci/drm/i915/display/intel_ddi.c

992

dig_port->aux_wakeref = intel_display_power_get(display, domain);

sys/dev/pci/drm/i915/display/intel_ddi.c

999

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_ddi.h

56

void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port);

sys/dev/pci/drm/i915/display/intel_ddi.h

57

void intel_ddi_init(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1410

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1413

if (display->platform.tigerlake_uy) {

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1712

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1714

if (DISPLAY_VER(display) >= 14) {

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1719

} else if (display->platform.dg2) {

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1721

} else if (display->platform.alderlake_p) {

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1726

} else if (display->platform.alderlake_s) {

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1728

} else if (display->platform.rocketlake) {

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1730

} else if (display->platform.dg1) {

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1732

} else if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1737

} else if (DISPLAY_VER(display) == 11) {

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1738

if (display->platform.jasperlake)

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1740

else if (display->platform.elkhartlake)

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1746

} else if (display->platform.geminilake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1748

} else if (display->platform.cometlake_ulx ||

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1749

display->platform.coffeelake_ulx ||

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1750

display->platform.kabylake_ulx) {

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1752

} else if (display->platform.cometlake_ult ||

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1753

display->platform.coffeelake_ult ||

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1754

display->platform.kabylake_ult) {

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1756

} else if (display->platform.cometlake ||

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1757

display->platform.coffeelake ||

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1758

display->platform.kabylake) {

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1760

} else if (display->platform.skylake_ulx) {

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1762

} else if (display->platform.skylake_ult) {

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1764

} else if (display->platform.skylake) {

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1766

} else if (display->platform.broadwell) {

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1768

} else if (display->platform.haswell) {

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1771

struct pci_dev *pdev = display->drm->pdev;

sys/dev/pci/drm/i915/display/intel_de.h

100

val = __intel_de_rmw_nowl(display, reg, clear, set);

sys/dev/pci/drm/i915/display/intel_de.h

102

intel_dmc_wl_put(display, reg);

sys/dev/pci/drm/i915/display/intel_de.h

108

__intel_de_wait_for_register_nowl(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_de.h

112

return intel_wait_for_register(__to_uncore(display), reg, mask,

sys/dev/pci/drm/i915/display/intel_de.h

117

__intel_de_wait_for_register_atomic_nowl(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_de.h

122

return __intel_wait_for_register(__to_uncore(display), reg, mask,

sys/dev/pci/drm/i915/display/intel_de.h

127

intel_de_wait(struct intel_display *display, i915_reg_t reg,

sys/dev/pci/drm/i915/display/intel_de.h

132

intel_dmc_wl_get(display, reg);

sys/dev/pci/drm/i915/display/intel_de.h

134

ret = __intel_de_wait_for_register_nowl(display, reg, mask, value,

sys/dev/pci/drm/i915/display/intel_de.h

137

intel_dmc_wl_put(display, reg);

sys/dev/pci/drm/i915/display/intel_de.h

143

intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,

sys/dev/pci/drm/i915/display/intel_de.h

148

intel_dmc_wl_get(display, reg);

sys/dev/pci/drm/i915/display/intel_de.h

15

static inline struct intel_uncore *__to_uncore(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_de.h

150

ret = intel_wait_for_register_fw(__to_uncore(display), reg, mask,

sys/dev/pci/drm/i915/display/intel_de.h

153

intel_dmc_wl_put(display, reg);

sys/dev/pci/drm/i915/display/intel_de.h

159

intel_de_wait_custom(struct intel_display *display, i915_reg_t reg,

sys/dev/pci/drm/i915/display/intel_de.h

166

intel_dmc_wl_get(display, reg);

sys/dev/pci/drm/i915/display/intel_de.h

168

ret = __intel_wait_for_register(__to_uncore(display), reg, mask,

sys/dev/pci/drm/i915/display/intel_de.h

17

return to_intel_uncore(display->drm);

sys/dev/pci/drm/i915/display/intel_de.h

172

intel_dmc_wl_put(display, reg);

sys/dev/pci/drm/i915/display/intel_de.h

178

intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg,

sys/dev/pci/drm/i915/display/intel_de.h

181

return intel_de_wait(display, reg, mask, mask, timeout_ms);

sys/dev/pci/drm/i915/display/intel_de.h

185

intel_de_wait_for_clear(struct intel_display *display, i915_reg_t reg,

sys/dev/pci/drm/i915/display/intel_de.h

188

return intel_de_wait(display, reg, mask, 0, timeout_ms);

sys/dev/pci/drm/i915/display/intel_de.h

200

intel_de_read_fw(struct intel_display *display, i915_reg_t reg)

sys/dev/pci/drm/i915/display/intel_de.h

204

val = intel_uncore_read_fw(__to_uncore(display), reg);

sys/dev/pci/drm/i915/display/intel_de.h

21

intel_de_read(struct intel_display *display, i915_reg_t reg)

sys/dev/pci/drm/i915/display/intel_de.h

211

intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val)

sys/dev/pci/drm/i915/display/intel_de.h

214

intel_uncore_write_fw(__to_uncore(display), reg, val);

sys/dev/pci/drm/i915/display/intel_de.h

218

intel_de_read_notrace(struct intel_display *display, i915_reg_t reg)

sys/dev/pci/drm/i915/display/intel_de.h

220

return intel_uncore_read_notrace(__to_uncore(display), reg);

sys/dev/pci/drm/i915/display/intel_de.h

224

intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, u32 val)

sys/dev/pci/drm/i915/display/intel_de.h

226

intel_uncore_write_notrace(__to_uncore(display), reg, val);

sys/dev/pci/drm/i915/display/intel_de.h

230

intel_de_write_dsb(struct intel_display *display, struct intel_dsb *dsb,

sys/dev/pci/drm/i915/display/intel_de.h

236

intel_de_write_fw(display, reg, val);

sys/dev/pci/drm/i915/display/intel_de.h

25

intel_dmc_wl_get(display, reg);

sys/dev/pci/drm/i915/display/intel_de.h

27

val = intel_uncore_read(__to_uncore(display), reg);

sys/dev/pci/drm/i915/display/intel_de.h

29

intel_dmc_wl_put(display, reg);

sys/dev/pci/drm/i915/display/intel_de.h

35

intel_de_read8(struct intel_display *display, i915_reg_t reg)

sys/dev/pci/drm/i915/display/intel_de.h

39

intel_dmc_wl_get(display, reg);

sys/dev/pci/drm/i915/display/intel_de.h

41

val = intel_uncore_read8(__to_uncore(display), reg);

sys/dev/pci/drm/i915/display/intel_de.h

43

intel_dmc_wl_put(display, reg);

sys/dev/pci/drm/i915/display/intel_de.h

49

intel_de_read64_2x32(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_de.h

54

intel_dmc_wl_get(display, lower_reg);

sys/dev/pci/drm/i915/display/intel_de.h

55

intel_dmc_wl_get(display, upper_reg);

sys/dev/pci/drm/i915/display/intel_de.h

57

val = intel_uncore_read64_2x32(__to_uncore(display), lower_reg,

sys/dev/pci/drm/i915/display/intel_de.h

60

intel_dmc_wl_put(display, upper_reg);

sys/dev/pci/drm/i915/display/intel_de.h

61

intel_dmc_wl_put(display, lower_reg);

sys/dev/pci/drm/i915/display/intel_de.h

67

intel_de_posting_read(struct intel_display *display, i915_reg_t reg)

sys/dev/pci/drm/i915/display/intel_de.h

69

intel_dmc_wl_get(display, reg);

sys/dev/pci/drm/i915/display/intel_de.h

71

intel_uncore_posting_read(__to_uncore(display), reg);

sys/dev/pci/drm/i915/display/intel_de.h

73

intel_dmc_wl_put(display, reg);

sys/dev/pci/drm/i915/display/intel_de.h

77

intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val)

sys/dev/pci/drm/i915/display/intel_de.h

79

intel_dmc_wl_get(display, reg);

sys/dev/pci/drm/i915/display/intel_de.h

81

intel_uncore_write(__to_uncore(display), reg, val);

sys/dev/pci/drm/i915/display/intel_de.h

83

intel_dmc_wl_put(display, reg);

sys/dev/pci/drm/i915/display/intel_de.h

87

__intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg,

sys/dev/pci/drm/i915/display/intel_de.h

90

return intel_uncore_rmw(__to_uncore(display), reg, clear, set);

sys/dev/pci/drm/i915/display/intel_de.h

94

intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set)

sys/dev/pci/drm/i915/display/intel_de.h

98

intel_dmc_wl_get(display, reg);

sys/dev/pci/drm/i915/display/intel_display.c

1049

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

1056

intel_frontbuffer_flip(display, new_crtc_state->fb_bits);

sys/dev/pci/drm/i915/display/intel_display.c

1059

intel_update_watermarks(display);

sys/dev/pci/drm/i915/display/intel_display.c

1065

intel_async_flip_vtd_wa(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

1069

skl_wa_827(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

1073

icl_wa_scalerclkgating(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

1077

icl_wa_cursorclkgating(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

1085

if (intel_display_wa(display, 14011503117)) {

sys/dev/pci/drm/i915/display/intel_display.c

1180

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

1208

intel_async_flip_vtd_wa(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1213

skl_wa_827(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1218

icl_wa_scalerclkgating(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1223

icl_wa_cursorclkgating(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1234

if (HAS_GMCH(display) && old_crtc_state->hw.active &&

sys/dev/pci/drm/i915/display/intel_display.c

1235

new_crtc_state->disable_cxsr && intel_set_memory_cxsr(display, false))

sys/dev/pci/drm/i915/display/intel_display.c

1245

if (!HAS_GMCH(display) && old_crtc_state->hw.active &&

sys/dev/pci/drm/i915/display/intel_display.c

1246

new_crtc_state->disable_cxsr && ilk_disable_cxsr(display))

sys/dev/pci/drm/i915/display/intel_display.c

1270

intel_update_watermarks(display);

sys/dev/pci/drm/i915/display/intel_display.c

1281

if (DISPLAY_VER(display) == 2 && planes_disabling(old_crtc_state, new_crtc_state))

sys/dev/pci/drm/i915/display/intel_display.c

1282

intel_set_cpu_fifo_underrun_reporting(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

1295

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

1317

intel_frontbuffer_flip(display, fb_bits);

sys/dev/pci/drm/i915/display/intel_display.c

1322

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

1331

if (display->dpll.mgr) {

sys/dev/pci/drm/i915/display/intel_display.c

1521

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

1526

if (drm_WARN_ON(display->drm, crtc->active))

sys/dev/pci/drm/i915/display/intel_display.c

1539

intel_set_cpu_fifo_underrun_reporting(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

1540

intel_set_pch_fifo_underrun_reporting(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

1553

assert_fdi_tx_disabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_display.c

1554

assert_fdi_rx_disabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_display.c

1575

if (HAS_PCH_CPT(display))

sys/dev/pci/drm/i915/display/intel_display.c

1588

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1589

intel_set_pch_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1595

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

1597

return DISPLAY_VER(display) == 10 && crtc_state->pch_pfit.enabled;

sys/dev/pci/drm/i915/display/intel_display.c

1602

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

1605

intel_de_rmw(display, CLKGATE_DIS_PSL(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_display.c

1611

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

1614

intel_de_write(display, WM_LINETIME(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_display.c

1621

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

1623

intel_de_rmw(display, CHICKEN_TRANS(display, crtc_state->cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

1630

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

1647

intel_de_write(display, TRANS_MULT(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

1658

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

1665

if (drm_WARN_ON(display->drm, crtc->active))

sys/dev/pci/drm/i915/display/intel_display.c

1667

for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {

sys/dev/pci/drm/i915/display/intel_display.c

1681

for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {

sys/dev/pci/drm/i915/display/intel_display.c

1687

if (HAS_UNCOMPRESSED_JOINER(display))

sys/dev/pci/drm/i915/display/intel_display.c

1692

if (DISPLAY_VER(display) >= 9 || display->platform.broadwell)

sys/dev/pci/drm/i915/display/intel_display.c

1699

for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {

sys/dev/pci/drm/i915/display/intel_display.c

1708

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_display.c

1721

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_display.c

1729

for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {

sys/dev/pci/drm/i915/display/intel_display.c

1744

if (display->platform.haswell && hsw_workaround_pipe != INVALID_PIPE) {

sys/dev/pci/drm/i915/display/intel_display.c

1746

intel_crtc_for_pipe(display, hsw_workaround_pipe);

sys/dev/pci/drm/i915/display/intel_display.c

1757

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

1767

intel_set_cpu_fifo_underrun_reporting(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

1768

intel_set_pch_fifo_underrun_reporting(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

1786

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1787

intel_set_pch_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1793

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

1810

for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {

sys/dev/pci/drm/i915/display/intel_display.c

1819

bool intel_phy_is_combo(struct intel_display *display, enum phy phy)

sys/dev/pci/drm/i915/display/intel_display.c

1823

else if (display->platform.alderlake_s)

sys/dev/pci/drm/i915/display/intel_display.c

1825

else if (display->platform.dg1 || display->platform.rocketlake)

sys/dev/pci/drm/i915/display/intel_display.c

1827

else if (display->platform.jasperlake || display->platform.elkhartlake)

sys/dev/pci/drm/i915/display/intel_display.c

1829

else if (display->platform.alderlake_p || IS_DISPLAY_VER(display, 11, 12))

sys/dev/pci/drm/i915/display/intel_display.c

1841

bool intel_phy_is_tc(struct intel_display *display, enum phy phy)

sys/dev/pci/drm/i915/display/intel_display.c

1847

if (display->platform.dgfx)

sys/dev/pci/drm/i915/display/intel_display.c

1850

if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/intel_display.c

1852

else if (display->platform.tigerlake)

sys/dev/pci/drm/i915/display/intel_display.c

1854

else if (display->platform.icelake)

sys/dev/pci/drm/i915/display/intel_display.c

1861

bool intel_phy_is_snps(struct intel_display *display, enum phy phy)

sys/dev/pci/drm/i915/display/intel_display.c

1867

return display->platform.dg2 && phy > PHY_NONE && phy <= PHY_E;

sys/dev/pci/drm/i915/display/intel_display.c

1871

enum phy intel_port_to_phy(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_display.c

1873

if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD)

sys/dev/pci/drm/i915/display/intel_display.c

1875

else if (DISPLAY_VER(display) >= 13 && port >= PORT_TC1)

sys/dev/pci/drm/i915/display/intel_display.c

1877

else if (display->platform.alderlake_s && port >= PORT_TC1)

sys/dev/pci/drm/i915/display/intel_display.c

1879

else if ((display->platform.dg1 || display->platform.rocketlake) && port >= PORT_TC1)

sys/dev/pci/drm/i915/display/intel_display.c

1881

else if ((display->platform.jasperlake || display->platform.elkhartlake) &&

sys/dev/pci/drm/i915/display/intel_display.c

1889

enum tc_port intel_port_to_tc(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_display.c

1891

if (!intel_phy_is_tc(display, intel_port_to_phy(display, port)))

sys/dev/pci/drm/i915/display/intel_display.c

1894

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_display.c

190

void intel_update_czclk(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display.c

1902

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_display.c

1904

return intel_port_to_phy(display, encoder->port);

sys/dev/pci/drm/i915/display/intel_display.c

1909

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_display.c

1911

return intel_phy_is_combo(display, intel_encoder_to_phy(encoder));

sys/dev/pci/drm/i915/display/intel_display.c

1916

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_display.c

1918

return intel_phy_is_snps(display, intel_encoder_to_phy(encoder));

sys/dev/pci/drm/i915/display/intel_display.c

192

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display.c

1923

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_display.c

1925

return intel_phy_is_tc(display, intel_encoder_to_phy(encoder));

sys/dev/pci/drm/i915/display/intel_display.c

1930

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_display.c

1932

return intel_port_to_tc(display, encoder->port);

sys/dev/pci/drm/i915/display/intel_display.c

1938

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_display.c

194

if (!display->platform.valleyview && !display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_display.c

1941

return intel_display_power_tbt_aux_domain(display, dig_port->aux_ch);

sys/dev/pci/drm/i915/display/intel_display.c

1943

return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch);

sys/dev/pci/drm/i915/display/intel_display.c

1949

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

1966

drm_for_each_encoder_mask(encoder, display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

197

dev_priv->czclk_freq = vlv_get_cck_clock_hpll(display->drm, "czclk",

sys/dev/pci/drm/i915/display/intel_display.c

1973

if (HAS_DDI(display) && crtc_state->has_audio)

sys/dev/pci/drm/i915/display/intel_display.c

1986

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

200

drm_dbg_kms(display->drm, "CZ clock rate: %d kHz\n", dev_priv->czclk_freq);

sys/dev/pci/drm/i915/display/intel_display.c

2003

intel_display_power_get_in_set(display,

sys/dev/pci/drm/i915/display/intel_display.c

2011

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

2013

intel_display_power_put_mask_in_set(display,

sys/dev/pci/drm/i915/display/intel_display.c

2038

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

2043

if (drm_WARN_ON(display->drm, crtc->active))

sys/dev/pci/drm/i915/display/intel_display.c

2050

intel_de_write(display, VLV_PIPE_MSA_MISC(display, pipe), 0);

sys/dev/pci/drm/i915/display/intel_display.c

2052

if (display->platform.cherryview && pipe == PIPE_B) {

sys/dev/pci/drm/i915/display/intel_display.c

2053

intel_de_write(display, CHV_BLEND(display, pipe),

sys/dev/pci/drm/i915/display/intel_display.c

2055

intel_de_write(display, CHV_CANVAS(display, pipe), 0);

sys/dev/pci/drm/i915/display/intel_display.c

2060

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

2064

if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_display.c

2086

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

2091

if (drm_WARN_ON(display->drm, crtc->active))

sys/dev/pci/drm/i915/display/intel_display.c

2100

if (DISPLAY_VER(display) != 2)

sys/dev/pci/drm/i915/display/intel_display.c

2101

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

211

skl_wa_827(struct intel_display *display, enum pipe pipe, bool enable)

sys/dev/pci/drm/i915/display/intel_display.c

2112

intel_update_watermarks(display);

sys/dev/pci/drm/i915/display/intel_display.c

2120

if (DISPLAY_VER(display) == 2)

sys/dev/pci/drm/i915/display/intel_display.c

2127

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

213

intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),

sys/dev/pci/drm/i915/display/intel_display.c

2136

if (DISPLAY_VER(display) == 2)

sys/dev/pci/drm/i915/display/intel_display.c

2150

if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_display.c

2151

chv_disable_pll(display, pipe);

sys/dev/pci/drm/i915/display/intel_display.c

2152

else if (display->platform.valleyview)

sys/dev/pci/drm/i915/display/intel_display.c

2153

vlv_disable_pll(display, pipe);

sys/dev/pci/drm/i915/display/intel_display.c

2160

if (DISPLAY_VER(display) != 2)

sys/dev/pci/drm/i915/display/intel_display.c

2161

intel_set_cpu_fifo_underrun_reporting(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

2163

if (!display->funcs.wm->initial_watermarks)

sys/dev/pci/drm/i915/display/intel_display.c

2164

intel_update_watermarks(display);

sys/dev/pci/drm/i915/display/intel_display.c

2167

if (display->platform.i830)

sys/dev/pci/drm/i915/display/intel_display.c

2168

i830_enable_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_display.c

2181

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

2184

return HAS_DOUBLE_WIDE(display) &&

sys/dev/pci/drm/i915/display/intel_display.c

2185

(crtc->pipe == PIPE_A || display->platform.i915g);

sys/dev/pci/drm/i915/display/intel_display.c

220

icl_wa_scalerclkgating(struct intel_display *display, enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_display.c

223

intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),

sys/dev/pci/drm/i915/display/intel_display.c

2232

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

2234

if (HAS_GMCH(display))

sys/dev/pci/drm/i915/display/intel_display.c

230

icl_wa_cursorclkgating(struct intel_display *display, enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_display.c

233

intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),

sys/dev/pci/drm/i915/display/intel_display.c

2345

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

2358

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

2365

intel_is_dual_link_lvds(display)) {

sys/dev/pci/drm/i915/display/intel_display.c

2366

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

2378

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

2382

int clock_limit = display->cdclk.max_dotclk_freq;

sys/dev/pci/drm/i915/display/intel_display.c

2397

if (DISPLAY_VER(display) < 4) {

sys/dev/pci/drm/i915/display/intel_display.c

2398

clock_limit = display->cdclk.max_cdclk_freq * 9 / 10;

sys/dev/pci/drm/i915/display/intel_display.c

2406

clock_limit = display->cdclk.max_dotclk_freq;

sys/dev/pci/drm/i915/display/intel_display.c

2412

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

2425

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

2428

if (!HAS_DSB(display))

sys/dev/pci/drm/i915/display/intel_display.c

2439

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

2450

drm_dbg_kms(display->drm, "[CRTC:%d:%s] vblank delay (%d) exceeds max (%d)\n",

sys/dev/pci/drm/i915/display/intel_display.c

2541

void intel_panel_sanitize_ssc(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display.c

2549

if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display)) {

sys/dev/pci/drm/i915/display/intel_display.c

2550

bool bios_lvds_use_ssc = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

2554

if (display->vbt.lvds_use_ssc != bios_lvds_use_ssc) {

sys/dev/pci/drm/i915/display/intel_display.c

2555

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

2558

str_enabled_disabled(display->vbt.lvds_use_ssc));

sys/dev/pci/drm/i915/display/intel_display.c

2559

display->vbt.lvds_use_ssc = bios_lvds_use_ssc;

sys/dev/pci/drm/i915/display/intel_display.c

2571

void intel_set_m_n(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display.c

2576

intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);

sys/dev/pci/drm/i915/display/intel_display.c

2577

intel_de_write(display, data_n_reg, m_n->data_n);

sys/dev/pci/drm/i915/display/intel_display.c

2578

intel_de_write(display, link_m_reg, m_n->link_m);

sys/dev/pci/drm/i915/display/intel_display.c

2583

intel_de_write(display, link_n_reg, m_n->link_n);

sys/dev/pci/drm/i915/display/intel_display.c

2586

bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display.c

2589

if (display->platform.haswell)

sys/dev/pci/drm/i915/display/intel_display.c

2592

return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview;

sys/dev/pci/drm/i915/display/intel_display.c

2599

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

2602

if (DISPLAY_VER(display) >= 5)

sys/dev/pci/drm/i915/display/intel_display.c

2603

intel_set_m_n(display, m_n,

sys/dev/pci/drm/i915/display/intel_display.c

2604

PIPE_DATA_M1(display, transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

2605

PIPE_DATA_N1(display, transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

2606

PIPE_LINK_M1(display, transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

2607

PIPE_LINK_N1(display, transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

2609

intel_set_m_n(display, m_n,

sys/dev/pci/drm/i915/display/intel_display.c

2618

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

2620

if (!intel_cpu_transcoder_has_m2_n2(display, transcoder))

sys/dev/pci/drm/i915/display/intel_display.c

2623

intel_set_m_n(display, m_n,

sys/dev/pci/drm/i915/display/intel_display.c

2624

PIPE_DATA_M2(display, transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

2625

PIPE_DATA_N2(display, transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

2626

PIPE_LINK_M2(display, transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

2627

PIPE_LINK_N2(display, transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

2633

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

2636

return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_display.c

2641

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

2649

drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

2676

if (DISPLAY_VER(display) >= 13) {

sys/dev/pci/drm/i915/display/intel_display.c

2677

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_display.c

2678

TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

2688

if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/intel_display.c

2689

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_display.c

2690

TRANS_VSYNCSHIFT(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

2693

intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

2696

intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

2699

intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

2709

if (intel_vrr_always_use_vrr_tg(display))

sys/dev/pci/drm/i915/display/intel_display.c

2712

intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

2715

intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

2718

intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

2726

if (display->platform.haswell && cpu_transcoder == TRANSCODER_EDP &&

sys/dev/pci/drm/i915/display/intel_display.c

2728

intel_de_write(display, TRANS_VTOTAL(display, pipe),

sys/dev/pci/drm/i915/display/intel_display.c

2732

if (DISPLAY_VER(display) >= 30) {

sys/dev/pci/drm/i915/display/intel_display.c

2741

intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

2748

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

2753

drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

2766

if (DISPLAY_VER(display) >= 13) {

sys/dev/pci/drm/i915/display/intel_display.c

2767

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_display.c

2768

TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

2782

intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

2791

if (intel_vrr_always_use_vrr_tg(display))

sys/dev/pci/drm/i915/display/intel_display.c

2798

intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

2808

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

2817

intel_de_write(display, PIPESRC(display, pipe),

sys/dev/pci/drm/i915/display/intel_display.c

2823

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

2826

if (DISPLAY_VER(display) == 2)

sys/dev/pci/drm/i915/display/intel_display.c

2829

if (DISPLAY_VER(display) >= 9 ||

sys/dev/pci/drm/i915/display/intel_display.c

2830

display->platform.broadwell || display->platform.haswell)

sys/dev/pci/drm/i915/display/intel_display.c

2831

return intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

2832

TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;

sys/dev/pci/drm/i915/display/intel_display.c

2834

return intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

2835

TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;

sys/dev/pci/drm/i915/display/intel_display.c

2841

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

2846

tmp = intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

2851

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

2852

TRANS_HBLANK(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

2857

tmp = intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

2861

tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

2867

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

2868

TRANS_VBLANK(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

2872

tmp = intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

2882

if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder))

sys/dev/pci/drm/i915/display/intel_display.c

2885

intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

2886

TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

2888

if (DISPLAY_VER(display) >= 30)

sys/dev/pci/drm/i915/display/intel_display.c

2889

pipe_config->min_hblank = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

2913

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

2916

tmp = intel_de_read(display, PIPESRC(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_display.c

2927

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

2936

if (display->platform.i830 || !intel_crtc_needs_modeset(crtc_state))

sys/dev/pci/drm/i915/display/intel_display.c

2943

if (display->platform.g4x || display->platform.valleyview ||

sys/dev/pci/drm/i915/display/intel_display.c

2944

display->platform.cherryview) {

sys/dev/pci/drm/i915/display/intel_display.c

2968

if (DISPLAY_VER(display) < 4 ||

sys/dev/pci/drm/i915/display/intel_display.c

2977

if ((display->platform.valleyview || display->platform.cherryview) &&

sys/dev/pci/drm/i915/display/intel_display.c

2988

intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);

sys/dev/pci/drm/i915/display/intel_display.c

2989

intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

2995

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

2998

tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_display.c

3006

if (DISPLAY_VER(display) < 30)

sys/dev/pci/drm/i915/display/intel_display.c

3007

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

3021

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

3029

wakeref = intel_display_power_get_if_enabled(display, power_domain);

sys/dev/pci/drm/i915/display/intel_display.c

3033

tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

3042

if (display->platform.g4x || display->platform.valleyview ||

sys/dev/pci/drm/i915/display/intel_display.c

3043

display->platform.cherryview) {

sys/dev/pci/drm/i915/display/intel_display.c

3060

if ((display->platform.valleyview || display->platform.cherryview) &&

sys/dev/pci/drm/i915/display/intel_display.c

3068

if ((display->platform.valleyview || display->platform.cherryview) &&

sys/dev/pci/drm/i915/display/intel_display.c

3074

if (HAS_DOUBLE_WIDE(display))

sys/dev/pci/drm/i915/display/intel_display.c

3084

if (DISPLAY_VER(display) >= 4) {

sys/dev/pci/drm/i915/display/intel_display.c

3089

} else if (display->platform.i945g || display->platform.i945gm ||

sys/dev/pci/drm/i915/display/intel_display.c

3090

display->platform.g33 || display->platform.pineview) {

sys/dev/pci/drm/i915/display/intel_display.c

3102

if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_display.c

3104

else if (display->platform.valleyview)

sys/dev/pci/drm/i915/display/intel_display.c

3120

intel_display_power_put(display, power_domain, wakeref);

sys/dev/pci/drm/i915/display/intel_display.c

3127

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

3169

drm_WARN_ON(display->drm, crtc_state->limited_color_range &&

sys/dev/pci/drm/i915/display/intel_display.c

3184

intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);

sys/dev/pci/drm/i915/display/intel_display.c

3185

intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

3190

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

3201

if (display->platform.haswell && crtc_state->dither)

sys/dev/pci/drm/i915/display/intel_display.c

3209

if (display->platform.haswell &&

sys/dev/pci/drm/i915/display/intel_display.c

3213

intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);

sys/dev/pci/drm/i915/display/intel_display.c

3214

intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

3220

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

3236

if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/intel_display.c

3252

val |= DISPLAY_VER(display) >= 30 ? PIPE_MISC_YUV420_ENABLE :

sys/dev/pci/drm/i915/display/intel_display.c

3255

if (DISPLAY_VER(display) >= 11 && is_hdr_mode(crtc_state))

sys/dev/pci/drm/i915/display/intel_display.c

3258

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_display.c

3262

if (display->platform.broadwell)

sys/dev/pci/drm/i915/display/intel_display.c

3265

intel_de_write_dsb(display, dsb, PIPE_MISC(crtc->pipe), val);

sys/dev/pci/drm/i915/display/intel_display.c

3270

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

3273

tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_display.c

3293

if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/intel_display.c

3313

void intel_get_m_n(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display.c

3318

m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK;

sys/dev/pci/drm/i915/display/intel_display.c

3319

m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK;

sys/dev/pci/drm/i915/display/intel_display.c

3320

m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK;

sys/dev/pci/drm/i915/display/intel_display.c

3321

m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK;

sys/dev/pci/drm/i915/display/intel_display.c

3322

m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;

sys/dev/pci/drm/i915/display/intel_display.c

3329

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

3332

if (DISPLAY_VER(display) >= 5)

sys/dev/pci/drm/i915/display/intel_display.c

3333

intel_get_m_n(display, m_n,

sys/dev/pci/drm/i915/display/intel_display.c

3334

PIPE_DATA_M1(display, transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

3335

PIPE_DATA_N1(display, transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

3336

PIPE_LINK_M1(display, transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

3337

PIPE_LINK_N1(display, transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

3339

intel_get_m_n(display, m_n,

sys/dev/pci/drm/i915/display/intel_display.c

3348

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

3350

if (!intel_cpu_transcoder_has_m2_n2(display, transcoder))

sys/dev/pci/drm/i915/display/intel_display.c

3353

intel_get_m_n(display, m_n,

sys/dev/pci/drm/i915/display/intel_display.c

3354

PIPE_DATA_M2(display, transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

3355

PIPE_DATA_N2(display, transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

3356

PIPE_LINK_M2(display, transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

3357

PIPE_LINK_N2(display, transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

3363

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

3371

wakeref = intel_display_power_get_if_enabled(display, power_domain);

sys/dev/pci/drm/i915/display/intel_display.c

3375

tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

3433

intel_display_power_put(display, power_domain, wakeref);

sys/dev/pci/drm/i915/display/intel_display.c

3438

static u8 joiner_pipes(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display.c

3442

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_display.c

3444

else if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_display.c

3449

return pipes & DISPLAY_RUNTIME_INFO(display)->pipe_mask;

sys/dev/pci/drm/i915/display/intel_display.c

3452

static bool transcoder_ddi_func_is_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display.c

3461

with_intel_display_power_if_enabled(display, power_domain, wakeref)

sys/dev/pci/drm/i915/display/intel_display.c

3462

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

3463

TRANS_DDI_FUNC_CTL(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

3468

static void enabled_uncompressed_joiner_pipes(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display.c

3476

if (!HAS_UNCOMPRESSED_JOINER(display))

sys/dev/pci/drm/i915/display/intel_display.c

3479

for_each_intel_crtc_in_pipe_mask(display->drm, crtc,

sys/dev/pci/drm/i915/display/intel_display.c

3480

joiner_pipes(display)) {

sys/dev/pci/drm/i915/display/intel_display.c

3486

with_intel_display_power_if_enabled(display, power_domain, wakeref) {

sys/dev/pci/drm/i915/display/intel_display.c

3487

u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

sys/dev/pci/drm/i915/display/intel_display.c

3497

static void enabled_bigjoiner_pipes(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display.c

3505

if (!HAS_BIGJOINER(display))

sys/dev/pci/drm/i915/display/intel_display.c

3508

for_each_intel_crtc_in_pipe_mask(display->drm, crtc,

sys/dev/pci/drm/i915/display/intel_display.c

3509

joiner_pipes(display)) {

sys/dev/pci/drm/i915/display/intel_display.c

3515

with_intel_display_power_if_enabled(display, power_domain, wakeref) {

sys/dev/pci/drm/i915/display/intel_display.c

3516

u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

sys/dev/pci/drm/i915/display/intel_display.c

3567

static void enabled_ultrajoiner_pipes(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display.c

3575

if (!HAS_ULTRAJOINER(display))

sys/dev/pci/drm/i915/display/intel_display.c

3578

for_each_intel_crtc_in_pipe_mask(display->drm, crtc,

sys/dev/pci/drm/i915/display/intel_display.c

3579

joiner_pipes(display)) {

sys/dev/pci/drm/i915/display/intel_display.c

3585

with_intel_display_power_if_enabled(display, power_domain, wakeref) {

sys/dev/pci/drm/i915/display/intel_display.c

3586

u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

sys/dev/pci/drm/i915/display/intel_display.c

3599

static void enabled_joiner_pipes(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display.c

3610

enabled_ultrajoiner_pipes(display, &primary_ultrajoiner_pipes,

sys/dev/pci/drm/i915/display/intel_display.c

3617

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

3624

drm_WARN_ON(display->drm, (primary_ultrajoiner_pipes & secondary_ultrajoiner_pipes) != 0);

sys/dev/pci/drm/i915/display/intel_display.c

3626

enabled_uncompressed_joiner_pipes(display, &primary_uncompressed_joiner_pipes,

sys/dev/pci/drm/i915/display/intel_display.c

3629

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

3632

enabled_bigjoiner_pipes(display, &primary_bigjoiner_pipes,

sys/dev/pci/drm/i915/display/intel_display.c

3635

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

3643

drm_WARN(display->drm, (ultrajoiner_pipes & bigjoiner_pipes) != ultrajoiner_pipes,

sys/dev/pci/drm/i915/display/intel_display.c

3647

drm_WARN(display->drm, secondary_ultrajoiner_pipes !=

sys/dev/pci/drm/i915/display/intel_display.c

3653

drm_WARN(display->drm, (uncompressed_joiner_pipes & bigjoiner_pipes) != 0,

sys/dev/pci/drm/i915/display/intel_display.c

3657

drm_WARN(display->drm, secondary_bigjoiner_pipes !=

sys/dev/pci/drm/i915/display/intel_display.c

3663

drm_WARN(display->drm, secondary_uncompressed_joiner_pipes !=

sys/dev/pci/drm/i915/display/intel_display.c

3677

drm_WARN(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

3692

drm_WARN(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

3707

drm_WARN(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

3718

static u8 hsw_panel_transcoders(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display.c

3722

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_display.c

3730

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

3731

u8 panel_transcoder_mask = hsw_panel_transcoders(display);

sys/dev/pci/drm/i915/display/intel_display.c

3740

for_each_cpu_transcoder_masked(display, cpu_transcoder,

sys/dev/pci/drm/i915/display/intel_display.c

3748

with_intel_display_power_if_enabled(display, power_domain, wakeref)

sys/dev/pci/drm/i915/display/intel_display.c

3749

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

3750

TRANS_DDI_FUNC_CTL(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

3757

drm_WARN(display->drm, 1,

sys/dev/pci/drm/i915/display/intel_display.c

3782

if (transcoder_ddi_func_is_enabled(display, cpu_transcoder))

sys/dev/pci/drm/i915/display/intel_display.c

3786

enabled_joiner_pipes(display, crtc->pipe, &primary_pipe, &secondary_pipes);

sys/dev/pci/drm/i915/display/intel_display.c

3789

if (transcoder_ddi_func_is_enabled(display, cpu_transcoder))

sys/dev/pci/drm/i915/display/intel_display.c

3814

static void assert_enabled_transcoders(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display.c

3818

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

3824

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

3833

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

3841

assert_enabled_transcoders(display, enabled_transcoders);

sys/dev/pci/drm/i915/display/intel_display.c

3850

if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set,

sys/dev/pci/drm/i915/display/intel_display.c

3854

if (hsw_panel_transcoders(display) & BIT(pipe_config->cpu_transcoder)) {

sys/dev/pci/drm/i915/display/intel_display.c

3855

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

3856

TRANS_DDI_FUNC_CTL(display, pipe_config->cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

3862

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

3863

TRANSCONF(display, pipe_config->cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

3872

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

3883

if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set,

sys/dev/pci/drm/i915/display/intel_display.c

3894

if (!bxt_dsi_pll_is_enabled(display))

sys/dev/pci/drm/i915/display/intel_display.c

3898

tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port));

sys/dev/pci/drm/i915/display/intel_display.c

3902

tmp = intel_de_read(display, MIPI_CTRL(display, port));

sys/dev/pci/drm/i915/display/intel_display.c

3915

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

3920

enabled_joiner_pipes(display, pipe, &primary_pipe, &secondary_pipes);

sys/dev/pci/drm/i915/display/intel_display.c

3931

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

3935

if (!intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains,

sys/dev/pci/drm/i915/display/intel_display.c

3941

if ((display->platform.geminilake || display->platform.broxton) &&

sys/dev/pci/drm/i915/display/intel_display.c

3943

drm_WARN_ON(display->drm, active);

sys/dev/pci/drm/i915/display/intel_display.c

3954

DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_display.c

3962

if (display->platform.haswell) {

sys/dev/pci/drm/i915/display/intel_display.c

3963

u32 tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

3964

TRANSCONF(display, pipe_config->cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

3979

tmp = intel_de_read(display, WM_LINETIME(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_display.c

3981

if (display->platform.broadwell || display->platform.haswell)

sys/dev/pci/drm/i915/display/intel_display.c

3985

if (intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains,

sys/dev/pci/drm/i915/display/intel_display.c

3987

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_display.c

3998

intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

3999

TRANS_MULT(display, pipe_config->cpu_transcoder)) + 1;

sys/dev/pci/drm/i915/display/intel_display.c

4005

tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

4014

intel_display_power_put_all_in_set(display, &crtc->hw_readout_power_domains);

sys/dev/pci/drm/i915/display/intel_display.c

402

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

4021

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

4024

if (!display->funcs.display->get_pipe_config(crtc, crtc_state))

sys/dev/pci/drm/i915/display/intel_display.c

405

return intel_crtc_for_pipe(display, joiner_primary_pipe(crtc_state));

sys/dev/pci/drm/i915/display/intel_display.c

4084

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_display.c

4093

crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_display.c

413

struct intel_display *display = to_intel_display(old_crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

416

if (DISPLAY_VER(display) >= 4) {

sys/dev/pci/drm/i915/display/intel_display.c

4183

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

4195

if ((display->platform.geminilake || display->platform.broxton) &&

sys/dev/pci/drm/i915/display/intel_display.c

4196

skl_watermark_ipc_enabled(display))

sys/dev/pci/drm/i915/display/intel_display.c

420

if (intel_de_wait_for_clear(display, TRANSCONF(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

4205

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

4210

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_display.c

422

drm_WARN(display->drm, 1, "pipe_off wait timed out\n");

sys/dev/pci/drm/i915/display/intel_display.c

4231

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

4236

if (DISPLAY_VER(display) < 5 && !display->platform.g4x &&

sys/dev/pci/drm/i915/display/intel_display.c

4253

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

4259

if (DISPLAY_VER(display) >= 9) {

sys/dev/pci/drm/i915/display/intel_display.c

4272

if (HAS_IPS(display)) {

sys/dev/pci/drm/i915/display/intel_display.c

4278

if (DISPLAY_VER(display) >= 9 ||

sys/dev/pci/drm/i915/display/intel_display.c

4279

display->platform.broadwell || display->platform.haswell) {

sys/dev/pci/drm/i915/display/intel_display.c

428

void assert_transcoder(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display.c

4297

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

4321

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

4340

int intel_display_max_pipe_bpp(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display.c

4342

if (display->platform.g4x || display->platform.valleyview ||

sys/dev/pci/drm/i915/display/intel_display.c

4343

display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_display.c

4345

else if (DISPLAY_VER(display) >= 5)

sys/dev/pci/drm/i915/display/intel_display.c

4355

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

436

if (display->platform.i830)

sys/dev/pci/drm/i915/display/intel_display.c

4362

crtc_state->pipe_bpp = intel_display_max_pipe_bpp(display);

sys/dev/pci/drm/i915/display/intel_display.c

4381

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

4392

drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_display.c

4399

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_display.c

440

wakeref = intel_display_power_get_if_enabled(display, power_domain);

sys/dev/pci/drm/i915/display/intel_display.c

4415

drm_WARN_ON(display->drm, !connector_state->crtc);

sys/dev/pci/drm/i915/display/intel_display.c

4419

if (drm_WARN_ON(display->drm, !HAS_DDI(display)))

sys/dev/pci/drm/i915/display/intel_display.c

442

u32 val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

443

TRANSCONF(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

446

intel_display_power_put(display, power_domain, wakeref);

sys/dev/pci/drm/i915/display/intel_display.c

451

INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

sys/dev/pci/drm/i915/display/intel_display.c

4567

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

459

struct intel_display *display = to_intel_display(plane->base.dev);

sys/dev/pci/drm/i915/display/intel_display.c

4600

if (display->platform.g4x ||

sys/dev/pci/drm/i915/display/intel_display.c

4601

display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_display.c

4617

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

465

INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

sys/dev/pci/drm/i915/display/intel_display.c

4650

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

4680

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

4722

drm_dbg_kms(display->drm, "[ENCODER:%d:%s] config failure: %d\n",

sys/dev/pci/drm/i915/display/intel_display.c

4738

drm_dbg_kms(display->drm, "[CRTC:%d:%s] config failure: %d\n",

sys/dev/pci/drm/i915/display/intel_display.c

4749

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

476

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

479

for_each_intel_plane_on_crtc(display->drm, crtc, plane)

sys/dev/pci/drm/i915/display/intel_display.c

485

struct intel_display *display = to_intel_display(new_crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

4881

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

4896

hdmi_infoframe_log(loglevel, display->drm->dev, a);

sys/dev/pci/drm/i915/display/intel_display.c

4898

hdmi_infoframe_log(loglevel, display->drm->dev, b);

sys/dev/pci/drm/i915/display/intel_display.c

491

drm_dbg_kms(display->drm, "enabling pipe %c\n", pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_display.c

4967

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

4972

intel_dpll_dump_hw_state(display, p, a);

sys/dev/pci/drm/i915/display/intel_display.c

4974

intel_dpll_dump_hw_state(display, p, b);

sys/dev/pci/drm/i915/display/intel_display.c

4984

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

4990

intel_cx0pll_dump_hw_state(display, a);

sys/dev/pci/drm/i915/display/intel_display.c

4992

intel_cx0pll_dump_hw_state(display, b);

sys/dev/pci/drm/i915/display/intel_display.c

4997

struct intel_display *display = to_intel_display(old_crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

500

if (HAS_GMCH(display)) {

sys/dev/pci/drm/i915/display/intel_display.c

5004

return HAS_LRR(display) && old_crtc_state->inherited &&

sys/dev/pci/drm/i915/display/intel_display.c

5013

struct intel_display *display = to_intel_display(current_config);

sys/dev/pci/drm/i915/display/intel_display.c

502

assert_dsi_pll_enabled(display);

sys/dev/pci/drm/i915/display/intel_display.c

5020

p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);

sys/dev/pci/drm/i915/display/intel_display.c

5022

p = drm_err_printer(display->drm, NULL);

sys/dev/pci/drm/i915/display/intel_display.c

504

assert_pll_enabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_display.c

508

assert_fdi_rx_pll_enabled(display,

sys/dev/pci/drm/i915/display/intel_display.c

510

assert_fdi_tx_pll_enabled(display,

sys/dev/pci/drm/i915/display/intel_display.c

5113

if (!intel_dpll_compare_hw_state(display, &current_config->name, \

sys/dev/pci/drm/i915/display/intel_display.c

517

if (DISPLAY_VER(display) == 13)

sys/dev/pci/drm/i915/display/intel_display.c

518

intel_de_rmw(display, PIPE_ARB_CTL(display, pipe),

sys/dev/pci/drm/i915/display/intel_display.c

521

if (DISPLAY_VER(display) >= 14) {

sys/dev/pci/drm/i915/display/intel_display.c

525

if (DISPLAY_VER(display) == 14)

sys/dev/pci/drm/i915/display/intel_display.c

5257

if (HAS_DOUBLE_BUFFERED_M_N(display)) {

sys/dev/pci/drm/i915/display/intel_display.c

528

intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

5291

if ((DISPLAY_VER(display) < 8 && !display->platform.haswell) ||

sys/dev/pci/drm/i915/display/intel_display.c

5292

display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_display.c

5308

if (DISPLAY_VER(display) < 4)

sys/dev/pci/drm/i915/display/intel_display.c

532

val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

5328

if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_display.c

5348

if (display->dpll.mgr)

sys/dev/pci/drm/i915/display/intel_display.c

535

drm_WARN_ON(display->drm, !display->platform.i830);

sys/dev/pci/drm/i915/display/intel_display.c

5352

if (display->dpll.mgr || HAS_GMCH(display))

sys/dev/pci/drm/i915/display/intel_display.c

5356

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_display.c

5362

if (display->platform.g4x || DISPLAY_VER(display) >= 5)

sys/dev/pci/drm/i915/display/intel_display.c

540

if (DISPLAY_VER(display) >= 13 &&

sys/dev/pci/drm/i915/display/intel_display.c

5445

if (!fastset || intel_vrr_always_use_vrr_tg(display)) {

sys/dev/pci/drm/i915/display/intel_display.c

547

intel_de_write(display, TRANSCONF(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

5481

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

5485

drm_dbg_kms(display->drm, "[CRTC:%d:%s] Full modeset due to %s\n",

sys/dev/pci/drm/i915/display/intel_display.c

549

intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

5525

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

5528

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, mask) {

sys/dev/pci/drm/i915/display/intel_display.c

5572

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

5575

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_display.c

5601

int intel_modeset_commit_pipes(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display.c

5609

state = drm_atomic_state_alloc(display->drm);

sys/dev/pci/drm/i915/display/intel_display.c

5616

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {

sys/dev/pci/drm/i915/display/intel_display.c

564

struct intel_display *display = to_intel_display(old_crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

570

drm_dbg_kms(display->drm, "disabling pipe %c\n", pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_display.c

5715

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

5719

if (display->platform.haswell)

sys/dev/pci/drm/i915/display/intel_display.c

5736

struct intel_display *display = to_intel_display(new_crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

5744

drm_dbg_kms(display->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n",

sys/dev/pci/drm/i915/display/intel_display.c

5768

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

5778

drm_dbg_atomic(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

578

val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

5825

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

5834

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

5838

if (primary_crtc_state->joiner_pipes & ~joiner_pipes(display)) {

sys/dev/pci/drm/i915/display/intel_display.c

5839

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

5843

primary_crtc_state->joiner_pipes, joiner_pipes(display));

sys/dev/pci/drm/i915/display/intel_display.c

5847

for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc,

sys/dev/pci/drm/i915/display/intel_display.c

5858

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

5877

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

5896

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

590

if (!display->platform.i830)

sys/dev/pci/drm/i915/display/intel_display.c

5901

for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc,

sys/dev/pci/drm/i915/display/intel_display.c

5935

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

594

if (DISPLAY_VER(display) >= 13 &&

sys/dev/pci/drm/i915/display/intel_display.c

5947

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

5954

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

5965

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

5973

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

598

intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);

sys/dev/pci/drm/i915/display/intel_display.c

5992

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

5999

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

600

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_display.c

601

intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

6011

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

6024

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

6031

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

6038

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

6054

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

6071

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

6088

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

6096

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

6104

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

611

struct intel_display *display = to_intel_display(drm);

sys/dev/pci/drm/i915/display/intel_display.c

6112

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

6120

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

6128

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

6135

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

6143

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

615

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display.c

6150

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

6157

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

6165

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

6177

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

6208

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, affected_pipes) {

sys/dev/pci/drm/i915/display/intel_display.c

6214

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, modeset_pipes) {

sys/dev/pci/drm/i915/display/intel_display.c

623

crtc = intel_first_crtc(display);

sys/dev/pci/drm/i915/display/intel_display.c

6244

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

6269

if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))

sys/dev/pci/drm/i915/display/intel_display.c

6288

if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))

sys/dev/pci/drm/i915/display/intel_display.c

6352

struct intel_display *display = to_intel_display(dev);

sys/dev/pci/drm/i915/display/intel_display.c

6359

if (!intel_display_driver_check_access(display))

sys/dev/pci/drm/i915/display/intel_display.c

6400

drm_WARN_ON(display->drm, new_crtc_state->uapi.enable);

sys/dev/pci/drm/i915/display/intel_display.c

6471

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

649

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

6527

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

6571

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

6573

if (DISPLAY_VER(display) != 2 || crtc_state->active_planes)

sys/dev/pci/drm/i915/display/intel_display.c

6574

intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

6580

intel_set_pch_fifo_underrun_reporting(display, pch_transcoder, true);

sys/dev/pci/drm/i915/display/intel_display.c

6587

struct intel_display *display = to_intel_display(new_crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

660

drm_for_each_plane_mask(plane, display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

6601

if (DISPLAY_VER(display) >= 9) {

sys/dev/pci/drm/i915/display/intel_display.c

6604

} else if (HAS_PCH_SPLIT(display)) {

sys/dev/pci/drm/i915/display/intel_display.c

6619

if (DISPLAY_VER(display) >= 9 ||

sys/dev/pci/drm/i915/display/intel_display.c

6620

display->platform.broadwell || display->platform.haswell)

sys/dev/pci/drm/i915/display/intel_display.c

6634

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

6641

drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq);

sys/dev/pci/drm/i915/display/intel_display.c

6651

if (DISPLAY_VER(display) >= 9 || display->platform.broadwell)

sys/dev/pci/drm/i915/display/intel_display.c

6666

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

6671

drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq);

sys/dev/pci/drm/i915/display/intel_display.c

6678

if (DISPLAY_VER(display) >= 9 && !modeset)

sys/dev/pci/drm/i915/display/intel_display.c

6684

HAS_DOUBLE_BUFFERED_LUT(display))

sys/dev/pci/drm/i915/display/intel_display.c

6694

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

670

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display.c

6702

for_each_intel_crtc_in_pipe_mask_reverse(display->drm, pipe_crtc,

sys/dev/pci/drm/i915/display/intel_display.c

6713

display->funcs.display->crtc_enable(state, crtc);

sys/dev/pci/drm/i915/display/intel_display.c

6722

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

6731

if (HAS_DPT(display))

sys/dev/pci/drm/i915/display/intel_display.c

6745

if (DISPLAY_VER(display) >= 11 &&

sys/dev/pci/drm/i915/display/intel_display.c

6756

drm_WARN_ON(display->drm, !intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF));

sys/dev/pci/drm/i915/display/intel_display.c

676

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

6826

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

6835

for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,

sys/dev/pci/drm/i915/display/intel_display.c

6841

display->funcs.display->crtc_disable(state, crtc);

sys/dev/pci/drm/i915/display/intel_display.c

6843

for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,

sys/dev/pci/drm/i915/display/intel_display.c

6858

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

6925

drm_WARN_ON(display->drm, disable_pipes);

sys/dev/pci/drm/i915/display/intel_display.c

6952

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

702

if (HAS_GMCH(display) &&

sys/dev/pci/drm/i915/display/intel_display.c

703

intel_set_memory_cxsr(display, false))

sys/dev/pci/drm/i915/display/intel_display.c

7094

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

710

if (DISPLAY_VER(display) == 2 && !crtc_state->active_planes)

sys/dev/pci/drm/i915/display/intel_display.c

7104

drm_WARN_ON(display->drm, modeset_pipes);

sys/dev/pci/drm/i915/display/intel_display.c

7105

drm_WARN_ON(display->drm, update_pipes);

sys/dev/pci/drm/i915/display/intel_display.c

711

intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

7151

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

7159

drm_atomic_helper_cleanup_planes(display->drm, &state->base);

sys/dev/pci/drm/i915/display/intel_display.c

7166

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

7203

drm_WARN_ON(display->drm, ret);

sys/dev/pci/drm/i915/display/intel_display.c

7210

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

7222

intel_flipq_supported(display) &&

sys/dev/pci/drm/i915/display/intel_display.c

7233

(DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) &&

sys/dev/pci/drm/i915/display/intel_display.c

7243

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

730

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

7302

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_display.c

7333

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_display.c

7334

struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display.c

7346

intel_td_flush(display);

sys/dev/pci/drm/i915/display/intel_display.c

735

tmp = intel_de_read(display, PIPE_CHICKEN(pipe));

sys/dev/pci/drm/i915/display/intel_display.c

7387

wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF);

sys/dev/pci/drm/i915/display/intel_display.c

7413

drm_atomic_helper_update_legacy_modeset_state(display->drm, &state->base);

sys/dev/pci/drm/i915/display/intel_display.c

7428

spin_lock_irq(&display->drm->event_lock);

sys/dev/pci/drm/i915/display/intel_display.c

7431

spin_unlock_irq(&display->drm->event_lock);

sys/dev/pci/drm/i915/display/intel_display.c

7447

display->funcs.display->commit_modeset_enables(state);

sys/dev/pci/drm/i915/display/intel_display.c

7463

drm_atomic_helper_wait_for_flip_done(display->drm, &state->base);

sys/dev/pci/drm/i915/display/intel_display.c

7495

if (DISPLAY_VER(display) == 2 && planes_enabling(old_crtc_state, new_crtc_state))

sys/dev/pci/drm/i915/display/intel_display.c

7496

intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

7524

intel_check_cpu_fifo_underruns(display);

sys/dev/pci/drm/i915/display/intel_display.c

7525

intel_check_pch_fifo_underruns(display);

sys/dev/pci/drm/i915/display/intel_display.c

755

if (display->platform.dg2)

sys/dev/pci/drm/i915/display/intel_display.c

7551

intel_display_power_put_async_delay(display, POWER_DOMAIN_DC_OFF, wakeref, 17);

sys/dev/pci/drm/i915/display/intel_display.c

7552

intel_display_rpm_put(display, state->wakeref);

sys/dev/pci/drm/i915/display/intel_display.c

7563

queue_work(display->wq.cleanup, &state->cleanup_work);

sys/dev/pci/drm/i915/display/intel_display.c

757

else if ((DISPLAY_VER(display) >= 13) && (DISPLAY_VER(display) < 30))

sys/dev/pci/drm/i915/display/intel_display.c

761

if (display->platform.dg2)

sys/dev/pci/drm/i915/display/intel_display.c

7622

struct intel_display *display = to_intel_display(dev);

sys/dev/pci/drm/i915/display/intel_display.c

7626

state->wakeref = intel_display_rpm_get(display);

sys/dev/pci/drm/i915/display/intel_display.c

764

intel_de_write(display, PIPE_CHICKEN(pipe), tmp);

sys/dev/pci/drm/i915/display/intel_display.c

7645

if (DISPLAY_VER(display) < 9 && state->base.legacy_cursor_update) {

sys/dev/pci/drm/i915/display/intel_display.c

7658

drm_dbg_atomic(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

7660

intel_display_rpm_put(display, state->wakeref);

sys/dev/pci/drm/i915/display/intel_display.c

767

bool intel_has_pending_fb_unpin(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display.c

7670

intel_display_rpm_put(display, state->wakeref);

sys/dev/pci/drm/i915/display/intel_display.c

7678

queue_work(display->wq.modeset, &state->base.commit_work);

sys/dev/pci/drm/i915/display/intel_display.c

7680

queue_work(display->wq.flip, &state->base.commit_work);

sys/dev/pci/drm/i915/display/intel_display.c

7683

flush_workqueue(display->wq.modeset);

sys/dev/pci/drm/i915/display/intel_display.c

7692

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_display.c

7696

for_each_intel_encoder(display->drm, source_encoder) {

sys/dev/pci/drm/i915/display/intel_display.c

7706

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_display.c

7710

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, encoder->pipe_mask)

sys/dev/pci/drm/i915/display/intel_display.c

7716

static bool ilk_has_edp_a(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display.c

7718

if (!display->platform.mobile)

sys/dev/pci/drm/i915/display/intel_display.c

772

drm_for_each_crtc(crtc, display->drm) {

sys/dev/pci/drm/i915/display/intel_display.c

7721

if ((intel_de_read(display, DP_A) & DP_DETECTED) == 0)

sys/dev/pci/drm/i915/display/intel_display.c

7724

if (display->platform.ironlake && (intel_de_read(display, FUSE_STRAP) & ILK_eDP_A_DISABLE))

sys/dev/pci/drm/i915/display/intel_display.c

7730

static bool intel_ddi_crt_present(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display.c

7732

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_display.c

7735

if (display->platform.haswell_ult || display->platform.broadwell_ult)

sys/dev/pci/drm/i915/display/intel_display.c

7738

if (HAS_PCH_LPT_H(display) &&

sys/dev/pci/drm/i915/display/intel_display.c

7739

intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)

sys/dev/pci/drm/i915/display/intel_display.c

7743

if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)

sys/dev/pci/drm/i915/display/intel_display.c

7746

if (!display->vbt.int_crt_support)

sys/dev/pci/drm/i915/display/intel_display.c

7752

bool assert_port_valid(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_display.c

7754

return !drm_WARN(display->drm, !(DISPLAY_RUNTIME_INFO(display)->port_mask & BIT(port)),

sys/dev/pci/drm/i915/display/intel_display.c

7758

void intel_setup_outputs(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display.c

7763

intel_pps_unlock_regs_wa(display);

sys/dev/pci/drm/i915/display/intel_display.c

7765

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display.c

7768

if (HAS_DDI(display)) {

sys/dev/pci/drm/i915/display/intel_display.c

7769

if (intel_ddi_crt_present(display))

sys/dev/pci/drm/i915/display/intel_display.c

7770

intel_crt_init(display);

sys/dev/pci/drm/i915/display/intel_display.c

7772

intel_bios_for_each_encoder(display, intel_ddi_init);

sys/dev/pci/drm/i915/display/intel_display.c

7774

if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_display.c

7775

vlv_dsi_init(display);

sys/dev/pci/drm/i915/display/intel_display.c

7776

} else if (HAS_PCH_SPLIT(display)) {

sys/dev/pci/drm/i915/display/intel_display.c

7784

intel_lvds_init(display);

sys/dev/pci/drm/i915/display/intel_display.c

7785

intel_crt_init(display);

sys/dev/pci/drm/i915/display/intel_display.c

7787

dpd_is_edp = intel_dp_is_port_edp(display, PORT_D);

sys/dev/pci/drm/i915/display/intel_display.c

7789

if (ilk_has_edp_a(display))

sys/dev/pci/drm/i915/display/intel_display.c

7790

g4x_dp_init(display, DP_A, PORT_A);

sys/dev/pci/drm/i915/display/intel_display.c

7792

if (intel_de_read(display, PCH_HDMIB) & SDVO_DETECTED) {

sys/dev/pci/drm/i915/display/intel_display.c

7794

found = intel_sdvo_init(display, PCH_SDVOB, PORT_B);

sys/dev/pci/drm/i915/display/intel_display.c

7796

g4x_hdmi_init(display, PCH_HDMIB, PORT_B);

sys/dev/pci/drm/i915/display/intel_display.c

7797

if (!found && (intel_de_read(display, PCH_DP_B) & DP_DETECTED))

sys/dev/pci/drm/i915/display/intel_display.c

7798

g4x_dp_init(display, PCH_DP_B, PORT_B);

sys/dev/pci/drm/i915/display/intel_display.c

7801

if (intel_de_read(display, PCH_HDMIC) & SDVO_DETECTED)

sys/dev/pci/drm/i915/display/intel_display.c

7802

g4x_hdmi_init(display, PCH_HDMIC, PORT_C);

sys/dev/pci/drm/i915/display/intel_display.c

7804

if (!dpd_is_edp && intel_de_read(display, PCH_HDMID) & SDVO_DETECTED)

sys/dev/pci/drm/i915/display/intel_display.c

7805

g4x_hdmi_init(display, PCH_HDMID, PORT_D);

sys/dev/pci/drm/i915/display/intel_display.c

7807

if (intel_de_read(display, PCH_DP_C) & DP_DETECTED)

sys/dev/pci/drm/i915/display/intel_display.c

7808

g4x_dp_init(display, PCH_DP_C, PORT_C);

sys/dev/pci/drm/i915/display/intel_display.c

7810

if (intel_de_read(display, PCH_DP_D) & DP_DETECTED)

sys/dev/pci/drm/i915/display/intel_display.c

7811

g4x_dp_init(display, PCH_DP_D, PORT_D);

sys/dev/pci/drm/i915/display/intel_display.c

7812

} else if (display->platform.valleyview || display->platform.cherryview) {

sys/dev/pci/drm/i915/display/intel_display.c

7815

if (display->platform.valleyview && display->vbt.int_crt_support)

sys/dev/pci/drm/i915/display/intel_display.c

7816

intel_crt_init(display);

sys/dev/pci/drm/i915/display/intel_display.c

7833

has_edp = intel_dp_is_port_edp(display, PORT_B);

sys/dev/pci/drm/i915/display/intel_display.c

7834

has_port = intel_bios_is_port_present(display, PORT_B);

sys/dev/pci/drm/i915/display/intel_display.c

7835

if (intel_de_read(display, VLV_DP_B) & DP_DETECTED || has_port)

sys/dev/pci/drm/i915/display/intel_display.c

7836

has_edp &= g4x_dp_init(display, VLV_DP_B, PORT_B);

sys/dev/pci/drm/i915/display/intel_display.c

7837

if ((intel_de_read(display, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)

sys/dev/pci/drm/i915/display/intel_display.c

7838

g4x_hdmi_init(display, VLV_HDMIB, PORT_B);

sys/dev/pci/drm/i915/display/intel_display.c

7840

has_edp = intel_dp_is_port_edp(display, PORT_C);

sys/dev/pci/drm/i915/display/intel_display.c

7841

has_port = intel_bios_is_port_present(display, PORT_C);

sys/dev/pci/drm/i915/display/intel_display.c

7842

if (intel_de_read(display, VLV_DP_C) & DP_DETECTED || has_port)

sys/dev/pci/drm/i915/display/intel_display.c

7843

has_edp &= g4x_dp_init(display, VLV_DP_C, PORT_C);

sys/dev/pci/drm/i915/display/intel_display.c

7844

if ((intel_de_read(display, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)

sys/dev/pci/drm/i915/display/intel_display.c

7845

g4x_hdmi_init(display, VLV_HDMIC, PORT_C);

sys/dev/pci/drm/i915/display/intel_display.c

7847

if (display->platform.cherryview) {

sys/dev/pci/drm/i915/display/intel_display.c

7852

has_port = intel_bios_is_port_present(display, PORT_D);

sys/dev/pci/drm/i915/display/intel_display.c

7853

if (intel_de_read(display, CHV_DP_D) & DP_DETECTED || has_port)

sys/dev/pci/drm/i915/display/intel_display.c

7854

g4x_dp_init(display, CHV_DP_D, PORT_D);

sys/dev/pci/drm/i915/display/intel_display.c

7855

if (intel_de_read(display, CHV_HDMID) & SDVO_DETECTED || has_port)

sys/dev/pci/drm/i915/display/intel_display.c

7856

g4x_hdmi_init(display, CHV_HDMID, PORT_D);

sys/dev/pci/drm/i915/display/intel_display.c

7859

vlv_dsi_init(display);

sys/dev/pci/drm/i915/display/intel_display.c

7860

} else if (display->platform.pineview) {

sys/dev/pci/drm/i915/display/intel_display.c

7861

intel_lvds_init(display);

sys/dev/pci/drm/i915/display/intel_display.c

7862

intel_crt_init(display);

sys/dev/pci/drm/i915/display/intel_display.c

7863

} else if (IS_DISPLAY_VER(display, 3, 4)) {

sys/dev/pci/drm/i915/display/intel_display.c

7866

if (display->platform.mobile)

sys/dev/pci/drm/i915/display/intel_display.c

7867

intel_lvds_init(display);

sys/dev/pci/drm/i915/display/intel_display.c

7869

intel_crt_init(display);

sys/dev/pci/drm/i915/display/intel_display.c

7871

if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) {

sys/dev/pci/drm/i915/display/intel_display.c

7872

drm_dbg_kms(display->drm, "probing SDVOB\n");

sys/dev/pci/drm/i915/display/intel_display.c

7873

found = intel_sdvo_init(display, GEN3_SDVOB, PORT_B);

sys/dev/pci/drm/i915/display/intel_display.c

7874

if (!found && display->platform.g4x) {

sys/dev/pci/drm/i915/display/intel_display.c

7875

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

7877

g4x_hdmi_init(display, GEN4_HDMIB, PORT_B);

sys/dev/pci/drm/i915/display/intel_display.c

7880

if (!found && display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_display.c

7881

g4x_dp_init(display, DP_B, PORT_B);

sys/dev/pci/drm/i915/display/intel_display.c

7886

if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) {

sys/dev/pci/drm/i915/display/intel_display.c

7887

drm_dbg_kms(display->drm, "probing SDVOC\n");

sys/dev/pci/drm/i915/display/intel_display.c

7888

found = intel_sdvo_init(display, GEN3_SDVOC, PORT_C);

sys/dev/pci/drm/i915/display/intel_display.c

7891

if (!found && (intel_de_read(display, GEN3_SDVOC) & SDVO_DETECTED)) {

sys/dev/pci/drm/i915/display/intel_display.c

7893

if (display->platform.g4x) {

sys/dev/pci/drm/i915/display/intel_display.c

7894

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

7896

g4x_hdmi_init(display, GEN4_HDMIC, PORT_C);

sys/dev/pci/drm/i915/display/intel_display.c

7898

if (display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_display.c

7899

g4x_dp_init(display, DP_C, PORT_C);

sys/dev/pci/drm/i915/display/intel_display.c

7902

if (display->platform.g4x && (intel_de_read(display, DP_D) & DP_DETECTED))

sys/dev/pci/drm/i915/display/intel_display.c

7903

g4x_dp_init(display, DP_D, PORT_D);

sys/dev/pci/drm/i915/display/intel_display.c

7905

if (SUPPORTS_TV(display))

sys/dev/pci/drm/i915/display/intel_display.c

7906

intel_tv_init(display);

sys/dev/pci/drm/i915/display/intel_display.c

7907

} else if (DISPLAY_VER(display) == 2) {

sys/dev/pci/drm/i915/display/intel_display.c

7908

if (display->platform.i85x)

sys/dev/pci/drm/i915/display/intel_display.c

7909

intel_lvds_init(display);

sys/dev/pci/drm/i915/display/intel_display.c

7911

intel_crt_init(display);

sys/dev/pci/drm/i915/display/intel_display.c

7912

intel_dvo_init(display);

sys/dev/pci/drm/i915/display/intel_display.c

7915

for_each_intel_encoder(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_display.c

7922

intel_init_pch_refclk(display);

sys/dev/pci/drm/i915/display/intel_display.c

7924

drm_helper_move_panel_connectors_to_head(display->drm);

sys/dev/pci/drm/i915/display/intel_display.c

7927

static int max_dotclock(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display.c

7929

int max_dotclock = display->cdclk.max_dotclk_freq;

sys/dev/pci/drm/i915/display/intel_display.c

7931

if (HAS_ULTRAJOINER(display))

sys/dev/pci/drm/i915/display/intel_display.c

7933

else if (HAS_UNCOMPRESSED_JOINER(display) || HAS_BIGJOINER(display))

sys/dev/pci/drm/i915/display/intel_display.c

7942

struct intel_display *display = to_intel_display(dev);

sys/dev/pci/drm/i915/display/intel_display.c

7979

if (mode->clock > max_dotclock(display))

sys/dev/pci/drm/i915/display/intel_display.c

7983

if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/intel_display.c

7988

} else if (DISPLAY_VER(display) >= 9 ||

sys/dev/pci/drm/i915/display/intel_display.c

7989

display->platform.broadwell || display->platform.haswell) {

sys/dev/pci/drm/i915/display/intel_display.c

7994

} else if (DISPLAY_VER(display) >= 3) {

sys/dev/pci/drm/i915/display/intel_display.c

8021

enum drm_mode_status intel_cpu_transcoder_mode_valid(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display.c

8028

if (DISPLAY_VER(display) >= 5) {

sys/dev/pci/drm/i915/display/intel_display.c

8047

if ((DISPLAY_VER(display) >= 5 || display->platform.g4x) &&

sys/dev/pci/drm/i915/display/intel_display.c

8055

intel_mode_valid_max_plane_size(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display.c

8065

if (DISPLAY_VER(display) < 9)

sys/dev/pci/drm/i915/display/intel_display.c

8073

if (DISPLAY_VER(display) >= 30) {

sys/dev/pci/drm/i915/display/intel_display.c

8076

} else if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/intel_display.c

8142

void intel_init_display_hooks(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display.c

8144

if (DISPLAY_VER(display) >= 9) {

sys/dev/pci/drm/i915/display/intel_display.c

8145

display->funcs.display = &skl_display_funcs;

sys/dev/pci/drm/i915/display/intel_display.c

8146

} else if (HAS_DDI(display)) {

sys/dev/pci/drm/i915/display/intel_display.c

8147

display->funcs.display = &ddi_display_funcs;

sys/dev/pci/drm/i915/display/intel_display.c

8148

} else if (HAS_PCH_SPLIT(display)) {

sys/dev/pci/drm/i915/display/intel_display.c

8149

display->funcs.display = &pch_split_display_funcs;

sys/dev/pci/drm/i915/display/intel_display.c

8150

} else if (display->platform.cherryview ||

sys/dev/pci/drm/i915/display/intel_display.c

8151

display->platform.valleyview) {

sys/dev/pci/drm/i915/display/intel_display.c

8152

display->funcs.display = &vlv_display_funcs;

sys/dev/pci/drm/i915/display/intel_display.c

8154

display->funcs.display = &i9xx_display_funcs;

sys/dev/pci/drm/i915/display/intel_display.c

8158

int intel_initial_commit(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display.c

8165

state = drm_atomic_state_alloc(display->drm);

sys/dev/pci/drm/i915/display/intel_display.c

8175

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_display.c

8202

for_each_intel_encoder_mask(display->drm, encoder,

sys/dev/pci/drm/i915/display/intel_display.c

8232

void i830_enable_pipe(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_display.c

8234

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_display.c

8247

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

8250

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

8262

intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

8264

intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

8266

intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

8268

intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

8270

intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

8272

intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

8274

intel_de_write(display, PIPESRC(display, pipe),

sys/dev/pci/drm/i915/display/intel_display.c

8277

intel_de_write(display, FP0(pipe), fp);

sys/dev/pci/drm/i915/display/intel_display.c

8278

intel_de_write(display, FP1(pipe), fp);

sys/dev/pci/drm/i915/display/intel_display.c

8285

intel_de_write(display, DPLL(display, pipe),

sys/dev/pci/drm/i915/display/intel_display.c

8287

intel_de_write(display, DPLL(display, pipe), dpll);

sys/dev/pci/drm/i915/display/intel_display.c

8290

intel_de_posting_read(display, DPLL(display, pipe));

sys/dev/pci/drm/i915/display/intel_display.c

8298

intel_de_write(display, DPLL(display, pipe), dpll);

sys/dev/pci/drm/i915/display/intel_display.c

8302

intel_de_write(display, DPLL(display, pipe), dpll);

sys/dev/pci/drm/i915/display/intel_display.c

8303

intel_de_posting_read(display, DPLL(display, pipe));

sys/dev/pci/drm/i915/display/intel_display.c

8307

intel_de_write(display, TRANSCONF(display, pipe), TRANSCONF_ENABLE);

sys/dev/pci/drm/i915/display/intel_display.c

8308

intel_de_posting_read(display, TRANSCONF(display, pipe));

sys/dev/pci/drm/i915/display/intel_display.c

8313

void i830_disable_pipe(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_display.c

8315

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_display.c

8317

drm_dbg_kms(display->drm, "disabling pipe %c due to force quirk\n",

sys/dev/pci/drm/i915/display/intel_display.c

8320

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

8321

intel_de_read(display, DSPCNTR(display, PLANE_A)) & DISP_ENABLE);

sys/dev/pci/drm/i915/display/intel_display.c

8322

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

8323

intel_de_read(display, DSPCNTR(display, PLANE_B)) & DISP_ENABLE);

sys/dev/pci/drm/i915/display/intel_display.c

8324

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

8325

intel_de_read(display, DSPCNTR(display, PLANE_C)) & DISP_ENABLE);

sys/dev/pci/drm/i915/display/intel_display.c

8326

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

8327

intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK);

sys/dev/pci/drm/i915/display/intel_display.c

8328

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

8329

intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK);

sys/dev/pci/drm/i915/display/intel_display.c

8331

intel_de_write(display, TRANSCONF(display, pipe), 0);

sys/dev/pci/drm/i915/display/intel_display.c

8332

intel_de_posting_read(display, TRANSCONF(display, pipe));

sys/dev/pci/drm/i915/display/intel_display.c

8336

intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS);

sys/dev/pci/drm/i915/display/intel_display.c

8337

intel_de_posting_read(display, DPLL(display, pipe));

sys/dev/pci/drm/i915/display/intel_display.c

8340

bool intel_scanout_needs_vtd_wa(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display.c

8342

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display.c

8344

return IS_DISPLAY_VER(display, 6, 11) && i915_vtd_active(i915);

sys/dev/pci/drm/i915/display/intel_display.c

836

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

842

if (DISPLAY_VER(display) == 9)

sys/dev/pci/drm/i915/display/intel_display.c

850

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

853

if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(display) == 11)

sys/dev/pci/drm/i915/display/intel_display.c

861

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

866

DISPLAY_VER(display) == 11)

sys/dev/pci/drm/i915/display/intel_display.c

872

static void intel_async_flip_vtd_wa(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display.c

875

if (DISPLAY_VER(display) == 9) {

sys/dev/pci/drm/i915/display/intel_display.c

880

intel_de_rmw(display, CHICKEN_PIPESL_1(pipe),

sys/dev/pci/drm/i915/display/intel_display.c

885

intel_de_rmw(display, CHICKEN_PIPESL_1(pipe),

sys/dev/pci/drm/i915/display/intel_display.c

893

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

897

(DISPLAY_VER(display) == 9 || display->platform.broadwell ||

sys/dev/pci/drm/i915/display/intel_display.c

898

display->platform.haswell);

sys/dev/pci/drm/i915/display/intel_display.h

372

#define for_each_crtc_in_masks(display, crtc, first_pipes, second_pipes, i) \

sys/dev/pci/drm/i915/display/intel_display.h

374

(i) < (I915_MAX_PIPES * 2) && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \

sys/dev/pci/drm/i915/display/intel_display.h

378

#define for_each_crtc_in_masks_reverse(display, crtc, first_pipes, second_pipes, i) \

sys/dev/pci/drm/i915/display/intel_display.h

380

(i) >= 0 && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \

sys/dev/pci/drm/i915/display/intel_display.h

384

#define for_each_pipe_crtc_modeset_disable(display, crtc, crtc_state, i) \

sys/dev/pci/drm/i915/display/intel_display.h

385

for_each_crtc_in_masks(display, crtc, \

sys/dev/pci/drm/i915/display/intel_display.h

390

#define for_each_pipe_crtc_modeset_enable(display, crtc, crtc_state, i) \

sys/dev/pci/drm/i915/display/intel_display.h

391

for_each_crtc_in_masks_reverse(display, crtc, \

sys/dev/pci/drm/i915/display/intel_display.h

406

intel_mode_valid_max_plane_size(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display.h

410

intel_cpu_transcoder_mode_valid(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display.h

412

enum phy intel_port_to_phy(struct intel_display *display, enum port port);

sys/dev/pci/drm/i915/display/intel_display.h

436

void i830_enable_pipe(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_display.h

437

void i830_disable_pipe(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_display.h

443

bool intel_has_pending_fb_unpin(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display.h

449

bool intel_phy_is_combo(struct intel_display *display, enum phy phy);

sys/dev/pci/drm/i915/display/intel_display.h

450

bool intel_phy_is_tc(struct intel_display *display, enum phy phy);

sys/dev/pci/drm/i915/display/intel_display.h

451

bool intel_phy_is_snps(struct intel_display *display, enum phy phy);

sys/dev/pci/drm/i915/display/intel_display.h

452

enum tc_port intel_port_to_tc(struct intel_display *display, enum port port);

sys/dev/pci/drm/i915/display/intel_display.h

465

void intel_set_m_n(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display.h

469

void intel_get_m_n(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display.h

473

bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display.h

511

int intel_display_max_pipe_bpp(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display.h

518

int intel_modeset_commit_pipes(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display.h

527

void intel_init_display_hooks(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display.h

528

void intel_setup_outputs(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display.h

529

int intel_initial_commit(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display.h

530

void intel_panel_sanitize_ssc(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display.h

531

void intel_update_czclk(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display.h

538

void assert_transcoder(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display.h

543

bool assert_port_valid(struct intel_display *display, enum port port);

sys/dev/pci/drm/i915/display/intel_display.h

560

bool intel_scanout_needs_vtd_wa(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_conversion.c

9

return i915->display;

sys/dev/pci/drm/i915/display/intel_display_core.h

297

const struct intel_display_funcs *display;

sys/dev/pci/drm/i915/display/intel_display_core.h

82

void (*update_wm)(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_core.h

92

void (*get_hw_state)(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_core.h

93

void (*sanitize)(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

100

display->platform.i945g || display->platform.i945gm)

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

1003

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

101

sr_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

1012

ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

102

else if (display->platform.i915gm)

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

1025

out: drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

103

sr_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

104

else if (display->platform.pineview)

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

105

sr_enabled = intel_de_read(display, DSPFW3(display)) & PINEVIEW_SELF_REFRESH_EN;

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

106

else if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

1069

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

107

sr_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

1078

ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

109

intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

1092

out: drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

1136

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

1145

ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

1160

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

1171

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

118

struct intel_display *display = node_to_intel_display(m->private);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

1180

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

1187

drm_dbg(display->drm, "Got %s for DSC Fractional BPP Enable\n",

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

122

fbdev_fb = intel_fbdev_framebuffer(display->fbdev.fbdev);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

1260

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

1278

if (HAS_ULTRAJOINER(display)) {

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

1316

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

1332

if (DISPLAY_VER(display) >= 11 &&

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

135

mutex_lock(&display->drm->mode_config.fb_lock);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

136

drm_for_each_fb(drm_fb, display->drm) {

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

151

mutex_unlock(&display->drm->mode_config.fb_lock);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

158

struct intel_display *display = node_to_intel_display(m->private);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

160

intel_display_power_debug(display, m);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

180

struct intel_display *display = node_to_intel_display(m->private);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

187

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

392

struct intel_display *display = node_to_intel_display(m->private);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

395

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

538

struct intel_display *display = node_to_intel_display(m->private);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

574

for_each_intel_encoder_mask(display->drm, encoder,

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

58

struct intel_display *display = node_to_intel_display(m->private);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

589

struct intel_display *display = node_to_intel_display(m->private);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

595

wakeref = intel_display_rpm_get(display);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

597

drm_modeset_lock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

601

for_each_intel_crtc(display->drm, crtc)

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

607

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

61

drm_printf(&p, "PCH type: %d\n", INTEL_PCH_TYPE(display));

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

612

drm_modeset_unlock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

614

intel_display_rpm_put(display, wakeref);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

621

struct intel_display *display = node_to_intel_display(m->private);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

626

drm_modeset_lock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

629

display->dpll.ref_clks.nssc,

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

63

intel_display_device_info_print(DISPLAY_INFO(display),

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

630

display->dpll.ref_clks.ssc);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

632

for_each_dpll(display, pll, i) {

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

639

intel_dpll_dump_hw_state(display, &p, &pll->state.hw_state);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

64

DISPLAY_RUNTIME_INFO(display), &p);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

641

drm_modeset_unlock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

648

struct intel_display *display = node_to_intel_display(m->private);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

65

intel_display_params_dump(&display->params, display->drm->driver->name, &p);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

652

if (DISPLAY_VER(display) < 9)

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

655

drm_modeset_lock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

659

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

679

drm_modeset_unlock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

685

intel_lpsp_power_well_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

690

with_intel_display_rpm(display)

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

691

is_enabled = intel_display_power_well_is_enabled(display,

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

699

struct intel_display *display = node_to_intel_display(m->private);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

702

if (DISPLAY_VER(display) >= 13 || IS_DISPLAY_VER(display, 9, 10)) {

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

703

lpsp_enabled = !intel_lpsp_power_well_enabled(display, SKL_DISP_PW_2);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

704

} else if (IS_DISPLAY_VER(display, 11, 12)) {

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

705

lpsp_enabled = !intel_lpsp_power_well_enabled(display, ICL_DISP_PW_3);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

706

} else if (display->platform.haswell || display->platform.broadwell) {

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

707

lpsp_enabled = !intel_lpsp_power_well_enabled(display, HSW_DISP_PW_GLOBAL);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

72

struct intel_display *display = node_to_intel_display(m->private);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

720

struct intel_display *display = node_to_intel_display(m->private);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

726

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

74

spin_lock(&display->fb_tracking.lock);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

754

struct intel_display *display = filp->private_data;

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

766

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

77

display->fb_tracking.busy_bits);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

783

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

796

intel_fbc_reset_underrun(display);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

80

display->fb_tracking.flip_bits);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

82

spin_unlock(&display->fb_tracking.lock);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

821

void intel_display_debugfs_register(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

823

struct dentry *debugfs_root = display->drm->debugfs_root;

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

826

display, &i915_fifo_underrun_reset_ops);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

830

debugfs_root, display->drm->primary);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

832

intel_bios_debugfs_register(display);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

833

intel_cdclk_debugfs_register(display);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

834

intel_dmc_debugfs_register(display);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

835

intel_dp_test_debugfs_register(display);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

836

intel_fbc_debugfs_register(display);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

837

intel_hpd_debugfs_register(display);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

838

intel_opregion_debugfs_register(display);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

839

intel_psr_debugfs_register(display);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

840

intel_wm_debugfs_register(display);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

841

intel_display_debugfs_params(display);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

847

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

858

if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

860

else if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

867

else if (DISPLAY_VER(display) == 11)

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

870

else if (IS_DISPLAY_VER(display, 9, 10))

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

875

else if (display->platform.haswell || display->platform.broadwell)

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

887

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

89

struct intel_display *display = node_to_intel_display(m->private);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

899

ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

93

wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

95

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

960

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

969

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

97

else if (HAS_PCH_SPLIT(display))

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

976

drm_dbg(display->drm, "Got %s for DSC Enable\n",

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

98

sr_enabled = intel_de_read(display, WM1_LP_ILK) & WM_LP_ENABLE;

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

99

else if (display->platform.i965gm || display->platform.g4x ||

sys/dev/pci/drm/i915/display/intel_display_debugfs.h

14

void intel_display_debugfs_register(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_debugfs.h

18

static inline void intel_display_debugfs_register(struct intel_display *display) {}

sys/dev/pci/drm/i915/display/intel_display_debugfs_params.c

154

void intel_display_debugfs_params(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_debugfs_params.c

156

struct dentry *debugfs_root = display->drm->debugfs_root;

sys/dev/pci/drm/i915/display/intel_display_debugfs_params.c

160

snprintf(dirname, sizeof(dirname), "%s_params", display->drm->driver->name);

sys/dev/pci/drm/i915/display/intel_display_debugfs_params.c

174

dir, #x, mode, &display->params.x);

sys/dev/pci/drm/i915/display/intel_display_debugfs_params.h

11

void intel_display_debugfs_params(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_device.c

1504

const struct intel_display_device_info *display;

sys/dev/pci/drm/i915/display/intel_display_device.c

1514

probe_gmdid_display(struct intel_display *display, struct intel_display_ip_ver *ip_ver)

sys/dev/pci/drm/i915/display/intel_display_device.c

1516

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_device.c

1517

struct pci_dev *pdev = display->drm->pdev;

sys/dev/pci/drm/i915/display/intel_display_device.c

1530

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_display_device.c

1542

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_display_device.c

1553

drm_dbg_kms(display->drm, "Device doesn't have display\n");

sys/dev/pci/drm/i915/display/intel_display_device.c

1565

return gmdid_display_map[i].display;

sys/dev/pci/drm/i915/display/intel_display_device.c

1569

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_display_device.c

1601

static enum intel_step get_pre_gmdid_step(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_device.c

1605

struct pci_dev *pdev = display->drm->pdev;

sys/dev/pci/drm/i915/display/intel_display_device.c

1624

drm_warn(display->drm, "Unknown revision 0x%02x\n", revision);

sys/dev/pci/drm/i915/display/intel_display_device.c

1638

drm_dbg_kms(display->drm, "Using display stepping for revision 0x%02x\n",

sys/dev/pci/drm/i915/display/intel_display_device.c

1642

drm_dbg_kms(display->drm, "Using future display stepping\n");

sys/dev/pci/drm/i915/display/intel_display_device.c

1647

drm_WARN_ON(display->drm, step == STEP_NONE);

sys/dev/pci/drm/i915/display/intel_display_device.c

1673

struct intel_display *display;

sys/dev/pci/drm/i915/display/intel_display_device.c

1680

display = kzalloc(sizeof(*display), GFP_KERNEL);

sys/dev/pci/drm/i915/display/intel_display_device.c

1681

if (!display)

sys/dev/pci/drm/i915/display/intel_display_device.c

1685

display->drm = pci_get_drvdata(pdev);

sys/dev/pci/drm/i915/display/intel_display_device.c

1687

intel_display_params_copy(&display->params);

sys/dev/pci/drm/i915/display/intel_display_device.c

1688

display->params.enable_psr = 0;

sys/dev/pci/drm/i915/display/intel_display_device.c

1691

drm_dbg_kms(display->drm, "Device doesn't have display\n");

sys/dev/pci/drm/i915/display/intel_display_device.c

1697

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display_device.c

1705

info = probe_gmdid_display(display, &ip_ver);

sys/dev/pci/drm/i915/display/intel_display_device.c

1709

DISPLAY_INFO(display) = info;

sys/dev/pci/drm/i915/display/intel_display_device.c

1711

memcpy(DISPLAY_RUNTIME_INFO(display),

sys/dev/pci/drm/i915/display/intel_display_device.c

1712

&DISPLAY_INFO(display)->__runtime_defaults,

sys/dev/pci/drm/i915/display/intel_display_device.c

1713

sizeof(*DISPLAY_RUNTIME_INFO(display)));

sys/dev/pci/drm/i915/display/intel_display_device.c

1715

drm_WARN_ON(display->drm, !desc->name ||

sys/dev/pci/drm/i915/display/intel_display_device.c

1718

display->platform = desc->platforms;

sys/dev/pci/drm/i915/display/intel_display_device.c

1722

drm_WARN_ON(display->drm, !subdesc->name ||

sys/dev/pci/drm/i915/display/intel_display_device.c

1725

display_platforms_or(&display->platform, &subdesc->platforms);

sys/dev/pci/drm/i915/display/intel_display_device.c

1728

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display_device.c

1729

display_platforms_weight(&display->platform) !=

sys/dev/pci/drm/i915/display/intel_display_device.c

1735

DISPLAY_RUNTIME_INFO(display)->ip = ip_ver;

sys/dev/pci/drm/i915/display/intel_display_device.c

1738

drm_dbg_kms(display->drm, "Using future display stepping\n");

sys/dev/pci/drm/i915/display/intel_display_device.c

1742

step = get_pre_gmdid_step(display, &desc->step_info,

sys/dev/pci/drm/i915/display/intel_display_device.c

1746

DISPLAY_RUNTIME_INFO(display)->step = step;

sys/dev/pci/drm/i915/display/intel_display_device.c

1748

drm_info(display->drm, "Found %s%s%s (device ID %04x) %s display version %u.%02u stepping %s\n",

sys/dev/pci/drm/i915/display/intel_display_device.c

1750

pdev->device, display->platform.dgfx ? "discrete" : "integrated",

sys/dev/pci/drm/i915/display/intel_display_device.c

1751

DISPLAY_RUNTIME_INFO(display)->ip.ver,

sys/dev/pci/drm/i915/display/intel_display_device.c

1752

DISPLAY_RUNTIME_INFO(display)->ip.rel,

sys/dev/pci/drm/i915/display/intel_display_device.c

1755

return display;

sys/dev/pci/drm/i915/display/intel_display_device.c

1758

DISPLAY_INFO(display) = &no_display;

sys/dev/pci/drm/i915/display/intel_display_device.c

1760

return display;

sys/dev/pci/drm/i915/display/intel_display_device.c

1763

void intel_display_device_remove(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_device.c

1765

if (!display)

sys/dev/pci/drm/i915/display/intel_display_device.c

1768

intel_display_params_free(&display->params);

sys/dev/pci/drm/i915/display/intel_display_device.c

1769

kfree(display);

sys/dev/pci/drm/i915/display/intel_display_device.c

1772

static void __intel_display_device_info_runtime_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_device.c

1774

struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(display);

sys/dev/pci/drm/i915/display/intel_display_device.c

1782

if (display->platform.haswell_ult || display->platform.broadwell_ult)

sys/dev/pci/drm/i915/display/intel_display_device.c

1785

if (display->platform.icelake_port_f)

sys/dev/pci/drm/i915/display/intel_display_device.c

1789

if (display->platform.alderlake_s && IS_DISPLAY_STEP(display, STEP_A0, STEP_A2))

sys/dev/pci/drm/i915/display/intel_display_device.c

1790

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_device.c

1792

else if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/intel_display_device.c

1793

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_device.c

1795

} else if (DISPLAY_VER(display) >= 9) {

sys/dev/pci/drm/i915/display/intel_display_device.c

1801

if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display))

sys/dev/pci/drm/i915/display/intel_display_device.c

1802

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_device.c

1804

else if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_display_device.c

1805

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_device.c

1807

else if (DISPLAY_VER(display) == 10)

sys/dev/pci/drm/i915/display/intel_display_device.c

1808

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_device.c

1810

else if (display->platform.broxton) {

sys/dev/pci/drm/i915/display/intel_display_device.c

1823

} else if (display->platform.valleyview || display->platform.cherryview) {

sys/dev/pci/drm/i915/display/intel_display_device.c

1824

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_device.c

1826

} else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) {

sys/dev/pci/drm/i915/display/intel_display_device.c

1827

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_device.c

1831

if ((display->platform.dgfx || DISPLAY_VER(display) >= 14) &&

sys/dev/pci/drm/i915/display/intel_display_device.c

1832

!(intel_de_read(display, GU_CNTL_PROTECTED) & DEPRESENT)) {

sys/dev/pci/drm/i915/display/intel_display_device.c

1833

drm_info(display->drm, "Display not present, disabling\n");

sys/dev/pci/drm/i915/display/intel_display_device.c

1837

if (IS_DISPLAY_VER(display, 7, 8) && HAS_PCH_SPLIT(display)) {

sys/dev/pci/drm/i915/display/intel_display_device.c

1838

u32 fuse_strap = intel_de_read(display, FUSE_STRAP);

sys/dev/pci/drm/i915/display/intel_display_device.c

1839

u32 sfuse_strap = intel_de_read(display, SFUSE_STRAP);

sys/dev/pci/drm/i915/display/intel_display_device.c

1852

(HAS_PCH_CPT(display) &&

sys/dev/pci/drm/i915/display/intel_display_device.c

1854

drm_info(display->drm,

sys/dev/pci/drm/i915/display/intel_display_device.c

1858

drm_info(display->drm, "PipeC fused off\n");

sys/dev/pci/drm/i915/display/intel_display_device.c

1862

} else if (DISPLAY_VER(display) >= 9) {

sys/dev/pci/drm/i915/display/intel_display_device.c

1863

u32 dfsm = intel_de_read(display, SKL_DFSM);

sys/dev/pci/drm/i915/display/intel_display_device.c

1881

if (DISPLAY_VER(display) >= 12 &&

sys/dev/pci/drm/i915/display/intel_display_device.c

1894

if (display->platform.dg2 || DISPLAY_VER(display) < 13) {

sys/dev/pci/drm/i915/display/intel_display_device.c

1899

if (DISPLAY_VER(display) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))

sys/dev/pci/drm/i915/display/intel_display_device.c

1902

if (IS_DISPLAY_VER(display, 10, 12) &&

sys/dev/pci/drm/i915/display/intel_display_device.c

1906

if (DISPLAY_VER(display) >= 20 &&

sys/dev/pci/drm/i915/display/intel_display_device.c

1911

if (DISPLAY_VER(display) >= 20) {

sys/dev/pci/drm/i915/display/intel_display_device.c

1912

u32 cap = intel_de_read(display, XE2LPD_DE_CAP);

sys/dev/pci/drm/i915/display/intel_display_device.c

1920

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_device.c

1926

if (DISPLAY_VER(display) >= 30)

sys/dev/pci/drm/i915/display/intel_display_device.c

1928

intel_de_read(display, PICA_PHY_CONFIG_CONTROL) & EDP_ON_TYPEC;

sys/dev/pci/drm/i915/display/intel_display_device.c

1930

display_runtime->rawclk_freq = intel_read_rawclk(display);

sys/dev/pci/drm/i915/display/intel_display_device.c

1931

drm_dbg_kms(display->drm, "rawclk rate: %d kHz\n",

sys/dev/pci/drm/i915/display/intel_display_device.c

1940

void intel_display_device_info_runtime_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_device.c

1942

if (HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_device.c

1943

__intel_display_device_info_runtime_init(display);

sys/dev/pci/drm/i915/display/intel_display_device.c

1946

if (!HAS_DISPLAY(display)) {

sys/dev/pci/drm/i915/display/intel_display_device.c

1947

display->drm->driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC);

sys/dev/pci/drm/i915/display/intel_display_device.c

1948

display->info.__device_info = &no_display;

sys/dev/pci/drm/i915/display/intel_display_device.c

1952

if (!display->params.nuclear_pageflip &&

sys/dev/pci/drm/i915/display/intel_display_device.c

1953

DISPLAY_VER(display) < 5 && !display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_display_device.c

1954

display->drm->driver_features &= ~DRIVER_ATOMIC;

sys/dev/pci/drm/i915/display/intel_display_device.c

1982

bool intel_display_device_present(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_device.c

1984

return display && HAS_DISPLAY(display);

sys/dev/pci/drm/i915/display/intel_display_device.c

1996

bool intel_display_device_enabled(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_device.c

1999

drm_WARN_ON(display->drm, !HAS_DISPLAY(display));

sys/dev/pci/drm/i915/display/intel_display_device.c

2001

return !display->params.disable_display &&

sys/dev/pci/drm/i915/display/intel_display_device.c

2002

!intel_opregion_headless_sku(display);

sys/dev/pci/drm/i915/display/intel_display_device.h

311

bool intel_display_device_present(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_device.h

312

bool intel_display_device_enabled(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_device.h

314

void intel_display_device_remove(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_device.h

315

void intel_display_device_info_runtime_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

114

static void intel_mode_config_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_driver.c

116

struct drm_mode_config *mode_config = &display->drm->mode_config;

sys/dev/pci/drm/i915/display/intel_display_driver.c

118

drm_mode_config_init(display->drm);

sys/dev/pci/drm/i915/display/intel_display_driver.c

119

INIT_LIST_HEAD(&display->global.obj_list);

sys/dev/pci/drm/i915/display/intel_display_driver.c

130

mode_config->async_page_flip = HAS_ASYNC_FLIPS(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

136

if (DISPLAY_VER(display) >= 7) {

sys/dev/pci/drm/i915/display/intel_display_driver.c

139

} else if (DISPLAY_VER(display) >= 4) {

sys/dev/pci/drm/i915/display/intel_display_driver.c

142

} else if (DISPLAY_VER(display) == 3) {

sys/dev/pci/drm/i915/display/intel_display_driver.c

150

if (display->platform.i845g || display->platform.i865g) {

sys/dev/pci/drm/i915/display/intel_display_driver.c

151

mode_config->cursor_width = display->platform.i845g ? 64 : 512;

sys/dev/pci/drm/i915/display/intel_display_driver.c

153

} else if (display->platform.i830 || display->platform.i85x ||

sys/dev/pci/drm/i915/display/intel_display_driver.c

154

display->platform.i915g || display->platform.i915gm) {

sys/dev/pci/drm/i915/display/intel_display_driver.c

163

static void intel_mode_config_cleanup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_driver.c

165

intel_atomic_global_obj_cleanup(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

166

drm_mode_config_cleanup(display->drm);

sys/dev/pci/drm/i915/display/intel_display_driver.c

169

static void intel_plane_possible_crtcs_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_driver.c

173

for_each_intel_plane(display->drm, plane) {

sys/dev/pci/drm/i915/display/intel_display_driver.c

174

struct intel_crtc *crtc = intel_crtc_for_pipe(display,

sys/dev/pci/drm/i915/display/intel_display_driver.c

181

void intel_display_driver_early_probe(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_driver.c

184

intel_pch_detect(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

186

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_driver.c

189

mtx_init(&display->fb_tracking.lock, IPL_NONE);

sys/dev/pci/drm/i915/display/intel_display_driver.c

190

rw_init(&display->backlight.lock, "blight");

sys/dev/pci/drm/i915/display/intel_display_driver.c

191

rw_init(&display->audio.mutex, "daud");

sys/dev/pci/drm/i915/display/intel_display_driver.c

192

rw_init(&display->wm.wm_mutex, "wmm");

sys/dev/pci/drm/i915/display/intel_display_driver.c

193

rw_init(&display->pps.mutex, "ppsm");

sys/dev/pci/drm/i915/display/intel_display_driver.c

194

rw_init(&display->hdcp.hdcp_mutex, "hdcpc");

sys/dev/pci/drm/i915/display/intel_display_driver.c

196

intel_display_irq_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

197

intel_dkl_phy_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

198

intel_color_init_hooks(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

199

intel_init_cdclk_hooks(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

200

intel_audio_hooks_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

201

intel_dpll_init_clock_hook(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

202

intel_init_display_hooks(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

203

intel_fdi_init_hook(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

204

intel_dmc_wl_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

208

int intel_display_driver_probe_noirq(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_driver.c

210

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_driver.c

216

if (HAS_DISPLAY(display)) {

sys/dev/pci/drm/i915/display/intel_display_driver.c

217

ret = drm_vblank_init(display->drm,

sys/dev/pci/drm/i915/display/intel_display_driver.c

218

INTEL_NUM_PIPES(display));

sys/dev/pci/drm/i915/display/intel_display_driver.c

223

intel_bios_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

225

ret = intel_vga_register(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

229

intel_psr_dc5_dc6_wa_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

232

ret = intel_power_domains_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

236

intel_pmdemand_init_early(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

238

intel_power_domains_init_hw(display, false);

sys/dev/pci/drm/i915/display/intel_display_driver.c

240

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_driver.c

243

display->hotplug.dp_wq = alloc_ordered_workqueue("intel-dp", 0);

sys/dev/pci/drm/i915/display/intel_display_driver.c

244

if (!display->hotplug.dp_wq) {

sys/dev/pci/drm/i915/display/intel_display_driver.c

249

display->wq.modeset = alloc_ordered_workqueue("i915_modeset", 0);

sys/dev/pci/drm/i915/display/intel_display_driver.c

250

if (!display->wq.modeset) {

sys/dev/pci/drm/i915/display/intel_display_driver.c

255

display->wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI |

sys/dev/pci/drm/i915/display/intel_display_driver.c

257

if (!display->wq.flip) {

sys/dev/pci/drm/i915/display/intel_display_driver.c

262

display->wq.cleanup = alloc_workqueue("i915_cleanup", WQ_HIGHPRI, 0);

sys/dev/pci/drm/i915/display/intel_display_driver.c

263

if (!display->wq.cleanup) {

sys/dev/pci/drm/i915/display/intel_display_driver.c

268

display->wq.unordered = alloc_workqueue("display_unordered", 0, 0);

sys/dev/pci/drm/i915/display/intel_display_driver.c

269

if (!display->wq.unordered) {

sys/dev/pci/drm/i915/display/intel_display_driver.c

274

intel_dmc_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

276

intel_mode_config_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

278

ret = intel_cdclk_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

282

ret = intel_color_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

286

ret = intel_dbuf_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

290

ret = intel_bw_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

294

ret = intel_pmdemand_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

298

intel_init_quirks(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

300

intel_fbc_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

305

destroy_workqueue(display->wq.unordered);

sys/dev/pci/drm/i915/display/intel_display_driver.c

307

destroy_workqueue(display->wq.cleanup);

sys/dev/pci/drm/i915/display/intel_display_driver.c

309

destroy_workqueue(display->wq.flip);

sys/dev/pci/drm/i915/display/intel_display_driver.c

311

destroy_workqueue(display->wq.modeset);

sys/dev/pci/drm/i915/display/intel_display_driver.c

313

destroy_workqueue(display->hotplug.dp_wq);

sys/dev/pci/drm/i915/display/intel_display_driver.c

315

intel_dmc_fini(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

316

intel_power_domains_driver_remove(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

318

intel_vga_unregister(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

320

intel_bios_driver_remove(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

325

static void set_display_access(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_driver.c

333

err = drm_modeset_lock_all_ctx(display->drm, &ctx);

sys/dev/pci/drm/i915/display/intel_display_driver.c

337

display->access.any_task_allowed = any_task_allowed;

sys/dev/pci/drm/i915/display/intel_display_driver.c

338

display->access.allowed_task = allowed_task;

sys/dev/pci/drm/i915/display/intel_display_driver.c

341

drm_WARN_ON(display->drm, err);

sys/dev/pci/drm/i915/display/intel_display_driver.c

354

void intel_display_driver_enable_user_access(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_driver.c

356

set_display_access(display, true, NULL);

sys/dev/pci/drm/i915/display/intel_display_driver.c

358

intel_hpd_enable_detection_work(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

378

void intel_display_driver_disable_user_access(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_driver.c

380

intel_hpd_disable_detection_work(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

383

set_display_access(display, false, current);

sys/dev/pci/drm/i915/display/intel_display_driver.c

385

set_display_access(display, false, curproc);

sys/dev/pci/drm/i915/display/intel_display_driver.c

401

void intel_display_driver_suspend_access(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_driver.c

403

set_display_access(display, false, NULL);

sys/dev/pci/drm/i915/display/intel_display_driver.c

420

void intel_display_driver_resume_access(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_driver.c

423

set_display_access(display, false, current);

sys/dev/pci/drm/i915/display/intel_display_driver.c

425

set_display_access(display, false, curproc);

sys/dev/pci/drm/i915/display/intel_display_driver.c

440

bool intel_display_driver_check_access(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_driver.c

445

if (display->access.any_task_allowed ||

sys/dev/pci/drm/i915/display/intel_display_driver.c

446

display->access.allowed_task == curproc)

sys/dev/pci/drm/i915/display/intel_display_driver.c

458

if (display->access.allowed_task)

sys/dev/pci/drm/i915/display/intel_display_driver.c

461

display->access.allowed_task->comm,

sys/dev/pci/drm/i915/display/intel_display_driver.c

462

task_pid_vnr(display->access.allowed_task));

sys/dev/pci/drm/i915/display/intel_display_driver.c

465

display->access.allowed_task->p_p->ps_comm,

sys/dev/pci/drm/i915/display/intel_display_driver.c

466

display->access.allowed_task->p_p->ps_pid);

sys/dev/pci/drm/i915/display/intel_display_driver.c

469

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display_driver.c

477

int intel_display_driver_probe_nogem(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_driver.c

482

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_driver.c

485

intel_wm_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

487

intel_panel_sanitize_ssc(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

489

intel_pps_setup(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

491

intel_gmbus_setup(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

493

drm_dbg_kms(display->drm, "%d display pipe%s available.\n",

sys/dev/pci/drm/i915/display/intel_display_driver.c

494

INTEL_NUM_PIPES(display),

sys/dev/pci/drm/i915/display/intel_display_driver.c

495

INTEL_NUM_PIPES(display) > 1 ? "s" : "");

sys/dev/pci/drm/i915/display/intel_display_driver.c

497

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_driver.c

498

ret = intel_crtc_init(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_driver.c

503

intel_plane_possible_crtcs_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

504

intel_dpll_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

505

intel_fdi_pll_freq_update(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

507

intel_update_czclk(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

508

intel_display_driver_init_hw(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

509

intel_dpll_update_ref_clks(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

511

if (display->cdclk.max_cdclk_freq == 0)

sys/dev/pci/drm/i915/display/intel_display_driver.c

512

intel_update_max_cdclk(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

514

intel_hti_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

516

intel_setup_outputs(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

518

ret = intel_dp_tunnel_mgr_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

522

intel_display_driver_disable_user_access(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

524

drm_modeset_lock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_display_driver.c

525

intel_modeset_setup_hw_state(display, display->drm->mode_config.acquire_ctx);

sys/dev/pci/drm/i915/display/intel_display_driver.c

526

intel_acpi_assign_connector_fwnodes(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

527

drm_modeset_unlock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_display_driver.c

529

intel_initial_plane_config(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

536

if (!HAS_GMCH(display))

sys/dev/pci/drm/i915/display/intel_display_driver.c

537

ilk_wm_sanitize(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

542

intel_hdcp_component_fini(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

544

intel_mode_config_cleanup(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

550

int intel_display_driver_probe(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_driver.c

554

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_driver.c

562

intel_hdcp_component_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

564

intel_flipq_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

572

ret = intel_initial_commit(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

574

drm_dbg_kms(display->drm, "Initial modeset failed, %d\n", ret);

sys/dev/pci/drm/i915/display/intel_display_driver.c

576

intel_overlay_setup(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

579

intel_hpd_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

581

skl_watermark_ipc_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

586

void intel_display_driver_register(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_driver.c

588

struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS,

sys/dev/pci/drm/i915/display/intel_display_driver.c

591

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_driver.c

595

intel_opregion_register(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

596

intel_acpi_video_register(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

598

intel_audio_init(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

600

intel_display_driver_enable_user_access(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

602

intel_audio_register(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

604

intel_display_debugfs_register(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

611

drm_kms_helper_poll_init(display->drm);

sys/dev/pci/drm/i915/display/intel_display_driver.c

612

intel_hpd_poll_disable(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

614

intel_fbdev_setup(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

616

intel_display_device_info_print(DISPLAY_INFO(display),

sys/dev/pci/drm/i915/display/intel_display_driver.c

617

DISPLAY_RUNTIME_INFO(display), &p);

sys/dev/pci/drm/i915/display/intel_display_driver.c

623

void intel_display_driver_remove(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_driver.c

625

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_driver.c

628

flush_workqueue(display->wq.flip);

sys/dev/pci/drm/i915/display/intel_display_driver.c

629

flush_workqueue(display->wq.modeset);

sys/dev/pci/drm/i915/display/intel_display_driver.c

630

flush_workqueue(display->wq.cleanup);

sys/dev/pci/drm/i915/display/intel_display_driver.c

631

flush_workqueue(display->wq.unordered);

sys/dev/pci/drm/i915/display/intel_display_driver.c

638

intel_dp_mst_suspend(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

642

void intel_display_driver_remove_noirq(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_driver.c

644

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_driver.c

647

intel_display_driver_suspend_access(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

653

intel_hpd_poll_fini(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

658

flush_workqueue(display->wq.unordered);

sys/dev/pci/drm/i915/display/intel_display_driver.c

660

intel_hdcp_component_fini(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

662

intel_mode_config_cleanup(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

664

intel_dp_tunnel_mgr_cleanup(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

666

intel_overlay_cleanup(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

668

intel_gmbus_teardown(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

670

destroy_workqueue(display->hotplug.dp_wq);

sys/dev/pci/drm/i915/display/intel_display_driver.c

671

destroy_workqueue(display->wq.flip);

sys/dev/pci/drm/i915/display/intel_display_driver.c

672

destroy_workqueue(display->wq.modeset);

sys/dev/pci/drm/i915/display/intel_display_driver.c

673

destroy_workqueue(display->wq.cleanup);

sys/dev/pci/drm/i915/display/intel_display_driver.c

674

destroy_workqueue(display->wq.unordered);

sys/dev/pci/drm/i915/display/intel_display_driver.c

676

intel_fbc_cleanup(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

680

void intel_display_driver_remove_nogem(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_driver.c

682

intel_dmc_fini(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

684

intel_power_domains_driver_remove(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

686

intel_vga_unregister(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

688

intel_bios_driver_remove(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

691

void intel_display_driver_unregister(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_driver.c

693

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_driver.c

698

drm_client_dev_unregister(display->drm);

sys/dev/pci/drm/i915/display/intel_display_driver.c

705

drm_kms_helper_poll_fini(display->drm);

sys/dev/pci/drm/i915/display/intel_display_driver.c

707

intel_display_driver_disable_user_access(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

709

intel_audio_deinit(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

711

drm_atomic_helper_shutdown(display->drm);

sys/dev/pci/drm/i915/display/intel_display_driver.c

714

intel_opregion_unregister(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

721

int intel_display_driver_suspend(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_driver.c

726

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_driver.c

729

state = drm_atomic_helper_suspend(display->drm);

sys/dev/pci/drm/i915/display/intel_display_driver.c

732

drm_err(display->drm, "Suspending crtc's failed with %i\n",

sys/dev/pci/drm/i915/display/intel_display_driver.c

735

display->restore.modeset_state = state;

sys/dev/pci/drm/i915/display/intel_display_driver.c

738

flush_workqueue(display->wq.cleanup);

sys/dev/pci/drm/i915/display/intel_display_driver.c

740

intel_dp_mst_suspend(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

746

__intel_display_driver_resume(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_driver.c

754

intel_modeset_setup_hw_state(display, ctx);

sys/dev/pci/drm/i915/display/intel_display_driver.c

774

if (!HAS_GMCH(display))

sys/dev/pci/drm/i915/display/intel_display_driver.c

779

drm_WARN_ON(display->drm, ret == -EDEADLK);

sys/dev/pci/drm/i915/display/intel_display_driver.c

784

void intel_display_driver_resume(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_driver.c

786

struct drm_atomic_state *state = display->restore.modeset_state;

sys/dev/pci/drm/i915/display/intel_display_driver.c

790

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_driver.c

794

intel_dp_mst_resume(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

796

display->restore.modeset_state = NULL;

sys/dev/pci/drm/i915/display/intel_display_driver.c

803

ret = drm_modeset_lock_all_ctx(display->drm, &ctx);

sys/dev/pci/drm/i915/display/intel_display_driver.c

811

ret = __intel_display_driver_resume(display, state, &ctx);

sys/dev/pci/drm/i915/display/intel_display_driver.c

813

skl_watermark_ipc_update(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

818

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_display_driver.c

89

void intel_display_driver_init_hw(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_driver.c

91

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_driver.c

94

intel_cdclk_read_hw(display);

sys/dev/pci/drm/i915/display/intel_display_driver.c

96

intel_display_wa_apply(display);

sys/dev/pci/drm/i915/display/intel_display_driver.h

17

void intel_display_driver_init_hw(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_driver.h

18

void intel_display_driver_early_probe(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_driver.h

19

int intel_display_driver_probe_noirq(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_driver.h

20

int intel_display_driver_probe_nogem(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_driver.h

21

int intel_display_driver_probe(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_driver.h

22

void intel_display_driver_register(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_driver.h

23

void intel_display_driver_remove(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_driver.h

24

void intel_display_driver_remove_noirq(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_driver.h

25

void intel_display_driver_remove_nogem(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_driver.h

26

void intel_display_driver_unregister(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_driver.h

27

int intel_display_driver_suspend(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_driver.h

28

void intel_display_driver_resume(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_driver.h

31

int __intel_display_driver_resume(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_driver.h

35

void intel_display_driver_enable_user_access(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_driver.h

36

void intel_display_driver_disable_user_access(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_driver.h

37

void intel_display_driver_suspend_access(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_driver.h

38

void intel_display_driver_resume_access(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_driver.h

39

bool intel_display_driver_check_access(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1006

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_display_irq.c

101

static void intel_pipe_fault_irq_handler(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1011

if (DISPLAY_VER(display) == 11) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

1019

static u32 gen8_de_pipe_fault_mask(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1021

if (DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1029

else if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1039

else if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display))

sys/dev/pci/drm/i915/display/intel_display_irq.c

1047

else if (DISPLAY_VER(display) == 12)

sys/dev/pci/drm/i915/display/intel_display_irq.c

105

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1057

else if (DISPLAY_VER(display) == 11)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1066

else if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1080

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1082

drm_err_ratelimited(display->drm,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1091

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1093

drm_err_ratelimited(display->drm,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1102

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1104

drm_err_ratelimited(display->drm,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1166

gen8_pipe_fault_handlers(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1168

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1170

else if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1172

else if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1174

else if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1180

static void intel_pmdemand_irq_handler(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1182

wake_up_all(&display->pmdemand.waitqueue);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1186

gen8_de_misc_irq_handler(struct intel_display *display, u32 iir)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1190

if (HAS_DBUF_OVERLAP_DETECTION(display)) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

1192

drm_warn(display->drm, "DBuf overlap detected\n");

sys/dev/pci/drm/i915/display/intel_display_irq.c

1197

if (DISPLAY_VER(display) >= 14) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

1201

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1204

intel_pmdemand_irq_handler(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1209

u32 val = intel_de_read(display, RM_TIMEOUT_REG_CAPTURE);

sys/dev/pci/drm/i915/display/intel_display_irq.c

121

intel_handle_vblank(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1210

drm_warn(display->drm, "Register Access Timeout = 0x%x\n", val);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1214

intel_opregion_asle_intr(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1223

for_each_intel_encoder_with_psr(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

1226

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1227

iir_reg = TRANS_PSR_IIR(display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

123

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1232

psr_iir = intel_de_rmw(display, iir_reg, 0, 0);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1240

if (DISPLAY_VER(display) < 12)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1246

drm_err(display->drm, "Unexpected DE Misc interrupt: 0x%08x\n", iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1249

static void gen11_dsi_te_interrupt_handler(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1261

val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_DSI_0));

sys/dev/pci/drm/i915/display/intel_display_irq.c

1273

val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));

sys/dev/pci/drm/i915/display/intel_display_irq.c

1277

drm_err(display->drm, "DSI trancoder not configured in command mode\n");

sys/dev/pci/drm/i915/display/intel_display_irq.c

1282

val = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, dsi_trans));

sys/dev/pci/drm/i915/display/intel_display_irq.c

1294

drm_err(display->drm, "Invalid PIPE\n");

sys/dev/pci/drm/i915/display/intel_display_irq.c

1298

intel_handle_vblank(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1302

intel_de_rmw(display, DSI_INTR_IDENT_REG(port), 0, 0);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1305

static u32 gen8_de_pipe_flip_done_mask(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1307

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1313

static void gen8_read_and_ack_pch_irqs(struct intel_display *display, u32 *pch_iir, u32 *pica_iir)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1318

*pch_iir = intel_de_read(display, SDEIIR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1328

drm_WARN_ON(display->drm, INTEL_PCH_TYPE(display) < PCH_MTL);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1330

pica_ier = intel_de_rmw(display, PICAINTERRUPT_IER, ~0, 0);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1331

*pica_iir = intel_de_read(display, PICAINTERRUPT_IIR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1332

intel_de_write(display, PICAINTERRUPT_IIR, *pica_iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1335

intel_de_write(display, SDEIIR, *pch_iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1338

intel_de_write(display, PICAINTERRUPT_IER, pica_ier);

sys/dev/pci/drm/i915/display/intel_display_irq.c

134

void ilk_update_display_irq(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1341

void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1346

drm_WARN_ON_ONCE(display->drm, !HAS_DISPLAY(display));

sys/dev/pci/drm/i915/display/intel_display_irq.c

1349

iir = intel_de_read(display, GEN8_DE_MISC_IIR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1351

intel_de_write(display, GEN8_DE_MISC_IIR, iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1352

gen8_de_misc_irq_handler(display, iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1354

drm_err_ratelimited(display->drm,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1359

if (DISPLAY_VER(display) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

1360

iir = intel_de_read(display, GEN11_DE_HPD_IIR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1362

intel_de_write(display, GEN11_DE_HPD_IIR, iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1363

gen11_hpd_irq_handler(display, iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1365

drm_err_ratelimited(display->drm,

sys/dev/pci/drm/i915/display/intel_display_irq.c

137

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1371

iir = intel_de_read(display, GEN8_DE_PORT_IIR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1375

intel_de_write(display, GEN8_DE_PORT_IIR, iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1377

if (iir & gen8_de_port_aux_mask(display)) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

1378

intel_dp_aux_irq_handler(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1382

if (display->platform.geminilake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

1386

bxt_hpd_irq_handler(display, hotplug_trigger);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1389

} else if (display->platform.broadwell) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

1393

ilk_hpd_irq_handler(display, hotplug_trigger);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1398

if ((display->platform.geminilake || display->platform.broxton) &&

sys/dev/pci/drm/i915/display/intel_display_irq.c

140

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1400

intel_gmbus_irq_handler(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1404

if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

1408

gen11_dsi_te_interrupt_handler(display, te_trigger);

sys/dev/pci/drm/i915/display/intel_display_irq.c

141

drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1414

drm_err_ratelimited(display->drm,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1417

drm_err_ratelimited(display->drm,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1422

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

1428

iir = intel_de_read(display, GEN8_DE_PIPE_IIR(pipe));

sys/dev/pci/drm/i915/display/intel_display_irq.c

1430

drm_err_ratelimited(display->drm,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1436

intel_de_write(display, GEN8_DE_PIPE_IIR(pipe), iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1439

intel_handle_vblank(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1441

if (iir & gen8_de_pipe_flip_done_mask(display))

sys/dev/pci/drm/i915/display/intel_display_irq.c

1442

flip_done_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1444

if (HAS_DSB(display)) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

1446

intel_dsb_irq_handler(display, pipe, INTEL_DSB_0);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1449

intel_dsb_irq_handler(display, pipe, INTEL_DSB_1);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1452

intel_dsb_irq_handler(display, pipe, INTEL_DSB_2);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1455

if (HAS_PIPEDMC(display) && iir & GEN12_PIPEDMC_INTERRUPT)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1456

intel_pipedmc_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1459

hsw_pipe_crc_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1462

intel_cpu_fifo_underrun_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1464

fault_errors = iir & gen8_de_pipe_fault_mask(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1466

intel_pipe_fault_irq_handler(display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1467

gen8_pipe_fault_handlers(display),

sys/dev/pci/drm/i915/display/intel_display_irq.c

1471

if (HAS_PCH_SPLIT(display) && !HAS_PCH_NOP(display) &&

sys/dev/pci/drm/i915/display/intel_display_irq.c

148

!drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv))) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

1480

gen8_read_and_ack_pch_irqs(display, &iir, &pica_iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1483

xelpdp_pica_irq_handler(display, pica_iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1485

if (INTEL_PCH_TYPE(display) >= PCH_ICP)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1486

icp_irq_handler(display, iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1487

else if (INTEL_PCH_TYPE(display) >= PCH_SPT)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1488

spt_irq_handler(display, iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1490

cpt_irq_handler(display, iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1496

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_display_irq.c

150

intel_de_write(display, DEIMR, dev_priv->irq_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1502

u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1509

intel_display_rpm_assert_block(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

151

intel_de_posting_read(display, DEIMR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1511

iir = intel_de_read(display, GEN11_GU_MISC_IIR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1513

intel_de_write(display, GEN11_GU_MISC_IIR, iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1515

intel_display_rpm_assert_unblock(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1520

void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1523

intel_opregion_asle_intr(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1526

void gen11_display_irq_handler(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1530

intel_display_rpm_assert_block(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1535

disp_ctl = intel_de_read(display, GEN11_DISPLAY_INT_CTL);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1537

intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1538

gen8_de_irq_handler(display, disp_ctl);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1539

intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1541

intel_display_rpm_assert_unblock(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1544

static void i915gm_irq_cstate_wa_enable(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1546

lockdep_assert_held(&display->drm->vblank_time_lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

155

void ilk_enable_display_irq(struct intel_display *display, u32 bits)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1554

if (display->irq.vblank_enabled++ == 0)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1555

intel_de_write(display, SCPD0,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1559

static void i915gm_irq_cstate_wa_disable(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1561

lockdep_assert_held(&display->drm->vblank_time_lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1563

if (--display->irq.vblank_enabled == 0)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1564

intel_de_write(display, SCPD0,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1568

void i915gm_irq_cstate_wa(struct intel_display *display, bool enable)

sys/dev/pci/drm/i915/display/intel_display_irq.c

157

ilk_update_display_irq(display, bits, bits);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1570

spin_lock_irq(&display->drm->vblank_time_lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1573

i915gm_irq_cstate_wa_enable(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1575

i915gm_irq_cstate_wa_disable(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1577

spin_unlock_irq(&display->drm->vblank_time_lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1582

struct intel_display *display = to_intel_display(crtc->dev);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1586

spin_lock_irqsave(&display->irq.lock, irqflags);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1587

i915_enable_pipestat(display, pipe, PIPE_VBLANK_INTERRUPT_STATUS);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1588

spin_unlock_irqrestore(&display->irq.lock, irqflags);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1595

struct intel_display *display = to_intel_display(crtc->dev);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1599

spin_lock_irqsave(&display->irq.lock, irqflags);

sys/dev/pci/drm/i915/display/intel_display_irq.c

160

void ilk_disable_display_irq(struct intel_display *display, u32 bits)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1600

i915_disable_pipestat(display, pipe, PIPE_VBLANK_INTERRUPT_STATUS);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1601

spin_unlock_irqrestore(&display->irq.lock, irqflags);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1606

struct intel_display *display = to_intel_display(crtc->dev);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1608

i915gm_irq_cstate_wa_enable(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1615

struct intel_display *display = to_intel_display(crtc->dev);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1619

i915gm_irq_cstate_wa_disable(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

162

ilk_update_display_irq(display, bits, 0);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1624

struct intel_display *display = to_intel_display(crtc->dev);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1628

spin_lock_irqsave(&display->irq.lock, irqflags);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1629

i915_enable_pipestat(display, pipe,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1631

spin_unlock_irqrestore(&display->irq.lock, irqflags);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1638

struct intel_display *display = to_intel_display(crtc->dev);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1642

spin_lock_irqsave(&display->irq.lock, irqflags);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1643

i915_disable_pipestat(display, pipe,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1645

spin_unlock_irqrestore(&display->irq.lock, irqflags);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1650

struct intel_display *display = to_intel_display(crtc->dev);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1653

u32 bit = DISPLAY_VER(display) >= 7 ?

sys/dev/pci/drm/i915/display/intel_display_irq.c

1656

spin_lock_irqsave(&display->irq.lock, irqflags);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1657

ilk_enable_display_irq(display, bit);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1658

spin_unlock_irqrestore(&display->irq.lock, irqflags);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1663

if (HAS_PSR(display))

sys/dev/pci/drm/i915/display/intel_display_irq.c

1671

struct intel_display *display = to_intel_display(crtc->dev);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1674

u32 bit = DISPLAY_VER(display) >= 7 ?

sys/dev/pci/drm/i915/display/intel_display_irq.c

1677

spin_lock_irqsave(&display->irq.lock, irqflags);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1678

ilk_disable_display_irq(display, bit);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1679

spin_unlock_irqrestore(&display->irq.lock, irqflags);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1685

struct intel_display *display = to_intel_display(intel_crtc);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1698

intel_de_rmw(display, DSI_INTR_MASK_REG(port), DSI_TE_EVENT, enable ? 0 : DSI_TE_EVENT);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1700

intel_de_rmw(display, DSI_INTR_IDENT_REG(port), 0, 0);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1707

struct intel_display *display =

sys/dev/pci/drm/i915/display/intel_display_irq.c

1708

container_of(work, typeof(*display), irq.vblank_notify_work);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1709

int vblank_enable_count = READ_ONCE(display->irq.vblank_enable_count);

sys/dev/pci/drm/i915/display/intel_display_irq.c

171

void bdw_update_port_irq(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1711

intel_psr_notify_vblank_enable_disable(display, vblank_enable_count);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1717

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1724

if (crtc->vblank_psr_notify && display->irq.vblank_enable_count++ == 0)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1725

schedule_work(&display->irq.vblank_notify_work);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1727

spin_lock_irqsave(&display->irq.lock, irqflags);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1728

bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_VBLANK);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1729

spin_unlock_irqrestore(&display->irq.lock, irqflags);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1734

if (HAS_PSR(display))

sys/dev/pci/drm/i915/display/intel_display_irq.c

174

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1743

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1750

spin_lock_irqsave(&display->irq.lock, irqflags);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1751

bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_VBLANK);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1752

spin_unlock_irqrestore(&display->irq.lock, irqflags);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1754

if (crtc->vblank_psr_notify && --display->irq.vblank_enable_count == 0)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1755

schedule_work(&display->irq.vblank_notify_work);

sys/dev/pci/drm/i915/display/intel_display_irq.c

178

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1797

static void vlv_page_table_error_irq_ack(struct intel_display *display, u32 *dpinvgtt)

sys/dev/pci/drm/i915/display/intel_display_irq.c

180

drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1801

tmp = intel_de_read(display, DPINVGTT);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1817

intel_de_write(display, DPINVGTT, status);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1818

intel_de_write(display, DPINVGTT, enable << 16);

sys/dev/pci/drm/i915/display/intel_display_irq.c

182

if (drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv)))

sys/dev/pci/drm/i915/display/intel_display_irq.c

1821

static void vlv_page_table_error_irq_handler(struct intel_display *display, u32 dpinvgtt)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1825

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

1830

intel_pipe_fault_irq_handler(display, vlv_pipe_fault_handlers,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1835

void vlv_display_error_irq_ack(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1840

*eir = intel_de_read(display, VLV_EIR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1843

vlv_page_table_error_irq_ack(display, dpinvgtt);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1845

intel_de_write(display, VLV_EIR, *eir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

185

old_val = intel_de_read(display, GEN8_DE_PORT_IMR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1852

emr = intel_de_read(display, VLV_EMR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1853

intel_de_write(display, VLV_EMR, 0xffffffff);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1854

intel_de_write(display, VLV_EMR, emr);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1857

void vlv_display_error_irq_handler(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1860

drm_dbg(display->drm, "Master Error, EIR 0x%08x\n", eir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1863

vlv_page_table_error_irq_handler(display, dpinvgtt);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1866

static void _vlv_display_irq_reset(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1868

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1870

if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1871

intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1873

intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_VLV);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1875

gen2_error_reset(to_intel_uncore(display->drm),

sys/dev/pci/drm/i915/display/intel_display_irq.c

1878

i915_hotplug_interrupt_update_locked(display, 0xffffffff, 0);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1879

intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1881

i9xx_pipestat_irq_reset(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1883

intel_display_irq_regs_reset(display, VLV_IRQ_REGS);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1887

void vlv_display_irq_reset(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1889

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1890

if (display->irq.vlv_display_irqs_enabled)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1891

_vlv_display_irq_reset(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1892

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1895

void i9xx_display_irq_reset(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1897

if (HAS_HOTPLUG(display)) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

1898

i915_hotplug_interrupt_update(display, 0xffffffff, 0);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1899

intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1902

i9xx_pipestat_irq_reset(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1905

void i915_display_irq_postinstall(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1911

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1912

i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1913

i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1914

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1916

i915_enable_asle_pipestat(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1919

void i965_display_irq_postinstall(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

192

intel_de_write(display, GEN8_DE_PORT_IMR, new_val);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1925

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1926

i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1927

i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1928

i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1929

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

193

intel_de_posting_read(display, GEN8_DE_PORT_IMR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1931

i915_enable_asle_pipestat(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1940

static void _vlv_display_irq_postinstall(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1942

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1947

if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1948

intel_de_write(display, DPINVGTT,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1952

intel_de_write(display, DPINVGTT,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1956

gen2_error_init(to_intel_uncore(display->drm),

sys/dev/pci/drm/i915/display/intel_display_irq.c

1961

i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1962

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1963

i915_enable_pipestat(display, pipe, pipestat_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1972

if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1976

drm_WARN_ON(display->drm, dev_priv->irq_mask != ~0u);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1980

intel_display_irq_regs_init(display, VLV_IRQ_REGS, dev_priv->irq_mask, enable_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1983

void vlv_display_irq_postinstall(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1985

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1986

if (display->irq.vlv_display_irqs_enabled)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1987

_vlv_display_irq_postinstall(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1988

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1991

void ibx_display_irq_reset(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1993

if (HAS_PCH_NOP(display))

sys/dev/pci/drm/i915/display/intel_display_irq.c

1996

gen2_irq_reset(to_intel_uncore(display->drm), SDE_IRQ_REGS);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1998

if (HAS_PCH_CPT(display) || HAS_PCH_LPT(display))

sys/dev/pci/drm/i915/display/intel_display_irq.c

1999

intel_de_write(display, SERR_INT, 0xffffffff);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2002

void gen8_display_irq_reset(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2006

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_irq.c

2009

intel_de_write(display, EDP_PSR_IMR, 0xffffffff);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2010

intel_de_write(display, EDP_PSR_IIR, 0xffffffff);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2012

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2013

if (intel_display_power_is_enabled(display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

2015

intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe));

sys/dev/pci/drm/i915/display/intel_display_irq.c

2017

intel_display_irq_regs_reset(display, GEN8_DE_PORT_IRQ_REGS);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2018

intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2020

if (HAS_PCH_SPLIT(display))

sys/dev/pci/drm/i915/display/intel_display_irq.c

2021

ibx_display_irq_reset(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2024

void gen11_display_irq_reset(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2030

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_irq.c

2033

intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2035

if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

2038

for_each_cpu_transcoder_masked(display, trans, trans_mask) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

204

static void bdw_update_pipe_irq(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

2042

if (!intel_display_power_is_enabled(display, domain))

sys/dev/pci/drm/i915/display/intel_display_irq.c

2045

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

2046

TRANS_PSR_IMR(display, trans),

sys/dev/pci/drm/i915/display/intel_display_irq.c

2048

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

2049

TRANS_PSR_IIR(display, trans),

sys/dev/pci/drm/i915/display/intel_display_irq.c

2053

intel_de_write(display, EDP_PSR_IMR, 0xffffffff);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2054

intel_de_write(display, EDP_PSR_IIR, 0xffffffff);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2057

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2058

if (intel_display_power_is_enabled(display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

2060

intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe));

sys/dev/pci/drm/i915/display/intel_display_irq.c

2062

intel_display_irq_regs_reset(display, GEN8_DE_PORT_IRQ_REGS);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2063

intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2065

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2066

intel_display_irq_regs_reset(display, PICAINTERRUPT_IRQ_REGS);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2068

intel_display_irq_regs_reset(display, GEN11_DE_HPD_IRQ_REGS);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2070

if (INTEL_PCH_TYPE(display) >= PCH_ICP)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2071

intel_display_irq_regs_reset(display, SDE_IRQ_REGS);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2074

void gen8_irq_power_well_post_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

2077

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2079

gen8_de_pipe_flip_done_mask(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

208

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2082

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2085

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2089

for_each_pipe_masked(display, pipe, pipe_mask)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2090

intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe),

sys/dev/pci/drm/i915/display/intel_display_irq.c

2091

display->irq.de_irq_mask[pipe],

sys/dev/pci/drm/i915/display/intel_display_irq.c

2092

~display->irq.de_irq_mask[pipe] | extra_ier);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2094

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2097

void gen8_irq_power_well_pre_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

2100

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2103

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2106

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

211

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2110

for_each_pipe_masked(display, pipe, pipe_mask)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2111

intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe));

sys/dev/pci/drm/i915/display/intel_display_irq.c

2113

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

213

drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2130

static void ibx_irq_postinstall(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2134

if (HAS_PCH_NOP(display))

sys/dev/pci/drm/i915/display/intel_display_irq.c

2137

if (HAS_PCH_IBX(display))

sys/dev/pci/drm/i915/display/intel_display_irq.c

2139

else if (HAS_PCH_CPT(display) || HAS_PCH_LPT(display))

sys/dev/pci/drm/i915/display/intel_display_irq.c

2144

intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2147

void valleyview_enable_display_irqs(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2149

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_irq.c

215

if (drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv)))

sys/dev/pci/drm/i915/display/intel_display_irq.c

2151

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2153

if (display->irq.vlv_display_irqs_enabled)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2156

display->irq.vlv_display_irqs_enabled = true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2159

_vlv_display_irq_reset(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2160

_vlv_display_irq_postinstall(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2164

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2167

void valleyview_disable_display_irqs(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2169

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2171

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2173

if (!display->irq.vlv_display_irqs_enabled)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2176

display->irq.vlv_display_irqs_enabled = false;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2179

_vlv_display_irq_reset(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

218

new_val = display->irq.de_irq_mask[pipe];

sys/dev/pci/drm/i915/display/intel_display_irq.c

2181

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2184

void ilk_de_irq_postinstall(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2186

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2190

if (DISPLAY_VER(display) >= 7) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

2211

if (display->platform.haswell) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

2212

intel_display_irq_regs_assert_irr_is_zero(display, EDP_PSR_IIR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2216

if (display->platform.ironlake && display->platform.mobile)

sys/dev/pci/drm/i915/display/intel_display_irq.c

222

if (new_val != display->irq.de_irq_mask[pipe]) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

2221

ibx_irq_postinstall(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2223

intel_display_irq_regs_init(display, DE_IRQ_REGS, i915->irq_mask,

sys/dev/pci/drm/i915/display/intel_display_irq.c

2227

static void mtp_irq_postinstall(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2228

static void icp_irq_postinstall(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

223

display->irq.de_irq_mask[pipe] = new_val;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2230

void gen8_de_irq_postinstall(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2232

u32 de_pipe_masked = gen8_de_pipe_fault_mask(display) |

sys/dev/pci/drm/i915/display/intel_display_irq.c

2235

u32 de_port_masked = gen8_de_port_aux_mask(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

224

intel_de_write(display, GEN8_DE_PIPE_IMR(pipe), display->irq.de_irq_mask[pipe]);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2242

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_irq.c

2245

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2246

mtp_irq_postinstall(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2247

else if (INTEL_PCH_TYPE(display) >= PCH_ICP)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2248

icp_irq_postinstall(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2249

else if (HAS_PCH_SPLIT(display))

sys/dev/pci/drm/i915/display/intel_display_irq.c

225

intel_de_posting_read(display, GEN8_DE_PIPE_IMR(pipe));

sys/dev/pci/drm/i915/display/intel_display_irq.c

2250

ibx_irq_postinstall(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2252

if (DISPLAY_VER(display) < 11)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2255

if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2258

if (DISPLAY_VER(display) >= 14) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

2261

} else if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

2264

if (intel_bios_is_dsi_present(display, &port))

sys/dev/pci/drm/i915/display/intel_display_irq.c

2268

if (HAS_DBUF_OVERLAP_DETECTION(display))

sys/dev/pci/drm/i915/display/intel_display_irq.c

2271

if (HAS_DSB(display))

sys/dev/pci/drm/i915/display/intel_display_irq.c

2277

if (DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2282

gen8_de_pipe_flip_done_mask(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2285

if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2287

else if (display->platform.broadwell)

sys/dev/pci/drm/i915/display/intel_display_irq.c

229

void bdw_enable_pipe_irq(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

2290

if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

2293

for_each_cpu_transcoder_masked(display, trans, trans_mask) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

2297

if (!intel_display_power_is_enabled(display, domain))

sys/dev/pci/drm/i915/display/intel_display_irq.c

2300

intel_display_irq_regs_assert_irr_is_zero(display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

2301

TRANS_PSR_IIR(display, trans));

sys/dev/pci/drm/i915/display/intel_display_irq.c

2304

intel_display_irq_regs_assert_irr_is_zero(display, EDP_PSR_IIR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2307

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

2308

display->irq.de_irq_mask[pipe] = ~de_pipe_masked;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2310

if (intel_display_power_is_enabled(display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

2312

intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe),

sys/dev/pci/drm/i915/display/intel_display_irq.c

2313

display->irq.de_irq_mask[pipe],

sys/dev/pci/drm/i915/display/intel_display_irq.c

2317

intel_display_irq_regs_init(display, GEN8_DE_PORT_IRQ_REGS, ~de_port_masked,

sys/dev/pci/drm/i915/display/intel_display_irq.c

2319

intel_display_irq_regs_init(display, GEN8_DE_MISC_IRQ_REGS, ~de_misc_masked,

sys/dev/pci/drm/i915/display/intel_display_irq.c

232

bdw_update_pipe_irq(display, pipe, bits, bits);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2322

if (IS_DISPLAY_VER(display, 11, 13)) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

2327

intel_display_irq_regs_init(display, GEN11_DE_HPD_IRQ_REGS, ~de_hpd_masked,

sys/dev/pci/drm/i915/display/intel_display_irq.c

2332

static void mtp_irq_postinstall(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2339

intel_display_irq_regs_init(display, PICAINTERRUPT_IRQ_REGS, ~de_hpd_mask,

sys/dev/pci/drm/i915/display/intel_display_irq.c

2342

intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~sde_mask, 0xffffffff);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2345

static void icp_irq_postinstall(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2349

intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);

sys/dev/pci/drm/i915/display/intel_display_irq.c

235

void bdw_disable_pipe_irq(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

2352

void gen11_de_irq_postinstall(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2354

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_irq.c

2357

gen8_de_irq_postinstall(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2359

intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2362

void dg1_de_irq_postinstall(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2364

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_irq.c

2367

gen8_de_irq_postinstall(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2368

intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2371

void intel_display_irq_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2373

mtx_init(&display->irq.lock, IPL_TTY);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2375

display->drm->vblank_disable_immediate = true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2377

intel_hotplug_irq_init(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2379

INIT_WORK(&display->irq.vblank_notify_work,

sys/dev/pci/drm/i915/display/intel_display_irq.c

238

bdw_update_pipe_irq(display, pipe, bits, 0);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2388

intel_display_irq_snapshot_capture(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2396

if (DISPLAY_VER(display) >= 6 && DISPLAY_VER(display) < 20 && !HAS_GMCH(display))

sys/dev/pci/drm/i915/display/intel_display_irq.c

2397

snapshot->derrmr = intel_de_read(display, DERRMR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

247

void ibx_display_interrupt_update(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

251

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_irq.c

252

u32 sdeimr = intel_de_read(display, SDEIMR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

257

drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.c

259

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

261

if (drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv)))

sys/dev/pci/drm/i915/display/intel_display_irq.c

264

intel_de_write(display, SDEIMR, sdeimr);

sys/dev/pci/drm/i915/display/intel_display_irq.c

265

intel_de_posting_read(display, SDEIMR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

268

void ibx_enable_display_interrupt(struct intel_display *display, u32 bits)

sys/dev/pci/drm/i915/display/intel_display_irq.c

270

ibx_display_interrupt_update(display, bits, bits);

sys/dev/pci/drm/i915/display/intel_display_irq.c

273

void ibx_disable_display_interrupt(struct intel_display *display, u32 bits)

sys/dev/pci/drm/i915/display/intel_display_irq.c

275

ibx_display_interrupt_update(display, bits, 0);

sys/dev/pci/drm/i915/display/intel_display_irq.c

278

u32 i915_pipestat_enable_mask(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

281

u32 status_mask = display->irq.pipestat_irq_mask[pipe];

sys/dev/pci/drm/i915/display/intel_display_irq.c

284

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

286

if (DISPLAY_VER(display) < 5)

sys/dev/pci/drm/i915/display/intel_display_irq.c

293

if (drm_WARN_ON_ONCE(display->drm,

sys/dev/pci/drm/i915/display/intel_display_irq.c

300

if (drm_WARN_ON_ONCE(display->drm,

sys/dev/pci/drm/i915/display/intel_display_irq.c

313

drm_WARN_ONCE(display->drm,

sys/dev/pci/drm/i915/display/intel_display_irq.c

322

void i915_enable_pipestat(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

325

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_irq.c

326

i915_reg_t reg = PIPESTAT(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

329

drm_WARN_ONCE(display->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,

sys/dev/pci/drm/i915/display/intel_display_irq.c

333

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

334

drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv));

sys/dev/pci/drm/i915/display/intel_display_irq.c

336

if ((display->irq.pipestat_irq_mask[pipe] & status_mask) == status_mask)

sys/dev/pci/drm/i915/display/intel_display_irq.c

339

display->irq.pipestat_irq_mask[pipe] |= status_mask;

sys/dev/pci/drm/i915/display/intel_display_irq.c

340

enable_mask = i915_pipestat_enable_mask(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

342

intel_de_write(display, reg, enable_mask | status_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.c

343

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_display_irq.c

346

void i915_disable_pipestat(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

349

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_irq.c

350

i915_reg_t reg = PIPESTAT(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

353

drm_WARN_ONCE(display->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,

sys/dev/pci/drm/i915/display/intel_display_irq.c

357

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

358

drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv));

sys/dev/pci/drm/i915/display/intel_display_irq.c

36

intel_display_irq_regs_init(struct intel_display *display, struct i915_irq_regs regs,

sys/dev/pci/drm/i915/display/intel_display_irq.c

360

if ((display->irq.pipestat_irq_mask[pipe] & status_mask) == 0)

sys/dev/pci/drm/i915/display/intel_display_irq.c

363

display->irq.pipestat_irq_mask[pipe] &= ~status_mask;

sys/dev/pci/drm/i915/display/intel_display_irq.c

364

enable_mask = i915_pipestat_enable_mask(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

366

intel_de_write(display, reg, enable_mask | status_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.c

367

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_display_irq.c

370

static bool i915_has_legacy_blc_interrupt(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

372

if (display->platform.i85x)

sys/dev/pci/drm/i915/display/intel_display_irq.c

375

if (display->platform.pineview)

sys/dev/pci/drm/i915/display/intel_display_irq.c

378

return IS_DISPLAY_VER(display, 3, 4) && display->platform.mobile;

sys/dev/pci/drm/i915/display/intel_display_irq.c

382

static void i915_enable_asle_pipestat(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

384

if (!intel_opregion_asle_present(display))

sys/dev/pci/drm/i915/display/intel_display_irq.c

387

if (!i915_has_legacy_blc_interrupt(display))

sys/dev/pci/drm/i915/display/intel_display_irq.c

39

intel_dmc_wl_get(display, regs.imr);

sys/dev/pci/drm/i915/display/intel_display_irq.c

390

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

392

i915_enable_pipestat(display, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);

sys/dev/pci/drm/i915/display/intel_display_irq.c

393

if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/intel_display_irq.c

394

i915_enable_pipestat(display, PIPE_A,

sys/dev/pci/drm/i915/display/intel_display_irq.c

397

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

40

intel_dmc_wl_get(display, regs.ier);

sys/dev/pci/drm/i915/display/intel_display_irq.c

401

static void display_pipe_crc_irq_handler(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

407

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

41

intel_dmc_wl_get(display, regs.iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

423

(DISPLAY_VER(display) >= 8 && pipe_crc->skipped == 1)) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

43

gen2_irq_init(to_intel_uncore(display->drm), regs, imr_val, ier_val);

sys/dev/pci/drm/i915/display/intel_display_irq.c

436

display_pipe_crc_irq_handler(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

443

static void flip_done_handler(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

446

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

448

spin_lock(&display->drm->event_lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

45

intel_dmc_wl_put(display, regs.iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

456

spin_unlock(&display->drm->event_lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

459

static void hsw_pipe_crc_irq_handler(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

46

intel_dmc_wl_put(display, regs.ier);

sys/dev/pci/drm/i915/display/intel_display_irq.c

462

display_pipe_crc_irq_handler(display, pipe,

sys/dev/pci/drm/i915/display/intel_display_irq.c

463

intel_de_read(display, PIPE_CRC_RES_HSW(pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

467

static void ivb_pipe_crc_irq_handler(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

47

intel_dmc_wl_put(display, regs.imr);

sys/dev/pci/drm/i915/display/intel_display_irq.c

470

display_pipe_crc_irq_handler(display, pipe,

sys/dev/pci/drm/i915/display/intel_display_irq.c

471

intel_de_read(display, PIPE_CRC_RES_1_IVB(pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

472

intel_de_read(display, PIPE_CRC_RES_2_IVB(pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

473

intel_de_read(display, PIPE_CRC_RES_3_IVB(pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

474

intel_de_read(display, PIPE_CRC_RES_4_IVB(pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

475

intel_de_read(display, PIPE_CRC_RES_5_IVB(pipe)));

sys/dev/pci/drm/i915/display/intel_display_irq.c

478

static void i9xx_pipe_crc_irq_handler(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

483

if (DISPLAY_VER(display) >= 3)

sys/dev/pci/drm/i915/display/intel_display_irq.c

484

res1 = intel_de_read(display, PIPE_CRC_RES_RES1_I915(display, pipe));

sys/dev/pci/drm/i915/display/intel_display_irq.c

488

if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_display_irq.c

489

res2 = intel_de_read(display, PIPE_CRC_RES_RES2_G4X(display, pipe));

sys/dev/pci/drm/i915/display/intel_display_irq.c

493

display_pipe_crc_irq_handler(display, pipe,

sys/dev/pci/drm/i915/display/intel_display_irq.c

494

intel_de_read(display, PIPE_CRC_RES_RED(display, pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

495

intel_de_read(display, PIPE_CRC_RES_GREEN(display, pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

496

intel_de_read(display, PIPE_CRC_RES_BLUE(display, pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

500

static void i9xx_pipestat_irq_reset(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

504

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

505

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

506

PIPESTAT(display, pipe),

sys/dev/pci/drm/i915/display/intel_display_irq.c

509

display->irq.pipestat_irq_mask[pipe] = 0;

sys/dev/pci/drm/i915/display/intel_display_irq.c

51

intel_display_irq_regs_reset(struct intel_display *display, struct i915_irq_regs regs)

sys/dev/pci/drm/i915/display/intel_display_irq.c

513

void i9xx_pipestat_irq_ack(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

518

spin_lock(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

520

if ((display->platform.valleyview || display->platform.cherryview) &&

sys/dev/pci/drm/i915/display/intel_display_irq.c

521

!display->irq.vlv_display_irqs_enabled) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

522

spin_unlock(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

526

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

53

intel_dmc_wl_get(display, regs.imr);

sys/dev/pci/drm/i915/display/intel_display_irq.c

54

intel_dmc_wl_get(display, regs.ier);

sys/dev/pci/drm/i915/display/intel_display_irq.c

55

intel_dmc_wl_get(display, regs.iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

554

status_mask |= display->irq.pipestat_irq_mask[pipe];

sys/dev/pci/drm/i915/display/intel_display_irq.c

559

reg = PIPESTAT(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

560

pipe_stats[pipe] = intel_de_read(display, reg) & status_mask;

sys/dev/pci/drm/i915/display/intel_display_irq.c

561

enable_mask = i915_pipestat_enable_mask(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

57

gen2_irq_reset(to_intel_uncore(display->drm), regs);

sys/dev/pci/drm/i915/display/intel_display_irq.c

573

intel_de_write(display, reg, pipe_stats[pipe]);

sys/dev/pci/drm/i915/display/intel_display_irq.c

574

intel_de_write(display, reg, enable_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.c

577

spin_unlock(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_irq.c

580

void i915_pipestat_irq_handler(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

586

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

588

intel_handle_vblank(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

59

intel_dmc_wl_put(display, regs.iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

594

i9xx_pipe_crc_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

597

intel_cpu_fifo_underrun_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

60

intel_dmc_wl_put(display, regs.ier);

sys/dev/pci/drm/i915/display/intel_display_irq.c

601

intel_opregion_asle_intr(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

604

void i965_pipestat_irq_handler(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

61

intel_dmc_wl_put(display, regs.imr);

sys/dev/pci/drm/i915/display/intel_display_irq.c

610

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

612

intel_handle_vblank(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

618

i9xx_pipe_crc_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

621

intel_cpu_fifo_underrun_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

625

intel_opregion_asle_intr(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

628

intel_gmbus_irq_handler(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

631

void valleyview_pipestat_irq_handler(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.c

636

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

638

intel_handle_vblank(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

641

flip_done_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

644

i9xx_pipe_crc_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

647

intel_cpu_fifo_underrun_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

65

intel_display_irq_regs_assert_irr_is_zero(struct intel_display *display, i915_reg_t reg)

sys/dev/pci/drm/i915/display/intel_display_irq.c

651

intel_gmbus_irq_handler(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

654

static void ibx_irq_handler(struct intel_display *display, u32 pch_iir)

sys/dev/pci/drm/i915/display/intel_display_irq.c

659

ibx_hpd_irq_handler(display, hotplug_trigger);

sys/dev/pci/drm/i915/display/intel_display_irq.c

664

drm_dbg(display->drm, "PCH audio power change on port %d\n",

sys/dev/pci/drm/i915/display/intel_display_irq.c

669

intel_dp_aux_irq_handler(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

67

intel_dmc_wl_get(display, reg);

sys/dev/pci/drm/i915/display/intel_display_irq.c

672

intel_gmbus_irq_handler(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

675

drm_dbg(display->drm, "PCH HDCP audio interrupt\n");

sys/dev/pci/drm/i915/display/intel_display_irq.c

678

drm_dbg(display->drm, "PCH transcoder audio interrupt\n");

sys/dev/pci/drm/i915/display/intel_display_irq.c

681

drm_err(display->drm, "PCH poison interrupt\n");

sys/dev/pci/drm/i915/display/intel_display_irq.c

684

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

685

drm_dbg(display->drm, " pipe %c FDI IIR: 0x%08x\n",

sys/dev/pci/drm/i915/display/intel_display_irq.c

687

intel_de_read(display, FDI_RX_IIR(pipe)));

sys/dev/pci/drm/i915/display/intel_display_irq.c

69

gen2_assert_iir_is_zero(to_intel_uncore(display->drm), reg);

sys/dev/pci/drm/i915/display/intel_display_irq.c

691

drm_dbg(display->drm, "PCH transcoder CRC done interrupt\n");

sys/dev/pci/drm/i915/display/intel_display_irq.c

694

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_display_irq.c

698

intel_pch_fifo_underrun_irq_handler(display, PIPE_A);

sys/dev/pci/drm/i915/display/intel_display_irq.c

701

intel_pch_fifo_underrun_irq_handler(display, PIPE_B);

sys/dev/pci/drm/i915/display/intel_display_irq.c

71

intel_dmc_wl_put(display, reg);

sys/dev/pci/drm/i915/display/intel_display_irq.c

737

static void ivb_err_int_handler(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

739

u32 err_int = intel_de_read(display, GEN7_ERR_INT);

sys/dev/pci/drm/i915/display/intel_display_irq.c

743

drm_err(display->drm, "Poison interrupt\n");

sys/dev/pci/drm/i915/display/intel_display_irq.c

746

drm_err_ratelimited(display->drm, "Invalid GTT PTE\n");

sys/dev/pci/drm/i915/display/intel_display_irq.c

749

drm_err_ratelimited(display->drm, "Invalid PTE data\n");

sys/dev/pci/drm/i915/display/intel_display_irq.c

751

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

755

intel_cpu_fifo_underrun_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

758

if (display->platform.ivybridge)

sys/dev/pci/drm/i915/display/intel_display_irq.c

759

ivb_pipe_crc_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

761

hsw_pipe_crc_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

766

intel_pipe_fault_irq_handler(display, ivb_pipe_fault_handlers,

sys/dev/pci/drm/i915/display/intel_display_irq.c

770

intel_de_write(display, GEN7_ERR_INT, err_int);

sys/dev/pci/drm/i915/display/intel_display_irq.c

773

static void cpt_serr_int_handler(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

775

u32 serr_int = intel_de_read(display, SERR_INT);

sys/dev/pci/drm/i915/display/intel_display_irq.c

779

drm_err(display->drm, "PCH poison interrupt\n");

sys/dev/pci/drm/i915/display/intel_display_irq.c

781

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

783

intel_pch_fifo_underrun_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

785

intel_de_write(display, SERR_INT, serr_int);

sys/dev/pci/drm/i915/display/intel_display_irq.c

788

static void cpt_irq_handler(struct intel_display *display, u32 pch_iir)

sys/dev/pci/drm/i915/display/intel_display_irq.c

793

ibx_hpd_irq_handler(display, hotplug_trigger);

sys/dev/pci/drm/i915/display/intel_display_irq.c

798

drm_dbg(display->drm, "PCH audio power change on port %c\n",

sys/dev/pci/drm/i915/display/intel_display_irq.c

803

intel_dp_aux_irq_handler(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

806

intel_gmbus_irq_handler(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

809

drm_dbg(display->drm, "Audio CP request interrupt\n");

sys/dev/pci/drm/i915/display/intel_display_irq.c

812

drm_dbg(display->drm, "Audio CP change interrupt\n");

sys/dev/pci/drm/i915/display/intel_display_irq.c

815

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

816

drm_dbg(display->drm, " pipe %c FDI IIR: 0x%08x\n",

sys/dev/pci/drm/i915/display/intel_display_irq.c

818

intel_de_read(display, FDI_RX_IIR(pipe)));

sys/dev/pci/drm/i915/display/intel_display_irq.c

82

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_display_irq.c

822

cpt_serr_int_handler(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

851

static void ilk_gtt_fault_irq_handler(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

856

gtt_fault = intel_de_read(display, ILK_GTT_FAULT);

sys/dev/pci/drm/i915/display/intel_display_irq.c

857

intel_de_write(display, ILK_GTT_FAULT, gtt_fault);

sys/dev/pci/drm/i915/display/intel_display_irq.c

860

drm_err_ratelimited(display->drm, "Invalid GTT PTE\n");

sys/dev/pci/drm/i915/display/intel_display_irq.c

863

drm_err_ratelimited(display->drm, "Invalid PTE data\n");

sys/dev/pci/drm/i915/display/intel_display_irq.c

865

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

870

intel_pipe_fault_irq_handler(display, ilk_pipe_fault_handlers,

sys/dev/pci/drm/i915/display/intel_display_irq.c

875

void ilk_display_irq_handler(struct intel_display *display, u32 de_iir)

sys/dev/pci/drm/i915/display/intel_display_irq.c

881

ilk_hpd_irq_handler(display, hotplug_trigger);

sys/dev/pci/drm/i915/display/intel_display_irq.c

884

intel_dp_aux_irq_handler(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

887

intel_opregion_asle_intr(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

890

drm_err(display->drm, "Poison interrupt\n");

sys/dev/pci/drm/i915/display/intel_display_irq.c

893

ilk_gtt_fault_irq_handler(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

895

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

897

intel_handle_vblank(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

900

flip_done_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

903

intel_cpu_fifo_underrun_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

906

i9xx_pipe_crc_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

911

u32 pch_iir = intel_de_read(display, SDEIIR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

913

if (HAS_PCH_CPT(display))

sys/dev/pci/drm/i915/display/intel_display_irq.c

914

cpt_irq_handler(display, pch_iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

916

ibx_irq_handler(display, pch_iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

919

intel_de_write(display, SDEIIR, pch_iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

92

drm_err_ratelimited(display->drm,

sys/dev/pci/drm/i915/display/intel_display_irq.c

922

if (DISPLAY_VER(display) == 5 && de_iir & DE_PCU_EVENT)

sys/dev/pci/drm/i915/display/intel_display_irq.c

923

ilk_display_rps_irq_handler(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

926

void ivb_display_irq_handler(struct intel_display *display, u32 de_iir)

sys/dev/pci/drm/i915/display/intel_display_irq.c

932

ilk_hpd_irq_handler(display, hotplug_trigger);

sys/dev/pci/drm/i915/display/intel_display_irq.c

935

ivb_err_int_handler(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

940

for_each_intel_encoder_with_psr(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

944

psr_iir = intel_de_rmw(display, EDP_PSR_IIR, 0, 0);

sys/dev/pci/drm/i915/display/intel_display_irq.c

951

intel_dp_aux_irq_handler(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

954

intel_opregion_asle_intr(display);

sys/dev/pci/drm/i915/display/intel_display_irq.c

956

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

958

intel_handle_vblank(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

961

flip_done_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

965

if (!HAS_PCH_NOP(display) && (de_iir & DE_PCH_EVENT_IVB)) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

966

u32 pch_iir = intel_de_read(display, SDEIIR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

968

cpt_irq_handler(display, pch_iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

971

intel_de_write(display, SDEIIR, pch_iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

975

static u32 gen8_de_port_aux_mask(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_irq.c

979

if (DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/intel_display_irq.c

981

else if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_display_irq.c

984

else if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/intel_display_irq.c

994

else if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_display_irq.h

19

void valleyview_enable_display_irqs(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_irq.h

20

void valleyview_disable_display_irqs(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_irq.h

22

void ilk_update_display_irq(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.h

24

void ilk_enable_display_irq(struct intel_display *display, u32 bits);

sys/dev/pci/drm/i915/display/intel_display_irq.h

25

void ilk_disable_display_irq(struct intel_display *display, u32 bits);

sys/dev/pci/drm/i915/display/intel_display_irq.h

27

void bdw_update_port_irq(struct intel_display *display, u32 interrupt_mask, u32 enabled_irq_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.h

28

void bdw_enable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits);

sys/dev/pci/drm/i915/display/intel_display_irq.h

29

void bdw_disable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits);

sys/dev/pci/drm/i915/display/intel_display_irq.h

31

void ibx_display_interrupt_update(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_irq.h

33

void ibx_enable_display_interrupt(struct intel_display *display, u32 bits);

sys/dev/pci/drm/i915/display/intel_display_irq.h

34

void ibx_disable_display_interrupt(struct intel_display *display, u32 bits);

sys/dev/pci/drm/i915/display/intel_display_irq.h

36

void gen8_irq_power_well_post_enable(struct intel_display *display, u8 pipe_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.h

37

void gen8_irq_power_well_pre_disable(struct intel_display *display, u8 pipe_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.h

50

void ivb_display_irq_handler(struct intel_display *display, u32 de_iir);

sys/dev/pci/drm/i915/display/intel_display_irq.h

51

void ilk_display_irq_handler(struct intel_display *display, u32 de_iir);

sys/dev/pci/drm/i915/display/intel_display_irq.h

52

void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl);

sys/dev/pci/drm/i915/display/intel_display_irq.h

53

void gen11_display_irq_handler(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_irq.h

55

u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);

sys/dev/pci/drm/i915/display/intel_display_irq.h

56

void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);

sys/dev/pci/drm/i915/display/intel_display_irq.h

58

void i9xx_display_irq_reset(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_irq.h

59

void ibx_display_irq_reset(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_irq.h

60

void vlv_display_irq_reset(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_irq.h

61

void gen8_display_irq_reset(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_irq.h

62

void gen11_display_irq_reset(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_irq.h

64

void i915_display_irq_postinstall(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_irq.h

65

void i965_display_irq_postinstall(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_irq.h

66

void vlv_display_irq_postinstall(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_irq.h

67

void ilk_de_irq_postinstall(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_irq.h

68

void gen8_de_irq_postinstall(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_irq.h

69

void gen11_de_irq_postinstall(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_irq.h

70

void dg1_de_irq_postinstall(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_irq.h

72

u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.h

73

void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.h

74

void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.h

76

void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);

sys/dev/pci/drm/i915/display/intel_display_irq.h

78

void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);

sys/dev/pci/drm/i915/display/intel_display_irq.h

79

void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);

sys/dev/pci/drm/i915/display/intel_display_irq.h

80

void valleyview_pipestat_irq_handler(struct intel_display *display, u32 pipe_stats[I915_MAX_PIPES]);

sys/dev/pci/drm/i915/display/intel_display_irq.h

82

void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt);

sys/dev/pci/drm/i915/display/intel_display_irq.h

83

void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);

sys/dev/pci/drm/i915/display/intel_display_irq.h

85

void intel_display_irq_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_irq.h

87

void i915gm_irq_cstate_wa(struct intel_display *display, bool enable);

sys/dev/pci/drm/i915/display/intel_display_irq.h

89

struct intel_display_irq_snapshot *intel_display_irq_snapshot_capture(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1016

drm_dbg_kms(display->drm, "Allowed DC state mask %02x\n", mask);

sys/dev/pci/drm/i915/display/intel_display_power.c

1028

int intel_power_domains_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

1030

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

1032

display->params.disable_power_well =

sys/dev/pci/drm/i915/display/intel_display_power.c

1033

sanitize_disable_power_well_option(display->params.disable_power_well);

sys/dev/pci/drm/i915/display/intel_display_power.c

1035

get_allowed_dc_mask(display, display->params.enable_dc);

sys/dev/pci/drm/i915/display/intel_display_power.c

1038

sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6);

sys/dev/pci/drm/i915/display/intel_display_power.c

1054

void intel_power_domains_cleanup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

1056

intel_display_power_map_cleanup(&display->power.domains);

sys/dev/pci/drm/i915/display/intel_display_power.c

1059

static void intel_power_domains_sync_hw(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

1061

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

1065

for_each_power_well(display, power_well)

sys/dev/pci/drm/i915/display/intel_display_power.c

1066

intel_power_well_sync_hw(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power.c

1070

static void gen9_dbuf_slice_set(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

1076

intel_de_rmw(display, reg, DBUF_POWER_REQUEST,

sys/dev/pci/drm/i915/display/intel_display_power.c

1078

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_display_power.c

1081

state = intel_de_read(display, reg) & DBUF_POWER_STATE;

sys/dev/pci/drm/i915/display/intel_display_power.c

1082

drm_WARN(display->drm, enable != state,

sys/dev/pci/drm/i915/display/intel_display_power.c

1087

void gen9_dbuf_slices_update(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

1090

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

1091

u8 slice_mask = DISPLAY_INFO(display)->dbuf.slice_mask;

sys/dev/pci/drm/i915/display/intel_display_power.c

1094

drm_WARN(display->drm, req_slices & ~slice_mask,

sys/dev/pci/drm/i915/display/intel_display_power.c

1098

drm_dbg_kms(display->drm, "Updating dbuf slices to 0x%x\n",

sys/dev/pci/drm/i915/display/intel_display_power.c

1110

for_each_dbuf_slice(display, slice)

sys/dev/pci/drm/i915/display/intel_display_power.c

1111

gen9_dbuf_slice_set(display, slice, req_slices & BIT(slice));

sys/dev/pci/drm/i915/display/intel_display_power.c

1113

display->dbuf.enabled_slices = req_slices;

sys/dev/pci/drm/i915/display/intel_display_power.c

1118

static void gen9_dbuf_enable(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

1122

display->dbuf.enabled_slices = intel_enabled_dbuf_slices_mask(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1124

slices_mask = BIT(DBUF_S1) | display->dbuf.enabled_slices;

sys/dev/pci/drm/i915/display/intel_display_power.c

1126

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_display_power.c

1127

intel_pmdemand_program_dbuf(display, slices_mask);

sys/dev/pci/drm/i915/display/intel_display_power.c

1133

gen9_dbuf_slices_update(display, slices_mask);

sys/dev/pci/drm/i915/display/intel_display_power.c

1136

static void gen9_dbuf_disable(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

1138

gen9_dbuf_slices_update(display, 0);

sys/dev/pci/drm/i915/display/intel_display_power.c

1140

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_display_power.c

1141

intel_pmdemand_program_dbuf(display, 0);

sys/dev/pci/drm/i915/display/intel_display_power.c

1144

static void gen12_dbuf_slices_config(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

1148

for_each_dbuf_slice(display, slice)

sys/dev/pci/drm/i915/display/intel_display_power.c

1149

intel_de_rmw(display, DBUF_CTL_S(slice),

sys/dev/pci/drm/i915/display/intel_display_power.c

1154

static void icl_mbus_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

1156

unsigned long abox_regs = DISPLAY_INFO(display)->abox_mask;

sys/dev/pci/drm/i915/display/intel_display_power.c

1159

if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_display_power.c

1176

if (DISPLAY_VER(display) == 12)

sys/dev/pci/drm/i915/display/intel_display_power.c

1180

intel_de_rmw(display, MBUS_ABOX_CTL(i), mask, val);

sys/dev/pci/drm/i915/display/intel_display_power.c

1183

static void hsw_assert_cdclk(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

1185

u32 val = intel_de_read(display, LCPLL_CTL);

sys/dev/pci/drm/i915/display/intel_display_power.c

1194

drm_err(display->drm, "CDCLK source is not LCPLL\n");

sys/dev/pci/drm/i915/display/intel_display_power.c

1197

drm_err(display->drm, "LCPLL is disabled\n");

sys/dev/pci/drm/i915/display/intel_display_power.c

1200

drm_err(display->drm, "LCPLL not using non-SSC reference\n");

sys/dev/pci/drm/i915/display/intel_display_power.c

1203

static void assert_can_disable_lcpll(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

1205

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_power.c

1208

for_each_intel_crtc(display->drm, crtc)

sys/dev/pci/drm/i915/display/intel_display_power.c

1209

INTEL_DISPLAY_STATE_WARN(display, crtc->active,

sys/dev/pci/drm/i915/display/intel_display_power.c

1213

INTEL_DISPLAY_STATE_WARN(display, intel_de_read(display, HSW_PWR_WELL_CTL2),

sys/dev/pci/drm/i915/display/intel_display_power.c

1215

INTEL_DISPLAY_STATE_WARN(display,

sys/dev/pci/drm/i915/display/intel_display_power.c

1216

intel_de_read(display, SPLL_CTL) & SPLL_PLL_ENABLE,

sys/dev/pci/drm/i915/display/intel_display_power.c

1218

INTEL_DISPLAY_STATE_WARN(display,

sys/dev/pci/drm/i915/display/intel_display_power.c

1219

intel_de_read(display, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE,

sys/dev/pci/drm/i915/display/intel_display_power.c

1221

INTEL_DISPLAY_STATE_WARN(display,

sys/dev/pci/drm/i915/display/intel_display_power.c

1222

intel_de_read(display, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE,

sys/dev/pci/drm/i915/display/intel_display_power.c

1224

INTEL_DISPLAY_STATE_WARN(display,

sys/dev/pci/drm/i915/display/intel_display_power.c

1225

intel_de_read(display, PP_STATUS(display, 0)) & PP_ON,

sys/dev/pci/drm/i915/display/intel_display_power.c

1227

INTEL_DISPLAY_STATE_WARN(display,

sys/dev/pci/drm/i915/display/intel_display_power.c

1228

intel_de_read(display, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,

sys/dev/pci/drm/i915/display/intel_display_power.c

1230

if (display->platform.haswell)

sys/dev/pci/drm/i915/display/intel_display_power.c

1231

INTEL_DISPLAY_STATE_WARN(display,

sys/dev/pci/drm/i915/display/intel_display_power.c

1232

intel_de_read(display, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,

sys/dev/pci/drm/i915/display/intel_display_power.c

1234

INTEL_DISPLAY_STATE_WARN(display,

sys/dev/pci/drm/i915/display/intel_display_power.c

1235

intel_de_read(display, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,

sys/dev/pci/drm/i915/display/intel_display_power.c

1237

INTEL_DISPLAY_STATE_WARN(display,

sys/dev/pci/drm/i915/display/intel_display_power.c

1238

(intel_de_read(display, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM),

sys/dev/pci/drm/i915/display/intel_display_power.c

1240

INTEL_DISPLAY_STATE_WARN(display,

sys/dev/pci/drm/i915/display/intel_display_power.c

1241

intel_de_read(display, PCH_GTC_CTL) & PCH_GTC_ENABLE,

sys/dev/pci/drm/i915/display/intel_display_power.c

1250

INTEL_DISPLAY_STATE_WARN(display, intel_irqs_enabled(dev_priv),

sys/dev/pci/drm/i915/display/intel_display_power.c

1254

static u32 hsw_read_dcomp(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

1256

if (display->platform.haswell)

sys/dev/pci/drm/i915/display/intel_display_power.c

1257

return intel_de_read(display, D_COMP_HSW);

sys/dev/pci/drm/i915/display/intel_display_power.c

1259

return intel_de_read(display, D_COMP_BDW);

sys/dev/pci/drm/i915/display/intel_display_power.c

1262

static void hsw_write_dcomp(struct intel_display *display, u32 val)

sys/dev/pci/drm/i915/display/intel_display_power.c

1264

if (display->platform.haswell) {

sys/dev/pci/drm/i915/display/intel_display_power.c

1265

if (intel_pcode_write(display->drm, GEN6_PCODE_WRITE_D_COMP, val))

sys/dev/pci/drm/i915/display/intel_display_power.c

1266

drm_dbg_kms(display->drm, "Failed to write to D_COMP\n");

sys/dev/pci/drm/i915/display/intel_display_power.c

1268

intel_de_write(display, D_COMP_BDW, val);

sys/dev/pci/drm/i915/display/intel_display_power.c

1269

intel_de_posting_read(display, D_COMP_BDW);

sys/dev/pci/drm/i915/display/intel_display_power.c

1281

static void hsw_disable_lcpll(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

1287

assert_can_disable_lcpll(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1289

val = intel_de_read(display, LCPLL_CTL);

sys/dev/pci/drm/i915/display/intel_display_power.c

1293

intel_de_write(display, LCPLL_CTL, val);

sys/dev/pci/drm/i915/display/intel_display_power.c

1295

ret = intel_de_wait_custom(display, LCPLL_CTL,

sys/dev/pci/drm/i915/display/intel_display_power.c

1299

drm_err(display->drm, "Switching to FCLK failed\n");

sys/dev/pci/drm/i915/display/intel_display_power.c

1301

val = intel_de_read(display, LCPLL_CTL);

sys/dev/pci/drm/i915/display/intel_display_power.c

1305

intel_de_write(display, LCPLL_CTL, val);

sys/dev/pci/drm/i915/display/intel_display_power.c

1306

intel_de_posting_read(display, LCPLL_CTL);

sys/dev/pci/drm/i915/display/intel_display_power.c

1308

if (intel_de_wait_for_clear(display, LCPLL_CTL, LCPLL_PLL_LOCK, 1))

sys/dev/pci/drm/i915/display/intel_display_power.c

1309

drm_err(display->drm, "LCPLL still locked\n");

sys/dev/pci/drm/i915/display/intel_display_power.c

1311

val = hsw_read_dcomp(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1313

hsw_write_dcomp(display, val);

sys/dev/pci/drm/i915/display/intel_display_power.c

1316

ret = poll_timeout_us(val = hsw_read_dcomp(display),

sys/dev/pci/drm/i915/display/intel_display_power.c

1320

drm_err(display->drm, "D_COMP RCOMP still in progress\n");

sys/dev/pci/drm/i915/display/intel_display_power.c

1323

intel_de_rmw(display, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW);

sys/dev/pci/drm/i915/display/intel_display_power.c

1324

intel_de_posting_read(display, LCPLL_CTL);

sys/dev/pci/drm/i915/display/intel_display_power.c

1332

static void hsw_restore_lcpll(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

1334

struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_power.c

1338

val = intel_de_read(display, LCPLL_CTL);

sys/dev/pci/drm/i915/display/intel_display_power.c

1352

intel_de_write(display, LCPLL_CTL, val);

sys/dev/pci/drm/i915/display/intel_display_power.c

1353

intel_de_posting_read(display, LCPLL_CTL);

sys/dev/pci/drm/i915/display/intel_display_power.c

1356

val = hsw_read_dcomp(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1359

hsw_write_dcomp(display, val);

sys/dev/pci/drm/i915/display/intel_display_power.c

1361

val = intel_de_read(display, LCPLL_CTL);

sys/dev/pci/drm/i915/display/intel_display_power.c

1363

intel_de_write(display, LCPLL_CTL, val);

sys/dev/pci/drm/i915/display/intel_display_power.c

1365

if (intel_de_wait_for_set(display, LCPLL_CTL, LCPLL_PLL_LOCK, 5))

sys/dev/pci/drm/i915/display/intel_display_power.c

1366

drm_err(display->drm, "LCPLL not locked yet\n");

sys/dev/pci/drm/i915/display/intel_display_power.c

1369

intel_de_rmw(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0);

sys/dev/pci/drm/i915/display/intel_display_power.c

1371

ret = intel_de_wait_custom(display, LCPLL_CTL,

sys/dev/pci/drm/i915/display/intel_display_power.c

1375

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power.c

1381

intel_update_cdclk(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1382

intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");

sys/dev/pci/drm/i915/display/intel_display_power.c

1408

static void hsw_enable_pc8(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

1410

drm_dbg_kms(display->drm, "Enabling package C8+\n");

sys/dev/pci/drm/i915/display/intel_display_power.c

1412

if (HAS_PCH_LPT_LP(display))

sys/dev/pci/drm/i915/display/intel_display_power.c

1413

intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,

sys/dev/pci/drm/i915/display/intel_display_power.c

1416

lpt_disable_clkout_dp(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1417

hsw_disable_lcpll(display, true, true);

sys/dev/pci/drm/i915/display/intel_display_power.c

1420

static void hsw_disable_pc8(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

1422

struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_power.c

1424

drm_dbg_kms(display->drm, "Disabling package C8+\n");

sys/dev/pci/drm/i915/display/intel_display_power.c

1426

hsw_restore_lcpll(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1427

intel_init_pch_refclk(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1435

static void intel_pch_reset_handshake(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

1441

if (display->platform.ivybridge) {

sys/dev/pci/drm/i915/display/intel_display_power.c

1449

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_display_power.c

1452

intel_de_rmw(display, reg, reset_bits, enable ? reset_bits : 0);

sys/dev/pci/drm/i915/display/intel_display_power.c

1455

static void skl_display_core_init(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

1458

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

1461

gen9_set_dc_state(display, DC_STATE_DISABLE);

sys/dev/pci/drm/i915/display/intel_display_power.c

1464

intel_pch_reset_handshake(display, !HAS_PCH_NOP(display));

sys/dev/pci/drm/i915/display/intel_display_power.c

1466

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_power.c

1472

well = lookup_power_well(display, SKL_DISP_PW_1);

sys/dev/pci/drm/i915/display/intel_display_power.c

1473

intel_power_well_enable(display, well);

sys/dev/pci/drm/i915/display/intel_display_power.c

1475

well = lookup_power_well(display, SKL_DISP_PW_MISC_IO);

sys/dev/pci/drm/i915/display/intel_display_power.c

1476

intel_power_well_enable(display, well);

sys/dev/pci/drm/i915/display/intel_display_power.c

1480

intel_cdclk_init_hw(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1482

gen9_dbuf_enable(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1485

intel_dmc_load_program(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1488

static void skl_display_core_uninit(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

1490

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

1493

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_power.c

1496

gen9_disable_dc_states(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1499

gen9_dbuf_disable(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1501

intel_cdclk_uninit_hw(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1514

well = lookup_power_well(display, SKL_DISP_PW_1);

sys/dev/pci/drm/i915/display/intel_display_power.c

1515

intel_power_well_disable(display, well);

sys/dev/pci/drm/i915/display/intel_display_power.c

1522

static void bxt_display_core_init(struct intel_display *display, bool resume)

sys/dev/pci/drm/i915/display/intel_display_power.c

1524

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

1527

gen9_set_dc_state(display, DC_STATE_DISABLE);

sys/dev/pci/drm/i915/display/intel_display_power.c

1535

intel_pch_reset_handshake(display, false);

sys/dev/pci/drm/i915/display/intel_display_power.c

1537

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_power.c

1543

well = lookup_power_well(display, SKL_DISP_PW_1);

sys/dev/pci/drm/i915/display/intel_display_power.c

1544

intel_power_well_enable(display, well);

sys/dev/pci/drm/i915/display/intel_display_power.c

1548

intel_cdclk_init_hw(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1550

gen9_dbuf_enable(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1553

intel_dmc_load_program(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1556

static void bxt_display_core_uninit(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

1558

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

1561

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_power.c

1564

gen9_disable_dc_states(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1567

gen9_dbuf_disable(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1569

intel_cdclk_uninit_hw(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1580

well = lookup_power_well(display, SKL_DISP_PW_1);

sys/dev/pci/drm/i915/display/intel_display_power.c

1581

intel_power_well_disable(display, well);

sys/dev/pci/drm/i915/display/intel_display_power.c

1618

static void tgl_bw_buddy_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

1620

const struct dram_info *dram_info = intel_dram_info(display->drm);

sys/dev/pci/drm/i915/display/intel_display_power.c

1622

unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask;

sys/dev/pci/drm/i915/display/intel_display_power.c

1626

if (display->platform.dgfx && !display->platform.dg1)

sys/dev/pci/drm/i915/display/intel_display_power.c

1629

if (display->platform.alderlake_s ||

sys/dev/pci/drm/i915/display/intel_display_power.c

1630

(display->platform.rocketlake && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)))

sys/dev/pci/drm/i915/display/intel_display_power.c

1642

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power.c

1645

intel_de_write(display, BW_BUDDY_CTL(i),

sys/dev/pci/drm/i915/display/intel_display_power.c

1649

intel_de_write(display, BW_BUDDY_PAGE_MASK(i),

sys/dev/pci/drm/i915/display/intel_display_power.c

1653

if (DISPLAY_VER(display) == 12)

sys/dev/pci/drm/i915/display/intel_display_power.c

1654

intel_de_rmw(display, BW_BUDDY_CTL(i),

sys/dev/pci/drm/i915/display/intel_display_power.c

1661

static void icl_display_core_init(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

1664

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

1667

gen9_set_dc_state(display, DC_STATE_DISABLE);

sys/dev/pci/drm/i915/display/intel_display_power.c

1670

if (INTEL_PCH_TYPE(display) >= PCH_TGP &&

sys/dev/pci/drm/i915/display/intel_display_power.c

1671

INTEL_PCH_TYPE(display) < PCH_DG1)

sys/dev/pci/drm/i915/display/intel_display_power.c

1672

intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0,

sys/dev/pci/drm/i915/display/intel_display_power.c

1676

intel_pch_reset_handshake(display, !HAS_PCH_NOP(display));

sys/dev/pci/drm/i915/display/intel_display_power.c

1678

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_power.c

1682

intel_combo_phy_init(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1689

well = lookup_power_well(display, SKL_DISP_PW_1);

sys/dev/pci/drm/i915/display/intel_display_power.c

1690

intel_power_well_enable(display, well);

sys/dev/pci/drm/i915/display/intel_display_power.c

1693

if (DISPLAY_VER(display) == 14)

sys/dev/pci/drm/i915/display/intel_display_power.c

1694

intel_de_rmw(display, DC_STATE_EN,

sys/dev/pci/drm/i915/display/intel_display_power.c

1698

intel_cdclk_init_hw(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1700

if (DISPLAY_VER(display) == 12 || display->platform.dg2)

sys/dev/pci/drm/i915/display/intel_display_power.c

1701

gen12_dbuf_slices_config(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1704

gen9_dbuf_enable(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1707

icl_mbus_init(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1710

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_display_power.c

1711

tgl_bw_buddy_init(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1714

if (display->platform.dg2)

sys/dev/pci/drm/i915/display/intel_display_power.c

1715

intel_snps_phy_wait_for_calibration(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1718

if (DISPLAY_VERx100(display) == 1401)

sys/dev/pci/drm/i915/display/intel_display_power.c

1719

intel_de_rmw(display, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1);

sys/dev/pci/drm/i915/display/intel_display_power.c

1722

intel_dmc_load_program(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1725

if (IS_DISPLAY_VERx100(display, 1200, 1300))

sys/dev/pci/drm/i915/display/intel_display_power.c

1726

intel_de_rmw(display, GEN11_CHICKEN_DCPR_2, 0,

sys/dev/pci/drm/i915/display/intel_display_power.c

1731

if (DISPLAY_VER(display) == 13)

sys/dev/pci/drm/i915/display/intel_display_power.c

1732

intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);

sys/dev/pci/drm/i915/display/intel_display_power.c

1735

if (DISPLAY_VER(display) == 20) {

sys/dev/pci/drm/i915/display/intel_display_power.c

1736

intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,

sys/dev/pci/drm/i915/display/intel_display_power.c

1738

intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,

sys/dev/pci/drm/i915/display/intel_display_power.c

1743

static void icl_display_core_uninit(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

1745

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

1748

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_power.c

1751

gen9_disable_dc_states(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1752

intel_dmc_disable_program(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1757

gen9_dbuf_disable(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1760

intel_cdclk_uninit_hw(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1762

if (DISPLAY_VER(display) == 14)

sys/dev/pci/drm/i915/display/intel_display_power.c

1763

intel_de_rmw(display, DC_STATE_EN, 0,

sys/dev/pci/drm/i915/display/intel_display_power.c

1772

well = lookup_power_well(display, SKL_DISP_PW_1);

sys/dev/pci/drm/i915/display/intel_display_power.c

1773

intel_power_well_disable(display, well);

sys/dev/pci/drm/i915/display/intel_display_power.c

1777

intel_combo_phy_uninit(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1780

static void chv_phy_control_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

1783

lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);

sys/dev/pci/drm/i915/display/intel_display_power.c

1785

lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D);

sys/dev/pci/drm/i915/display/intel_display_power.c

1794

display->power.chv_phy_control =

sys/dev/pci/drm/i915/display/intel_display_power.c

1808

if (intel_power_well_is_enabled(display, cmn_bc)) {

sys/dev/pci/drm/i915/display/intel_display_power.c

1809

u32 status = intel_de_read(display, DPLL(display, PIPE_A));

sys/dev/pci/drm/i915/display/intel_display_power.c

1816

display->power.chv_phy_control |=

sys/dev/pci/drm/i915/display/intel_display_power.c

1819

display->power.chv_phy_control |=

sys/dev/pci/drm/i915/display/intel_display_power.c

1826

display->power.chv_phy_control |=

sys/dev/pci/drm/i915/display/intel_display_power.c

1829

display->power.chv_phy_control |=

sys/dev/pci/drm/i915/display/intel_display_power.c

1832

display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);

sys/dev/pci/drm/i915/display/intel_display_power.c

1834

display->power.chv_phy_assert[DPIO_PHY0] = false;

sys/dev/pci/drm/i915/display/intel_display_power.c

1836

display->power.chv_phy_assert[DPIO_PHY0] = true;

sys/dev/pci/drm/i915/display/intel_display_power.c

1839

if (intel_power_well_is_enabled(display, cmn_d)) {

sys/dev/pci/drm/i915/display/intel_display_power.c

1840

u32 status = intel_de_read(display, DPIO_PHY_STATUS);

sys/dev/pci/drm/i915/display/intel_display_power.c

1848

display->power.chv_phy_control |=

sys/dev/pci/drm/i915/display/intel_display_power.c

1851

display->power.chv_phy_control |=

sys/dev/pci/drm/i915/display/intel_display_power.c

1854

display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);

sys/dev/pci/drm/i915/display/intel_display_power.c

1856

display->power.chv_phy_assert[DPIO_PHY1] = false;

sys/dev/pci/drm/i915/display/intel_display_power.c

1858

display->power.chv_phy_assert[DPIO_PHY1] = true;

sys/dev/pci/drm/i915/display/intel_display_power.c

1861

drm_dbg_kms(display->drm, "Initial PHY_CONTROL=0x%08x\n",

sys/dev/pci/drm/i915/display/intel_display_power.c

1862

display->power.chv_phy_control);

sys/dev/pci/drm/i915/display/intel_display_power.c

1867

static void vlv_cmnlane_wa(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

1870

lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);

sys/dev/pci/drm/i915/display/intel_display_power.c

1872

lookup_power_well(display, VLV_DISP_PW_DISP2D);

sys/dev/pci/drm/i915/display/intel_display_power.c

1875

if (intel_power_well_is_enabled(display, cmn) &&

sys/dev/pci/drm/i915/display/intel_display_power.c

1876

intel_power_well_is_enabled(display, disp2d) &&

sys/dev/pci/drm/i915/display/intel_display_power.c

1877

intel_de_read(display, DPIO_CTL) & DPIO_CMNRST)

sys/dev/pci/drm/i915/display/intel_display_power.c

1880

drm_dbg_kms(display->drm, "toggling display PHY side reset\n");

sys/dev/pci/drm/i915/display/intel_display_power.c

1883

intel_power_well_enable(display, disp2d);

sys/dev/pci/drm/i915/display/intel_display_power.c

1892

intel_power_well_disable(display, cmn);

sys/dev/pci/drm/i915/display/intel_display_power.c

1895

static bool vlv_punit_is_power_gated(struct intel_display *display, u32 reg0)

sys/dev/pci/drm/i915/display/intel_display_power.c

1899

vlv_punit_get(display->drm);

sys/dev/pci/drm/i915/display/intel_display_power.c

1900

ret = (vlv_punit_read(display->drm, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE;

sys/dev/pci/drm/i915/display/intel_display_power.c

1901

vlv_punit_put(display->drm);

sys/dev/pci/drm/i915/display/intel_display_power.c

1906

static void assert_ved_power_gated(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

1908

drm_WARN(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power.c

1909

!vlv_punit_is_power_gated(display, PUNIT_REG_VEDSSPM0),

sys/dev/pci/drm/i915/display/intel_display_power.c

1913

static void assert_isp_power_gated(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

1922

drm_WARN(display->drm, !pci_dev_present(isp_ids) &&

sys/dev/pci/drm/i915/display/intel_display_power.c

1923

!vlv_punit_is_power_gated(display, PUNIT_REG_ISPSSPM0),

sys/dev/pci/drm/i915/display/intel_display_power.c

1928

static void intel_power_domains_verify_state(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1946

void intel_power_domains_init_hw(struct intel_display *display, bool resume)

sys/dev/pci/drm/i915/display/intel_display_power.c

1948

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

1952

if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/intel_display_power.c

1953

icl_display_core_init(display, resume);

sys/dev/pci/drm/i915/display/intel_display_power.c

1954

} else if (display->platform.geminilake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/intel_display_power.c

1955

bxt_display_core_init(display, resume);

sys/dev/pci/drm/i915/display/intel_display_power.c

1956

} else if (DISPLAY_VER(display) == 9) {

sys/dev/pci/drm/i915/display/intel_display_power.c

1957

skl_display_core_init(display, resume);

sys/dev/pci/drm/i915/display/intel_display_power.c

1958

} else if (display->platform.cherryview) {

sys/dev/pci/drm/i915/display/intel_display_power.c

1960

chv_phy_control_init(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1962

assert_isp_power_gated(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1963

} else if (display->platform.valleyview) {

sys/dev/pci/drm/i915/display/intel_display_power.c

1965

vlv_cmnlane_wa(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1967

assert_ved_power_gated(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1968

assert_isp_power_gated(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1969

} else if (display->platform.broadwell || display->platform.haswell) {

sys/dev/pci/drm/i915/display/intel_display_power.c

1970

hsw_assert_cdclk(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

1971

intel_pch_reset_handshake(display, !HAS_PCH_NOP(display));

sys/dev/pci/drm/i915/display/intel_display_power.c

1972

} else if (display->platform.ivybridge) {

sys/dev/pci/drm/i915/display/intel_display_power.c

1973

intel_pch_reset_handshake(display, !HAS_PCH_NOP(display));

sys/dev/pci/drm/i915/display/intel_display_power.c

1982

drm_WARN_ON(display->drm, power_domains->init_wakeref);

sys/dev/pci/drm/i915/display/intel_display_power.c

1984

intel_display_power_get(display, POWER_DOMAIN_INIT);

sys/dev/pci/drm/i915/display/intel_display_power.c

1987

if (!display->params.disable_power_well) {

sys/dev/pci/drm/i915/display/intel_display_power.c

1988

drm_WARN_ON(display->drm, power_domains->disable_wakeref);

sys/dev/pci/drm/i915/display/intel_display_power.c

1989

display->power.domains.disable_wakeref = intel_display_power_get(display,

sys/dev/pci/drm/i915/display/intel_display_power.c

1992

intel_power_domains_sync_hw(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2008

void intel_power_domains_driver_remove(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

2011

fetch_and_zero(&display->power.domains.init_wakeref);

sys/dev/pci/drm/i915/display/intel_display_power.c

2014

if (!display->params.disable_power_well)

sys/dev/pci/drm/i915/display/intel_display_power.c

2015

intel_display_power_put(display, POWER_DOMAIN_INIT,

sys/dev/pci/drm/i915/display/intel_display_power.c

2016

fetch_and_zero(&display->power.domains.disable_wakeref));

sys/dev/pci/drm/i915/display/intel_display_power.c

2018

intel_display_power_flush_work_sync(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2020

intel_power_domains_verify_state(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2023

intel_display_rpm_put(display, wakeref);

sys/dev/pci/drm/i915/display/intel_display_power.c

2036

void intel_power_domains_sanitize_state(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

2038

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

2043

for_each_power_well_reverse(display, power_well) {

sys/dev/pci/drm/i915/display/intel_display_power.c

2045

!intel_power_well_is_enabled(display, power_well))

sys/dev/pci/drm/i915/display/intel_display_power.c

2048

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power.c

2051

intel_power_well_disable(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power.c

2069

void intel_power_domains_enable(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

207

static bool __intel_display_power_is_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

2072

fetch_and_zero(&display->power.domains.init_wakeref);

sys/dev/pci/drm/i915/display/intel_display_power.c

2074

intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);

sys/dev/pci/drm/i915/display/intel_display_power.c

2075

intel_power_domains_verify_state(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2085

void intel_power_domains_disable(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

2087

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

2089

drm_WARN_ON(display->drm, power_domains->init_wakeref);

sys/dev/pci/drm/i915/display/intel_display_power.c

2091

intel_display_power_get(display, POWER_DOMAIN_INIT);

sys/dev/pci/drm/i915/display/intel_display_power.c

2093

intel_power_domains_verify_state(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2107

void intel_power_domains_suspend(struct intel_display *display, bool s2idle)

sys/dev/pci/drm/i915/display/intel_display_power.c

2109

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

2113

intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);

sys/dev/pci/drm/i915/display/intel_display_power.c

2123

intel_dmc_has_payload(display)) {

sys/dev/pci/drm/i915/display/intel_display_power.c

2124

intel_display_power_flush_work(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2125

intel_power_domains_verify_state(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

213

if (intel_display_rpm_suspended(display))

sys/dev/pci/drm/i915/display/intel_display_power.c

2133

if (!display->params.disable_power_well)

sys/dev/pci/drm/i915/display/intel_display_power.c

2134

intel_display_power_put(display, POWER_DOMAIN_INIT,

sys/dev/pci/drm/i915/display/intel_display_power.c

2135

fetch_and_zero(&display->power.domains.disable_wakeref));

sys/dev/pci/drm/i915/display/intel_display_power.c

2137

intel_display_power_flush_work(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2138

intel_power_domains_verify_state(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2140

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_display_power.c

2141

icl_display_core_uninit(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2142

else if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_display_power.c

2143

bxt_display_core_uninit(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2144

else if (DISPLAY_VER(display) == 9)

sys/dev/pci/drm/i915/display/intel_display_power.c

2145

skl_display_core_uninit(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2160

void intel_power_domains_resume(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

2162

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

2165

intel_power_domains_init_hw(display, true);

sys/dev/pci/drm/i915/display/intel_display_power.c

2168

drm_WARN_ON(display->drm, power_domains->init_wakeref);

sys/dev/pci/drm/i915/display/intel_display_power.c

2170

intel_display_power_get(display, POWER_DOMAIN_INIT);

sys/dev/pci/drm/i915/display/intel_display_power.c

2176

static void intel_power_domains_dump_info(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

2178

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

218

for_each_power_domain_well_reverse(display, power_well, domain) {

sys/dev/pci/drm/i915/display/intel_display_power.c

2181

for_each_power_well(display, power_well) {

sys/dev/pci/drm/i915/display/intel_display_power.c

2184

drm_dbg_kms(display->drm, "%-25s %d\n",

sys/dev/pci/drm/i915/display/intel_display_power.c

2188

drm_dbg_kms(display->drm, " %-23s %d\n",

sys/dev/pci/drm/i915/display/intel_display_power.c

2204

static void intel_power_domains_verify_state(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

2206

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

2215

for_each_power_well(display, power_well) {

sys/dev/pci/drm/i915/display/intel_display_power.c

2220

enabled = intel_power_well_is_enabled(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power.c

2224

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power.c

2234

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power.c

2248

intel_power_domains_dump_info(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2258

static void intel_power_domains_verify_state(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

2264

void intel_display_power_suspend_late(struct intel_display *display, bool s2idle)

sys/dev/pci/drm/i915/display/intel_display_power.c

2266

intel_power_domains_suspend(display, s2idle);

sys/dev/pci/drm/i915/display/intel_display_power.c

2268

if (DISPLAY_VER(display) >= 11 || display->platform.geminilake ||

sys/dev/pci/drm/i915/display/intel_display_power.c

2269

display->platform.broxton) {

sys/dev/pci/drm/i915/display/intel_display_power.c

2270

bxt_enable_dc9(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2271

} else if (display->platform.haswell || display->platform.broadwell) {

sys/dev/pci/drm/i915/display/intel_display_power.c

2272

hsw_enable_pc8(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2276

if (INTEL_PCH_TYPE(display) >= PCH_CNP && INTEL_PCH_TYPE(display) < PCH_DG1)

sys/dev/pci/drm/i915/display/intel_display_power.c

2277

intel_de_rmw(display, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);

sys/dev/pci/drm/i915/display/intel_display_power.c

2280

void intel_display_power_resume_early(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

2282

if (DISPLAY_VER(display) >= 11 || display->platform.geminilake ||

sys/dev/pci/drm/i915/display/intel_display_power.c

2283

display->platform.broxton) {

sys/dev/pci/drm/i915/display/intel_display_power.c

2284

gen9_sanitize_dc_state(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2285

bxt_disable_dc9(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2286

} else if (display->platform.haswell || display->platform.broadwell) {

sys/dev/pci/drm/i915/display/intel_display_power.c

2287

hsw_disable_pc8(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2291

if (INTEL_PCH_TYPE(display) >= PCH_CNP && INTEL_PCH_TYPE(display) < PCH_DG1)

sys/dev/pci/drm/i915/display/intel_display_power.c

2292

intel_de_rmw(display, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);

sys/dev/pci/drm/i915/display/intel_display_power.c

2294

intel_power_domains_resume(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2297

void intel_display_power_suspend(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

2299

if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/intel_display_power.c

2300

icl_display_core_uninit(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2301

bxt_enable_dc9(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2302

} else if (display->platform.geminilake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/intel_display_power.c

2303

bxt_display_core_uninit(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2304

bxt_enable_dc9(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2305

} else if (display->platform.haswell || display->platform.broadwell) {

sys/dev/pci/drm/i915/display/intel_display_power.c

2306

hsw_enable_pc8(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2310

void intel_display_power_resume(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

2312

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

2314

if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/intel_display_power.c

2315

bxt_disable_dc9(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2316

icl_display_core_init(display, true);

sys/dev/pci/drm/i915/display/intel_display_power.c

2317

if (intel_dmc_has_payload(display)) {

sys/dev/pci/drm/i915/display/intel_display_power.c

2319

skl_enable_dc6(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2321

gen9_enable_dc5(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2323

} else if (display->platform.geminilake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/intel_display_power.c

2324

bxt_disable_dc9(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2325

bxt_display_core_init(display, true);

sys/dev/pci/drm/i915/display/intel_display_power.c

2326

if (intel_dmc_has_payload(display) &&

sys/dev/pci/drm/i915/display/intel_display_power.c

2328

gen9_enable_dc5(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2329

} else if (display->platform.haswell || display->platform.broadwell) {

sys/dev/pci/drm/i915/display/intel_display_power.c

2330

hsw_disable_pc8(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

2334

void intel_display_power_debug(struct intel_display *display, struct seq_file *m)

sys/dev/pci/drm/i915/display/intel_display_power.c

2336

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

248

bool intel_display_power_is_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

2484

intel_port_domains_for_platform(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

2488

if (DISPLAY_VER(display) >= 13) {

sys/dev/pci/drm/i915/display/intel_display_power.c

2491

} else if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_display_power.c

2494

} else if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/intel_display_power.c

2504

intel_port_domains_for_port(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_display_power.c

251

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

2510

intel_port_domains_for_platform(display, &domains, &domains_size);

sys/dev/pci/drm/i915/display/intel_display_power.c

2519

intel_display_power_ddi_io_domain(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_display_power.c

2521

const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port);

sys/dev/pci/drm/i915/display/intel_display_power.c

2523

if (drm_WARN_ON(display->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID))

sys/dev/pci/drm/i915/display/intel_display_power.c

2530

intel_display_power_ddi_lanes_domain(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_display_power.c

2532

const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port);

sys/dev/pci/drm/i915/display/intel_display_power.c

2534

if (drm_WARN_ON(display->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID))

sys/dev/pci/drm/i915/display/intel_display_power.c

2541

intel_port_domains_for_aux_ch(struct intel_display *display, enum aux_ch aux_ch)

sys/dev/pci/drm/i915/display/intel_display_power.c

2547

intel_port_domains_for_platform(display, &domains, &domains_size);

sys/dev/pci/drm/i915/display/intel_display_power.c

255

ret = __intel_display_power_is_enabled(display, domain);

sys/dev/pci/drm/i915/display/intel_display_power.c

2556

intel_display_power_aux_io_domain(struct intel_display *display, enum aux_ch aux_ch)

sys/dev/pci/drm/i915/display/intel_display_power.c

2558

const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch);

sys/dev/pci/drm/i915/display/intel_display_power.c

2560

if (drm_WARN_ON(display->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID))

sys/dev/pci/drm/i915/display/intel_display_power.c

2567

intel_display_power_legacy_aux_domain(struct intel_display *display, enum aux_ch aux_ch)

sys/dev/pci/drm/i915/display/intel_display_power.c

2569

const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch);

sys/dev/pci/drm/i915/display/intel_display_power.c

2571

if (drm_WARN_ON(display->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID))

sys/dev/pci/drm/i915/display/intel_display_power.c

2578

intel_display_power_tbt_aux_domain(struct intel_display *display, enum aux_ch aux_ch)

sys/dev/pci/drm/i915/display/intel_display_power.c

2580

const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch);

sys/dev/pci/drm/i915/display/intel_display_power.c

2582

if (drm_WARN_ON(display->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID))

sys/dev/pci/drm/i915/display/intel_display_power.c

262

sanitize_target_dc_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

265

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

296

void intel_display_power_set_target_dc_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

301

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

304

power_well = lookup_power_well(display, SKL_DISP_DC_OFF);

sys/dev/pci/drm/i915/display/intel_display_power.c

306

if (drm_WARN_ON(display->drm, !power_well))

sys/dev/pci/drm/i915/display/intel_display_power.c

309

state = sanitize_target_dc_state(display, state);

sys/dev/pci/drm/i915/display/intel_display_power.c

314

dc_off_enabled = intel_power_well_is_enabled(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power.c

320

intel_power_well_enable(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power.c

325

intel_power_well_disable(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power.c

339

u32 intel_display_power_get_current_dc_state(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

342

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

346

power_well = lookup_power_well(display, SKL_DISP_DC_OFF);

sys/dev/pci/drm/i915/display/intel_display_power.c

348

if (drm_WARN_ON(display->drm, !power_well))

sys/dev/pci/drm/i915/display/intel_display_power.c

351

current_dc_state = intel_power_well_is_enabled(display, power_well) ?

sys/dev/pci/drm/i915/display/intel_display_power.c

374

struct intel_display *display = container_of(power_domains,

sys/dev/pci/drm/i915/display/intel_display_power.c

378

return !drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power.c

387

struct intel_display *display = container_of(power_domains,

sys/dev/pci/drm/i915/display/intel_display_power.c

396

err |= drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power.c

401

err |= drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power.c

410

struct intel_display *display = container_of(power_domains,

sys/dev/pci/drm/i915/display/intel_display_power.c

415

drm_dbg_kms(display->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM));

sys/dev/pci/drm/i915/display/intel_display_power.c

417

drm_dbg_kms(display->drm, "%s use_count %d\n",

sys/dev/pci/drm/i915/display/intel_display_power.c

425

struct intel_display *display = container_of(power_domains,

sys/dev/pci/drm/i915/display/intel_display_power.c

429

drm_dbg_kms(display->drm, "async_put_wakeref: %s\n",

sys/dev/pci/drm/i915/display/intel_display_power.c

490

intel_display_power_grab_async_put_ref(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

493

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

510

intel_display_rpm_put_raw(display,

sys/dev/pci/drm/i915/display/intel_display_power.c

519

__intel_display_power_get_domain(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

522

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

525

if (intel_display_power_grab_async_put_ref(display, domain))

sys/dev/pci/drm/i915/display/intel_display_power.c

528

for_each_power_domain_well(display, power_well, domain)

sys/dev/pci/drm/i915/display/intel_display_power.c

529

intel_power_well_get(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power.c

546

intel_wakeref_t intel_display_power_get(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

549

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

552

wakeref = intel_display_rpm_get(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

555

__intel_display_power_get_domain(display, domain);

sys/dev/pci/drm/i915/display/intel_display_power.c

574

intel_display_power_get_if_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

577

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

581

wakeref = intel_display_rpm_get_if_in_use(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

587

if (__intel_display_power_is_enabled(display, domain)) {

sys/dev/pci/drm/i915/display/intel_display_power.c

588

__intel_display_power_get_domain(display, domain);

sys/dev/pci/drm/i915/display/intel_display_power.c

597

intel_display_rpm_put(display, wakeref);

sys/dev/pci/drm/i915/display/intel_display_power.c

605

__intel_display_power_put_domain(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

608

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

613

drm_WARN(display->drm, !power_domains->domain_use_count[domain],

sys/dev/pci/drm/i915/display/intel_display_power.c

617

drm_WARN(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power.c

624

for_each_power_domain_well_reverse(display, power_well, domain)

sys/dev/pci/drm/i915/display/intel_display_power.c

625

intel_power_well_put(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power.c

628

static void __intel_display_power_put(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

631

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

634

__intel_display_power_put_domain(display, domain);

sys/dev/pci/drm/i915/display/intel_display_power.c

643

struct intel_display *display = container_of(power_domains,

sys/dev/pci/drm/i915/display/intel_display_power.c

646

drm_WARN_ON(display->drm, power_domains->async_put_wakeref);

sys/dev/pci/drm/i915/display/intel_display_power.c

648

drm_WARN_ON(display->drm, !queue_delayed_work(system_unbound_wq,

sys/dev/pci/drm/i915/display/intel_display_power.c

657

struct intel_display *display = container_of(power_domains,

sys/dev/pci/drm/i915/display/intel_display_power.c

663

wakeref = intel_display_rpm_get_noresume(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

668

__intel_display_power_put_domain(display, domain);

sys/dev/pci/drm/i915/display/intel_display_power.c

671

intel_display_rpm_put(display, wakeref);

sys/dev/pci/drm/i915/display/intel_display_power.c

677

struct intel_display *display = container_of(work, struct intel_display,

sys/dev/pci/drm/i915/display/intel_display_power.c

679

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

682

new_work_wakeref = intel_display_rpm_get_raw(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

722

intel_display_rpm_put_raw(display, old_work_wakeref);

sys/dev/pci/drm/i915/display/intel_display_power.c

724

intel_display_rpm_put_raw(display, new_work_wakeref);

sys/dev/pci/drm/i915/display/intel_display_power.c

740

void __intel_display_power_put_async(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

745

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

748

work_wakeref = intel_display_rpm_get_raw(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

755

__intel_display_power_put_domain(display, domain);

sys/dev/pci/drm/i915/display/intel_display_power.c

760

drm_WARN_ON(display->drm, power_domains->domain_use_count[domain] != 1);

sys/dev/pci/drm/i915/display/intel_display_power.c

780

intel_display_rpm_put_raw(display, work_wakeref);

sys/dev/pci/drm/i915/display/intel_display_power.c

782

intel_display_rpm_put(display, wakeref);

sys/dev/pci/drm/i915/display/intel_display_power.c

797

void intel_display_power_flush_work(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

799

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

819

intel_display_rpm_put_raw(display, work_wakeref);

sys/dev/pci/drm/i915/display/intel_display_power.c

830

intel_display_power_flush_work_sync(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power.c

832

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power.c

834

intel_display_power_flush_work(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

839

drm_WARN_ON(display->drm, power_domains->async_put_wakeref);

sys/dev/pci/drm/i915/display/intel_display_power.c

853

void intel_display_power_put(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

857

__intel_display_power_put(display, domain);

sys/dev/pci/drm/i915/display/intel_display_power.c

858

intel_display_rpm_put(display, wakeref);

sys/dev/pci/drm/i915/display/intel_display_power.c

874

void intel_display_power_put_unchecked(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

877

__intel_display_power_put(display, domain);

sys/dev/pci/drm/i915/display/intel_display_power.c

878

intel_display_rpm_put_unchecked(display);

sys/dev/pci/drm/i915/display/intel_display_power.c

883

intel_display_power_get_in_set(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

889

drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits));

sys/dev/pci/drm/i915/display/intel_display_power.c

891

wf = intel_display_power_get(display, domain);

sys/dev/pci/drm/i915/display/intel_display_power.c

899

intel_display_power_get_in_set_if_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

905

drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits));

sys/dev/pci/drm/i915/display/intel_display_power.c

907

wf = intel_display_power_get_if_enabled(display, domain);

sys/dev/pci/drm/i915/display/intel_display_power.c

920

intel_display_power_put_mask_in_set(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.c

927

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power.c

937

intel_display_power_put(display, domain, wf);

sys/dev/pci/drm/i915/display/intel_display_power.c

951

static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc)

sys/dev/pci/drm/i915/display/intel_display_power.c

957

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_power.c

960

if (DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/intel_display_power.c

962

else if (display->platform.dg2)

sys/dev/pci/drm/i915/display/intel_display_power.c

964

else if (display->platform.dg1)

sys/dev/pci/drm/i915/display/intel_display_power.c

966

else if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_display_power.c

968

else if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_display_power.c

970

else if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_display_power.c

980

mask = display->platform.geminilake || display->platform.broxton ||

sys/dev/pci/drm/i915/display/intel_display_power.c

981

DISPLAY_VER(display) >= 11 ? DC_STATE_EN_DC9 : 0;

sys/dev/pci/drm/i915/display/intel_display_power.c

983

if (!display->params.disable_power_well)

sys/dev/pci/drm/i915/display/intel_display_power.c

991

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power.c

996

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power.h

170

int intel_power_domains_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_power.h

171

void intel_power_domains_cleanup(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_power.h

172

void intel_power_domains_init_hw(struct intel_display *display, bool resume);

sys/dev/pci/drm/i915/display/intel_display_power.h

173

void intel_power_domains_driver_remove(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_power.h

174

void intel_power_domains_enable(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_power.h

175

void intel_power_domains_disable(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_power.h

176

void intel_power_domains_suspend(struct intel_display *display, bool s2idle);

sys/dev/pci/drm/i915/display/intel_display_power.h

177

void intel_power_domains_resume(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_power.h

178

void intel_power_domains_sanitize_state(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_power.h

180

void intel_display_power_suspend_late(struct intel_display *display, bool s2idle);

sys/dev/pci/drm/i915/display/intel_display_power.h

181

void intel_display_power_resume_early(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_power.h

182

void intel_display_power_suspend(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_power.h

183

void intel_display_power_resume(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_power.h

184

void intel_display_power_set_target_dc_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.h

186

u32 intel_display_power_get_current_dc_state(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_power.h

188

bool intel_display_power_is_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.h

190

intel_wakeref_t intel_display_power_get(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.h

193

intel_display_power_get_if_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.h

195

void __intel_display_power_put_async(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.h

199

void intel_display_power_flush_work(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_power.h

201

void intel_display_power_put(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.h

205

intel_display_power_put_async(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.h

209

__intel_display_power_put_async(display, domain, wakeref, -1);

sys/dev/pci/drm/i915/display/intel_display_power.h

213

intel_display_power_put_async_delay(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.h

218

__intel_display_power_put_async(display, domain, wakeref, delay_ms);

sys/dev/pci/drm/i915/display/intel_display_power.h

221

void intel_display_power_put_unchecked(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.h

225

intel_display_power_put(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.h

229

intel_display_power_put_unchecked(display, domain);

sys/dev/pci/drm/i915/display/intel_display_power.h

233

intel_display_power_put_async(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.h

237

__intel_display_power_put_async(display, domain, INTEL_WAKEREF_DEF, -1);

sys/dev/pci/drm/i915/display/intel_display_power.h

241

intel_display_power_put_async_delay(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.h

246

__intel_display_power_put_async(display, domain, INTEL_WAKEREF_DEF, delay_ms);

sys/dev/pci/drm/i915/display/intel_display_power.h

251

intel_display_power_get_in_set(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.h

256

intel_display_power_get_in_set_if_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.h

261

intel_display_power_put_mask_in_set(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.h

266

intel_display_power_put_all_in_set(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.h

269

intel_display_power_put_mask_in_set(display, power_domain_set, &power_domain_set->mask);

sys/dev/pci/drm/i915/display/intel_display_power.h

272

void intel_display_power_debug(struct intel_display *display, struct seq_file *m);

sys/dev/pci/drm/i915/display/intel_display_power.h

275

intel_display_power_ddi_lanes_domain(struct intel_display *display, enum port port);

sys/dev/pci/drm/i915/display/intel_display_power.h

277

intel_display_power_ddi_io_domain(struct intel_display *display, enum port port);

sys/dev/pci/drm/i915/display/intel_display_power.h

279

intel_display_power_aux_io_domain(struct intel_display *display, enum aux_ch aux_ch);

sys/dev/pci/drm/i915/display/intel_display_power.h

281

intel_display_power_legacy_aux_domain(struct intel_display *display, enum aux_ch aux_ch);

sys/dev/pci/drm/i915/display/intel_display_power.h

283

intel_display_power_tbt_aux_domain(struct intel_display *display, enum aux_ch aux_ch);

sys/dev/pci/drm/i915/display/intel_display_power.h

297

void gen9_dbuf_slices_update(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power.h

300

#define with_intel_display_power(display, domain, wf) \

sys/dev/pci/drm/i915/display/intel_display_power.h

301

for ((wf) = intel_display_power_get((display), (domain)); (wf); \

sys/dev/pci/drm/i915/display/intel_display_power.h

302

intel_display_power_put_async((display), (domain), (wf)), (wf) = NULL)

sys/dev/pci/drm/i915/display/intel_display_power.h

304

#define with_intel_display_power_if_enabled(display, domain, wf) \

sys/dev/pci/drm/i915/display/intel_display_power.h

305

for ((wf) = intel_display_power_get_if_enabled((display), (domain)); (wf); \

sys/dev/pci/drm/i915/display/intel_display_power.h

306

intel_display_power_put_async((display), (domain), (wf)), (wf) = NULL)

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1809

struct intel_display *display = container_of(power_domains,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1835

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1846

drm_WARN_ON(display->drm, id >= sizeof(power_well_ids) * 8);

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1847

drm_WARN_ON(display->drm, power_well_ids & BIT_ULL(id));

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1868

struct intel_display *display = container_of(power_domains,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1875

if (!HAS_DISPLAY(display)) {

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1880

if (DISPLAY_VERx100(display) == 3002)

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1882

else if (DISPLAY_VER(display) >= 30)

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1884

else if (DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1886

else if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1888

else if (display->platform.dg2)

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1890

else if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1892

else if (display->platform.dg1)

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1894

else if (display->platform.alderlake_s)

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1896

else if (display->platform.rocketlake)

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1898

else if (DISPLAY_VER(display) == 12)

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1900

else if (DISPLAY_VER(display) == 11)

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1902

else if (display->platform.geminilake)

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1904

else if (display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1906

else if (DISPLAY_VER(display) == 9)

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1908

else if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1910

else if (display->platform.broadwell)

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1912

else if (display->platform.haswell)

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1914

else if (display->platform.valleyview)

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1916

else if (display->platform.i830)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1003

void gen9_disable_dc_states(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1005

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1010

tgl_disable_dc3co(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1014

if (HAS_DISPLAY(display)) {

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1015

intel_dmc_wl_get_noreg(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1016

gen9_set_dc_state(display, DC_STATE_DISABLE);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1017

intel_dmc_wl_put_noreg(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1019

gen9_set_dc_state(display, DC_STATE_DISABLE);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1025

intel_dmc_wl_disable(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1027

intel_cdclk_get_cdclk(display, &cdclk_config);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1029

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1030

intel_cdclk_clock_changed(&display->cdclk.hw,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1033

gen9_assert_dbuf_enabled(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1035

if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1036

bxt_verify_dpio_phy_power_wells(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1038

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1044

intel_combo_phy_init(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1047

static void gen9_dc_off_power_well_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1050

gen9_disable_dc_states(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1053

static void gen9_dc_off_power_well_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1056

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1058

if (!intel_dmc_has_payload(display))

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1063

tgl_enable_dc3co(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1066

skl_enable_dc6(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1069

gen9_enable_dc5(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1074

static void i9xx_power_well_sync_hw_noop(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1079

static void i9xx_always_on_power_well_noop(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1084

static bool i9xx_always_on_power_well_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

109

drm_WARN(display->drm, 1,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1090

static void i830_pipes_power_well_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1093

if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1094

i830_enable_pipe(display, PIPE_A);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1095

if ((intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE) == 0)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1096

i830_enable_pipe(display, PIPE_B);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1099

static void i830_pipes_power_well_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1102

i830_disable_pipe(display, PIPE_B);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1103

i830_disable_pipe(display, PIPE_A);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1106

static bool i830_pipes_power_well_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1109

return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE &&

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1110

intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1113

static void i830_pipes_power_well_sync_hw(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1117

i830_pipes_power_well_enable(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1119

i830_pipes_power_well_disable(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

112

return &display->power.domains.power_wells[0];

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1122

static void vlv_set_power_well(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1136

vlv_punit_get(display->drm);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1138

val = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1142

ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1145

vlv_punit_write(display->drm, PUNIT_REG_PWRGT_CTRL, ctrl);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1147

ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS),

sys/dev/pci/drm/i915/display/intel_display_power_well.c

115

void intel_power_well_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1151

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1154

vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL));

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1157

vlv_punit_put(display->drm);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1160

static void vlv_power_well_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1163

vlv_set_power_well(display, power_well, true);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1166

static void vlv_power_well_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1169

vlv_set_power_well(display, power_well, false);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1172

static bool vlv_power_well_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

118

drm_dbg_kms(display->drm, "enabling %s\n", intel_power_well_name(power_well));

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1184

vlv_punit_get(display->drm);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1186

state = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS) & mask;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

119

power_well->desc->ops->enable(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1191

drm_WARN_ON(display->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) &&

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1200

ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL) & mask;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1201

drm_WARN_ON(display->drm, ctrl != state);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1203

vlv_punit_put(display->drm);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1208

static void vlv_init_display_clock_gating(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1216

intel_de_rmw(display, VLV_DSPCLK_GATE_D,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1222

intel_de_write(display, MI_ARB_VLV,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1224

intel_de_write(display, CBR1_VLV, 0);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1226

drm_WARN_ON(display->drm, DISPLAY_RUNTIME_INFO(display)->rawclk_freq == 0);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1227

intel_de_write(display, RAWCLK_FREQ_VLV,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1228

DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(display)->rawclk_freq,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

123

void intel_power_well_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1232

static void vlv_display_power_well_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1245

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1246

u32 val = intel_de_read(display, DPLL(display, pipe));

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1252

intel_de_write(display, DPLL(display, pipe), val);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1255

vlv_init_display_clock_gating(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1257

valleyview_enable_display_irqs(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

126

drm_dbg_kms(display->drm, "disabling %s\n", intel_power_well_name(power_well));

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1263

if (display->power.domains.initializing)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1266

intel_hpd_init(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1267

intel_hpd_poll_disable(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1270

for_each_intel_encoder(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1275

intel_vga_disable(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1277

intel_pps_unlock_regs_wa(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

128

power_well->desc->ops->disable(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1280

static void vlv_display_power_well_deinit(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1282

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1284

valleyview_disable_display_irqs(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1289

vlv_pps_reset_all(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1293

if (!display->drm->dev->power.is_suspended)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1297

intel_hpd_poll_enable(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1300

static void vlv_display_power_well_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1303

vlv_set_power_well(display, power_well, true);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1305

vlv_display_power_well_init(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1308

static void vlv_display_power_well_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

131

void intel_power_well_sync_hw(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1311

vlv_display_power_well_deinit(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1313

vlv_set_power_well(display, power_well, false);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1316

static void vlv_dpio_cmn_power_well_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1322

vlv_set_power_well(display, power_well, true);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1335

intel_de_rmw(display, DPIO_CTL, 0, DPIO_CMNRST);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1338

static void vlv_dpio_cmn_power_well_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

134

power_well->desc->ops->sync_hw(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1343

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1344

assert_pll_disabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1347

intel_de_rmw(display, DPIO_CTL, DPIO_CMNRST, 0);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1349

vlv_set_power_well(display, power_well, false);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

135

power_well->hw_enabled = power_well->desc->ops->is_enabled(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1354

static void assert_chv_phy_status(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1357

lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1359

lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1360

u32 phy_control = display->power.chv_phy_control;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1371

if (!display->power.chv_phy_assert[DPIO_PHY0])

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1379

if (!display->power.chv_phy_assert[DPIO_PHY1])

sys/dev/pci/drm/i915/display/intel_display_power_well.c

138

void intel_power_well_get(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1384

if (intel_power_well_is_enabled(display, cmn_bc)) {

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1407

(intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

142

intel_power_well_enable(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1425

if (intel_power_well_is_enabled(display, cmn_d)) {

sys/dev/pci/drm/i915/display/intel_display_power_well.c

145

void intel_power_well_put(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1450

if (intel_de_wait(display, DISPLAY_PHY_STATUS,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1452

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1454

intel_de_read(display, DISPLAY_PHY_STATUS) & phy_status_mask,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1455

phy_status, display->power.chv_phy_control);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1460

static void chv_dpio_cmn_power_well_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1467

drm_WARN_ON_ONCE(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1478

vlv_set_power_well(display, power_well, true);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

148

drm_WARN(display->drm, !power_well->count,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1481

if (intel_de_wait_for_set(display, DISPLAY_PHY_STATUS,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1483

drm_err(display->drm, "Display PHY %d is not power up\n",

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1486

vlv_dpio_get(display->drm);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1489

tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW28);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1492

vlv_dpio_write(display->drm, phy, CHV_CMN_DW28, tmp);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1495

tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW6_CH1);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1497

vlv_dpio_write(display->drm, phy, CHV_CMN_DW6_CH1, tmp);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1504

tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW30);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1506

vlv_dpio_write(display->drm, phy, CHV_CMN_DW30, tmp);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1509

vlv_dpio_put(display->drm);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1511

display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1512

intel_de_write(display, DISPLAY_PHY_CONTROL,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1513

display->power.chv_phy_control);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1515

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1517

phy, display->power.chv_phy_control);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1519

assert_chv_phy_status(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1522

static void chv_dpio_cmn_power_well_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1528

drm_WARN_ON_ONCE(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

153

intel_power_well_disable(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1534

assert_pll_disabled(display, PIPE_A);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1535

assert_pll_disabled(display, PIPE_B);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1538

assert_pll_disabled(display, PIPE_C);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1541

display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1542

intel_de_write(display, DISPLAY_PHY_CONTROL,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1543

display->power.chv_phy_control);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1545

vlv_set_power_well(display, power_well, false);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1547

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1549

phy, display->power.chv_phy_control);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1552

display->power.chv_phy_assert[phy] = true;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1554

assert_chv_phy_status(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1557

static void assert_chv_phy_powergate(struct intel_display *display, enum dpio_phy phy,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

156

bool intel_power_well_is_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1569

if (!display->power.chv_phy_assert[phy])

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1577

vlv_dpio_get(display->drm);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1578

val = vlv_dpio_read(display->drm, phy, reg);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1579

vlv_dpio_put(display->drm);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

159

return power_well->desc->ops->is_enabled(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1612

drm_WARN(display->drm, actual != expected,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1621

bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1624

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1629

was_override = display->power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1635

display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1637

display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1639

intel_de_write(display, DISPLAY_PHY_CONTROL,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1640

display->power.chv_phy_control);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1642

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1644

phy, ch, display->power.chv_phy_control);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1646

assert_chv_phy_status(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1657

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1658

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1664

display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1665

display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1668

display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

167

bool intel_display_power_well_is_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1670

display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1672

intel_de_write(display, DISPLAY_PHY_CONTROL,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1673

display->power.chv_phy_control);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1675

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1677

phy, ch, mask, display->power.chv_phy_control);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1679

assert_chv_phy_status(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1681

assert_chv_phy_powergate(display, phy, ch, override, mask);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1686

static bool chv_pipe_power_well_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1693

vlv_punit_get(display->drm);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1695

state = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1700

drm_WARN_ON(display->drm, state != DP_SSS_PWR_ON(pipe) &&

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1708

ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1709

drm_WARN_ON(display->drm, ctrl << 16 != state);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1711

vlv_punit_put(display->drm);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1716

static void chv_set_pipe_power_well(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

172

power_well = lookup_power_well(display, power_well_id);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1727

vlv_punit_get(display->drm);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1729

ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1735

vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, ctrl);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1737

ret = poll_timeout_us(ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),

sys/dev/pci/drm/i915/display/intel_display_power_well.c

174

return intel_power_well_is_enabled(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1741

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1744

vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM));

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1749

vlv_punit_put(display->drm);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1752

static void chv_pipe_power_well_sync_hw(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1755

intel_de_write(display, DISPLAY_PHY_CONTROL,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1756

display->power.chv_phy_control);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1759

static void chv_pipe_power_well_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1762

chv_set_pipe_power_well(display, power_well, true);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1764

vlv_display_power_well_init(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1767

static void chv_pipe_power_well_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1770

vlv_display_power_well_deinit(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1772

chv_set_pipe_power_well(display, power_well, false);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1776

tgl_tc_cold_request(struct intel_display *display, bool block)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1794

ret = intel_pcode_read(display->drm, TGL_PCODE_TCCOLD, &low_val, &high_val);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1810

drm_err(display->drm, "TC cold %sblock failed\n", block ? "" : "un");

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1812

drm_dbg_kms(display->drm, "TC cold %sblock succeeded\n",

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1817

tgl_tc_cold_off_power_well_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1820

tgl_tc_cold_request(display, true);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1824

tgl_tc_cold_off_power_well_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1827

tgl_tc_cold_request(display, false);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1831

tgl_tc_cold_off_power_well_sync_hw(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1835

tgl_tc_cold_off_power_well_enable(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1837

tgl_tc_cold_off_power_well_disable(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1841

tgl_tc_cold_off_power_well_is_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1851

static void xelpdp_aux_power_well_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1855

enum phy phy = icl_aux_pw_to_phy(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1857

if (intel_phy_is_tc(display, phy))

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1858

icl_tc_port_assert_ref_held(display, power_well,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1859

aux_ch_to_digital_port(display, aux_ch));

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1861

intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1874

static void xelpdp_aux_power_well_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1879

intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1885

static bool xelpdp_aux_power_well_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1890

return intel_de_read(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch)) &

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1894

static void xe2lpd_pica_power_well_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1897

intel_de_write(display, XE2LPD_PICA_PW_CTL,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1900

if (intel_de_wait_for_set(display, XE2LPD_PICA_PW_CTL,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1902

drm_dbg_kms(display->drm, "pica power well enable timeout\n");

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1904

drm_WARN(display->drm, 1, "Power well PICA timeout when enabled");

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1908

static void xe2lpd_pica_power_well_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1911

intel_de_write(display, XE2LPD_PICA_PW_CTL, 0);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1913

if (intel_de_wait_for_clear(display, XE2LPD_PICA_PW_CTL,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1915

drm_dbg_kms(display->drm, "pica power well disable timeout\n");

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1917

drm_WARN(display->drm, 1, "Power well PICA timeout when disabled");

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1921

static bool xe2lpd_pica_power_well_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1924

return intel_de_read(display, XE2LPD_PICA_PW_CTL) &

sys/dev/pci/drm/i915/display/intel_display_power_well.c

203

static void hsw_power_well_post_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

207

intel_vga_reset_io_mem(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

210

gen8_irq_power_well_post_enable(display, irq_pipe_mask);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

213

static void hsw_power_well_pre_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

217

gen8_irq_power_well_pre_disable(display, irq_pipe_mask);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

238

aux_ch_to_digital_port(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

243

for_each_intel_encoder(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_display_power_well.c

259

static enum phy icl_aux_pw_to_phy(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

263

struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

275

static void hsw_wait_for_power_well_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

288

if (display->platform.dg2 && power_well->desc->fixed_enable_delay) {

sys/dev/pci/drm/i915/display/intel_display_power_well.c

294

if (intel_de_wait_for_set(display, regs->driver,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

296

drm_dbg_kms(display->drm, "%s power well enable timeout\n",

sys/dev/pci/drm/i915/display/intel_display_power_well.c

299

drm_WARN_ON(display->drm, !timeout_expected);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

304

static u32 hsw_power_well_requesters(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

311

ret = intel_de_read(display, regs->bios) & req_mask ? 1 : 0;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

312

ret |= intel_de_read(display, regs->driver) & req_mask ? 2 : 0;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

314

ret |= intel_de_read(display, regs->kvmr) & req_mask ? 4 : 0;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

315

ret |= intel_de_read(display, regs->debug) & req_mask ? 8 : 0;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

320

static void hsw_wait_for_power_well_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

337

reqs = hsw_power_well_requesters(display, regs, pw_idx);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

339

ret = intel_de_wait_for_clear(display, regs->driver,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

347

reqs = hsw_power_well_requesters(display, regs, pw_idx);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

349

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

355

static void gen9_wait_for_power_well_fuses(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

359

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

360

intel_de_wait_for_set(display, SKL_FUSE_STATUS,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

364

static void hsw_power_well_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

373

pg = pw_idx_to_pg(display, pw_idx);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

376

if (display->platform.alderlake_p && pg == SKL_PG1)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

377

intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

387

gen9_wait_for_power_well_fuses(display, SKL_PG0);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

390

intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx));

sys/dev/pci/drm/i915/display/intel_display_power_well.c

392

hsw_wait_for_power_well_enable(display, power_well, false);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

397

pg = pw_idx_to_pg(display, pw_idx);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

399

gen9_wait_for_power_well_fuses(display, pg);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

402

hsw_power_well_post_enable(display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

407

static void hsw_power_well_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

413

hsw_power_well_pre_disable(display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

416

intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

417

hsw_wait_for_power_well_disable(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

420

static bool intel_aux_ch_is_edp(struct intel_display *display, enum aux_ch aux_ch)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

422

struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

428

icl_combo_phy_aux_power_well_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

434

drm_WARN_ON(display->drm, !display->platform.icelake);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

436

intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx));

sys/dev/pci/drm/i915/display/intel_display_power_well.c

44

static enum skl_power_gate pw_idx_to_pg(struct intel_display *display, int pw_idx)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

442

intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)),

sys/dev/pci/drm/i915/display/intel_display_power_well.c

445

hsw_wait_for_power_well_enable(display, power_well, false);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

449

!intel_aux_ch_is_edp(display, ICL_AUX_PW_TO_CH(pw_idx)))

sys/dev/pci/drm/i915/display/intel_display_power_well.c

450

intel_de_rmw(display, ICL_PORT_TX_DW6_AUX(ICL_AUX_PW_TO_PHY(pw_idx)),

sys/dev/pci/drm/i915/display/intel_display_power_well.c

455

icl_combo_phy_aux_power_well_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

46

int pw1_idx = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_PW_1 : SKL_PW_CTL_IDX_PW_1;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

461

drm_WARN_ON(display->drm, !display->platform.icelake);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

467

intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)),

sys/dev/pci/drm/i915/display/intel_display_power_well.c

470

intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

472

hsw_wait_for_power_well_disable(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

477

static void icl_tc_port_assert_ref_held(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

481

if (drm_WARN_ON(display->drm, !dig_port))

sys/dev/pci/drm/i915/display/intel_display_power_well.c

484

if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port))

sys/dev/pci/drm/i915/display/intel_display_power_well.c

487

drm_WARN_ON(display->drm, !intel_tc_port_ref_held(dig_port));

sys/dev/pci/drm/i915/display/intel_display_power_well.c

492

static void icl_tc_port_assert_ref_held(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

502

static void icl_tc_cold_exit(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

507

ret = intel_pcode_write(display->drm, ICL_PCODE_EXIT_TCCOLD, 0);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

518

drm_dbg_kms(display->drm, "TC cold block %s\n", ret ? "failed" :

sys/dev/pci/drm/i915/display/intel_display_power_well.c

523

icl_tc_phy_aux_power_well_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

527

struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

534

icl_tc_port_assert_ref_held(display, power_well, dig_port);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

536

intel_de_rmw(display, DP_AUX_CH_CTL(aux_ch),

sys/dev/pci/drm/i915/display/intel_display_power_well.c

539

intel_de_rmw(display, regs->driver,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

549

if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port))

sys/dev/pci/drm/i915/display/intel_display_power_well.c

550

icl_tc_cold_exit(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

552

hsw_wait_for_power_well_enable(display, power_well, timeout_expected);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

554

if (DISPLAY_VER(display) >= 12 && !is_tbt) {

sys/dev/pci/drm/i915/display/intel_display_power_well.c

559

ret = poll_timeout_us(val = intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)),

sys/dev/pci/drm/i915/display/intel_display_power_well.c

563

drm_warn(display->drm, "Timeout waiting TC uC health\n");

sys/dev/pci/drm/i915/display/intel_display_power_well.c

568

icl_aux_power_well_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

571

enum phy phy = icl_aux_pw_to_phy(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

573

if (intel_phy_is_tc(display, phy))

sys/dev/pci/drm/i915/display/intel_display_power_well.c

574

return icl_tc_phy_aux_power_well_enable(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

575

else if (display->platform.icelake)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

576

return icl_combo_phy_aux_power_well_enable(display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

579

return hsw_power_well_enable(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

583

icl_aux_power_well_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

586

enum phy phy = icl_aux_pw_to_phy(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

588

if (intel_phy_is_tc(display, phy))

sys/dev/pci/drm/i915/display/intel_display_power_well.c

589

return hsw_power_well_disable(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

590

else if (display->platform.icelake)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

591

return icl_combo_phy_aux_power_well_disable(display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

594

return hsw_power_well_disable(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

602

static bool hsw_power_well_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

612

val = intel_de_read(display, regs->driver);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

620

if (DISPLAY_VER(display) == 9 && !display->platform.broxton &&

sys/dev/pci/drm/i915/display/intel_display_power_well.c

622

val |= intel_de_read(display, regs->bios);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

627

static void assert_can_enable_dc9(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

629

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

631

drm_WARN_ONCE(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

632

(intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9),

sys/dev/pci/drm/i915/display/intel_display_power_well.c

634

drm_WARN_ONCE(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

635

intel_de_read(display, DC_STATE_EN) &

sys/dev/pci/drm/i915/display/intel_display_power_well.c

638

drm_WARN_ONCE(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

639

intel_de_read(display, HSW_PWR_WELL_CTL2) &

sys/dev/pci/drm/i915/display/intel_display_power_well.c

642

drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv),

sys/dev/pci/drm/i915/display/intel_display_power_well.c

654

static void assert_can_disable_dc9(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

656

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

658

drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv),

sys/dev/pci/drm/i915/display/intel_display_power_well.c

66

void (*sync_hw)(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

660

drm_WARN_ONCE(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

661

intel_de_read(display, DC_STATE_EN) &

sys/dev/pci/drm/i915/display/intel_display_power_well.c

674

static void gen9_write_dc_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

681

intel_de_write(display, DC_STATE_EN, state);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

689

v = intel_de_read(display, DC_STATE_EN);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

692

intel_de_write(display, DC_STATE_EN, state);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

702

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

708

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

713

static u32 gen9_dc_mask(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

719

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

722

else if (DISPLAY_VER(display) == 11)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

724

else if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

73

void (*enable)(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

732

void gen9_sanitize_dc_state(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

734

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

737

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_power_well.c

740

val = intel_de_read(display, DC_STATE_EN) & gen9_dc_mask(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

742

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

771

void gen9_set_dc_state(struct intel_display *display, u32 state)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

773

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

778

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_power_well.c

781

if (drm_WARN_ON_ONCE(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

786

intel_psr_notify_dc5_dc6(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

788

val = intel_de_read(display, DC_STATE_EN);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

789

mask = gen9_dc_mask(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

79

void (*disable)(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

790

drm_dbg_kms(display->drm, "Setting DC state from %02x to %02x\n",

sys/dev/pci/drm/i915/display/intel_display_power_well.c

795

drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n",

sys/dev/pci/drm/i915/display/intel_display_power_well.c

801

intel_dmc_update_dc6_allowed_count(display, true);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

806

gen9_write_dc_state(display, val);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

809

intel_dmc_update_dc6_allowed_count(display, false);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

814

static void tgl_enable_dc3co(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

816

drm_dbg_kms(display->drm, "Enabling DC3CO\n");

sys/dev/pci/drm/i915/display/intel_display_power_well.c

817

gen9_set_dc_state(display, DC_STATE_EN_DC3CO);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

82

bool (*is_enabled)(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

820

static void tgl_disable_dc3co(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

822

drm_dbg_kms(display->drm, "Disabling DC3CO\n");

sys/dev/pci/drm/i915/display/intel_display_power_well.c

823

intel_de_rmw(display, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

824

gen9_set_dc_state(display, DC_STATE_DISABLE);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

831

static void assert_can_enable_dc5(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

836

if (DISPLAY_VER(display) == 12)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

841

drm_WARN_ONCE(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

842

intel_display_power_well_is_enabled(display, high_pg),

sys/dev/pci/drm/i915/display/intel_display_power_well.c

845

drm_WARN_ONCE(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

846

(intel_de_read(display, DC_STATE_EN) &

sys/dev/pci/drm/i915/display/intel_display_power_well.c

850

assert_display_rpm_held(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

852

assert_main_dmc_loaded(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

855

void gen9_enable_dc5(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

857

assert_can_enable_dc5(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

859

drm_dbg_kms(display->drm, "Enabling DC5\n");

sys/dev/pci/drm/i915/display/intel_display_power_well.c

862

if (DISPLAY_VER(display) == 9 && !display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

863

intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

866

intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC5);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

868

gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC5);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

871

static void assert_can_enable_dc6(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

873

drm_WARN_ONCE(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

874

(intel_de_read(display, UTIL_PIN_CTL) &

sys/dev/pci/drm/i915/display/intel_display_power_well.c

878

drm_WARN_ONCE(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

879

(intel_de_read(display, DC_STATE_EN) &

sys/dev/pci/drm/i915/display/intel_display_power_well.c

883

assert_main_dmc_loaded(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

886

void skl_enable_dc6(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

888

assert_can_enable_dc6(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

890

drm_dbg_kms(display->drm, "Enabling DC6\n");

sys/dev/pci/drm/i915/display/intel_display_power_well.c

893

if (DISPLAY_VER(display) == 9 && !display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

894

intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

897

intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

899

gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

902

void bxt_enable_dc9(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

904

assert_can_enable_dc9(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

906

drm_dbg_kms(display->drm, "Enabling DC9\n");

sys/dev/pci/drm/i915/display/intel_display_power_well.c

911

if (display->platform.broxton || display->platform.geminilake)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

912

bxt_pps_reset_all(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

913

gen9_set_dc_state(display, DC_STATE_EN_DC9);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

916

void bxt_disable_dc9(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

918

assert_can_disable_dc9(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

920

drm_dbg_kms(display->drm, "Disabling DC9\n");

sys/dev/pci/drm/i915/display/intel_display_power_well.c

922

gen9_set_dc_state(display, DC_STATE_DISABLE);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

924

intel_pps_unlock_regs_wa(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

927

static void hsw_power_well_sync_hw(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

93

lookup_power_well(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

933

u32 bios_req = intel_de_read(display, regs->bios);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

937

u32 drv_req = intel_de_read(display, regs->driver);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

940

intel_de_write(display, regs->driver, drv_req | mask);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

941

intel_de_write(display, regs->bios, bios_req & ~mask);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

945

static void bxt_dpio_cmn_power_well_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

948

bxt_dpio_phy_init(display, i915_power_well_instance(power_well)->bxt.phy);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

951

static void bxt_dpio_cmn_power_well_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

954

bxt_dpio_phy_uninit(display, i915_power_well_instance(power_well)->bxt.phy);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

957

static bool bxt_dpio_cmn_power_well_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

960

return bxt_dpio_phy_is_enabled(display, i915_power_well_instance(power_well)->bxt.phy);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

963

static void bxt_verify_dpio_phy_power_wells(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

967

power_well = lookup_power_well(display, BXT_DISP_PW_DPIO_CMN_A);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

969

bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

971

power_well = lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

973

bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

975

if (display->platform.geminilake) {

sys/dev/pci/drm/i915/display/intel_display_power_well.c

976

power_well = lookup_power_well(display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

979

bxt_dpio_phy_verify_state(display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

98

for_each_power_well(display, power_well)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

984

static bool gen9_dc_off_power_well_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

987

return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&

sys/dev/pci/drm/i915/display/intel_display_power_well.c

988

(intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

991

static void gen9_assert_dbuf_enabled(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

993

u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

994

u8 enabled_dbuf_slices = display->dbuf.enabled_slices;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

996

drm_WARN(display->drm,

sys/dev/pci/drm/i915/display/intel_display_power_well.h

129

struct i915_power_well *lookup_power_well(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.h

132

void intel_power_well_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.h

134

void intel_power_well_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.h

136

void intel_power_well_sync_hw(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.h

138

void intel_power_well_get(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.h

140

void intel_power_well_put(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.h

142

bool intel_power_well_is_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.h

145

bool intel_display_power_well_is_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_power_well.h

154

bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy,

sys/dev/pci/drm/i915/display/intel_display_power_well.h

157

void gen9_enable_dc5(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_power_well.h

158

void skl_enable_dc6(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_power_well.h

159

void gen9_sanitize_dc_state(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_power_well.h

160

void gen9_set_dc_state(struct intel_display *display, u32 state);

sys/dev/pci/drm/i915/display/intel_display_power_well.h

161

void gen9_disable_dc_states(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_power_well.h

162

void bxt_enable_dc9(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_power_well.h

163

void bxt_disable_dc9(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

39

#define _MMIO_PIPE2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->pipe_offsets[(pipe)] - \

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

40

DISPLAY_INFO(display)->pipe_offsets[PIPE_A] + \

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

41

DISPLAY_MMIO_BASE(display) + (reg))

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

42

#define _MMIO_TRANS2(display, tran, reg) _MMIO(DISPLAY_INFO(display)->trans_offsets[(tran)] - \

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

43

DISPLAY_INFO(display)->trans_offsets[TRANSCODER_A] + \

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

44

DISPLAY_MMIO_BASE(display) + (reg))

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

45

#define _MMIO_CURSOR2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->cursor_offsets[(pipe)] - \

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

46

DISPLAY_INFO(display)->cursor_offsets[PIPE_A] + \

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

47

DISPLAY_MMIO_BASE(display) + (reg))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1469

#define CHICKEN_TRANS(display, trans) (DISPLAY_VER(display) >= 14 ? _MTL_CHICKEN_TRANS(trans) : _CHICKEN_TRANS(trans))

sys/dev/pci/drm/i915/display/intel_display_reset.c

107

intel_pps_unlock_regs_wa(display);

sys/dev/pci/drm/i915/display/intel_display_reset.c

108

intel_display_driver_init_hw(display);

sys/dev/pci/drm/i915/display/intel_display_reset.c

110

intel_cx0_pll_power_save_wa(display);

sys/dev/pci/drm/i915/display/intel_display_reset.c

111

intel_hpd_init(display);

sys/dev/pci/drm/i915/display/intel_display_reset.c

113

ret = __intel_display_driver_resume(display, state, ctx);

sys/dev/pci/drm/i915/display/intel_display_reset.c

115

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_display_reset.c

118

intel_hpd_poll_disable(display);

sys/dev/pci/drm/i915/display/intel_display_reset.c

125

mutex_unlock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/intel_display_reset.c

18

bool intel_display_reset_test(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_reset.c

20

return display->params.force_reset_modeset_test;

sys/dev/pci/drm/i915/display/intel_display_reset.c

24

bool intel_display_reset_prepare(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_reset.c

27

struct drm_modeset_acquire_ctx *ctx = &display->restore.reset_ctx;

sys/dev/pci/drm/i915/display/intel_display_reset.c

31

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_reset.c

34

if (atomic_read(&display->restore.pending_fb_pin)) {

sys/dev/pci/drm/i915/display/intel_display_reset.c

35

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_display_reset.c

44

mutex_lock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/intel_display_reset.c

47

ret = drm_modeset_lock_all_ctx(display->drm, ctx);

sys/dev/pci/drm/i915/display/intel_display_reset.c

57

state = drm_atomic_helper_duplicate_state(display->drm, ctx);

sys/dev/pci/drm/i915/display/intel_display_reset.c

60

drm_err(display->drm, "Duplicating state failed with %i\n",

sys/dev/pci/drm/i915/display/intel_display_reset.c

65

ret = drm_atomic_helper_disable_all(display->drm, ctx);

sys/dev/pci/drm/i915/display/intel_display_reset.c

67

drm_err(display->drm, "Suspending crtc's failed with %i\n",

sys/dev/pci/drm/i915/display/intel_display_reset.c

73

display->restore.modeset_state = state;

sys/dev/pci/drm/i915/display/intel_display_reset.c

79

void intel_display_reset_finish(struct intel_display *display, bool test_only)

sys/dev/pci/drm/i915/display/intel_display_reset.c

81

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_reset.c

82

struct drm_modeset_acquire_ctx *ctx = &display->restore.reset_ctx;

sys/dev/pci/drm/i915/display/intel_display_reset.c

86

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_display_reset.c

89

state = fetch_and_zero(&display->restore.modeset_state);

sys/dev/pci/drm/i915/display/intel_display_reset.c

98

drm_WARN_ON(display->drm, ret == -EDEADLK);

sys/dev/pci/drm/i915/display/intel_display_reset.c

99

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_display_reset.h

15

bool intel_display_reset_test(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_reset.h

16

bool intel_display_reset_prepare(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_reset.h

18

void intel_display_reset_finish(struct intel_display *display, bool test_only);

sys/dev/pci/drm/i915/display/intel_display_rpm.c

11

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_rpm.c

16

struct ref_tracker *intel_display_rpm_get_raw(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_rpm.c

18

return intel_runtime_pm_get_raw(display_to_rpm(display));

sys/dev/pci/drm/i915/display/intel_display_rpm.c

21

void intel_display_rpm_put_raw(struct intel_display *display, struct ref_tracker *wakeref)

sys/dev/pci/drm/i915/display/intel_display_rpm.c

23

intel_runtime_pm_put_raw(display_to_rpm(display), wakeref);

sys/dev/pci/drm/i915/display/intel_display_rpm.c

26

struct ref_tracker *intel_display_rpm_get(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_rpm.c

28

return intel_runtime_pm_get(display_to_rpm(display));

sys/dev/pci/drm/i915/display/intel_display_rpm.c

31

struct ref_tracker *intel_display_rpm_get_if_in_use(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_rpm.c

33

return intel_runtime_pm_get_if_in_use(display_to_rpm(display));

sys/dev/pci/drm/i915/display/intel_display_rpm.c

36

struct ref_tracker *intel_display_rpm_get_noresume(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_rpm.c

38

return intel_runtime_pm_get_noresume(display_to_rpm(display));

sys/dev/pci/drm/i915/display/intel_display_rpm.c

41

void intel_display_rpm_put(struct intel_display *display, struct ref_tracker *wakeref)

sys/dev/pci/drm/i915/display/intel_display_rpm.c

43

intel_runtime_pm_put(display_to_rpm(display), wakeref);

sys/dev/pci/drm/i915/display/intel_display_rpm.c

46

void intel_display_rpm_put_unchecked(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_rpm.c

48

intel_runtime_pm_put_unchecked(display_to_rpm(display));

sys/dev/pci/drm/i915/display/intel_display_rpm.c

51

bool intel_display_rpm_suspended(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_rpm.c

53

return intel_runtime_pm_suspended(display_to_rpm(display));

sys/dev/pci/drm/i915/display/intel_display_rpm.c

56

void assert_display_rpm_held(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_rpm.c

58

assert_rpm_wakelock_held(display_to_rpm(display));

sys/dev/pci/drm/i915/display/intel_display_rpm.c

61

void intel_display_rpm_assert_block(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_rpm.c

63

disable_rpm_wakeref_asserts(display_to_rpm(display));

sys/dev/pci/drm/i915/display/intel_display_rpm.c

66

void intel_display_rpm_assert_unblock(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_rpm.c

68

enable_rpm_wakeref_asserts(display_to_rpm(display));

sys/dev/pci/drm/i915/display/intel_display_rpm.c

9

static struct intel_runtime_pm *display_to_rpm(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_rpm.h

12

struct ref_tracker *intel_display_rpm_get(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_rpm.h

13

void intel_display_rpm_put(struct intel_display *display, struct ref_tracker *wakeref);

sys/dev/pci/drm/i915/display/intel_display_rpm.h

23

bool intel_display_rpm_suspended(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_rpm.h

25

void assert_display_rpm_held(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_rpm.h

26

void intel_display_rpm_assert_block(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_rpm.h

27

void intel_display_rpm_assert_unblock(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_rpm.h

30

struct ref_tracker *intel_display_rpm_get_raw(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_rpm.h

31

void intel_display_rpm_put_raw(struct intel_display *display, struct ref_tracker *wakeref);

sys/dev/pci/drm/i915/display/intel_display_rpm.h

33

struct ref_tracker *intel_display_rpm_get_if_in_use(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_rpm.h

34

struct ref_tracker *intel_display_rpm_get_noresume(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_rpm.h

35

void intel_display_rpm_put_unchecked(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_rps.c

100

spin_unlock(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_rps.c

103

void ilk_display_rps_irq_handler(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_rps.c

105

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_rps.c

49

struct intel_display *display = to_intel_display(crtc->dev);

sys/dev/pci/drm/i915/display/intel_display_rps.c

55

if (DISPLAY_VER(display) < 6)

sys/dev/pci/drm/i915/display/intel_display_rps.c

76

void intel_display_rps_mark_interactive(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_rps.c

80

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_display_rps.c

89

void ilk_display_rps_enable(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_rps.c

91

spin_lock(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_rps.c

92

ilk_enable_display_irq(display, DE_PCU_EVENT);

sys/dev/pci/drm/i915/display/intel_display_rps.c

93

spin_unlock(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_rps.c

96

void ilk_display_rps_disable(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_rps.c

98

spin_lock(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_display_rps.c

99

ilk_disable_display_irq(display, DE_PCU_EVENT);

sys/dev/pci/drm/i915/display/intel_display_rps.h

19

void intel_display_rps_mark_interactive(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_rps.h

22

void ilk_display_rps_enable(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_rps.h

23

void ilk_display_rps_disable(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_rps.h

24

void ilk_display_rps_irq_handler(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_rps.h

30

static inline void intel_display_rps_mark_interactive(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_rps.h

35

static inline void ilk_display_rps_enable(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_rps.h

38

static inline void ilk_display_rps_disable(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_rps.h

41

static inline void ilk_display_rps_irq_handler(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_snapshot.c

17

struct intel_display *display;

sys/dev/pci/drm/i915/display/intel_display_snapshot.c

27

struct intel_display_snapshot *intel_display_snapshot_capture(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_snapshot.c

35

snapshot->display = display;

sys/dev/pci/drm/i915/display/intel_display_snapshot.c

37

memcpy(&snapshot->info, DISPLAY_INFO(display), sizeof(snapshot->info));

sys/dev/pci/drm/i915/display/intel_display_snapshot.c

38

memcpy(&snapshot->runtime_info, DISPLAY_RUNTIME_INFO(display),

sys/dev/pci/drm/i915/display/intel_display_snapshot.c

43

snapshot->irq = intel_display_irq_snapshot_capture(display);

sys/dev/pci/drm/i915/display/intel_display_snapshot.c

44

snapshot->overlay = intel_overlay_snapshot_capture(display);

sys/dev/pci/drm/i915/display/intel_display_snapshot.c

45

snapshot->dmc = intel_dmc_snapshot_capture(display);

sys/dev/pci/drm/i915/display/intel_display_snapshot.c

53

struct intel_display *display;

sys/dev/pci/drm/i915/display/intel_display_snapshot.c

58

display = snapshot->display;

sys/dev/pci/drm/i915/display/intel_display_snapshot.c

61

intel_display_params_dump(&snapshot->params, display->drm->driver->name, p);

sys/dev/pci/drm/i915/display/intel_display_snapshot.h

11

struct intel_display_snapshot *intel_display_snapshot_capture(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_wa.c

14

static void gen11_display_wa_apply(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_wa.c

17

intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, ICL_DELAY_PMRSP);

sys/dev/pci/drm/i915/display/intel_display_wa.c

20

static void xe_d_display_wa_apply(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_wa.c

23

intel_de_rmw(display, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, 0);

sys/dev/pci/drm/i915/display/intel_display_wa.c

26

static void adlp_display_wa_apply(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_wa.c

29

intel_de_rmw(display, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);

sys/dev/pci/drm/i915/display/intel_display_wa.c

32

intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);

sys/dev/pci/drm/i915/display/intel_display_wa.c

35

void intel_display_wa_apply(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_wa.c

37

if (display->platform.alderlake_p)

sys/dev/pci/drm/i915/display/intel_display_wa.c

38

adlp_display_wa_apply(display);

sys/dev/pci/drm/i915/display/intel_display_wa.c

39

else if (DISPLAY_VER(display) == 12)

sys/dev/pci/drm/i915/display/intel_display_wa.c

40

xe_d_display_wa_apply(display);

sys/dev/pci/drm/i915/display/intel_display_wa.c

41

else if (DISPLAY_VER(display) == 11)

sys/dev/pci/drm/i915/display/intel_display_wa.c

42

gen11_display_wa_apply(display);

sys/dev/pci/drm/i915/display/intel_display_wa.c

50

static bool intel_display_needs_wa_16025573575(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_wa.c

52

return DISPLAY_VERx100(display) == 3000 || DISPLAY_VERx100(display) == 3002;

sys/dev/pci/drm/i915/display/intel_display_wa.c

61

bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name)

sys/dev/pci/drm/i915/display/intel_display_wa.c

65

return intel_display_needs_wa_16023588340(display);

sys/dev/pci/drm/i915/display/intel_display_wa.c

67

return intel_display_needs_wa_16025573575(display);

sys/dev/pci/drm/i915/display/intel_display_wa.c

69

return DISPLAY_VER(display) == 13;

sys/dev/pci/drm/i915/display/intel_display_wa.c

71

drm_WARN(display->drm, 1, "Missing Wa number: %s\n", name);

sys/dev/pci/drm/i915/display/intel_display_wa.h

13

void intel_display_wa_apply(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_wa.h

16

static inline bool intel_display_needs_wa_16023588340(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display_wa.h

21

bool intel_display_needs_wa_16023588340(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_display_wa.h

30

bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name);

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

109

intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg)

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

111

spin_lock(&display->dkl.phy_lock);

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

113

dkl_phy_set_hip_idx(display, reg);

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

114

intel_de_posting_read(display, DKL_REG_MMIO(reg));

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

116

spin_unlock(&display->dkl.phy_lock);

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

18

void intel_dkl_phy_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

20

mtx_init(&display->dkl.phy_lock, IPL_NONE);

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

24

dkl_phy_set_hip_idx(struct intel_display *display, struct intel_dkl_phy_reg reg)

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

28

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

32

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

47

intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg)

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

51

spin_lock(&display->dkl.phy_lock);

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

53

dkl_phy_set_hip_idx(display, reg);

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

54

val = intel_de_read(display, DKL_REG_MMIO(reg));

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

56

spin_unlock(&display->dkl.phy_lock);

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

70

intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val)

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

72

spin_lock(&display->dkl.phy_lock);

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

74

dkl_phy_set_hip_idx(display, reg);

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

75

intel_de_write(display, DKL_REG_MMIO(reg), val);

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

77

spin_unlock(&display->dkl.phy_lock);

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

91

intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set)

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

93

spin_lock(&display->dkl.phy_lock);

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

95

dkl_phy_set_hip_idx(display, reg);

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

96

intel_de_rmw(display, DKL_REG_MMIO(reg), clear, set);

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

98

spin_unlock(&display->dkl.phy_lock);

sys/dev/pci/drm/i915/display/intel_dkl_phy.h

15

void intel_dkl_phy_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dkl_phy.h

17

intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg);

sys/dev/pci/drm/i915/display/intel_dkl_phy.h

19

intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val);

sys/dev/pci/drm/i915/display/intel_dkl_phy.h

21

intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set);

sys/dev/pci/drm/i915/display/intel_dkl_phy.h

23

intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg);

sys/dev/pci/drm/i915/display/intel_dmc.c

1003

} else if (DISPLAY_VER(display) >= 13) {

sys/dev/pci/drm/i915/display/intel_dmc.c

1006

} else if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_dmc.c

101

const char *p = dmc_firmware_param(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

1010

drm_warn(display->drm, "Unknown mmio range for sanity check");

sys/dev/pci/drm/i915/display/intel_dmc.c

1026

struct intel_display *display = dmc->display;

sys/dev/pci/drm/i915/display/intel_dmc.c

1074

drm_err(display->drm, "Unknown DMC fw header version: %u\n",

sys/dev/pci/drm/i915/display/intel_dmc.c

1080

drm_err(display->drm, "DMC firmware has wrong dmc header length "

sys/dev/pci/drm/i915/display/intel_dmc.c

1087

drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count);

sys/dev/pci/drm/i915/display/intel_dmc.c

1093

drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n");

sys/dev/pci/drm/i915/display/intel_dmc.c

1097

drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id);

sys/dev/pci/drm/i915/display/intel_dmc.c

1109

if (!fixup_dmc_evt(display, dmc_id,

sys/dev/pci/drm/i915/display/intel_dmc.c

1114

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dmc.c

1118

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dmc.c

1125

drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n",

sys/dev/pci/drm/i915/display/intel_dmc.c

1127

is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" :

sys/dev/pci/drm/i915/display/intel_dmc.c

1128

is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "",

sys/dev/pci/drm/i915/display/intel_dmc.c

1129

disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i],

sys/dev/pci/drm/i915/display/intel_dmc.c

1143

drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size);

sys/dev/pci/drm/i915/display/intel_dmc.c

1158

drm_err(display->drm, "Truncated DMC firmware, refusing.\n");

sys/dev/pci/drm/i915/display/intel_dmc.c

1168

struct intel_display *display = dmc->display;

sys/dev/pci/drm/i915/display/intel_dmc.c

1181

drm_err(display->drm, "DMC firmware has unknown header version %u\n",

sys/dev/pci/drm/i915/display/intel_dmc.c

1195

drm_err(display->drm, "DMC firmware has wrong package header length "

sys/dev/pci/drm/i915/display/intel_dmc.c

1213

drm_err(display->drm, "Truncated DMC firmware, refusing.\n");

sys/dev/pci/drm/i915/display/intel_dmc.c

1222

struct intel_display *display = dmc->display;

sys/dev/pci/drm/i915/display/intel_dmc.c

1225

drm_err(display->drm, "Truncated DMC firmware, refusing.\n");

sys/dev/pci/drm/i915/display/intel_dmc.c

1231

drm_err(display->drm, "DMC firmware has wrong CSS header length "

sys/dev/pci/drm/i915/display/intel_dmc.c

1244

struct intel_display *display = dmc->display;

sys/dev/pci/drm/i915/display/intel_dmc.c

1249

const struct stepping_info *si = intel_get_stepping_info(display, &display_info);

sys/dev/pci/drm/i915/display/intel_dmc.c

1279

drm_err(display->drm, "Reading beyond the fw_size\n");

sys/dev/pci/drm/i915/display/intel_dmc.c

1287

if (!intel_dmc_has_payload(display)) {

sys/dev/pci/drm/i915/display/intel_dmc.c

1288

drm_err(display->drm, "DMC firmware main program not found\n");

sys/dev/pci/drm/i915/display/intel_dmc.c

1295

static void intel_dmc_runtime_pm_get(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc.c

1297

drm_WARN_ON(display->drm, display->dmc.wakeref);

sys/dev/pci/drm/i915/display/intel_dmc.c

1298

display->dmc.wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT);

sys/dev/pci/drm/i915/display/intel_dmc.c

1301

static void intel_dmc_runtime_pm_put(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc.c

1304

fetch_and_zero(&display->dmc.wakeref);

sys/dev/pci/drm/i915/display/intel_dmc.c

1306

intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);

sys/dev/pci/drm/i915/display/intel_dmc.c

1309

static const char *dmc_fallback_path(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc.c

1311

if (display->platform.alderlake_p)

sys/dev/pci/drm/i915/display/intel_dmc.c

1320

struct intel_display *display = dmc->display;

sys/dev/pci/drm/i915/display/intel_dmc.c

1325

err = request_firmware(&fw, dmc->fw_path, display->drm->dev);

sys/dev/pci/drm/i915/display/intel_dmc.c

1327

if (err == -ENOENT && !dmc_firmware_param(display)) {

sys/dev/pci/drm/i915/display/intel_dmc.c

1328

fallback_path = dmc_fallback_path(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

1330

drm_dbg_kms(display->drm, "%s not found, falling back to %s\n",

sys/dev/pci/drm/i915/display/intel_dmc.c

1332

err = request_firmware(&fw, fallback_path, display->drm->dev);

sys/dev/pci/drm/i915/display/intel_dmc.c

1339

drm_notice(display->drm,

sys/dev/pci/drm/i915/display/intel_dmc.c

1343

drm_notice(display->drm, "DMC firmware homepage: %s",

sys/dev/pci/drm/i915/display/intel_dmc.c

1351

drm_notice(display->drm,

sys/dev/pci/drm/i915/display/intel_dmc.c

1357

intel_dmc_load_program(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

1358

intel_dmc_runtime_pm_put(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

1360

drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n",

sys/dev/pci/drm/i915/display/intel_dmc.c

1375

void intel_dmc_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc.c

1379

if (!HAS_DMC(display))

sys/dev/pci/drm/i915/display/intel_dmc.c

1390

intel_dmc_runtime_pm_get(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

1396

dmc->display = display;

sys/dev/pci/drm/i915/display/intel_dmc.c

1400

dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size);

sys/dev/pci/drm/i915/display/intel_dmc.c

1402

if (dmc_firmware_param_disabled(display)) {

sys/dev/pci/drm/i915/display/intel_dmc.c

1403

drm_info(display->drm, "Disabling DMC firmware and runtime PM\n");

sys/dev/pci/drm/i915/display/intel_dmc.c

1407

if (dmc_firmware_param(display))

sys/dev/pci/drm/i915/display/intel_dmc.c

1408

dmc->fw_path = dmc_firmware_param(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

1411

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dmc.c

1416

display->dmc.dmc = dmc;

sys/dev/pci/drm/i915/display/intel_dmc.c

1418

drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path);

sys/dev/pci/drm/i915/display/intel_dmc.c

1419

queue_work(display->wq.unordered, &dmc->work);

sys/dev/pci/drm/i915/display/intel_dmc.c

1435

void intel_dmc_suspend(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc.c

1437

struct intel_dmc *dmc = display_to_dmc(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

1439

if (!HAS_DMC(display))

sys/dev/pci/drm/i915/display/intel_dmc.c

1446

if (!intel_dmc_has_payload(display))

sys/dev/pci/drm/i915/display/intel_dmc.c

1447

intel_dmc_runtime_pm_put(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

1450

void intel_dmc_wait_fw_load(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc.c

1452

struct intel_dmc *dmc = display_to_dmc(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

1454

if (!HAS_DMC(display))

sys/dev/pci/drm/i915/display/intel_dmc.c

1468

void intel_dmc_resume(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc.c

1470

if (!HAS_DMC(display))

sys/dev/pci/drm/i915/display/intel_dmc.c

1477

if (!intel_dmc_has_payload(display))

sys/dev/pci/drm/i915/display/intel_dmc.c

1478

intel_dmc_runtime_pm_get(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

1488

void intel_dmc_fini(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc.c

1490

struct intel_dmc *dmc = display_to_dmc(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

1493

if (!HAS_DMC(display))

sys/dev/pci/drm/i915/display/intel_dmc.c

1496

intel_dmc_suspend(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

1497

drm_WARN_ON(display->drm, display->dmc.wakeref);

sys/dev/pci/drm/i915/display/intel_dmc.c

1504

display->dmc.dmc = NULL;

sys/dev/pci/drm/i915/display/intel_dmc.c

1514

struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc.c

1516

struct intel_dmc *dmc = display_to_dmc(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

1519

if (!HAS_DMC(display))

sys/dev/pci/drm/i915/display/intel_dmc.c

1527

snapshot->loaded = intel_dmc_has_payload(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

1547

void intel_dmc_update_dc6_allowed_count(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dmc.c

1550

struct intel_dmc *dmc = display_to_dmc(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

1553

if (DISPLAY_VER(dmc->display) < 14)

sys/dev/pci/drm/i915/display/intel_dmc.c

1556

dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT);

sys/dev/pci/drm/i915/display/intel_dmc.c

1564

static bool intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count)

sys/dev/pci/drm/i915/display/intel_dmc.c

1566

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_dmc.c

1567

struct intel_dmc *dmc = display_to_dmc(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

1570

if (DISPLAY_VER(display) < 14)

sys/dev/pci/drm/i915/display/intel_dmc.c

1576

intel_dmc_update_dc6_allowed_count(display, false);

sys/dev/pci/drm/i915/display/intel_dmc.c

1588

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/intel_dmc.c

1589

struct intel_dmc *dmc = display_to_dmc(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

1594

if (!HAS_DMC(display))

sys/dev/pci/drm/i915/display/intel_dmc.c

1597

wakeref = intel_display_rpm_get(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

1601

str_yes_no(intel_dmc_has_payload(display)));

sys/dev/pci/drm/i915/display/intel_dmc.c

1604

str_yes_no(DISPLAY_VER(display) >= 12));

sys/dev/pci/drm/i915/display/intel_dmc.c

1606

str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA)));

sys/dev/pci/drm/i915/display/intel_dmc.c

1608

str_yes_no(display->platform.alderlake_p ||

sys/dev/pci/drm/i915/display/intel_dmc.c

1609

DISPLAY_VER(display) >= 14));

sys/dev/pci/drm/i915/display/intel_dmc.c

1611

str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB)));

sys/dev/pci/drm/i915/display/intel_dmc.c

1613

if (!intel_dmc_has_payload(display))

sys/dev/pci/drm/i915/display/intel_dmc.c

1619

if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_dmc.c

1622

if (display->platform.dgfx || DISPLAY_VER(display) >= 14) {

sys/dev/pci/drm/i915/display/intel_dmc.c

1632

intel_de_read(display, dc3co_reg));

sys/dev/pci/drm/i915/display/intel_dmc.c

1634

dc5_reg = display->platform.broxton ? BXT_DMC_DC3_DC5_COUNT :

sys/dev/pci/drm/i915/display/intel_dmc.c

1636

if (!display->platform.geminilake && !display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_dmc.c

1640

seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));

sys/dev/pci/drm/i915/display/intel_dmc.c

1642

if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count))

sys/dev/pci/drm/i915/display/intel_dmc.c

1647

intel_de_read(display, dc6_reg));

sys/dev/pci/drm/i915/display/intel_dmc.c

1650

intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));

sys/dev/pci/drm/i915/display/intel_dmc.c

1654

intel_de_read(display, DMC_SSP_BASE));

sys/dev/pci/drm/i915/display/intel_dmc.c

1655

seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL));

sys/dev/pci/drm/i915/display/intel_dmc.c

1657

intel_display_rpm_put(display, wakeref);

sys/dev/pci/drm/i915/display/intel_dmc.c

1666

void intel_dmc_debugfs_register(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc.c

1668

debugfs_create_file("i915_dmc_info", 0444, display->drm->debugfs_root,

sys/dev/pci/drm/i915/display/intel_dmc.c

1669

display, &intel_dmc_debugfs_status_fops);

sys/dev/pci/drm/i915/display/intel_dmc.c

1672

void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_dmc.c

1674

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_dmc.c

1677

if (DISPLAY_VER(display) >= 20) {

sys/dev/pci/drm/i915/display/intel_dmc.c

1678

tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe));

sys/dev/pci/drm/i915/display/intel_dmc.c

1679

intel_de_write(display, PIPEDMC_INTERRUPT(pipe), tmp);

sys/dev/pci/drm/i915/display/intel_dmc.c

1682

spin_lock(&display->drm->event_lock);

sys/dev/pci/drm/i915/display/intel_dmc.c

1695

spin_unlock(&display->drm->event_lock);

sys/dev/pci/drm/i915/display/intel_dmc.c

1699

drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC ATS fault\n",

sys/dev/pci/drm/i915/display/intel_dmc.c

1702

drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC GTT fault\n",

sys/dev/pci/drm/i915/display/intel_dmc.c

1705

drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC error\n",

sys/dev/pci/drm/i915/display/intel_dmc.c

1709

int_vector = intel_de_read(display, PIPEDMC_STATUS(pipe)) & PIPEDMC_INT_VECTOR_MASK;

sys/dev/pci/drm/i915/display/intel_dmc.c

1711

drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC interrupt vector 0x%x\n",

sys/dev/pci/drm/i915/display/intel_dmc.c

1718

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_dmc.c

1721

dmc_configure_event(display, dmc_id, event, true);

sys/dev/pci/drm/i915/display/intel_dmc.c

1727

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_dmc.c

1730

dmc_configure_event(display, dmc_id, event, false);

sys/dev/pci/drm/i915/display/intel_dmc.c

1735

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_dmc.c

1736

struct intel_dmc *dmc = display_to_dmc(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

185

static const char *dmc_firmware_default(struct intel_display *display, u32 *size)

sys/dev/pci/drm/i915/display/intel_dmc.c

189

if (DISPLAY_VERx100(display) == 3002) {

sys/dev/pci/drm/i915/display/intel_dmc.c

192

} else if (DISPLAY_VERx100(display) == 3000) {

sys/dev/pci/drm/i915/display/intel_dmc.c

195

} else if (DISPLAY_VERx100(display) == 2000) {

sys/dev/pci/drm/i915/display/intel_dmc.c

198

} else if (DISPLAY_VERx100(display) == 1401) {

sys/dev/pci/drm/i915/display/intel_dmc.c

201

} else if (DISPLAY_VERx100(display) == 1400) {

sys/dev/pci/drm/i915/display/intel_dmc.c

204

} else if (display->platform.dg2) {

sys/dev/pci/drm/i915/display/intel_dmc.c

207

} else if (display->platform.alderlake_p) {

sys/dev/pci/drm/i915/display/intel_dmc.c

210

} else if (display->platform.alderlake_s) {

sys/dev/pci/drm/i915/display/intel_dmc.c

213

} else if (display->platform.dg1) {

sys/dev/pci/drm/i915/display/intel_dmc.c

216

} else if (display->platform.rocketlake) {

sys/dev/pci/drm/i915/display/intel_dmc.c

219

} else if (display->platform.tigerlake) {

sys/dev/pci/drm/i915/display/intel_dmc.c

222

} else if (DISPLAY_VER(display) == 11) {

sys/dev/pci/drm/i915/display/intel_dmc.c

225

} else if (display->platform.geminilake) {

sys/dev/pci/drm/i915/display/intel_dmc.c

228

} else if (display->platform.kabylake ||

sys/dev/pci/drm/i915/display/intel_dmc.c

229

display->platform.coffeelake ||

sys/dev/pci/drm/i915/display/intel_dmc.c

230

display->platform.cometlake) {

sys/dev/pci/drm/i915/display/intel_dmc.c

233

} else if (display->platform.skylake) {

sys/dev/pci/drm/i915/display/intel_dmc.c

236

} else if (display->platform.broxton) {

sys/dev/pci/drm/i915/display/intel_dmc.c

403

static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id)

sys/dev/pci/drm/i915/display/intel_dmc.c

405

struct intel_dmc *dmc = display_to_dmc(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

410

bool intel_dmc_has_payload(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc.c

412

return has_dmc_id_fw(display, DMC_FW_MAIN);

sys/dev/pci/drm/i915/display/intel_dmc.c

416

intel_get_stepping_info(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dmc.c

419

const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(display));

sys/dev/pci/drm/i915/display/intel_dmc.c

426

static void gen9_set_dc_state_debugmask(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc.c

429

intel_de_rmw(display, DC_STATE_DEBUG, 0,

sys/dev/pci/drm/i915/display/intel_dmc.c

431

intel_de_posting_read(display, DC_STATE_DEBUG);

sys/dev/pci/drm/i915/display/intel_dmc.c

434

static void disable_event_handler(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dmc.c

437

intel_de_write(display, ctl_reg,

sys/dev/pci/drm/i915/display/intel_dmc.c

442

intel_de_write(display, htp_reg, 0);

sys/dev/pci/drm/i915/display/intel_dmc.c

445

static void disable_all_event_handlers(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dmc.c

451

if (DISPLAY_VER(display) < 12)

sys/dev/pci/drm/i915/display/intel_dmc.c

454

if (!has_dmc_id_fw(display, dmc_id))

sys/dev/pci/drm/i915/display/intel_dmc.c

458

disable_event_handler(display,

sys/dev/pci/drm/i915/display/intel_dmc.c

459

DMC_EVT_CTL(display, dmc_id, handler),

sys/dev/pci/drm/i915/display/intel_dmc.c

460

DMC_EVT_HTP(display, dmc_id, handler));

sys/dev/pci/drm/i915/display/intel_dmc.c

463

static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable)

sys/dev/pci/drm/i915/display/intel_dmc.c

476

intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe),

sys/dev/pci/drm/i915/display/intel_dmc.c

480

intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe),

sys/dev/pci/drm/i915/display/intel_dmc.c

484

static void mtl_pipedmc_clock_gating_wa(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc.c

491

intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0,

sys/dev/pci/drm/i915/display/intel_dmc.c

496

static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable)

sys/dev/pci/drm/i915/display/intel_dmc.c

498

if (display->platform.meteorlake && enable)

sys/dev/pci/drm/i915/display/intel_dmc.c

499

mtl_pipedmc_clock_gating_wa(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

500

else if (DISPLAY_VER(display) == 13)

sys/dev/pci/drm/i915/display/intel_dmc.c

501

adlp_pipedmc_clock_gating_wa(display, enable);

sys/dev/pci/drm/i915/display/intel_dmc.c

504

static u32 pipedmc_interrupt_mask(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc.c

524

static bool is_dmc_evt_ctl_reg(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dmc.c

528

u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0));

sys/dev/pci/drm/i915/display/intel_dmc.c

529

u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));

sys/dev/pci/drm/i915/display/intel_dmc.c

534

static bool is_dmc_evt_htp_reg(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dmc.c

538

u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0));

sys/dev/pci/drm/i915/display/intel_dmc.c

539

u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));

sys/dev/pci/drm/i915/display/intel_dmc.c

544

static bool is_event_handler(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dmc.c

549

return is_dmc_evt_ctl_reg(display, dmc_id, reg) &&

sys/dev/pci/drm/i915/display/intel_dmc.c

553

static bool fixup_dmc_evt(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dmc.c

558

if (!is_dmc_evt_ctl_reg(display, dmc_id, reg_ctl))

sys/dev/pci/drm/i915/display/intel_dmc.c

561

if (!is_dmc_evt_htp_reg(display, dmc_id, reg_htp))

sys/dev/pci/drm/i915/display/intel_dmc.c

565

if (i915_mmio_reg_offset(reg_ctl) - i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)) !=

sys/dev/pci/drm/i915/display/intel_dmc.c

566

i915_mmio_reg_offset(reg_htp) - i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)))

sys/dev/pci/drm/i915/display/intel_dmc.c

573

if (display->platform.alderlake_s && dmc_id == DMC_FW_MAIN &&

sys/dev/pci/drm/i915/display/intel_dmc.c

574

is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) {

sys/dev/pci/drm/i915/display/intel_dmc.c

583

static bool disable_dmc_evt(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dmc.c

587

if (!is_dmc_evt_ctl_reg(display, dmc_id, reg))

sys/dev/pci/drm/i915/display/intel_dmc.c

595

if (display->platform.tigerlake &&

sys/dev/pci/drm/i915/display/intel_dmc.c

596

is_event_handler(display, dmc_id, MAINDMC_EVENT_CLK_MSEC, reg, data))

sys/dev/pci/drm/i915/display/intel_dmc.c

600

if ((display->platform.tigerlake || display->platform.alderlake_s) &&

sys/dev/pci/drm/i915/display/intel_dmc.c

601

is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg, data))

sys/dev/pci/drm/i915/display/intel_dmc.c

607

static u32 dmc_mmiodata(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dmc.c

611

if (disable_dmc_evt(display, dmc_id,

sys/dev/pci/drm/i915/display/intel_dmc.c

619

static void dmc_load_mmio(struct intel_display *display, enum intel_dmc_id dmc_id)

sys/dev/pci/drm/i915/display/intel_dmc.c

621

struct intel_dmc *dmc = display_to_dmc(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

625

intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i],

sys/dev/pci/drm/i915/display/intel_dmc.c

626

dmc_mmiodata(display, dmc, dmc_id, i));

sys/dev/pci/drm/i915/display/intel_dmc.c

630

static void dmc_load_program(struct intel_display *display, enum intel_dmc_id dmc_id)

sys/dev/pci/drm/i915/display/intel_dmc.c

632

struct intel_dmc *dmc = display_to_dmc(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

635

disable_all_event_handlers(display, dmc_id);

sys/dev/pci/drm/i915/display/intel_dmc.c

640

intel_de_write_fw(display,

sys/dev/pci/drm/i915/display/intel_dmc.c

647

dmc_load_mmio(display, dmc_id);

sys/dev/pci/drm/i915/display/intel_dmc.c

65

struct intel_display *display;

sys/dev/pci/drm/i915/display/intel_dmc.c

650

static void assert_dmc_loaded(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dmc.c

653

struct intel_dmc *dmc = display_to_dmc(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

657

if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))

sys/dev/pci/drm/i915/display/intel_dmc.c

660

found = intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, 0));

sys/dev/pci/drm/i915/display/intel_dmc.c

663

drm_WARN(display->drm, found != expected,

sys/dev/pci/drm/i915/display/intel_dmc.c

670

found = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_dmc.c

671

expected = dmc_mmiodata(display, dmc, dmc_id, i);

sys/dev/pci/drm/i915/display/intel_dmc.c

674

if (is_dmc_evt_ctl_reg(display, dmc_id, reg)) {

sys/dev/pci/drm/i915/display/intel_dmc.c

679

drm_WARN(display->drm, found != expected,

sys/dev/pci/drm/i915/display/intel_dmc.c

685

void assert_main_dmc_loaded(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc.c

687

assert_dmc_loaded(display, DMC_FW_MAIN);

sys/dev/pci/drm/i915/display/intel_dmc.c

690

static bool need_pipedmc_load_program(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc.c

693

return DISPLAY_VER(display) == 12;

sys/dev/pci/drm/i915/display/intel_dmc.c

696

static bool need_pipedmc_load_mmio(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_dmc.c

703

if (DISPLAY_VER(display) == 30)

sys/dev/pci/drm/i915/display/intel_dmc.c

712

if (DISPLAY_VER(display) == 20)

sys/dev/pci/drm/i915/display/intel_dmc.c

719

if (display->platform.battlemage)

sys/dev/pci/drm/i915/display/intel_dmc.c

728

if (display->platform.dg2)

sys/dev/pci/drm/i915/display/intel_dmc.c

736

if (IS_DISPLAY_VER(display, 13, 14))

sys/dev/pci/drm/i915/display/intel_dmc.c

744

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dmc.c

751

if (DISPLAY_VER(display) == 12 && crtc_state->has_psr)

sys/dev/pci/drm/i915/display/intel_dmc.c

759

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dmc.c

764

if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))

sys/dev/pci/drm/i915/display/intel_dmc.c

772

if (need_pipedmc_load_program(display))

sys/dev/pci/drm/i915/display/intel_dmc.c

773

dmc_load_program(display, dmc_id);

sys/dev/pci/drm/i915/display/intel_dmc.c

774

else if (need_pipedmc_load_mmio(display, pipe))

sys/dev/pci/drm/i915/display/intel_dmc.c

775

dmc_load_mmio(display, dmc_id);

sys/dev/pci/drm/i915/display/intel_dmc.c

777

assert_dmc_loaded(display, dmc_id);

sys/dev/pci/drm/i915/display/intel_dmc.c

779

if (DISPLAY_VER(display) >= 20) {

sys/dev/pci/drm/i915/display/intel_dmc.c

780

intel_flipq_reset(display, pipe);

sys/dev/pci/drm/i915/display/intel_dmc.c

782

intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display));

sys/dev/pci/drm/i915/display/intel_dmc.c

783

intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~pipedmc_interrupt_mask(display));

sys/dev/pci/drm/i915/display/intel_dmc.c

786

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_dmc.c

787

intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe));

sys/dev/pci/drm/i915/display/intel_dmc.c

789

intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE);

sys/dev/pci/drm/i915/display/intel_dmc.c

794

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dmc.c

799

if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))

sys/dev/pci/drm/i915/display/intel_dmc.c

802

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_dmc.c

803

intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0);

sys/dev/pci/drm/i915/display/intel_dmc.c

805

intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_dmc.c

807

if (DISPLAY_VER(display) >= 20) {

sys/dev/pci/drm/i915/display/intel_dmc.c

808

intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~0);

sys/dev/pci/drm/i915/display/intel_dmc.c

809

intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display));

sys/dev/pci/drm/i915/display/intel_dmc.c

811

intel_flipq_reset(display, pipe);

sys/dev/pci/drm/i915/display/intel_dmc.c

815

static void dmc_configure_event(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dmc.c

820

struct intel_dmc *dmc = display_to_dmc(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

828

if (!is_event_handler(display, dmc_id, event_id, reg, data))

sys/dev/pci/drm/i915/display/intel_dmc.c

831

intel_de_write(display, reg, enable ? data : dmc_evt_ctl_disable());

sys/dev/pci/drm/i915/display/intel_dmc.c

835

drm_WARN_ONCE(display->drm, num_handlers != 1,

sys/dev/pci/drm/i915/display/intel_dmc.c

849

void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_dmc.c

852

intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(pipe),

sys/dev/pci/drm/i915/display/intel_dmc.c

867

void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dmc.c

87

static struct intel_dmc *display_to_dmc(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc.c

872

dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_VBLANK, enable);

sys/dev/pci/drm/i915/display/intel_dmc.c

883

void intel_dmc_load_program(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc.c

885

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_dmc.c

888

if (!intel_dmc_has_payload(display))

sys/dev/pci/drm/i915/display/intel_dmc.c

89

return display->dmc.dmc;

sys/dev/pci/drm/i915/display/intel_dmc.c

891

assert_display_rpm_held(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

893

pipedmc_clock_gating_wa(display, true);

sys/dev/pci/drm/i915/display/intel_dmc.c

896

dmc_load_program(display, dmc_id);

sys/dev/pci/drm/i915/display/intel_dmc.c

897

assert_dmc_loaded(display, dmc_id);

sys/dev/pci/drm/i915/display/intel_dmc.c

900

if (DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/intel_dmc.c

901

intel_de_write(display, DMC_FQ_W2_PTS_CFG_SEL,

sys/dev/pci/drm/i915/display/intel_dmc.c

909

gen9_set_dc_state_debugmask(display);

sys/dev/pci/drm/i915/display/intel_dmc.c

911

pipedmc_clock_gating_wa(display, false);

sys/dev/pci/drm/i915/display/intel_dmc.c

92

static const char *dmc_firmware_param(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc.c

921

void intel_dmc_disable_program(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc.c

925

if (!intel_dmc_has_payload(display))

sys/dev/pci/drm/i915/display/intel_dmc.c

928

pipedmc_clock_gating_wa(display, true);

sys/dev/pci/drm/i915/display/intel_dmc.c

931

disable_all_event_handlers(display, dmc_id);

sys/dev/pci/drm/i915/display/intel_dmc.c

933

pipedmc_clock_gating_wa(display, false);

sys/dev/pci/drm/i915/display/intel_dmc.c

94

const char *p = display->params.dmc_firmware_path;

sys/dev/pci/drm/i915/display/intel_dmc.c

963

struct intel_display *display = dmc->display;

sys/dev/pci/drm/i915/display/intel_dmc.c

971

drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id);

sys/dev/pci/drm/i915/display/intel_dmc.c

99

static bool dmc_firmware_param_disabled(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc.c

993

struct intel_display *display = dmc->display;

sys/dev/pci/drm/i915/display/intel_dmc.h

19

void intel_dmc_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dmc.h

20

void intel_dmc_load_program(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dmc.h

21

void intel_dmc_wait_fw_load(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dmc.h

22

void intel_dmc_disable_program(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dmc.h

25

void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_dmc.h

27

void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dmc.h

29

void intel_dmc_fini(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dmc.h

30

void intel_dmc_suspend(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dmc.h

31

void intel_dmc_resume(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dmc.h

32

bool intel_dmc_has_payload(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dmc.h

33

void intel_dmc_debugfs_register(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dmc.h

35

struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dmc.h

37

void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool start_tracking);

sys/dev/pci/drm/i915/display/intel_dmc.h

39

void assert_main_dmc_loaded(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dmc.h

41

void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_dmc.h

49

void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

155

static void __intel_dmc_wl_release(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

157

struct intel_dmc_wl *wl = &display->wl;

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

161

queue_delayed_work(display->wq.unordered, &wl->work,

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

169

struct intel_display *display =

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

182

__intel_de_rmw_nowl(display, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 0);

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

184

if (__intel_de_wait_for_register_atomic_nowl(display, DMC_WAKELOCK1_CTL,

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

197

static void __intel_dmc_wl_take(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

199

struct intel_dmc_wl *wl = &display->wl;

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

210

__intel_de_rmw_nowl(display, DMC_WAKELOCK1_CTL, 0,

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

217

if (__intel_de_wait_for_register_atomic_nowl(display, DMC_WAKELOCK1_CTL,

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

243

static bool intel_dmc_wl_check_range(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

249

if (display->params.enable_dmc_wl == ENABLE_DMC_WL_ANY_REGISTER)

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

281

static bool __intel_dmc_wl_supported(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

283

return display->params.enable_dmc_wl;

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

286

static void intel_dmc_wl_sanitize_param(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

290

if (!HAS_DMC_WAKELOCK(display)) {

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

291

display->params.enable_dmc_wl = ENABLE_DMC_WL_DISABLED;

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

292

} else if (display->params.enable_dmc_wl < 0) {

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

293

if (DISPLAY_VER(display) >= 30)

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

294

display->params.enable_dmc_wl = ENABLE_DMC_WL_ENABLED;

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

296

display->params.enable_dmc_wl = ENABLE_DMC_WL_DISABLED;

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

297

} else if (display->params.enable_dmc_wl >= ENABLE_DMC_WL_MAX) {

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

298

display->params.enable_dmc_wl = ENABLE_DMC_WL_ENABLED;

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

301

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

302

display->params.enable_dmc_wl < 0 ||

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

303

display->params.enable_dmc_wl >= ENABLE_DMC_WL_MAX);

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

305

switch (display->params.enable_dmc_wl) {

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

323

drm_dbg_kms(display->drm, "Sanitized enable_dmc_wl value: %d (%s)\n",

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

324

display->params.enable_dmc_wl, desc);

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

327

void intel_dmc_wl_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

329

struct intel_dmc_wl *wl = &display->wl;

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

331

intel_dmc_wl_sanitize_param(display);

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

333

if (!display->params.enable_dmc_wl)

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

339

display->params.enable_dmc_wl == ENABLE_DMC_WL_ALWAYS_LOCKED ? 1 : 0);

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

343

void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state)

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

345

struct intel_dmc_wl *wl = &display->wl;

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

348

if (!__intel_dmc_wl_supported(display))

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

355

if (drm_WARN_ON(display->drm, wl->enabled))

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

363

__intel_de_rmw_nowl(display, DMC_WAKELOCK_CFG, 0, DMC_WAKELOCK_CFG_ENABLE);

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

382

__intel_dmc_wl_take(display);

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

389

void intel_dmc_wl_disable(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

391

struct intel_dmc_wl *wl = &display->wl;

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

394

if (!__intel_dmc_wl_supported(display))

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

397

intel_dmc_wl_flush_release_work(display);

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

401

if (drm_WARN_ON(display->drm, !wl->enabled))

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

405

__intel_de_rmw_nowl(display, DMC_WAKELOCK_CFG, DMC_WAKELOCK_CFG_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

417

__intel_de_rmw_nowl(display, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 0);

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

425

void intel_dmc_wl_flush_release_work(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

427

struct intel_dmc_wl *wl = &display->wl;

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

429

if (!__intel_dmc_wl_supported(display))

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

435

void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg)

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

437

struct intel_dmc_wl *wl = &display->wl;

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

440

if (!__intel_dmc_wl_supported(display))

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

446

!intel_dmc_wl_check_range(display, reg, wl->dc_state))

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

462

__intel_dmc_wl_take(display);

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

468

void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg)

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

470

struct intel_dmc_wl *wl = &display->wl;

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

473

if (!__intel_dmc_wl_supported(display))

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

479

!intel_dmc_wl_check_range(display, reg, wl->dc_state))

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

490

__intel_dmc_wl_release(display);

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

499

void intel_dmc_wl_get_noreg(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

501

intel_dmc_wl_get(display, INVALID_MMIO_REG);

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

504

void intel_dmc_wl_put_noreg(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

506

intel_dmc_wl_put(display, INVALID_MMIO_REG);

sys/dev/pci/drm/i915/display/intel_dmc_wl.h

32

void intel_dmc_wl_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dmc_wl.h

33

void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state);

sys/dev/pci/drm/i915/display/intel_dmc_wl.h

34

void intel_dmc_wl_disable(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dmc_wl.h

35

void intel_dmc_wl_flush_release_work(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dmc_wl.h

36

void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg);

sys/dev/pci/drm/i915/display/intel_dmc_wl.h

37

void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg);

sys/dev/pci/drm/i915/display/intel_dmc_wl.h

38

void intel_dmc_wl_get_noreg(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dmc_wl.h

39

void intel_dmc_wl_put_noreg(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dp.c

1005

joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, mode_clock,

sys/dev/pci/drm/i915/display/intel_dp.c

1009

bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(display, bits_per_pixel, pipe_bpp);

sys/dev/pci/drm/i915/display/intel_dp.c

1018

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp.c

1033

if (mode_clock >= ((display->cdclk.max_cdclk_freq * 85) / 100))

sys/dev/pci/drm/i915/display/intel_dp.c

1038

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

1057

(!HAS_DSC_3ENGINES(display) || num_joined_pipes != 4))

sys/dev/pci/drm/i915/display/intel_dp.c

1079

drm_dbg_kms(display->drm, "Unsupported Slice Count %d\n",

sys/dev/pci/drm/i915/display/intel_dp.c

1087

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

1099

return !HAS_GMCH(display) && !display->platform.ironlake;

sys/dev/pci/drm/i915/display/intel_dp.c

1103

return DISPLAY_VER(display) >= 11;

sys/dev/pci/drm/i915/display/intel_dp.c

1163

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp.c

1175

drm_dbg_kms(display->drm, "Cannot force DSC output format\n");

sys/dev/pci/drm/i915/display/intel_dp.c

1189

drm_WARN_ON(display->drm, !source_can_output(intel_dp, output_format));

sys/dev/pci/drm/i915/display/intel_dp.c

1240

static bool intel_dp_hdisplay_bad(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dp.c

1256

return hdisplay == 4096 && !HAS_DDI(display);

sys/dev/pci/drm/i915/display/intel_dp.c

1357

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

1365

hdisplay_limit = DISPLAY_VER(display) >= 30 ? 6144 : 5120;

sys/dev/pci/drm/i915/display/intel_dp.c

1367

return clock > num_joined_pipes * display->cdclk.max_dotclk_freq ||

sys/dev/pci/drm/i915/display/intel_dp.c

1375

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

1380

if (HAS_ULTRAJOINER(display) &&

sys/dev/pci/drm/i915/display/intel_dp.c

1384

if ((HAS_BIGJOINER(display) || HAS_UNCOMPRESSED_JOINER(display)) &&

sys/dev/pci/drm/i915/display/intel_dp.c

1393

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp.c

1395

if (!HAS_DSC(display))

sys/dev/pci/drm/i915/display/intel_dp.c

1398

if (connector->mst.dp && !HAS_DSC_MST(display))

sys/dev/pci/drm/i915/display/intel_dp.c

1415

struct intel_display *display = to_intel_display(_connector->dev);

sys/dev/pci/drm/i915/display/intel_dp.c

1422

int max_dotclk = display->cdclk.max_dotclk_freq;

sys/dev/pci/drm/i915/display/intel_dp.c

1429

status = intel_cpu_transcoder_mode_valid(display, mode);

sys/dev/pci/drm/i915/display/intel_dp.c

1455

status = intel_pfit_mode_valid(display, mode, output_format, num_joined_pipes);

sys/dev/pci/drm/i915/display/intel_dp.c

1462

if (intel_dp_hdisplay_bad(display, mode->hdisplay))

sys/dev/pci/drm/i915/display/intel_dp.c

1494

intel_dp_dsc_get_max_compressed_bpp(display,

sys/dev/pci/drm/i915/display/intel_dp.c

1512

if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc)

sys/dev/pci/drm/i915/display/intel_dp.c

1522

return intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);

sys/dev/pci/drm/i915/display/intel_dp.c

1525

bool intel_dp_source_supports_tps3(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dp.c

1527

return DISPLAY_VER(display) >= 9 ||

sys/dev/pci/drm/i915/display/intel_dp.c

1528

display->platform.broadwell || display->platform.haswell;

sys/dev/pci/drm/i915/display/intel_dp.c

1531

bool intel_dp_source_supports_tps4(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dp.c

1533

return DISPLAY_VER(display) >= 10;

sys/dev/pci/drm/i915/display/intel_dp.c

1546

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

1553

drm_dbg_kms(display->drm, "source rates: %s\n", seq_buf_str(&s));

sys/dev/pci/drm/i915/display/intel_dp.c

1557

drm_dbg_kms(display->drm, "sink rates: %s\n", seq_buf_str(&s));

sys/dev/pci/drm/i915/display/intel_dp.c

1561

drm_dbg_kms(display->drm, "common rates: %s\n", seq_buf_str(&s));

sys/dev/pci/drm/i915/display/intel_dp.c

1598

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

1602

if (drm_WARN_ON(display->drm, i < 0))

sys/dev/pci/drm/i915/display/intel_dp.c

1611

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

1614

if (display->platform.g4x && port_clock == 268800)

sys/dev/pci/drm/i915/display/intel_dp.c

1638

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

1641

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_dp.c

1644

if (DISPLAY_VER(display) == 11 && encoder->port != PORT_A &&

sys/dev/pci/drm/i915/display/intel_dp.c

1709

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

1735

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

1747

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp.c

1753

return HAS_DOUBLE_BUFFERED_M_N(display) &&

sys/dev/pci/drm/i915/display/intel_dp.c

177

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

1815

int intel_dp_dsc_max_src_input_bpc(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dp.c

1818

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_dp.c

1820

if (DISPLAY_VER(display) == 11)

sys/dev/pci/drm/i915/display/intel_dp.c

1829

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp.c

1834

dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);

sys/dev/pci/drm/i915/display/intel_dp.c

1851

static int intel_dp_source_dsc_version_minor(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dp.c

1853

return DISPLAY_VER(display) >= 14 ? 2 : 1;

sys/dev/pci/drm/i915/display/intel_dp.c

1887

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp.c

191

if (intel_dp_is_edp(intel_dp) && intel_has_quirk(display, QUIRK_EDP_LIMIT_RATE_HBR2))

sys/dev/pci/drm/i915/display/intel_dp.c

1910

min(intel_dp_source_dsc_version_minor(display),

sys/dev/pci/drm/i915/display/intel_dp.c

1920

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

1935

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp.c

1946

if (min(intel_dp_source_dsc_version_minor(display),

sys/dev/pci/drm/i915/display/intel_dp.c

2088

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

2103

if (DISPLAY_VER(display) < 13)

sys/dev/pci/drm/i915/display/intel_dp.c

2114

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp.c

2117

if (DISPLAY_VER(display) < 14 || !incr)

sys/dev/pci/drm/i915/display/intel_dp.c

2134

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

2137

if (DISPLAY_VER(display) >= 13) {

sys/dev/pci/drm/i915/display/intel_dp.c

2166

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

2176

dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, adjusted_mode->clock,

sys/dev/pci/drm/i915/display/intel_dp.c

2187

drm_WARN_ON(display->drm, !is_power_of_2(bpp_step_x16));

sys/dev/pci/drm/i915/display/intel_dp.c

2205

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

2233

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

2242

drm_dbg_kms(display->drm, "Input DSC BPC forced to %d\n",

sys/dev/pci/drm/i915/display/intel_dp.c

2247

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

2303

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

2320

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

2369

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

2395

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

2407

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

2421

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

2445

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

2454

drm_dbg_kms(display->drm, "DP DSC computed with Input Bpp = %d "

sys/dev/pci/drm/i915/display/intel_dp.c

2474

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

2512

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

2530

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp.c

2533

int dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);

sys/dev/pci/drm/i915/display/intel_dp.c

2540

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

2560

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

2594

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

2641

bool intel_dp_joiner_needs_dsc(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dp.c

2650

return (!HAS_UNCOMPRESSED_JOINER(display) && num_joined_pipes == 2) ||

sys/dev/pci/drm/i915/display/intel_dp.c

2660

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dp.c

2682

joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);

sys/dev/pci/drm/i915/display/intel_dp.c

2709

drm_dbg_kms(display->drm, "DSC required but not available\n");

sys/dev/pci/drm/i915/display/intel_dp.c

2714

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

2731

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

2778

static bool intel_dp_port_has_audio(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_dp.c

2780

if (display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_dp.c

2782

if (DISPLAY_VER(display) < 12 && port == PORT_A)

sys/dev/pci/drm/i915/display/intel_dp.c

2792

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dp.c

284

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

2869

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

294

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

2970

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

2980

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

2993

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp.c

3011

if (!intel_cpu_transcoder_has_drrs(display, pipe_config->cpu_transcoder))

sys/dev/pci/drm/i915/display/intel_dp.c

3023

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp.c

3036

if (intel_cpu_transcoder_has_m2_n2(display, pipe_config->cpu_transcoder))

sys/dev/pci/drm/i915/display/intel_dp.c

3041

if (display->platform.ironlake || display->platform.sandybridge ||

sys/dev/pci/drm/i915/display/intel_dp.c

3042

display->platform.ivybridge)

sys/dev/pci/drm/i915/display/intel_dp.c

3064

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dp.c

3070

if (!intel_dp_port_has_audio(display, encoder->port))

sys/dev/pci/drm/i915/display/intel_dp.c

3085

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dp.c

309

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

3096

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

3169

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dp.c

3187

if (DISPLAY_VER(display) < 30)

sys/dev/pci/drm/i915/display/intel_dp.c

3200

drm_dbg(display->drm, "failed to calculate dsc slice count\n");

sys/dev/pci/drm/i915/display/intel_dp.c

323

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

3241

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

3260

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dp.c

3285

if (intel_dp_hdisplay_bad(display, adjusted_mode->crtc_hdisplay))

sys/dev/pci/drm/i915/display/intel_dp.c

3330

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

3398

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dp.c

3404

drm_dbg_kms(display->drm, "\n");

sys/dev/pci/drm/i915/display/intel_dp.c

3414

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

3419

drm_dbg_kms(display->drm, "\n");

sys/dev/pci/drm/i915/display/intel_dp.c

3462

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp.c

3466

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

3475

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp.c

3484

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

3493

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dp.c

3518

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

356

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

3565

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dp.c

3570

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

358

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

3596

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dp.c

3601

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

3616

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

3630

drm_dbg_kms(display->drm, "Failed to read source OUI\n");

sys/dev/pci/drm/i915/display/intel_dp.c

3639

drm_dbg_kms(display->drm, "Failed to write source OUI\n");

sys/dev/pci/drm/i915/display/intel_dp.c

3653

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

3656

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

3668

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

3705

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

3749

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dp.c

3759

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

3774

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

3782

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

3794

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

3806

drm_err(display->drm, "Failed to read DPCD register 0x%x\n",

sys/dev/pci/drm/i915/display/intel_dp.c

3809

drm_dbg_kms(display->drm, "PCON ENCODER DSC DPCD: %*ph\n",

sys/dev/pci/drm/i915/display/intel_dp.c

3881

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

3889

drm_dbg(display->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);

sys/dev/pci/drm/i915/display/intel_dp.c

3892

drm_dbg(display->drm, "Sink max rate from EDID = %d Gbps\n",

sys/dev/pci/drm/i915/display/intel_dp.c

3901

drm_dbg(display->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);

sys/dev/pci/drm/i915/display/intel_dp.c

3938

drm_dbg(display->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);

sys/dev/pci/drm/i915/display/intel_dp.c

3941

drm_dbg(display->drm, "FRL trained with : %d Gbps\n",

sys/dev/pci/drm/i915/display/intel_dp.c

3981

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

3996

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

4002

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

4005

drm_dbg(display->drm, "FRL training Completed\n");

sys/dev/pci/drm/i915/display/intel_dp.c

4055

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

4105

drm_dbg_kms(display->drm, "Failed to set pcon DSC\n");

sys/dev/pci/drm/i915/display/intel_dp.c

4111

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

4126

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

4162

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

4169

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

4202

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp.c

4221

drm_err(display->drm, "Failed to read FEC DPCD register\n");

sys/dev/pci/drm/i915/display/intel_dp.c

4225

drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n",

sys/dev/pci/drm/i915/display/intel_dp.c

4240

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

4243

if (!HAS_DSC(display))

sys/dev/pci/drm/i915/display/intel_dp.c

4257

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp.c

4273

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

4281

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dp.c

4299

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

4308

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

4317

drm_err(display->drm, "Failed to read MSO cap\n");

sys/dev/pci/drm/i915/display/intel_dp.c

4324

drm_err(display->drm, "Invalid MSO link count cap %u\n", mso);

sys/dev/pci/drm/i915/display/intel_dp.c

4329

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

4333

if (!HAS_MSO(display)) {

sys/dev/pci/drm/i915/display/intel_dp.c

4334

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

4364

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

4395

intel_has_quirk(display, QUIRK_EDP_LIMIT_RATE_HBR2))

sys/dev/pci/drm/i915/display/intel_dp.c

4418

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

4421

drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);

sys/dev/pci/drm/i915/display/intel_dp.c

4445

drm_dbg_kms(display->drm, "eDP DPCD: %*ph\n",

sys/dev/pci/drm/i915/display/intel_dp.c

4556

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

4558

if (!display->params.enable_dp_mst)

sys/dev/pci/drm/i915/display/intel_dp.c

4574

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

4583

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

4588

str_yes_no(display->params.enable_dp_mst),

sys/dev/pci/drm/i915/display/intel_dp.c

4614

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

4619

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

4629

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

4637

if (IS_DISPLAY_VER(display, 14, 20) && !display->platform.battlemage) {

sys/dev/pci/drm/i915/display/intel_dp.c

4718

intel_dp_hdr_metadata_infoframe_sdp_pack(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dp.c

4735

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

4741

drm_dbg_kms(display->drm, "wrong static hdr metadata size\n");

sys/dev/pci/drm/i915/display/intel_dp.c

4799

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dp.c

4813

len = intel_dp_hdr_metadata_infoframe_sdp_pack(display,

sys/dev/pci/drm/i915/display/intel_dp.c

4826

if (drm_WARN_ON(display->drm, len < 0))

sys/dev/pci/drm/i915/display/intel_dp.c

4837

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dp.c

4838

i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_dp.c

4843

if (HAS_AS_SDP(display))

sys/dev/pci/drm/i915/display/intel_dp.c

4846

u32 val = intel_de_read(display, reg) & ~dip_enable;

sys/dev/pci/drm/i915/display/intel_dp.c

4849

if (!enable && HAS_DSC(display))

sys/dev/pci/drm/i915/display/intel_dp.c

485

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

4859

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_dp.c

4860

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_dp.c

493

return DISPLAY_VER(display) >= 12 ||

sys/dev/pci/drm/i915/display/intel_dp.c

494

(DISPLAY_VER(display) == 11 &&

sys/dev/pci/drm/i915/display/intel_dp.c

4981

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dp.c

4996

drm_dbg_kms(display->drm, "Failed to unpack DP AS SDP\n");

sys/dev/pci/drm/i915/display/intel_dp.c

5049

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dp.c

5064

drm_dbg_kms(display->drm, "Failed to unpack DP VSC SDP\n");

sys/dev/pci/drm/i915/display/intel_dp.c

5071

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dp.c

5088

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

5118

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

5133

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

5156

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

5163

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

5189

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

5200

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

5207

drm_dbg_kms(display->drm, "DPRX ESI: %4ph\n", esi);

sys/dev/pci/drm/i915/display/intel_dp.c

5219

if (drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr,

sys/dev/pci/drm/i915/display/intel_dp.c

5229

drm_dbg_kms(display->drm, "Failed to ack ESI\n");

sys/dev/pci/drm/i915/display/intel_dp.c

523

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

529

if (DISPLAY_VERx100(display) == 1401)

sys/dev/pci/drm/i915/display/intel_dp.c

5317

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

5330

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_dp.c

5342

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp.c

5344

drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp.c

5349

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

5358

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

5365

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_dp.c

5385

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

5416

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dp.c

5424

ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,

sys/dev/pci/drm/i915/display/intel_dp.c

5442

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

5447

ret = intel_modeset_commit_pipes(display, pipe_mask, ctx);

sys/dev/pci/drm/i915/display/intel_dp.c

5454

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

5487

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

5506

drm_dbg_kms(display->drm, "Sink specific irq unhandled\n");

sys/dev/pci/drm/i915/display/intel_dp.c

5511

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

5523

drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr,

sys/dev/pci/drm/i915/display/intel_dp.c

5597

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

5602

if (drm_WARN_ON(display->drm, intel_dp_is_edp(intel_dp)))

sys/dev/pci/drm/i915/display/intel_dp.c

5645

drm_dbg_kms(display->drm, "Broken DP branch device, ignoring\n");

sys/dev/pci/drm/i915/display/intel_dp.c

5687

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dp.c

5693

with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) {

sys/dev/pci/drm/i915/display/intel_dp.c

5735

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

5759

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

5792

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

5810

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

5821

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

583

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

5834

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",

sys/dev/pci/drm/i915/display/intel_dp.c

5871

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

5873

intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&

sys/dev/pci/drm/i915/display/intel_dp.c

588

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

5904

struct intel_display *display = to_intel_display(_connector->dev);

sys/dev/pci/drm/i915/display/intel_dp.c

591

if (DISPLAY_VER(display) >= 14) {

sys/dev/pci/drm/i915/display/intel_dp.c

5912

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",

sys/dev/pci/drm/i915/display/intel_dp.c

5914

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

5915

!drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));

sys/dev/pci/drm/i915/display/intel_dp.c

5917

if (!intel_display_device_enabled(display))

sys/dev/pci/drm/i915/display/intel_dp.c

592

if (display->platform.battlemage) {

sys/dev/pci/drm/i915/display/intel_dp.c

5920

if (!intel_display_driver_check_access(display))

sys/dev/pci/drm/i915/display/intel_dp.c

600

} else if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/intel_dp.c

603

if (display->platform.dg2)

sys/dev/pci/drm/i915/display/intel_dp.c

6044

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp.c

6047

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",

sys/dev/pci/drm/i915/display/intel_dp.c

605

else if (display->platform.alderlake_p || display->platform.alderlake_s ||

sys/dev/pci/drm/i915/display/intel_dp.c

6050

if (!intel_display_driver_check_access(display))

sys/dev/pci/drm/i915/display/intel_dp.c

606

display->platform.dg1 || display->platform.rocketlake)

sys/dev/pci/drm/i915/display/intel_dp.c

6065

struct intel_display *display = to_intel_display(_connector->dev);

sys/dev/pci/drm/i915/display/intel_dp.c

608

else if (display->platform.jasperlake || display->platform.elkhartlake)

sys/dev/pci/drm/i915/display/intel_dp.c

6083

mode = drm_dp_downstream_mode(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

6099

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp.c

6109

drm_dbg_kms(display->drm, "registering %s bus for %s\n",

sys/dev/pci/drm/i915/display/intel_dp.c

612

} else if (display->platform.geminilake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/intel_dp.c

6147

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp.c

615

} else if (DISPLAY_VER(display) == 9) {

sys/dev/pci/drm/i915/display/intel_dp.c

6150

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

618

} else if ((display->platform.haswell && !display->platform.haswell_ulx) ||

sys/dev/pci/drm/i915/display/intel_dp.c

619

display->platform.broadwell) {

sys/dev/pci/drm/i915/display/intel_dp.c

6200

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dp.c

6205

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_dp.c

6241

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dp.c

6247

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_dp.c

6274

drm_WARN_ON(display->drm, transcoders != 0);

sys/dev/pci/drm/i915/display/intel_dp.c

6310

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp.c

6340

if (DISPLAY_VER(display) < 9)

sys/dev/pci/drm/i915/display/intel_dp.c

6356

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp.c

6362

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_dp.c

6363

if (hpd_high != test_bit(hpd_pin, &display->hotplug.oob_hotplug_last_state)) {

sys/dev/pci/drm/i915/display/intel_dp.c

6364

display->hotplug.event_bits |= BIT(hpd_pin);

sys/dev/pci/drm/i915/display/intel_dp.c

6367

&display->hotplug.oob_hotplug_last_state,

sys/dev/pci/drm/i915/display/intel_dp.c

6371

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_dp.c

6374

intel_hpd_schedule_detection(display);

sys/dev/pci/drm/i915/display/intel_dp.c

6400

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_dp.c

6406

intel_display_rpm_suspended(display) ||

sys/dev/pci/drm/i915/display/intel_dp.c

6414

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

6422

drm_dbg_kms(display->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",

sys/dev/pci/drm/i915/display/intel_dp.c

6456

static bool _intel_dp_is_port_edp(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dp.c

6464

if (DISPLAY_VER(display) < 5)

sys/dev/pci/drm/i915/display/intel_dp.c

6467

if (DISPLAY_VER(display) < 9 && port == PORT_A)

sys/dev/pci/drm/i915/display/intel_dp.c

6473

bool intel_dp_is_port_edp(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_dp.c

6476

intel_bios_encoder_data_lookup(display, port);

sys/dev/pci/drm/i915/display/intel_dp.c

6478

return _intel_dp_is_port_edp(display, devdata, port);

sys/dev/pci/drm/i915/display/intel_dp.c

6484

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dp.c

6490

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_dp.c

6496

if (display->platform.haswell || display->platform.broadwell ||

sys/dev/pci/drm/i915/display/intel_dp.c

6497

DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_dp.c

6507

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

6513

if (!display->platform.g4x && port != PORT_A)

sys/dev/pci/drm/i915/display/intel_dp.c

6517

if (HAS_GMCH(display))

sys/dev/pci/drm/i915/display/intel_dp.c

6519

else if (DISPLAY_VER(display) >= 5)

sys/dev/pci/drm/i915/display/intel_dp.c

6533

if (HAS_VRR(display))

sys/dev/pci/drm/i915/display/intel_dp.c

6540

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

6548

display->vbt.orientation,

sys/dev/pci/drm/i915/display/intel_dp.c

6556

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

6559

if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_dp.c

6568

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

6583

if (intel_get_lvds_encoder(display)) {

sys/dev/pci/drm/i915/display/intel_dp.c

6584

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

6585

!(HAS_PCH_IBX(display) || HAS_PCH_CPT(display)));

sys/dev/pci/drm/i915/display/intel_dp.c

6586

drm_info(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

6592

intel_bios_init_panel_early(display, &connector->panel,

sys/dev/pci/drm/i915/display/intel_dp.c

6596

drm_info(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

6623

drm_info(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

6646

drm_info(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

6658

if (DISPLAY_VER(display) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&

sys/dev/pci/drm/i915/display/intel_dp.c

6661

drm_info(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

6668

mutex_lock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/intel_dp.c

6674

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

6689

intel_bios_init_panel_late(display, &connector->panel, encoder->devdata,

sys/dev/pci/drm/i915/display/intel_dp.c

6705

mutex_unlock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/intel_dp.c

6708

drm_info(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

6735

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_dp.c

6751

intel_dp->DP = intel_de_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/intel_dp.c

6754

if (_intel_dp_is_port_edp(display, encoder->devdata, port)) {

sys/dev/pci/drm/i915/display/intel_dp.c

6760

DISPLAY_VER(display) < 30);

sys/dev/pci/drm/i915/display/intel_dp.c

6765

if (drm_WARN_ON(dev, (display->platform.valleyview ||

sys/dev/pci/drm/i915/display/intel_dp.c

6766

display->platform.cherryview) &&

sys/dev/pci/drm/i915/display/intel_dp.c

6776

if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_dp.c

6782

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

6791

if (!HAS_GMCH(display) && DISPLAY_VER(display) < 12)

sys/dev/pci/drm/i915/display/intel_dp.c

6800

if (HAS_DDI(display))

sys/dev/pci/drm/i915/display/intel_dp.c

6820

if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) {

sys/dev/pci/drm/i915/display/intel_dp.c

6823

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

6835

intel_display_power_flush_work(display);

sys/dev/pci/drm/i915/display/intel_dp.c

6841

void intel_dp_mst_suspend(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dp.c

6845

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_dp.c

6848

for_each_intel_encoder(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_dp.c

6864

void intel_dp_mst_resume(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dp.c

6868

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_dp.c

6871

for_each_intel_encoder(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_dp.c

710

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

716

if (drm_WARN_ON(display->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp))))

sys/dev/pci/drm/i915/display/intel_dp.c

721

if (drm_WARN_ON(display->drm, intel_dp->num_common_rates * num_common_lane_configs >

sys/dev/pci/drm/i915/display/intel_dp.c

745

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

748

if (drm_WARN_ON(display->drm, idx < 0 || idx >= intel_dp->link.num_configs))

sys/dev/pci/drm/i915/display/intel_dp.c

777

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

779

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

789

if (drm_WARN_ON(display->drm, intel_dp->num_common_rates == 0)) {

sys/dev/pci/drm/i915/display/intel_dp.c

837

small_joiner_ram_size_bits(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dp.c

839

if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/intel_dp.c

841

else if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_dp.c

847

static u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp)

sys/dev/pci/drm/i915/display/intel_dp.c

854

drm_dbg_kms(display->drm, "Unsupported BPP %u, min %u\n",

sys/dev/pci/drm/i915/display/intel_dp.c

860

if (DISPLAY_VER(display) >= 13) {

sys/dev/pci/drm/i915/display/intel_dp.c

872

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp.c

884

drm_dbg_kms(display->drm, "Set dsc bpp from %d to VESA %d\n",

sys/dev/pci/drm/i915/display/intel_dp.c

893

static int bigjoiner_interface_bits(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dp.c

895

return DISPLAY_VER(display) >= 14 ? 36 : 24;

sys/dev/pci/drm/i915/display/intel_dp.c

898

static u32 bigjoiner_bw_max_bpp(struct intel_display *display, u32 mode_clock,

sys/dev/pci/drm/i915/display/intel_dp.c

906

max_bpp = display->cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits(display) /

sys/dev/pci/drm/i915/display/intel_dp.c

915

static u32 small_joiner_ram_max_bpp(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dp.c

922

max_bpp = small_joiner_ram_size_bits(display) / mode_hdisplay;

sys/dev/pci/drm/i915/display/intel_dp.c

941

u32 get_max_compressed_bpp_with_joiner(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dp.c

945

u32 max_bpp = small_joiner_ram_max_bpp(display, mode_hdisplay, num_joined_pipes);

sys/dev/pci/drm/i915/display/intel_dp.c

948

max_bpp = min(max_bpp, bigjoiner_bw_max_bpp(display, mode_clock,

sys/dev/pci/drm/i915/display/intel_dp.c

957

u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dp.c

999

drm_dbg_kms(display->drm, "Max link bpp is %u for %u timeslots "

sys/dev/pci/drm/i915/display/intel_dp.h

114

bool intel_dp_source_supports_tps3(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dp.h

115

bool intel_dp_source_supports_tps4(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dp.h

122

bool intel_dp_joiner_needs_dsc(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dp.h

139

u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dp.h

209

int intel_dp_dsc_max_src_input_bpc(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dp.h

89

bool intel_dp_is_port_edp(struct intel_display *display, enum port port);

sys/dev/pci/drm/i915/display/intel_dp.h

96

void intel_dp_mst_suspend(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dp.h

97

void intel_dp_mst_resume(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

106

freq = display->cdclk.hw.cdclk;

sys/dev/pci/drm/i915/display/intel_dp_aux.c

108

freq = DISPLAY_RUNTIME_INFO(display)->rawclk_freq;

sys/dev/pci/drm/i915/display/intel_dp_aux.c

114

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

117

if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(display)) {

sys/dev/pci/drm/i915/display/intel_dp_aux.c

180

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

184

if (display->platform.broadwell)

sys/dev/pci/drm/i915/display/intel_dp_aux.c

204

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

21

static const char *aux_ch_name(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dp_aux.c

230

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_dp_aux.c

24

if (DISPLAY_VER(display) >= 13 && aux_ch >= AUX_CH_D_XELPD)

sys/dev/pci/drm/i915/display/intel_dp_aux.c

242

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

26

else if (DISPLAY_VER(display) >= 12 && aux_ch >= AUX_CH_USBC1)

sys/dev/pci/drm/i915/display/intel_dp_aux.c

273

aux_wakeref = intel_display_power_get(display, aux_domain);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

286

display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_dp_aux.c

313

status = intel_de_read_notrace(display, ch_ctl);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

322

const u32 status = intel_de_read(display, ch_ctl);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

325

drm_WARN(display->drm, 1,

sys/dev/pci/drm/i915/display/intel_dp_aux.c

336

if (drm_WARN_ON(display->drm, send_bytes > 20 || recv_size > 20)) {

sys/dev/pci/drm/i915/display/intel_dp_aux.c

352

intel_de_write(display, ch_data[i >> 2],

sys/dev/pci/drm/i915/display/intel_dp_aux.c

357

intel_de_write(display, ch_ctl, send_ctl);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

362

intel_de_write(display, ch_ctl,

sys/dev/pci/drm/i915/display/intel_dp_aux.c

386

drm_err(display->drm, "%s: not done (status 0x%08x)\n",

sys/dev/pci/drm/i915/display/intel_dp_aux.c

398

drm_err(display->drm, "%s: receive error (status 0x%08x)\n",

sys/dev/pci/drm/i915/display/intel_dp_aux.c

409

drm_dbg_kms(display->drm, "%s: timeout (status 0x%08x)\n",

sys/dev/pci/drm/i915/display/intel_dp_aux.c

424

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_aux.c

435

intel_dp_aux_unpack(intel_de_read(display, ch_data[i >> 2]),

sys/dev/pci/drm/i915/display/intel_dp_aux.c

448

intel_display_power_put_async(display, aux_domain, aux_wakeref);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

486

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

501

if (drm_WARN_ON(display->drm, txsize > 20))

sys/dev/pci/drm/i915/display/intel_dp_aux.c

504

drm_WARN_ON(display->drm, !msg->buffer != !msg->size);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

529

if (drm_WARN_ON(display->drm, rxsize > 20))

sys/dev/pci/drm/i915/display/intel_dp_aux.c

59

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

65

ret = intel_de_wait_custom(display, ch_ctl, DP_AUX_CH_CTL_SEND_BUSY,

sys/dev/pci/drm/i915/display/intel_dp_aux.c

70

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_aux.c

739

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

750

return XELPDP_DP_AUX_CH_CTL(display, aux_ch);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

753

return XELPDP_DP_AUX_CH_CTL(display, AUX_CH_A);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

759

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

770

return XELPDP_DP_AUX_CH_DATA(display, aux_ch, index);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

773

return XELPDP_DP_AUX_CH_DATA(display, AUX_CH_A, index);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

787

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

79

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

793

if (DISPLAY_VER(display) >= 14) {

sys/dev/pci/drm/i915/display/intel_dp_aux.c

796

} else if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_dp_aux.c

799

} else if (DISPLAY_VER(display) >= 9) {

sys/dev/pci/drm/i915/display/intel_dp_aux.c

802

} else if (HAS_PCH_SPLIT(display)) {

sys/dev/pci/drm/i915/display/intel_dp_aux.c

805

} else if (display->platform.valleyview || display->platform.cherryview) {

sys/dev/pci/drm/i915/display/intel_dp_aux.c

813

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_dp_aux.c

815

else if (display->platform.broadwell || display->platform.haswell)

sys/dev/pci/drm/i915/display/intel_dp_aux.c

817

else if (HAS_PCH_SPLIT(display))

sys/dev/pci/drm/i915/display/intel_dp_aux.c

822

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_dp_aux.c

827

intel_dp->aux.drm_dev = display->drm;

sys/dev/pci/drm/i915/display/intel_dp_aux.c

832

aux_ch_name(display, buf, sizeof(buf), aux_ch),

sys/dev/pci/drm/i915/display/intel_dp_aux.c

843

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

846

if (DISPLAY_VER(display) == 9 && encoder->port == PORT_E)

sys/dev/pci/drm/i915/display/intel_dp_aux.c

856

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

859

for_each_intel_encoder(display->drm, other) {

sys/dev/pci/drm/i915/display/intel_dp_aux.c

875

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

88

return DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(display)->rawclk_freq, 2000);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

896

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_aux.c

899

aux_ch_name(display, buf, sizeof(buf), aux_ch),

sys/dev/pci/drm/i915/display/intel_dp_aux.c

904

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_aux.c

907

aux_ch_name(display, buf, sizeof(buf), aux_ch), source);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

912

void intel_dp_aux_irq_handler(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dp_aux.c

914

wake_up_all(&display->gmbus.wait_queue);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

93

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_aux.h

21

void intel_dp_aux_irq_handler(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

115

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

128

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

148

if (display->params.enable_dpcd_backlight != INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL &&

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

151

drm_info(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

177

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

184

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

203

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

249

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

266

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

276

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

287

if (DISPLAY_VER(display) < 11)

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

307

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

319

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

343

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

375

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

390

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

398

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

404

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

412

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

429

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

521

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

538

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

542

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

551

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

568

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

594

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

604

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

610

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

618

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

644

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

653

switch (display->params.enable_dpcd_backlight) {

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

102

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

112

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

123

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

132

struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

140

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

152

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

156

ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, display, &bcaps);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

168

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

174

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

186

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

193

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

205

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

217

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

230

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

240

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

260

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

267

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

279

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

283

ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, display, &bcaps);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

346

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

355

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

401

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

434

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

518

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

572

drm_dbg_kms(display->drm, "msg_id %d, ret %zd\n",

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

585

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

61

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

69

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

701

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

714

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

717

ret = intel_dp_hdcp_read_bcaps(aux, display, &bcaps);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

750

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

759

drm_err(display->drm, "%s HDCP stream select failed (%d)\n",

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

768

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

785

if (intel_de_wait(display, HDCP_STATUS(display, cpu_transcoder, port),

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

788

drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

800

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

811

if (DISPLAY_VER(display) < 30) {

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

812

val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

813

HDCP2_AUTH_STREAM(display, cpu_transcoder, port));

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

815

drm_WARN_ON(display->drm, enable &&

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

824

if (intel_de_wait(display, HDCP2_STREAM_STATUS(display, cpu_transcoder, pipe),

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

828

drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

833

if (DISPLAY_VER(display) >= 30) {

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

834

val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

835

HDCP2_STREAM_STATUS(display, cpu_transcoder, port));

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

837

drm_WARN_ON(display->drm, enable &&

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

85

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

892

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

897

if (!is_hdcp_supported(display, port))

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

96

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1137

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1156

if (!display->hotplug.ignore_long_hpd &&

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1641

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1689

if (display->hotplug.ignore_long_hpd) {

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1731

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1738

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1746

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1804

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1813

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1820

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1831

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1838

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1846

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1906

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1915

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1922

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1935

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1939

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1945

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1954

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1958

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1964

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1973

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1977

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1983

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1991

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1998

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

2004

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

2015

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

2019

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

2025

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

2033

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

2037

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

2043

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

2056

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

2060

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

2066

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

214

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

223

if (DISPLAY_VER(display) >= 10 && !display->platform.geminilake)

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

254

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

262

(DISPLAY_VER(display) >= 10 && !display->platform.geminilake)) {

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

325

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

328

drm_WARN_ON_ONCE(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

338

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

350

drm_WARN_ON_ONCE(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

360

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

372

drm_WARN_ON_ONCE(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

382

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

385

DISPLAY_VER(display) >= 10 || display->platform.broxton;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

779

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

792

source_tps4 = intel_dp_source_supports_tps4(display);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

810

source_tps3 = intel_dp_source_supports_tps3(display);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1038

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1058

drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 12 && last_mst_stream &&

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1061

for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1074

intel_de_rmw(display,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1075

TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1088

for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1094

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1119

if (DISPLAY_VER(display) < 12 || !last_mst_stream)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1195

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

120

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1213

drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 12 && first_mst_stream &&

sys/dev/pci/drm/i915/display/intel_dp_mst.c

122

drm_dbg_kms(display->drm, "active MST streams %d -> %d\n",

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1242

if (DISPLAY_VER(display) < 12 || !first_mst_stream)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1245

if (DISPLAY_VER(display) >= 13 && !first_mst_stream)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

125

if (drm_WARN_ON(display->drm, intel_dp->mst.active_streams == 0))

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1254

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1258

if (!display->platform.alderlake_p)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1261

if (!IS_DISPLAY_STEP(display, STEP_D0, STEP_FOREVER))

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1269

if (IS_DISPLAY_STEP(display, STEP_E0, STEP_FOREVER)) {

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1282

intel_de_rmw(display, CHICKEN_MISC_3, clear, set);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1290

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1301

drm_WARN_ON(display->drm, pipe_config->has_pch_encoder);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1308

intel_de_write(display, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1310

intel_de_write(display, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1322

intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, trans), 0,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

133

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1337

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1338

intel_de_rmw(display, CHICKEN_TRANS(display, trans),

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1344

for_each_pipe_crtc_modeset_enable(display, pipe_crtc, pipe_config, i) {

sys/dev/pci/drm/i915/display/intel_dp_mst.c

135

drm_dbg_kms(display->drm, "active MST streams %d -> %d\n",

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1383

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1391

if (!intel_display_driver_check_access(display))

sys/dev/pci/drm/i915/display/intel_dp_mst.c

145

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1454

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1459

int max_dotclk = display->cdclk.max_dotclk_freq;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1473

*status = intel_cpu_transcoder_mode_valid(display, mode);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

149

if (!intel_dp_is_uhbr(crtc_state) || DISPLAY_VER(display) >= 20 || !dsc)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1529

intel_dp_dsc_get_max_compressed_bpp(display,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1547

if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc) {

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1557

*status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1579

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1582

if (!intel_display_device_enabled(display))

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1588

if (!intel_display_driver_check_access(display))

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1633

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1637

display->drm->mode_config.path_property, 0);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1639

display->drm->mode_config.tile_property, 0);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1673

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1711

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1724

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1740

ret = drm_connector_dynamic_init(display->drm, &connector->base, &mst_connector_funcs,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1752

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1767

drm_dbg_kms(display->drm, "[%s:%d] HDCP MST init failed, skipping.\n",

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1798

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1812

drm_encoder_init(display->drm, &encoder->base, &mst_stream_encoder_funcs,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1852

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1856

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1864

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1869

if (!HAS_DP_MST(display) || intel_dp_is_edp(intel_dp))

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1872

if (DISPLAY_VER(display) < 12 && port == PORT_A)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1875

if (DISPLAY_VER(display) < 11 && port == PORT_E)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1882

ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst.mgr, display->drm,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1884

INTEL_NUM_PIPES(display), conn_base_id);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

2116

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

2130

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

262

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

275

drm_WARN_ON(display->drm, !dsc && (fxp_q4_to_frac(min_bpp_x16) ||

sys/dev/pci/drm/i915/display/intel_dp_mst.c

281

drm_WARN_ON(display->drm, min_bpp_x16 != max_bpp_x16);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

305

drm_dbg_kms(display->drm, "Limiting bpp to max DPT bpp (" FXP_Q4_FMT " -> " FXP_Q4_FMT ")\n",

sys/dev/pci/drm/i915/display/intel_dp_mst.c

310

drm_dbg_kms(display->drm, "Looking for slots in range min bpp " FXP_Q4_FMT " max bpp " FXP_Q4_FMT "\n",

sys/dev/pci/drm/i915/display/intel_dp_mst.c

316

drm_dbg_kms(display->drm, "Can't get valid DSC slice count\n");

sys/dev/pci/drm/i915/display/intel_dp_mst.c

322

drm_WARN_ON(display->drm, min_bpp_x16 % bpp_step_x16 || max_bpp_x16 % bpp_step_x16);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

328

drm_dbg_kms(display->drm, "Trying bpp " FXP_Q4_FMT "\n", FXP_Q4_ARGS(bpp_x16));

sys/dev/pci/drm/i915/display/intel_dp_mst.c

332

drm_WARN_ON(display->drm, !is_mst);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

393

drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

418

drm_WARN_ON(display->drm, slots != crtc_state->dp_m_n.tu);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

425

drm_dbg_kms(display->drm, "failed finding vcpi slots:%d\n",

sys/dev/pci/drm/i915/display/intel_dp_mst.c

435

drm_dbg_kms(display->drm, "Got %d slots for pipe bpp " FXP_Q4_FMT " dsc %d\n",

sys/dev/pci/drm/i915/display/intel_dp_mst.c

464

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

478

drm_dbg_kms(display->drm, "DSC Source supported min bpp %d max bpp %d\n",

sys/dev/pci/drm/i915/display/intel_dp_mst.c

484

drm_dbg_kms(display->drm, "DSC Sink supported min bpp %d max bpp %d\n",

sys/dev/pci/drm/i915/display/intel_dp_mst.c

498

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

506

drm_WARN_ON(display->drm, !is_power_of_2(bpp_step_x16));

sys/dev/pci/drm/i915/display/intel_dp_mst.c

559

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

568

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

575

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

588

drm_WARN_ON(display->drm, limits->min_rate != limits->max_rate);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

598

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

638

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

668

joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

686

drm_dbg_kms(display->drm, "DSC required but not available\n");

sys/dev/pci/drm/i915/display/intel_dp_mst.c

692

drm_dbg_kms(display->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",

sys/dev/pci/drm/i915/display/intel_dp_mst.c

706

drm_WARN(display->drm, intel_dp->force_dsc_bpc,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

712

drm_dbg_kms(display->drm, "Trying to find VCPI slots in DSC mode\n");

sys/dev/pci/drm/i915/display/intel_dp_mst.c

730

if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

758

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

764

if (DISPLAY_VER(display) < 12)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

818

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

826

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, mst_pipe_mask) {

sys/dev/pci/drm/i915/display/intel_dp_mst.c

831

if (drm_WARN_ON(display->drm, !crtc_state))

sys/dev/pci/drm/i915/display/intel_dp_mst.c

941

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

949

drm_connector_list_iter_begin(display->drm, &connector_list_iter);

sys/dev/pci/drm/i915/display/intel_dp_test.c

115

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_test.c

125

drm_dbg_kms(display->drm, "Test pattern read failed\n");

sys/dev/pci/drm/i915/display/intel_dp_test.c

134

drm_dbg_kms(display->drm, "H Width read failed\n");

sys/dev/pci/drm/i915/display/intel_dp_test.c

141

drm_dbg_kms(display->drm, "V Height read failed\n");

sys/dev/pci/drm/i915/display/intel_dp_test.c

148

drm_dbg_kms(display->drm, "TEST MISC read failed\n");

sys/dev/pci/drm/i915/display/intel_dp_test.c

177

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_test.c

193

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_test.c

207

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_test.c

223

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_test.c

233

drm_dbg_kms(display->drm, "Disable Phy Test Pattern\n");

sys/dev/pci/drm/i915/display/intel_dp_test.c

234

intel_de_write(display, DDI_DP_COMP_CTL(pipe), 0x0);

sys/dev/pci/drm/i915/display/intel_dp_test.c

235

if (DISPLAY_VER(display) >= 10)

sys/dev/pci/drm/i915/display/intel_dp_test.c

236

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

sys/dev/pci/drm/i915/display/intel_dp_test.c

241

drm_dbg_kms(display->drm, "Set D10.2 Phy Test Pattern\n");

sys/dev/pci/drm/i915/display/intel_dp_test.c

242

intel_de_write(display, DDI_DP_COMP_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_dp_test.c

246

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_test.c

248

intel_de_write(display, DDI_DP_COMP_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_dp_test.c

253

drm_dbg_kms(display->drm, "Set PRBS7 Phy Test Pattern\n");

sys/dev/pci/drm/i915/display/intel_dp_test.c

254

intel_de_write(display, DDI_DP_COMP_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_dp_test.c

263

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_test.c

266

intel_de_write(display, DDI_DP_COMP_PAT(pipe, 0), pattern_val);

sys/dev/pci/drm/i915/display/intel_dp_test.c

268

intel_de_write(display, DDI_DP_COMP_PAT(pipe, 1), pattern_val);

sys/dev/pci/drm/i915/display/intel_dp_test.c

270

intel_de_write(display, DDI_DP_COMP_PAT(pipe, 2), pattern_val);

sys/dev/pci/drm/i915/display/intel_dp_test.c

271

intel_de_write(display, DDI_DP_COMP_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_dp_test.c

281

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_test.c

284

intel_de_write(display, DDI_DP_COMP_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_dp_test.c

289

if (DISPLAY_VER(display) < 10) {

sys/dev/pci/drm/i915/display/intel_dp_test.c

290

drm_warn(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_test.c

294

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_test.c

296

intel_de_write(display, DDI_DP_COMP_CTL(pipe), 0x0);

sys/dev/pci/drm/i915/display/intel_dp_test.c

297

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

sys/dev/pci/drm/i915/display/intel_dp_test.c

302

drm_warn(display->drm, "Invalid Phy Test Pattern\n");

sys/dev/pci/drm/i915/display/intel_dp_test.c

309

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_test.c

316

drm_dbg_kms(display->drm, "failed to get link status\n");

sys/dev/pci/drm/i915/display/intel_dp_test.c

337

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_test.c

342

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_test.c

35

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_test.c

355

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_test.c

362

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_test.c

369

drm_dbg_kms(display->drm, "LINK_TRAINING test requested\n");

sys/dev/pci/drm/i915/display/intel_dp_test.c

373

drm_dbg_kms(display->drm, "TEST_PATTERN test requested\n");

sys/dev/pci/drm/i915/display/intel_dp_test.c

377

drm_dbg_kms(display->drm, "EDID test requested\n");

sys/dev/pci/drm/i915/display/intel_dp_test.c

381

drm_dbg_kms(display->drm, "PHY_PATTERN test requested\n");

sys/dev/pci/drm/i915/display/intel_dp_test.c

385

drm_dbg_kms(display->drm, "Invalid test request '%02x'\n",

sys/dev/pci/drm/i915/display/intel_dp_test.c

396

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_test.c

406

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_test.c

413

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_dp_test.c

433

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_test.c

45

drm_dbg_kms(display->drm, "Setting pipe_bpp to %d\n", bpp);

sys/dev/pci/drm/i915/display/intel_dp_test.c

453

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dp_test.c

459

ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,

sys/dev/pci/drm/i915/display/intel_dp_test.c

471

drm_dbg_kms(display->drm, "[ENCODER:%d:%s] PHY test\n",

sys/dev/pci/drm/i915/display/intel_dp_test.c

474

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {

sys/dev/pci/drm/i915/display/intel_dp_test.c

479

if (DISPLAY_VER(display) >= 12 &&

sys/dev/pci/drm/i915/display/intel_dp_test.c

525

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_test.c

530

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_test.c

533

drm_kms_helper_hotplug_event(display->drm);

sys/dev/pci/drm/i915/display/intel_dp_test.c

536

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_test.c

557

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/intel_dp_test.c

572

drm_dbg_kms(display->drm, "Copied %d bytes from user\n", (unsigned int)len);

sys/dev/pci/drm/i915/display/intel_dp_test.c

574

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_dp_test.c

591

drm_dbg_kms(display->drm, "Got %d for test active\n", val);

sys/dev/pci/drm/i915/display/intel_dp_test.c

612

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/intel_dp_test.c

617

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_dp_test.c

662

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/intel_dp_test.c

667

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_dp_test.c

716

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/intel_dp_test.c

721

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_dp_test.c

757

void intel_dp_test_debugfs_register(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dp_test.c

765

display->drm->debugfs_root,

sys/dev/pci/drm/i915/display/intel_dp_test.c

766

display,

sys/dev/pci/drm/i915/display/intel_dp_test.c

77

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_test.c

89

drm_dbg_kms(display->drm, "Lane count read failed\n");

sys/dev/pci/drm/i915/display/intel_dp_test.c

97

drm_dbg_kms(display->drm, "Link Rate read failed\n");

sys/dev/pci/drm/i915/display/intel_dp_test.h

21

void intel_dp_test_debugfs_register(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

106

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

124

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

130

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

137

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

148

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

175

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

180

tunnel = drm_dp_tunnel_detect(display->dp_tunnel_mgr,

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

192

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

269

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

276

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

299

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

311

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

352

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

374

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

379

drm_WARN_ON(display->drm, old_tunnel != tunnel);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

399

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

427

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

446

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

452

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

463

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

472

drm_WARN_ON(display->drm, pipe_mask & ~((1 << I915_MAX_PIPES) - 1));

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

510

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

518

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

589

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

598

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

72

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

722

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

730

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

787

int intel_dp_tunnel_mgr_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

794

drm_connector_list_iter_begin(display->drm, &connector_list_iter);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

803

tunnel_mgr = drm_dp_tunnel_mgr_create(display->drm, dp_connectors);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

807

display->dp_tunnel_mgr = tunnel_mgr;

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

818

void intel_dp_tunnel_mgr_cleanup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

820

drm_dp_tunnel_mgr_destroy(display->dp_tunnel_mgr);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

821

display->dp_tunnel_mgr = NULL;

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

84

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dp_tunnel.h

127

intel_dp_tunnel_mgr_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dp_tunnel.h

132

static inline void intel_dp_tunnel_mgr_cleanup(struct intel_display *display) {}

sys/dev/pci/drm/i915/display/intel_dp_tunnel.h

56

int intel_dp_tunnel_mgr_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.h

57

void intel_dp_tunnel_mgr_cleanup(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1001

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW11(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1004

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW12(ch),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1012

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW12(ch),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1023

vlv_dpio_put(display->drm);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1028

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1032

chv_phy_powergate_ch(display, DPIO_PHY0, DPIO_CH1, false);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1040

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1045

vlv_dpio_get(display->drm);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1049

val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW5_CH0);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1051

vlv_dpio_write(display->drm, phy, CHV_CMN_DW5_CH0, val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1053

val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW1_CH1);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1055

vlv_dpio_write(display->drm, phy, CHV_CMN_DW1_CH1, val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1058

vlv_dpio_put(display->drm);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1077

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1082

vlv_dpio_get(display->drm);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1084

vlv_dpio_write(display->drm, phy, VLV_TX_DW5_GRP(ch), 0x00000000);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1085

vlv_dpio_write(display->drm, phy, VLV_TX_DW4_GRP(ch), demph_reg_value);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1086

vlv_dpio_write(display->drm, phy, VLV_TX_DW2_GRP(ch),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1088

vlv_dpio_write(display->drm, phy, VLV_TX_DW3_GRP(ch), 0x0C782040);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1091

vlv_dpio_write(display->drm, phy, VLV_TX_DW4(ch, 3), tx3_demph);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1093

vlv_dpio_write(display->drm, phy, VLV_PCS_DW11_GRP(ch), 0x00030000);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1094

vlv_dpio_write(display->drm, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1095

vlv_dpio_write(display->drm, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1097

vlv_dpio_put(display->drm);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1103

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1109

vlv_dpio_get(display->drm);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1111

vlv_dpio_write(display->drm, phy, VLV_PCS_DW0_GRP(ch),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1114

vlv_dpio_write(display->drm, phy, VLV_PCS_DW1_GRP(ch),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1121

vlv_dpio_write(display->drm, phy, VLV_PCS_DW12_GRP(ch), 0x00750f00);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1122

vlv_dpio_write(display->drm, phy, VLV_TX_DW11_GRP(ch), 0x00001500);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1123

vlv_dpio_write(display->drm, phy, VLV_TX_DW14_GRP(ch), 0x40400000);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1125

vlv_dpio_put(display->drm);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1131

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1140

vlv_dpio_get(display->drm);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1147

vlv_dpio_write(display->drm, phy, VLV_PCS_DW8_GRP(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1150

vlv_dpio_write(display->drm, phy, VLV_PCS_DW14_GRP(ch), 0x00760018);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1151

vlv_dpio_write(display->drm, phy, VLV_PCS_DW23_GRP(ch), 0x00400888);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1153

vlv_dpio_put(display->drm);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1159

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1164

vlv_dpio_get(display->drm);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1165

vlv_dpio_write(display->drm, phy, VLV_PCS_DW0_GRP(ch), 0x00000000);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1166

vlv_dpio_write(display->drm, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1167

vlv_dpio_put(display->drm);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1173

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1183

dpll_reg = DPLL(display, 0);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1187

dpll_reg = DPLL(display, 0);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1196

if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000))

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1197

drm_WARN(display->drm, 1,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1200

intel_de_read(display, dpll_reg) & port_mask,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

225

bxt_get_phy_list(struct intel_display *display, int *count)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

227

if (display->platform.geminilake) {

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

237

bxt_get_phy_info(struct intel_display *display, enum dpio_phy phy)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

241

bxt_get_phy_list(display, &count);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

246

void bxt_port_to_phy_channel(struct intel_display *display, enum port port,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

252

phys = bxt_get_phy_list(display, &count);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

271

drm_WARN(display->drm, 1, "PHY not found for PORT %c",

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

281

static u32 bxt_dpio_phy_rmw_grp(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

288

old = intel_de_read(display, reg_single);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

290

intel_de_write(display, reg_group, val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

298

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

305

if (drm_WARN_ON_ONCE(display->drm, !trans))

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

308

bxt_port_to_phy_channel(display, encoder->port, &phy, &ch);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

314

bxt_dpio_phy_rmw_grp(display, BXT_PORT_PCS_DW10_LN01(phy, ch),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

321

intel_de_rmw(display, BXT_PORT_TX_DW2_LN(phy, ch, lane),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

331

intel_de_rmw(display, BXT_PORT_TX_DW3_LN(phy, ch, lane),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

336

val = intel_de_read(display, BXT_PORT_TX_DW3_LN(phy, ch, lane));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

338

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

345

intel_de_rmw(display, BXT_PORT_TX_DW4_LN(phy, ch, lane),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

350

bxt_dpio_phy_rmw_grp(display, BXT_PORT_PCS_DW10_LN01(phy, ch),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

355

bool bxt_dpio_phy_is_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

360

phy_info = bxt_get_phy_info(display, phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

362

if (!(intel_de_read(display, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

365

if ((intel_de_read(display, BXT_PORT_CL1CM_DW0(phy)) &

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

367

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

373

if (!(intel_de_read(display, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

374

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

383

static u32 bxt_get_grc(struct intel_display *display, enum dpio_phy phy)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

385

u32 val = intel_de_read(display, BXT_PORT_REF_DW6(phy));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

390

static void bxt_phy_wait_grc_done(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

393

if (intel_de_wait_for_set(display, BXT_PORT_REF_DW3(phy), GRC_DONE, 10))

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

394

drm_err(display->drm, "timeout waiting for PHY%d GRC\n", phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

397

static void _bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

402

phy_info = bxt_get_phy_info(display, phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

404

if (bxt_dpio_phy_is_enabled(display, phy)) {

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

407

display->state.bxt_phy_grc = bxt_get_grc(display, phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

409

if (bxt_dpio_phy_verify_state(display, phy)) {

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

410

drm_dbg(display->drm, "DDI PHY %d already enabled, "

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

415

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

420

intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

430

if (intel_de_wait_fw(display, BXT_PORT_CL1CM_DW0(phy),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

432

drm_err(display->drm, "timeout during PHY%d power on\n",

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

436

intel_de_rmw(display, BXT_PORT_CL1CM_DW9(phy),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

439

intel_de_rmw(display, BXT_PORT_CL1CM_DW10(phy),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

443

intel_de_rmw(display, BXT_PORT_CL1CM_DW28(phy), 0,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

447

intel_de_rmw(display, BXT_PORT_CL2CM_DW6(phy), 0,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

453

bxt_phy_wait_grc_done(display, phy_info->rcomp_phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

460

val = bxt_get_grc(display, phy_info->rcomp_phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

461

display->state.bxt_phy_grc = val;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

466

intel_de_write(display, BXT_PORT_REF_DW6(phy), grc_code);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

467

intel_de_rmw(display, BXT_PORT_REF_DW8(phy),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

474

intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

477

void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

481

phy_info = bxt_get_phy_info(display, phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

483

intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

485

intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

488

void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

490

const struct bxt_dpio_phy_info *phy_info = bxt_get_phy_info(display, phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

494

lockdep_assert_held(&display->power.domains.lock);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

498

was_enabled = bxt_dpio_phy_is_enabled(display, rcomp_phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

505

_bxt_dpio_phy_init(display, rcomp_phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

507

_bxt_dpio_phy_init(display, phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

510

bxt_dpio_phy_uninit(display, rcomp_phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

514

__phy_reg_verify_state(struct intel_display *display, enum dpio_phy phy,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

522

val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

530

drm_dbg(display->drm, "DDI PHY %d reg %pV [%08x] state mismatch: "

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

540

bool bxt_dpio_phy_verify_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

547

phy_info = bxt_get_phy_info(display, phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

550

__phy_reg_verify_state(display, phy, reg, mask, exp, fmt, \

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

553

if (!bxt_dpio_phy_is_enabled(display, phy))

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

577

u32 grc_code = display->state.bxt_phy_grc;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

616

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

622

bxt_port_to_phy_channel(display, port, &phy, &ch);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

629

intel_de_rmw(display, BXT_PORT_TX_DW14_LN(phy, ch, lane),

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

638

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

645

bxt_port_to_phy_channel(display, port, &phy, &ch);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

649

u32 val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

720

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

727

vlv_dpio_get(display->drm);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

730

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW10(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

734

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW10(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

737

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW10(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

741

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW10(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

744

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW9(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

747

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW9(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

750

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW9(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

753

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW9(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

758

val = vlv_dpio_read(display->drm, phy, CHV_TX_DW4(ch, i));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

761

vlv_dpio_write(display->drm, phy, CHV_TX_DW4(ch, i), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

766

val = vlv_dpio_read(display->drm, phy, CHV_TX_DW2(ch, i));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

779

vlv_dpio_write(display->drm, phy, CHV_TX_DW2(ch, i), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

789

val = vlv_dpio_read(display->drm, phy, CHV_TX_DW3(ch, i));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

794

vlv_dpio_write(display->drm, phy, CHV_TX_DW3(ch, i), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

798

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW10(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

800

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW10(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

803

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW10(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

805

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW10(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

808

vlv_dpio_put(display->drm);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

815

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

821

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW0(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

826

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW0(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

829

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW0(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

834

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW0(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

837

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW1(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

843

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW1(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

846

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW1(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

852

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW1(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

860

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

862

vlv_dpio_get(display->drm);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

864

vlv_dpio_put(display->drm);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

870

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

886

!chv_phy_powergate_ch(display, DPIO_PHY0, DPIO_CH1, true);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

890

vlv_dpio_get(display->drm);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

897

val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW5_CH0);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

903

vlv_dpio_write(display->drm, phy, CHV_CMN_DW5_CH0, val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

905

val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW1_CH1);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

911

vlv_dpio_write(display->drm, phy, CHV_CMN_DW1_CH1, val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

915

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW8(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

921

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW8(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

924

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW8(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

930

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW8(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

938

val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW19(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

943

vlv_dpio_write(display->drm, phy, CHV_CMN_DW19(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

945

vlv_dpio_put(display->drm);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

951

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

959

vlv_dpio_get(display->drm);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

962

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW11(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

964

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW11(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

967

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW11(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

969

vlv_dpio_write(display->drm, phy, VLV_PCS23_DW11(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

979

vlv_dpio_write(display->drm, phy, CHV_TX_DW14(ch, i), data);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

994

val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW11(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

996

vlv_dpio_write(display->drm, phy, VLV_PCS01_DW11(ch), val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

999

val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW11(ch));

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

30

void bxt_port_to_phy_channel(struct intel_display *display, enum port port,

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

34

void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

35

void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy);

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

36

bool bxt_dpio_phy_is_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

38

bool bxt_dpio_phy_verify_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

78

static inline void bxt_port_to_phy_channel(struct intel_display *display, enum port port,

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

86

static inline void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

89

static inline void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy)

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

92

static inline bool bxt_dpio_phy_is_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

97

static inline bool bxt_dpio_phy_verify_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll.c

1006

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

1016

if (display->platform.i945g || display->platform.i945gm ||

sys/dev/pci/drm/i915/display/intel_dpll.c

1017

display->platform.g33 || display->platform.pineview) {

sys/dev/pci/drm/i915/display/intel_dpll.c

1030

if (display->platform.g4x) {

sys/dev/pci/drm/i915/display/intel_dpll.c

1033

} else if (display->platform.pineview) {

sys/dev/pci/drm/i915/display/intel_dpll.c

1057

if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/intel_dpll.c

1063

intel_panel_use_ssc(display))

sys/dev/pci/drm/i915/display/intel_dpll.c

1075

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

1078

if (display->platform.pineview) {

sys/dev/pci/drm/i915/display/intel_dpll.c

1088

if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/intel_dpll.c

1096

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

1126

if (display->platform.i830 ||

sys/dev/pci/drm/i915/display/intel_dpll.c

1131

intel_panel_use_ssc(display))

sys/dev/pci/drm/i915/display/intel_dpll.c

1154

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dpll.c

1161

if (DISPLAY_VER(display) < 11 &&

sys/dev/pci/drm/i915/display/intel_dpll.c

1183

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dpll.c

1189

if (DISPLAY_VER(display) < 11 &&

sys/dev/pci/drm/i915/display/intel_dpll.c

1237

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

1240

((intel_panel_use_ssc(display) && display->vbt.lvds_ssc_freq == 100000) ||

sys/dev/pci/drm/i915/display/intel_dpll.c

1241

(HAS_PCH_IBX(display) && intel_is_dual_link_lvds(display))))

sys/dev/pci/drm/i915/display/intel_dpll.c

1270

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

1304

if (INTEL_NUM_PIPES(display) == 3 &&

sys/dev/pci/drm/i915/display/intel_dpll.c

1330

intel_panel_use_ssc(display))

sys/dev/pci/drm/i915/display/intel_dpll.c

1354

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dpll.c

1366

if (intel_panel_use_ssc(display)) {

sys/dev/pci/drm/i915/display/intel_dpll.c

1367

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dpll.c

1369

display->vbt.lvds_ssc_freq);

sys/dev/pci/drm/i915/display/intel_dpll.c

1370

refclk = display->vbt.lvds_ssc_freq;

sys/dev/pci/drm/i915/display/intel_dpll.c

1373

if (intel_is_dual_link_lvds(display)) {

sys/dev/pci/drm/i915/display/intel_dpll.c

1530

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dpll.c

1537

if (intel_panel_use_ssc(display)) {

sys/dev/pci/drm/i915/display/intel_dpll.c

1538

refclk = display->vbt.lvds_ssc_freq;

sys/dev/pci/drm/i915/display/intel_dpll.c

1539

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dpll.c

1544

if (intel_is_dual_link_lvds(display))

sys/dev/pci/drm/i915/display/intel_dpll.c

1579

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dpll.c

1586

if (intel_panel_use_ssc(display)) {

sys/dev/pci/drm/i915/display/intel_dpll.c

1587

refclk = display->vbt.lvds_ssc_freq;

sys/dev/pci/drm/i915/display/intel_dpll.c

1588

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dpll.c

1617

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dpll.c

1624

if (intel_panel_use_ssc(display)) {

sys/dev/pci/drm/i915/display/intel_dpll.c

1625

refclk = display->vbt.lvds_ssc_freq;

sys/dev/pci/drm/i915/display/intel_dpll.c

1626

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dpll.c

1657

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dpll.c

1664

if (intel_panel_use_ssc(display)) {

sys/dev/pci/drm/i915/display/intel_dpll.c

1665

refclk = display->vbt.lvds_ssc_freq;

sys/dev/pci/drm/i915/display/intel_dpll.c

1666

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dpll.c

1739

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dpll.c

1744

drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state));

sys/dev/pci/drm/i915/display/intel_dpll.c

1752

ret = display->funcs.dpll->crtc_compute_clock(state, crtc);

sys/dev/pci/drm/i915/display/intel_dpll.c

1754

drm_dbg_kms(display->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n",

sys/dev/pci/drm/i915/display/intel_dpll.c

1765

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dpll.c

1770

drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state));

sys/dev/pci/drm/i915/display/intel_dpll.c

1771

drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state->intel_dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1776

if (!display->funcs.dpll->crtc_get_dpll)

sys/dev/pci/drm/i915/display/intel_dpll.c

1779

ret = display->funcs.dpll->crtc_get_dpll(state, crtc);

sys/dev/pci/drm/i915/display/intel_dpll.c

1781

drm_dbg_kms(display->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",

sys/dev/pci/drm/i915/display/intel_dpll.c

1790

intel_dpll_init_clock_hook(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dpll.c

1792

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_dpll.c

1793

display->funcs.dpll = &mtl_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1794

else if (display->platform.dg2)

sys/dev/pci/drm/i915/display/intel_dpll.c

1795

display->funcs.dpll = &dg2_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1796

else if (DISPLAY_VER(display) >= 9 || HAS_DDI(display))

sys/dev/pci/drm/i915/display/intel_dpll.c

1797

display->funcs.dpll = &hsw_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1798

else if (HAS_PCH_SPLIT(display))

sys/dev/pci/drm/i915/display/intel_dpll.c

1799

display->funcs.dpll = &ilk_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1800

else if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_dpll.c

1801

display->funcs.dpll = &chv_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1802

else if (display->platform.valleyview)

sys/dev/pci/drm/i915/display/intel_dpll.c

1803

display->funcs.dpll = &vlv_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1804

else if (display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_dpll.c

1805

display->funcs.dpll = &g4x_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1806

else if (display->platform.pineview)

sys/dev/pci/drm/i915/display/intel_dpll.c

1807

display->funcs.dpll = &pnv_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1808

else if (DISPLAY_VER(display) != 2)

sys/dev/pci/drm/i915/display/intel_dpll.c

1809

display->funcs.dpll = &i9xx_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1811

display->funcs.dpll = &i8xx_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1814

static bool i9xx_has_pps(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dpll.c

1816

if (display->platform.i830)

sys/dev/pci/drm/i915/display/intel_dpll.c

1819

return display->platform.pineview || display->platform.mobile;

sys/dev/pci/drm/i915/display/intel_dpll.c

1824

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

1830

assert_transcoder_disabled(display, crtc_state->cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_dpll.c

1833

if (i9xx_has_pps(display))

sys/dev/pci/drm/i915/display/intel_dpll.c

1834

assert_pps_unlocked(display, pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

1836

intel_de_write(display, FP0(pipe), hw_state->fp0);

sys/dev/pci/drm/i915/display/intel_dpll.c

1837

intel_de_write(display, FP1(pipe), hw_state->fp1);

sys/dev/pci/drm/i915/display/intel_dpll.c

1844

intel_de_write(display, DPLL(display, pipe),

sys/dev/pci/drm/i915/display/intel_dpll.c

1846

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1849

intel_de_posting_read(display, DPLL(display, pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

1852

if (DISPLAY_VER(display) >= 4) {

sys/dev/pci/drm/i915/display/intel_dpll.c

1853

intel_de_write(display, DPLL_MD(display, pipe),

sys/dev/pci/drm/i915/display/intel_dpll.c

1861

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1866

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1867

intel_de_posting_read(display, DPLL(display, pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

1872

static void vlv_pllb_recal_opamp(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll.c

1881

tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW17(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

1884

vlv_dpio_write(display->drm, phy, VLV_PLL_DW17(ch), tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

1886

tmp = vlv_dpio_read(display->drm, phy, VLV_REF_DW11);

sys/dev/pci/drm/i915/display/intel_dpll.c

1889

vlv_dpio_write(display->drm, phy, VLV_REF_DW11, tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

1891

tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW17(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

1893

vlv_dpio_write(display->drm, phy, VLV_PLL_DW17(ch), tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

1895

tmp = vlv_dpio_read(display->drm, phy, VLV_REF_DW11);

sys/dev/pci/drm/i915/display/intel_dpll.c

1898

vlv_dpio_write(display->drm, phy, VLV_REF_DW11, tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

1903

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

1911

vlv_dpio_get(display->drm);

sys/dev/pci/drm/i915/display/intel_dpll.c

1917

vlv_pllb_recal_opamp(display, phy, ch);

sys/dev/pci/drm/i915/display/intel_dpll.c

1920

vlv_dpio_write(display->drm, phy, VLV_PCS_DW17_BCAST, 0x0100000f);

sys/dev/pci/drm/i915/display/intel_dpll.c

1923

tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW16(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

1925

vlv_dpio_write(display->drm, phy, VLV_PLL_DW16(ch), tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

1928

vlv_dpio_write(display->drm, phy, VLV_CMN_DW0, 0x610);

sys/dev/pci/drm/i915/display/intel_dpll.c

1944

vlv_dpio_write(display->drm, phy, VLV_PLL_DW3(ch), tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

1947

vlv_dpio_write(display->drm, phy, VLV_PLL_DW3(ch), tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

1953

vlv_dpio_write(display->drm, phy, VLV_PLL_DW18(ch), 0x009f0003);

sys/dev/pci/drm/i915/display/intel_dpll.c

1955

vlv_dpio_write(display->drm, phy, VLV_PLL_DW18(ch), 0x00d0000f);

sys/dev/pci/drm/i915/display/intel_dpll.c

1960

vlv_dpio_write(display->drm, phy, VLV_PLL_DW5(ch), 0x0df40000);

sys/dev/pci/drm/i915/display/intel_dpll.c

1962

vlv_dpio_write(display->drm, phy, VLV_PLL_DW5(ch), 0x0df70000);

sys/dev/pci/drm/i915/display/intel_dpll.c

1966

vlv_dpio_write(display->drm, phy, VLV_PLL_DW5(ch), 0x0df70000);

sys/dev/pci/drm/i915/display/intel_dpll.c

1968

vlv_dpio_write(display->drm, phy, VLV_PLL_DW5(ch), 0x0df40000);

sys/dev/pci/drm/i915/display/intel_dpll.c

1971

coreclk = vlv_dpio_read(display->drm, phy, VLV_PLL_DW7(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

1975

vlv_dpio_write(display->drm, phy, VLV_PLL_DW7(ch), coreclk);

sys/dev/pci/drm/i915/display/intel_dpll.c

1977

vlv_dpio_write(display->drm, phy, VLV_PLL_DW19(ch), 0x87871000);

sys/dev/pci/drm/i915/display/intel_dpll.c

1979

vlv_dpio_put(display->drm);

sys/dev/pci/drm/i915/display/intel_dpll.c

1984

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

1989

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1990

intel_de_posting_read(display, DPLL(display, pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

1993

if (intel_de_wait_for_set(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1))

sys/dev/pci/drm/i915/display/intel_dpll.c

1994

drm_err(display->drm, "DPLL %d failed to lock\n", pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

1999

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

2004

assert_transcoder_disabled(display, crtc_state->cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_dpll.c

2007

assert_pps_unlocked(display, pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2010

intel_de_write(display, DPLL(display, pipe),

sys/dev/pci/drm/i915/display/intel_dpll.c

2018

intel_de_write(display, DPLL_MD(display, pipe), hw_state->dpll_md);

sys/dev/pci/drm/i915/display/intel_dpll.c

2019

intel_de_posting_read(display, DPLL_MD(display, pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

2024

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

2034

vlv_dpio_get(display->drm);

sys/dev/pci/drm/i915/display/intel_dpll.c

2037

vlv_dpio_write(display->drm, phy, CHV_CMN_DW13(ch),

sys/dev/pci/drm/i915/display/intel_dpll.c

2044

vlv_dpio_write(display->drm, phy, CHV_PLL_DW0(ch),

sys/dev/pci/drm/i915/display/intel_dpll.c

2048

vlv_dpio_write(display->drm, phy, CHV_PLL_DW1(ch),

sys/dev/pci/drm/i915/display/intel_dpll.c

2053

vlv_dpio_write(display->drm, phy, CHV_PLL_DW2(ch),

sys/dev/pci/drm/i915/display/intel_dpll.c

2057

tmp = vlv_dpio_read(display->drm, phy, CHV_PLL_DW3(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

2062

vlv_dpio_write(display->drm, phy, CHV_PLL_DW3(ch), tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

2065

tmp = vlv_dpio_read(display->drm, phy, CHV_PLL_DW9(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

2071

vlv_dpio_write(display->drm, phy, CHV_PLL_DW9(ch), tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

2096

vlv_dpio_write(display->drm, phy, CHV_PLL_DW6(ch), loopfilter);

sys/dev/pci/drm/i915/display/intel_dpll.c

2098

tmp = vlv_dpio_read(display->drm, phy, CHV_PLL_DW8(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

2101

vlv_dpio_write(display->drm, phy, CHV_PLL_DW8(ch), tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

2104

vlv_dpio_write(display->drm, phy, CHV_CMN_DW14(ch),

sys/dev/pci/drm/i915/display/intel_dpll.c

2105

vlv_dpio_read(display->drm, phy, CHV_CMN_DW14(ch)) |

sys/dev/pci/drm/i915/display/intel_dpll.c

2108

vlv_dpio_put(display->drm);

sys/dev/pci/drm/i915/display/intel_dpll.c

2113

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

2121

vlv_dpio_get(display->drm);

sys/dev/pci/drm/i915/display/intel_dpll.c

2124

tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW14(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

2126

vlv_dpio_write(display->drm, phy, CHV_CMN_DW14(ch), tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

2128

vlv_dpio_put(display->drm);

sys/dev/pci/drm/i915/display/intel_dpll.c

2136

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

2139

if (intel_de_wait_for_set(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1))

sys/dev/pci/drm/i915/display/intel_dpll.c

2140

drm_err(display->drm, "PLL %d failed to lock\n", pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2145

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

2150

assert_transcoder_disabled(display, crtc_state->cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_dpll.c

2153

assert_pps_unlocked(display, pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2156

intel_de_write(display, DPLL(display, pipe),

sys/dev/pci/drm/i915/display/intel_dpll.c

2171

intel_de_write(display, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

2172

intel_de_write(display, DPLL_MD(display, PIPE_B),

sys/dev/pci/drm/i915/display/intel_dpll.c

2174

intel_de_write(display, CBR4_VLV, 0);

sys/dev/pci/drm/i915/display/intel_dpll.c

2175

display->state.chv_dpll_md[pipe] = hw_state->dpll_md;

sys/dev/pci/drm/i915/display/intel_dpll.c

2181

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_dpll.c

2182

(intel_de_read(display, DPLL(display, PIPE_B)) &

sys/dev/pci/drm/i915/display/intel_dpll.c

2185

intel_de_write(display, DPLL_MD(display, pipe),

sys/dev/pci/drm/i915/display/intel_dpll.c

2187

intel_de_posting_read(display, DPLL_MD(display, pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

2201

int vlv_force_pll_on(struct intel_display *display, enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_dpll.c

2204

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2216

if (display->platform.cherryview) {

sys/dev/pci/drm/i915/display/intel_dpll.c

2229

void vlv_disable_pll(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_dpll.c

2234

assert_transcoder_disabled(display, (enum transcoder)pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2241

intel_de_write(display, DPLL(display, pipe), val);

sys/dev/pci/drm/i915/display/intel_dpll.c

2242

intel_de_posting_read(display, DPLL(display, pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

2245

void chv_disable_pll(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_dpll.c

2252

assert_transcoder_disabled(display, (enum transcoder)pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2259

intel_de_write(display, DPLL(display, pipe), val);

sys/dev/pci/drm/i915/display/intel_dpll.c

2260

intel_de_posting_read(display, DPLL(display, pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

2262

vlv_dpio_get(display->drm);

sys/dev/pci/drm/i915/display/intel_dpll.c

2265

val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW14(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

2267

vlv_dpio_write(display->drm, phy, CHV_CMN_DW14(ch), val);

sys/dev/pci/drm/i915/display/intel_dpll.c

2269

vlv_dpio_put(display->drm);

sys/dev/pci/drm/i915/display/intel_dpll.c

2274

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

2279

if (display->platform.i830)

sys/dev/pci/drm/i915/display/intel_dpll.c

2283

assert_transcoder_disabled(display, crtc_state->cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_dpll.c

2285

intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS);

sys/dev/pci/drm/i915/display/intel_dpll.c

2286

intel_de_posting_read(display, DPLL(display, pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

2298

void vlv_force_pll_off(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_dpll.c

2300

if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_dpll.c

2301

chv_disable_pll(display, pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2303

vlv_disable_pll(display, pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2307

static void assert_pll(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll.c

2312

cur_state = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;

sys/dev/pci/drm/i915/display/intel_dpll.c

2313

INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

sys/dev/pci/drm/i915/display/intel_dpll.c

2318

void assert_pll_enabled(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_dpll.c

2320

assert_pll(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_dpll.c

2323

void assert_pll_disabled(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_dpll.c

2325

assert_pll(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_dpll.c

377

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

381

return display->vbt.lvds_ssc_freq;

sys/dev/pci/drm/i915/display/intel_dpll.c

382

else if (HAS_PCH_SPLIT(display))

sys/dev/pci/drm/i915/display/intel_dpll.c

384

else if (DISPLAY_VER(display) != 2)

sys/dev/pci/drm/i915/display/intel_dpll.c

393

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_dpll.c

396

if (DISPLAY_VER(display) >= 4) {

sys/dev/pci/drm/i915/display/intel_dpll.c

400

if (display->platform.cherryview && crtc->pipe != PIPE_A)

sys/dev/pci/drm/i915/display/intel_dpll.c

401

tmp = display->state.chv_dpll_md[crtc->pipe];

sys/dev/pci/drm/i915/display/intel_dpll.c

403

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll.c

404

DPLL_MD(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

409

hw_state->dpll = intel_de_read(display, DPLL(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

411

if (!display->platform.valleyview && !display->platform.cherryview) {

sys/dev/pci/drm/i915/display/intel_dpll.c

412

hw_state->fp0 = intel_de_read(display, FP0(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

413

hw_state->fp1 = intel_de_read(display, FP1(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

425

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

440

if (display->platform.pineview) {

sys/dev/pci/drm/i915/display/intel_dpll.c

448

if (DISPLAY_VER(display) != 2) {

sys/dev/pci/drm/i915/display/intel_dpll.c

449

if (display->platform.pineview)

sys/dev/pci/drm/i915/display/intel_dpll.c

466

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dpll.c

472

if (display->platform.pineview)

sys/dev/pci/drm/i915/display/intel_dpll.c

479

if (display->platform.i85x &&

sys/dev/pci/drm/i915/display/intel_dpll.c

480

intel_lvds_port_enabled(display, LVDS, &lvds_pipe) &&

sys/dev/pci/drm/i915/display/intel_dpll.c

482

u32 lvds = intel_de_read(display, LVDS);

sys/dev/pci/drm/i915/display/intel_dpll.c

517

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

530

vlv_dpio_get(display->drm);

sys/dev/pci/drm/i915/display/intel_dpll.c

531

tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW3(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

532

vlv_dpio_put(display->drm);

sys/dev/pci/drm/i915/display/intel_dpll.c

545

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

558

vlv_dpio_get(display->drm);

sys/dev/pci/drm/i915/display/intel_dpll.c

559

cmn_dw13 = vlv_dpio_read(display->drm, phy, CHV_CMN_DW13(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

560

pll_dw0 = vlv_dpio_read(display->drm, phy, CHV_PLL_DW0(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

561

pll_dw1 = vlv_dpio_read(display->drm, phy, CHV_PLL_DW1(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

562

pll_dw2 = vlv_dpio_read(display->drm, phy, CHV_PLL_DW2(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

563

pll_dw3 = vlv_dpio_read(display->drm, phy, CHV_PLL_DW3(ch));

sys/dev/pci/drm/i915/display/intel_dpll.c

564

vlv_dpio_put(display->drm);

sys/dev/pci/drm/i915/display/intel_dpll.c

581

static bool intel_pll_is_valid(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll.c

594

if (!display->platform.pineview &&

sys/dev/pci/drm/i915/display/intel_dpll.c

595

!display->platform.valleyview && !display->platform.cherryview &&

sys/dev/pci/drm/i915/display/intel_dpll.c

596

!display->platform.broxton && !display->platform.geminilake)

sys/dev/pci/drm/i915/display/intel_dpll.c

600

if (!display->platform.valleyview && !display->platform.cherryview &&

sys/dev/pci/drm/i915/display/intel_dpll.c

601

!display->platform.broxton && !display->platform.geminilake) {

sys/dev/pci/drm/i915/display/intel_dpll.c

624

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

632

if (intel_is_dual_link_lvds(display))

sys/dev/pci/drm/i915/display/intel_dpll.c

660

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

681

if (!intel_pll_is_valid(display,

sys/dev/pci/drm/i915/display/intel_dpll.c

718

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

737

if (!intel_pll_is_valid(display,

sys/dev/pci/drm/i915/display/intel_dpll.c

774

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

798

if (!intel_pll_is_valid(display,

sys/dev/pci/drm/i915/display/intel_dpll.c

821

static bool vlv_PLL_is_optimal(struct intel_display *display, int target_freq,

sys/dev/pci/drm/i915/display/intel_dpll.c

831

if (display->platform.cherryview) {

sys/dev/pci/drm/i915/display/intel_dpll.c

837

if (drm_WARN_ON_ONCE(display->drm, !target_freq))

sys/dev/pci/drm/i915/display/intel_dpll.c

868

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

892

if (!intel_pll_is_valid(display,

sys/dev/pci/drm/i915/display/intel_dpll.c

897

if (!vlv_PLL_is_optimal(display, target,

sys/dev/pci/drm/i915/display/intel_dpll.c

925

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

960

if (!intel_pll_is_valid(display, limit, &clock))

sys/dev/pci/drm/i915/display/intel_dpll.c

963

if (!vlv_PLL_is_optimal(display, target, &clock, best_clock,

sys/dev/pci/drm/i915/display/intel_dpll.h

19

void intel_dpll_init_clock_hook(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dpll.h

31

int vlv_force_pll_on(struct intel_display *display, enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_dpll.h

33

void vlv_force_pll_off(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_dpll.h

36

void chv_disable_pll(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_dpll.h

38

void vlv_disable_pll(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_dpll.h

49

void assert_pll_enabled(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_dpll.h

50

void assert_pll_disabled(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1010

if (display->platform.haswell && !display->platform.haswell_ult) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1011

refclk = display->dpll.ref_clks.nssc;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1021

refclk = display->dpll.ref_clks.ssc;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1043

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1056

crtc_state->port_clock = hsw_ddi_wrpll_get_freq(display, NULL,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1078

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1087

drm_dbg_kms(display->drm, "Invalid clock for DP: %d\n",

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1096

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1116

pll = intel_get_dpll_by_id(display, pll_id);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1124

static int hsw_ddi_lcpll_get_freq(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1141

drm_WARN(display->drm, 1, "bad port clock sel\n");

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

116

void (*update_ref_clks)(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1176

static int hsw_ddi_spll_get_freq(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1194

drm_WARN(display->drm, 1, "bad spll freq\n");

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

124

intel_atomic_duplicate_dpll_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1244

static void hsw_update_dpll_ref_clks(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1246

display->dpll.ref_clks.ssc = 135000;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1248

if (intel_de_read(display, FUSE_STRAP3) & HSW_REF_CLK_SELECT)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1249

display->dpll.ref_clks.nssc = 24000;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1251

display->dpll.ref_clks.nssc = 135000;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1287

static void hsw_ddi_lcpll_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1293

static void hsw_ddi_lcpll_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1298

static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

131

for_each_dpll(display, pll, i)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1366

static void skl_ddi_pll_write_ctrl1(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1372

intel_de_rmw(display, DPLL_CTRL1,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1377

intel_de_posting_read(display, DPLL_CTRL1);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1380

static void skl_ddi_pll_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1388

skl_ddi_pll_write_ctrl1(display, pll, hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

139

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1390

intel_de_write(display, regs[id].cfgcr1, hw_state->cfgcr1);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1391

intel_de_write(display, regs[id].cfgcr2, hw_state->cfgcr2);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1392

intel_de_posting_read(display, regs[id].cfgcr1);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1393

intel_de_posting_read(display, regs[id].cfgcr2);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1396

intel_de_rmw(display, regs[id].ctl, 0, LCPLL_PLL_ENABLE);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1398

if (intel_de_wait_for_set(display, DPLL_STATUS, DPLL_LOCK(id), 5))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1399

drm_err(display->drm, "DPLL %d not locked\n", id);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1402

static void skl_ddi_dpll0_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1408

skl_ddi_pll_write_ctrl1(display, pll, hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1411

static void skl_ddi_pll_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1418

intel_de_rmw(display, regs[id].ctl, LCPLL_PLL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1419

intel_de_posting_read(display, regs[id].ctl);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1422

static void skl_ddi_dpll0_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1427

static bool skl_ddi_pll_get_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1438

wakeref = intel_display_power_get_if_enabled(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1445

val = intel_de_read(display, regs[id].ctl);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1449

val = intel_de_read(display, DPLL_CTRL1);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1454

hw_state->cfgcr1 = intel_de_read(display, regs[id].cfgcr1);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1455

hw_state->cfgcr2 = intel_de_read(display, regs[id].cfgcr2);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

146

intel_atomic_duplicate_dpll_state(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1460

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1465

static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1476

wakeref = intel_display_power_get_if_enabled(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1484

val = intel_de_read(display, regs[id].ctl);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1485

if (drm_WARN_ON(display->drm, !(val & LCPLL_PLL_ENABLE)))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1488

val = intel_de_read(display, DPLL_CTRL1);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1494

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

162

intel_get_dpll_by_id(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

168

for_each_dpll(display, pll, i) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1738

static int skl_ddi_wrpll_get_freq(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1743

int ref_clock = display->dpll.ref_clks.nssc;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1770

drm_dbg_kms(display->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

178

void assert_dpll(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1804

if (drm_WARN_ON(display->drm, p0 == 0 || p1 == 0 || p2 == 0))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1812

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1818

display->dpll.ref_clks.nssc, &wrpll_params);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1842

crtc_state->port_clock = skl_ddi_wrpll_get_freq(display, NULL,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

185

if (drm_WARN(display->drm, !pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1886

static int skl_ddi_lcpll_get_freq(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

189

cur_state = intel_dpll_get_hw_state(display, pll, &hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

190

INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1914

drm_WARN(display->drm, 1, "Unsupported link rate\n");

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1965

static int skl_ddi_pll_get_freq(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1976

return skl_ddi_wrpll_get_freq(display, pll, dpll_hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1978

return skl_ddi_lcpll_get_freq(display, pll, dpll_hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1981

static void skl_update_dpll_ref_clks(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1984

display->dpll.ref_clks.nssc = display->cdclk.hw.ref;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2040

static void bxt_ddi_pll_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2051

bxt_port_to_phy_channel(display, port, &phy, &ch);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2054

intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2056

if (display->platform.geminilake) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2057

intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2060

ret = intel_de_wait_custom(display, BXT_PORT_PLL_ENABLE(port),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2064

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2069

intel_de_rmw(display, BXT_PORT_PLL_EBB_4(phy, ch),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

207

intel_combo_pll_enable_reg(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2073

intel_de_rmw(display, BXT_PORT_PLL_EBB_0(phy, ch),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2077

intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 0),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2081

intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 1),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2085

intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 2),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2089

intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 3),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2093

temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2098

intel_de_write(display, BXT_PORT_PLL(phy, ch, 6), temp);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

210

if (display->platform.dg1)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2101

intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 8),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2104

intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 9),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2107

temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2111

intel_de_write(display, BXT_PORT_PLL(phy, ch, 10), temp);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2114

temp = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2116

intel_de_write(display, BXT_PORT_PLL_EBB_4(phy, ch), temp);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2119

intel_de_write(display, BXT_PORT_PLL_EBB_4(phy, ch), temp);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

212

else if ((display->platform.jasperlake || display->platform.elkhartlake) &&

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2122

intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2123

intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2125

ret = intel_de_wait_custom(display, BXT_PORT_PLL_ENABLE(port),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2129

drm_err(display->drm, "PLL %d not locked\n", port);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2131

if (display->platform.geminilake) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2132

temp = intel_de_read(display, BXT_PORT_TX_DW5_LN(phy, ch, 0));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2134

intel_de_write(display, BXT_PORT_TX_DW5_GRP(phy, ch), temp);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2141

temp = intel_de_read(display, BXT_PORT_PCS_DW12_LN01(phy, ch));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2145

intel_de_write(display, BXT_PORT_PCS_DW12_GRP(phy, ch), temp);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2148

static void bxt_ddi_pll_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2154

intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2155

intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2157

if (display->platform.geminilake) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2158

intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2161

ret = intel_de_wait_custom(display, BXT_PORT_PLL_ENABLE(port),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2165

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2170

static bool bxt_ddi_pll_get_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2182

bxt_port_to_phy_channel(display, port, &phy, &ch);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2184

wakeref = intel_display_power_get_if_enabled(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2191

val = intel_de_read(display, BXT_PORT_PLL_ENABLE(port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2195

hw_state->ebb0 = intel_de_read(display, BXT_PORT_PLL_EBB_0(phy, ch));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2198

hw_state->ebb4 = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

220

intel_tc_pll_enable_reg(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2201

hw_state->pll0 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 0));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2204

hw_state->pll1 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 1));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2207

hw_state->pll2 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 2));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2210

hw_state->pll3 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 3));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2213

hw_state->pll6 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2218

hw_state->pll8 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 8));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2221

hw_state->pll9 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 9));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2224

hw_state->pll10 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2233

hw_state->pcsdw12 = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2235

if (intel_de_read(display, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2236

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2239

intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2246

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

226

if (display->platform.alderlake_p)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2267

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2277

drm_WARN_ON(display->drm, clk_div->m1 != 2);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2285

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2296

chv_calc_dpll_params(display->dpll.ref_clks.nssc, clk_div);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2298

drm_WARN_ON(display->drm, clk_div->vco == 0 ||

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2305

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

232

static void _intel_enable_shared_dpll(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2329

drm_err(display->drm, "Invalid VCO\n");

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

236

pll->wakeref = intel_display_power_get(display, pll->info->power_domain);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2370

static int bxt_ddi_pll_get_freq(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

238

pll->info->funcs->enable(display, pll, &pll->state.hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2386

return chv_calc_dpll_params(display->dpll.ref_clks.nssc, &clock);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2402

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2412

crtc_state->port_clock = bxt_ddi_pll_get_freq(display, NULL,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

242

static void _intel_disable_shared_dpll(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2437

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2445

pll = intel_get_dpll_by_id(display, id);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2447

drm_dbg_kms(display->drm, "[CRTC:%d:%s] using pre-allocated %s\n",

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

245

pll->info->funcs->disable(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2458

static void bxt_update_dpll_ref_clks(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2460

display->dpll.ref_clks.ssc = 100000;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2461

display->dpll.ref_clks.nssc = 100000;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

249

intel_display_power_put(display, pll->info->power_domain, pll->wakeref);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

260

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2613

ehl_combo_pll_div_frac_wa_needed(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2615

return ((display->platform.elkhartlake &&

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2616

IS_DISPLAY_STEP(display, STEP_B0, STEP_FOREVER)) ||

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2617

DISPLAY_VER(display) >= 12) &&

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2618

display->dpll.ref_clks.nssc == 38400;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

266

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

269

mutex_lock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2710

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2712

display->dpll.ref_clks.nssc == 24000 ?

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

272

if (drm_WARN_ON(display->drm, !(pll->state.pipe_mask & pipe_mask)) ||

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

273

drm_WARN_ON(display->drm, pll->active_mask & pipe_mask))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2732

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2734

if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2735

switch (display->dpll.ref_clks.nssc) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2737

MISSING_CASE(display->dpll.ref_clks.nssc);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2748

switch (display->dpll.ref_clks.nssc) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2750

MISSING_CASE(display->dpll.ref_clks.nssc);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2765

static int icl_ddi_tbt_pll_get_freq(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2773

drm_WARN_ON(display->drm, 1);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2778

static int icl_wrpll_ref_clock(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

278

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2780

int ref_clock = display->dpll.ref_clks.nssc;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2796

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2797

int ref_clock = icl_wrpll_ref_clock(display);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2836

static int icl_ddi_combo_pll_get_freq(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

284

drm_WARN_ON(display->drm, !pll->on);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2841

int ref_clock = icl_wrpll_ref_clock(display);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

285

assert_dpll_enabled(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

288

drm_WARN_ON(display->drm, pll->on);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2887

if (ehl_combo_pll_div_frac_wa_needed(display))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2892

if (drm_WARN_ON(display->drm, p0 == 0 || p1 == 0 || p2 == 0))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2898

static void icl_calc_dpll_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

290

drm_dbg_kms(display->drm, "enabling %s\n", pll->info->name);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2905

if (ehl_combo_pll_div_frac_wa_needed(display))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2916

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

292

_intel_enable_shared_dpll(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2921

if (display->vbt.override_afc_startup)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2922

hw_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(display->vbt.override_afc_startup_val);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

295

mutex_unlock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3008

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3010

int refclk_khz = display->dpll.ref_clks.nssc;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3020

bool is_dkl = DISPLAY_VER(display) >= 12;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

306

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3118

if (display->vbt.override_afc_startup) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3119

u8 val = display->vbt.override_afc_startup_val;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

312

if (DISPLAY_VER(display) < 5)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

318

mutex_lock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

319

if (drm_WARN(display->drm, !(pll->active_mask & pipe_mask),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3209

static int icl_ddi_mg_pll_get_freq(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3217

ref_clock = display->dpll.ref_clks.nssc;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3219

if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

324

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

329

assert_dpll_enabled(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

330

drm_WARN_ON(display->drm, !pll->on);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3324

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3341

icl_calc_dpll_state(display, &pll_params, &port_dpll->hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3346

crtc_state->port_clock = icl_ddi_combo_pll_get_freq(display, NULL,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3356

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

336

drm_dbg_kms(display->drm, "disabling %s\n", pll->info->name);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3364

if (display->platform.alderlake_s) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3370

} else if (display->platform.dg1) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

338

_intel_disable_shared_dpll(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3380

} else if (display->platform.rocketlake) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3385

} else if ((display->platform.jasperlake ||

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3386

display->platform.elkhartlake) &&

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3397

dpll_mask &= ~intel_hti_dpll_mask(display);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

341

mutex_unlock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3416

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3431

icl_calc_dpll_state(display, &pll_params, &port_dpll->hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3445

crtc_state->port_clock = icl_ddi_mg_pll_get_freq(display, NULL,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

345

intel_dpll_mask_all(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

351

for_each_dpll(display, pll, i) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

352

drm_WARN_ON(display->drm, dpll_mask & BIT(pll->info->id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3548

static bool mg_pll_get_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3559

i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3561

wakeref = intel_display_power_get_if_enabled(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3566

val = intel_de_read(display, enable_reg);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3570

hw_state->mg_refclkin_ctl = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3575

intel_de_read(display, MG_CLKTOP2_CORECLKCTL1(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3580

intel_de_read(display, MG_CLKTOP2_HSCLKCTL(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3587

hw_state->mg_pll_div0 = intel_de_read(display, MG_PLL_DIV0(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3588

hw_state->mg_pll_div1 = intel_de_read(display, MG_PLL_DIV1(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3589

hw_state->mg_pll_lf = intel_de_read(display, MG_PLL_LF(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3590

hw_state->mg_pll_frac_lock = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3592

hw_state->mg_pll_ssc = intel_de_read(display, MG_PLL_SSC(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3594

hw_state->mg_pll_bias = intel_de_read(display, MG_PLL_BIAS(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3596

intel_de_read(display, MG_PLL_TDC_COLDST_BIAS(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3598

if (display->dpll.ref_clks.nssc == 38400) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3611

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3615

static bool dkl_pll_get_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3626

wakeref = intel_display_power_get_if_enabled(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3631

val = intel_de_read(display, intel_tc_pll_enable_reg(display, pll));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3639

hw_state->mg_refclkin_ctl = intel_dkl_phy_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3644

intel_dkl_phy_read(display, DKL_CLKTOP2_HSCLKCTL(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3652

intel_dkl_phy_read(display, DKL_CLKTOP2_CORECLKCTL1(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3656

hw_state->mg_pll_div0 = intel_dkl_phy_read(display, DKL_PLL_DIV0(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3658

if (display->vbt.override_afc_startup)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

366

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3662

hw_state->mg_pll_div1 = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3666

hw_state->mg_pll_ssc = intel_dkl_phy_read(display, DKL_PLL_SSC(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

367

unsigned long dpll_mask_all = intel_dpll_mask_all(display);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3672

hw_state->mg_pll_bias = intel_dkl_phy_read(display, DKL_PLL_BIAS(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3677

intel_dkl_phy_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3683

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3687

static bool icl_pll_get_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3698

wakeref = intel_display_power_get_if_enabled(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3703

val = intel_de_read(display, enable_reg);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3707

if (display->platform.alderlake_s) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3708

hw_state->cfgcr0 = intel_de_read(display, ADLS_DPLL_CFGCR0(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3709

hw_state->cfgcr1 = intel_de_read(display, ADLS_DPLL_CFGCR1(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3710

} else if (display->platform.dg1) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3711

hw_state->cfgcr0 = intel_de_read(display, DG1_DPLL_CFGCR0(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3712

hw_state->cfgcr1 = intel_de_read(display, DG1_DPLL_CFGCR1(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3713

} else if (display->platform.rocketlake) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3714

hw_state->cfgcr0 = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3716

hw_state->cfgcr1 = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3718

} else if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3719

hw_state->cfgcr0 = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3721

hw_state->cfgcr1 = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3723

if (display->vbt.override_afc_startup) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3724

hw_state->div0 = intel_de_read(display, TGL_DPLL0_DIV0(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3728

if ((display->platform.jasperlake || display->platform.elkhartlake) &&

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3730

hw_state->cfgcr0 = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3732

hw_state->cfgcr1 = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3735

hw_state->cfgcr0 = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3737

hw_state->cfgcr1 = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

374

drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3744

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3748

static bool combo_pll_get_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3752

i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3754

return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3757

static bool tbt_pll_get_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3761

return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3764

static void icl_dpll_write(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3771

if (display->platform.alderlake_s) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3774

} else if (display->platform.dg1) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3777

} else if (display->platform.rocketlake) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3780

} else if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3785

if ((display->platform.jasperlake || display->platform.elkhartlake) &&

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

379

pll = intel_get_dpll_by_id(display, id);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3795

intel_de_write(display, cfgcr0_reg, hw_state->cfgcr0);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3796

intel_de_write(display, cfgcr1_reg, hw_state->cfgcr1);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3797

drm_WARN_ON_ONCE(display->drm, display->vbt.override_afc_startup &&

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3799

if (display->vbt.override_afc_startup &&

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3801

intel_de_rmw(display, div0_reg,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3803

intel_de_posting_read(display, cfgcr1_reg);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3806

static void icl_mg_pll_write(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3818

intel_de_rmw(display, MG_REFCLKIN_CTL(tc_port),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3821

intel_de_rmw(display, MG_CLKTOP2_CORECLKCTL1(tc_port),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3825

intel_de_rmw(display, MG_CLKTOP2_HSCLKCTL(tc_port),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3832

intel_de_write(display, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3833

intel_de_write(display, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3834

intel_de_write(display, MG_PLL_LF(tc_port), hw_state->mg_pll_lf);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3835

intel_de_write(display, MG_PLL_FRAC_LOCK(tc_port),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3837

intel_de_write(display, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3839

intel_de_rmw(display, MG_PLL_BIAS(tc_port),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3842

intel_de_rmw(display, MG_PLL_TDC_COLDST_BIAS(tc_port),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3846

intel_de_posting_read(display, MG_PLL_TDC_COLDST_BIAS(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3849

static void dkl_pll_write(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3861

val = intel_dkl_phy_read(display, DKL_REFCLKIN_CTL(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3864

intel_dkl_phy_write(display, DKL_REFCLKIN_CTL(tc_port), val);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3866

val = intel_dkl_phy_read(display, DKL_CLKTOP2_CORECLKCTL1(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3869

intel_dkl_phy_write(display, DKL_CLKTOP2_CORECLKCTL1(tc_port), val);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3871

val = intel_dkl_phy_read(display, DKL_CLKTOP2_HSCLKCTL(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3877

intel_dkl_phy_write(display, DKL_CLKTOP2_HSCLKCTL(tc_port), val);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3880

if (display->vbt.override_afc_startup)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3882

intel_dkl_phy_rmw(display, DKL_PLL_DIV0(tc_port), val,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3885

val = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3889

intel_dkl_phy_write(display, DKL_PLL_DIV1(tc_port), val);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3891

val = intel_dkl_phy_read(display, DKL_PLL_SSC(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3897

intel_dkl_phy_write(display, DKL_PLL_SSC(tc_port), val);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3899

val = intel_dkl_phy_read(display, DKL_PLL_BIAS(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3903

intel_dkl_phy_write(display, DKL_PLL_BIAS(tc_port), val);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3905

val = intel_dkl_phy_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3909

intel_dkl_phy_write(display, DKL_PLL_TDC_COLDST_BIAS(tc_port), val);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3911

intel_dkl_phy_posting_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3914

static void icl_pll_power_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3918

intel_de_rmw(display, enable_reg, 0, PLL_POWER_ENABLE);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3924

if (intel_de_wait_for_set(display, enable_reg, PLL_POWER_STATE, 1))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3925

drm_err(display->drm, "PLL %d Power not enabled\n",

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3929

static void icl_pll_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

393

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3933

intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3936

if (intel_de_wait_for_set(display, enable_reg, PLL_LOCK, 1))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3937

drm_err(display->drm, "PLL %d not locked\n", pll->info->id);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3940

static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3944

if (!(display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) ||

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3958

val = intel_de_read(display, TRANS_CMTG_CHICKEN);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3959

val = intel_de_rmw(display, TRANS_CMTG_CHICKEN, ~0, DISABLE_DPT_CLK_GATING);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3960

if (drm_WARN_ON(display->drm, val & ~DISABLE_DPT_CLK_GATING))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3961

drm_dbg_kms(display->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3964

static void combo_pll_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3969

i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3971

icl_pll_power_enable(display, pll, enable_reg);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3973

icl_dpll_write(display, pll, hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3981

icl_pll_enable(display, pll, enable_reg);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3983

adlp_cmtg_clock_gating_wa(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3988

static void tbt_pll_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3994

icl_pll_power_enable(display, pll, TBT_PLL_ENABLE);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3996

icl_dpll_write(display, pll, hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4004

icl_pll_enable(display, pll, TBT_PLL_ENABLE);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4009

static void mg_pll_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4014

i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4016

icl_pll_power_enable(display, pll, enable_reg);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4018

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4019

dkl_pll_write(display, pll, hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4021

icl_mg_pll_write(display, pll, hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4029

icl_pll_enable(display, pll, enable_reg);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4034

static void icl_pll_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4046

intel_de_rmw(display, enable_reg, PLL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4049

if (intel_de_wait_for_clear(display, enable_reg, PLL_LOCK, 1))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

405

drm_dbg_kms(display->drm, "[CRTC:%d:%s] allocated %s\n",

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4050

drm_err(display->drm, "PLL %d locked\n", pll->info->id);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4054

intel_de_rmw(display, enable_reg, PLL_POWER_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4060

if (intel_de_wait_for_clear(display, enable_reg, PLL_POWER_STATE, 1))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4061

drm_err(display->drm, "PLL %d Power not disabled\n",

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4065

static void combo_pll_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4068

i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4070

icl_pll_disable(display, pll, enable_reg);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4073

static void tbt_pll_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4076

icl_pll_disable(display, pll, TBT_PLL_ENABLE);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4079

static void mg_pll_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4082

i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4084

icl_pll_disable(display, pll, enable_reg);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4087

static void icl_update_dpll_ref_clks(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4090

display->dpll.ref_clks.nssc = display->cdclk.hw.ref;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

427

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

429

drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4315

void intel_dpll_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4321

rw_init(&display->dpll.lock, "dplllk");

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4323

if (DISPLAY_VER(display) >= 14 || display->platform.dg2)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4326

else if (display->platform.alderlake_p)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4328

else if (display->platform.alderlake_s)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

433

drm_dbg_kms(display->drm, "[CRTC:%d:%s] reserving %s\n",

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4330

else if (display->platform.dg1)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4332

else if (display->platform.rocketlake)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4334

else if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4336

else if (display->platform.jasperlake || display->platform.elkhartlake)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4338

else if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4340

else if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4342

else if (DISPLAY_VER(display) == 9)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4344

else if (HAS_DDI(display))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4346

else if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4355

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4356

i >= ARRAY_SIZE(display->dpll.dplls)))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4360

if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4363

display->dpll.dplls[i].info = &dpll_info[i];

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4364

display->dpll.dplls[i].index = i;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4367

display->dpll.mgr = dpll_mgr;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4368

display->dpll.num_dpll = i;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4389

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4390

const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4392

if (drm_WARN_ON(display->drm, !dpll_mgr))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4422

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4423

const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4425

if (drm_WARN_ON(display->drm, !dpll_mgr))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4445

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4446

const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4474

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4475

const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4477

if (drm_WARN_ON(display->drm, !dpll_mgr))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4491

int intel_dpll_get_freq(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4495

if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4498

return pll->info->funcs->get_freq(display, pll, dpll_hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4509

bool intel_dpll_get_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4513

return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4516

static void readout_dpll_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4521

pll->on = intel_dpll_get_hw_state(display, pll, &pll->state.hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4524

pll->wakeref = intel_display_power_get(display, pll->info->power_domain);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4527

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4536

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4541

void intel_dpll_update_ref_clks(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4543

if (display->dpll.mgr && display->dpll.mgr->update_ref_clks)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4544

display->dpll.mgr->update_ref_clks(display);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4547

void intel_dpll_readout_hw_state(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4552

for_each_dpll(display, pll, i)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4553

readout_dpll_hw_state(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4556

static void sanitize_dpll_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4562

adlp_cmtg_clock_gating_wa(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4567

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4571

_intel_disable_shared_dpll(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4574

void intel_dpll_sanitize_state(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4579

intel_cx0_pll_power_save_wa(display);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4581

for_each_dpll(display, pll, i)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4582

sanitize_dpll_state(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4593

void intel_dpll_dump_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4597

if (display->dpll.mgr) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4598

display->dpll.mgr->dump_hw_state(p, dpll_hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4617

bool intel_dpll_compare_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4621

if (display->dpll.mgr) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4622

return display->dpll.mgr->compare_hw_state(a, b);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4632

verify_single_dpll_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4641

active = intel_dpll_get_hw_state(display, pll, &dpll_hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4644

INTEL_DISPLAY_STATE_WARN(display, !pll->on && pll->active_mask,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4647

INTEL_DISPLAY_STATE_WARN(display, pll->on && !pll->active_mask,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4650

INTEL_DISPLAY_STATE_WARN(display, pll->on != active,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4656

INTEL_DISPLAY_STATE_WARN(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

466

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4667

INTEL_DISPLAY_STATE_WARN(display, !(pll->active_mask & pipe_mask),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4671

INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4675

INTEL_DISPLAY_STATE_WARN(display, !(pll->state.pipe_mask & pipe_mask),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4679

INTEL_DISPLAY_STATE_WARN(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

468

drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4696

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4703

verify_single_dpll_state(display, new_crtc_state->intel_dpll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4711

INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4716

INTEL_DISPLAY_STATE_WARN(display, !has_alt_port_dpll(old_crtc_state->intel_dpll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

472

drm_dbg_kms(display->drm, "[CRTC:%d:%s] releasing %s\n",

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4726

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4730

for_each_dpll(display, pll, i)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4731

verify_single_dpll_state(display, pll, NULL, NULL);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

516

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

524

for_each_dpll(display, pll, i)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

528

static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

537

wakeref = intel_display_power_get_if_enabled(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

542

val = intel_de_read(display, PCH_DPLL(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

544

hw_state->fp0 = intel_de_read(display, PCH_FP0(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

545

hw_state->fp1 = intel_de_read(display, PCH_FP1(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

547

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

552

static void ibx_assert_pch_refclk_enabled(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

557

val = intel_de_read(display, PCH_DREF_CONTROL);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

560

INTEL_DISPLAY_STATE_WARN(display, !enabled,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

564

static void ibx_pch_dpll_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

572

ibx_assert_pch_refclk_enabled(display);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

574

intel_de_write(display, PCH_FP0(id), hw_state->fp0);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

575

intel_de_write(display, PCH_FP1(id), hw_state->fp1);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

577

intel_de_write(display, PCH_DPLL(id), hw_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

580

intel_de_posting_read(display, PCH_DPLL(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

588

intel_de_write(display, PCH_DPLL(id), hw_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

589

intel_de_posting_read(display, PCH_DPLL(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

593

static void ibx_pch_dpll_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

598

intel_de_write(display, PCH_DPLL(id), 0);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

599

intel_de_posting_read(display, PCH_DPLL(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

614

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

620

if (HAS_PCH_IBX(display)) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

623

pll = intel_get_dpll_by_id(display, id);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

625

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

694

static void hsw_ddi_wrpll_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

701

intel_de_write(display, WRPLL_CTL(id), hw_state->wrpll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

702

intel_de_posting_read(display, WRPLL_CTL(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

706

static void hsw_ddi_spll_enable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

712

intel_de_write(display, SPLL_CTL, hw_state->spll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

713

intel_de_posting_read(display, SPLL_CTL);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

717

static void hsw_ddi_wrpll_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

72

void (*enable)(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

722

intel_de_rmw(display, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

723

intel_de_posting_read(display, WRPLL_CTL(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

729

if (display->dpll.pch_ssc_use & BIT(id))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

730

intel_init_pch_refclk(display);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

733

static void hsw_ddi_spll_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

738

intel_de_rmw(display, SPLL_CTL, SPLL_PLL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

739

intel_de_posting_read(display, SPLL_CTL);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

745

if (display->dpll.pch_ssc_use & BIT(id))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

746

intel_init_pch_refclk(display);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

749

static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

758

wakeref = intel_display_power_get_if_enabled(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

763

val = intel_de_read(display, WRPLL_CTL(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

766

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

771

static bool hsw_ddi_spll_get_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

779

wakeref = intel_display_power_get_if_enabled(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

784

val = intel_de_read(display, SPLL_CTL);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

787

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

81

void (*disable)(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

89

bool (*get_hw_state)(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

998

static int hsw_ddi_wrpll_get_freq(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

399

intel_get_dpll_by_id(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

401

void assert_dpll(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

422

int intel_dpll_get_freq(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

425

bool intel_dpll_get_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

431

void intel_dpll_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

432

void intel_dpll_update_ref_clks(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

433

void intel_dpll_readout_hw_state(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

434

void intel_dpll_sanitize_state(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

436

void intel_dpll_dump_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

439

bool intel_dpll_compare_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dpt.c

128

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/display/intel_dpt.c

140

wakeref = intel_display_rpm_get(display);

sys/dev/pci/drm/i915/display/intel_dpt.c

141

atomic_inc(&display->restore.pending_fb_pin);

sys/dev/pci/drm/i915/display/intel_dpt.c

171

atomic_dec(&display->restore.pending_fb_pin);

sys/dev/pci/drm/i915/display/intel_dpt.c

172

intel_display_rpm_put(display, wakeref);

sys/dev/pci/drm/i915/display/intel_dpt.c

197

void intel_dpt_resume(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dpt.c

201

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_dpt.c

204

mutex_lock(&display->drm->mode_config.fb_lock);

sys/dev/pci/drm/i915/display/intel_dpt.c

205

drm_for_each_fb(drm_fb, display->drm) {

sys/dev/pci/drm/i915/display/intel_dpt.c

211

mutex_unlock(&display->drm->mode_config.fb_lock);

sys/dev/pci/drm/i915/display/intel_dpt.c

224

void intel_dpt_suspend(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dpt.c

228

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_dpt.c

231

mutex_lock(&display->drm->mode_config.fb_lock);

sys/dev/pci/drm/i915/display/intel_dpt.c

233

drm_for_each_fb(drm_fb, display->drm) {

sys/dev/pci/drm/i915/display/intel_dpt.c

240

mutex_unlock(&display->drm->mode_config.fb_lock);

sys/dev/pci/drm/i915/display/intel_dpt.h

20

void intel_dpt_suspend(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dpt.h

21

void intel_dpt_resume(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dpt_common.c

14

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_dpt_common.c

16

if (DISPLAY_VER(display) == 14) {

sys/dev/pci/drm/i915/display/intel_dpt_common.c

24

intel_de_rmw(display, PLANE_CHICKEN(pipe, plane_id),

sys/dev/pci/drm/i915/display/intel_dpt_common.c

26

display->params.enable_dpt ? 0 :

sys/dev/pci/drm/i915/display/intel_dpt_common.c

29

} else if (DISPLAY_VER(display) == 13) {

sys/dev/pci/drm/i915/display/intel_dpt_common.c

30

intel_de_rmw(display, CHICKEN_MISC_2,

sys/dev/pci/drm/i915/display/intel_dpt_common.c

32

display->params.enable_dpt ? 0 :

sys/dev/pci/drm/i915/display/intel_drrs.c

112

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_drrs.c

117

if (intel_cpu_transcoder_has_m2_n2(display, crtc->drrs.cpu_transcoder))

sys/dev/pci/drm/i915/display/intel_drrs.c

127

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_drrs.c

129

mod_delayed_work(display->wq.unordered, &crtc->drrs.work, msecs_to_jiffies(1000));

sys/dev/pci/drm/i915/display/intel_drrs.c

134

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_drrs.c

140

for_each_intel_crtc_in_pipe_mask(display->drm, crtc,

sys/dev/pci/drm/i915/display/intel_drrs.c

224

static void intel_drrs_frontbuffer_update(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_drrs.c

230

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_drrs.c

272

void intel_drrs_invalidate(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_drrs.c

275

intel_drrs_frontbuffer_update(display, frontbuffer_bits, true);

sys/dev/pci/drm/i915/display/intel_drrs.c

290

void intel_drrs_flush(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_drrs.c

293

intel_drrs_frontbuffer_update(display, frontbuffer_bits, false);

sys/dev/pci/drm/i915/display/intel_drrs.c

314

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_drrs.c

327

str_yes_no(intel_cpu_transcoder_has_drrs(display,

sys/dev/pci/drm/i915/display/intel_drrs.c

355

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_drrs.c

377

drm_dbg_kms(display->drm, "Manually %sactivating DRRS\n", val ? "" : "de");

sys/dev/pci/drm/i915/display/intel_drrs.c

69

bool intel_cpu_transcoder_has_drrs(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_drrs.c

72

if (HAS_DOUBLE_BUFFERED_M_N(display))

sys/dev/pci/drm/i915/display/intel_drrs.c

75

return intel_cpu_transcoder_has_m2_n2(display, cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_drrs.c

82

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_drrs.c

86

if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_drrs.c

91

intel_de_rmw(display, TRANSCONF(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_drrs.h

19

bool intel_cpu_transcoder_has_drrs(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_drrs.h

25

void intel_drrs_invalidate(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_drrs.h

27

void intel_drrs_flush(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dsb.c

1009

spin_unlock(&display->drm->event_lock);

sys/dev/pci/drm/i915/display/intel_dsb.c

1012

errors = tmp & dsb_error_int_status(display);

sys/dev/pci/drm/i915/display/intel_dsb.c

1014

drm_err(display->drm, "[CRTC:%d:%s] DSB %d ATS fault\n",

sys/dev/pci/drm/i915/display/intel_dsb.c

1017

drm_err(display->drm, "[CRTC:%d:%s] DSB %d GTT fault\n",

sys/dev/pci/drm/i915/display/intel_dsb.c

1020

drm_err(display->drm, "[CRTC:%d:%s] DSB %d response timeout\n",

sys/dev/pci/drm/i915/display/intel_dsb.c

1023

drm_err(display->drm, "[CRTC:%d:%s] DSB %d poll error\n",

sys/dev/pci/drm/i915/display/intel_dsb.c

1026

drm_err(display->drm, "[CRTC:%d:%s] DSB %d GOSUB programming error\n",

sys/dev/pci/drm/i915/display/intel_dsb.c

151

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dsb.c

154

unsigned int latency = skl_watermark_max_latency(display, 0);

sys/dev/pci/drm/i915/display/intel_dsb.c

204

struct intel_display *display = to_intel_display(crtc->base.dev);

sys/dev/pci/drm/i915/display/intel_dsb.c

207

return !drm_WARN(display->drm, dsb->free_pos > dsb->size - 2,

sys/dev/pci/drm/i915/display/intel_dsb.c

215

struct intel_display *display = to_intel_display(crtc->base.dev);

sys/dev/pci/drm/i915/display/intel_dsb.c

217

return !drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_dsb.c

224

struct intel_display *display = to_intel_display(crtc->base.dev);

sys/dev/pci/drm/i915/display/intel_dsb.c

227

drm_dbg_kms(display->drm, "[CRTC:%d:%s] DSB %d commands {\n",

sys/dev/pci/drm/i915/display/intel_dsb.c

230

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dsb.c

236

drm_dbg_kms(display->drm, "}\n");

sys/dev/pci/drm/i915/display/intel_dsb.c

239

static bool is_dsb_busy(struct intel_display *display, enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_dsb.c

242

return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY;

sys/dev/pci/drm/i915/display/intel_dsb.c

572

struct intel_display *display = to_intel_display(crtc->base.dev);

sys/dev/pci/drm/i915/display/intel_dsb.c

576

if (drm_WARN_ON(display->drm, dsb->id != sub_dsb->id))

sys/dev/pci/drm/i915/display/intel_dsb.c

637

static u32 dsb_error_int_status(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dsb.c

651

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_dsb.c

654

if (DISPLAY_VER(display) >= 30)

sys/dev/pci/drm/i915/display/intel_dsb.c

660

static u32 dsb_error_int_en(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dsb.c

668

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_dsb.c

675

if (0 && DISPLAY_VER(display) >= 30)

sys/dev/pci/drm/i915/display/intel_dsb.c

749

struct intel_display *display = to_intel_display(state->base.dev);

sys/dev/pci/drm/i915/display/intel_dsb.c

753

if (drm_WARN_ON(display->drm, dsb->id == chained_dsb->id))

sys/dev/pci/drm/i915/display/intel_dsb.c

766

dsb_error_int_status(display) | DSB_PROG_INT_STATUS |

sys/dev/pci/drm/i915/display/intel_dsb.c

767

dsb_error_int_en(display) | DSB_PROG_INT_EN);

sys/dev/pci/drm/i915/display/intel_dsb.c

839

struct intel_display *display = to_intel_display(crtc->base.dev);

sys/dev/pci/drm/i915/display/intel_dsb.c

845

if (is_dsb_busy(display, pipe, dsb->id)) {

sys/dev/pci/drm/i915/display/intel_dsb.c

846

drm_err(display->drm, "[CRTC:%d:%s] DSB %d is busy\n",

sys/dev/pci/drm/i915/display/intel_dsb.c

851

intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

854

intel_de_write_fw(display, DSB_CHICKEN(pipe, dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

857

intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

858

dsb_error_int_status(display) | DSB_PROG_INT_STATUS |

sys/dev/pci/drm/i915/display/intel_dsb.c

859

dsb_error_int_en(display) | DSB_PROG_INT_EN);

sys/dev/pci/drm/i915/display/intel_dsb.c

861

intel_de_write_fw(display, DSB_PMCTRL(pipe, dsb->id), 0);

sys/dev/pci/drm/i915/display/intel_dsb.c

863

intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

866

intel_de_write_fw(display, DSB_TAIL(pipe, dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

873

struct intel_display *display = to_intel_display(crtc->base.dev);

sys/dev/pci/drm/i915/display/intel_dsb.c

878

ret = poll_timeout_us(is_busy = is_dsb_busy(display, pipe, dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

884

intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

887

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dsb.c

890

intel_de_read_fw(display, DSB_CURRENT_HEAD(pipe, dsb->id)) - offset,

sys/dev/pci/drm/i915/display/intel_dsb.c

891

intel_de_read_fw(display, DSB_HEAD(pipe, dsb->id)) - offset,

sys/dev/pci/drm/i915/display/intel_dsb.c

892

intel_de_read_fw(display, DSB_TAIL(pipe, dsb->id)) - offset);

sys/dev/pci/drm/i915/display/intel_dsb.c

903

intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), 0);

sys/dev/pci/drm/i915/display/intel_dsb.c

905

intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

906

dsb_error_int_status(display) | DSB_PROG_INT_STATUS);

sys/dev/pci/drm/i915/display/intel_dsb.c

927

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_dsb.c

932

if (!HAS_DSB(display))

sys/dev/pci/drm/i915/display/intel_dsb.c

935

if (!display->params.enable_dsb)

sys/dev/pci/drm/i915/display/intel_dsb.c

942

wakeref = intel_display_rpm_get(display);

sys/dev/pci/drm/i915/display/intel_dsb.c

950

intel_display_rpm_put(display, wakeref);

sys/dev/pci/drm/i915/display/intel_dsb.c

963

intel_display_rpm_put(display, wakeref);

sys/dev/pci/drm/i915/display/intel_dsb.c

966

drm_info_once(display->drm,

sys/dev/pci/drm/i915/display/intel_dsb.c

986

void intel_dsb_irq_handler(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dsb.c

989

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_dsb.c

992

tmp = intel_de_read_fw(display, DSB_INTERRUPT(pipe, dsb_id));

sys/dev/pci/drm/i915/display/intel_dsb.c

993

intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb_id), tmp);

sys/dev/pci/drm/i915/display/intel_dsb.c

996

spin_lock(&display->drm->event_lock);

sys/dev/pci/drm/i915/display/intel_dsb.h

74

void intel_dsb_irq_handler(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dsi.c

120

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dsi.c

127

orientation = display->vbt.orientation;

sys/dev/pci/drm/i915/display/intel_dsi.c

64

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_dsi.c

68

int max_dotclk = display->cdclk.max_dotclk_freq;

sys/dev/pci/drm/i915/display/intel_dsi.c

71

drm_dbg_kms(display->drm, "\n");

sys/dev/pci/drm/i915/display/intel_dsi.c

80

return intel_mode_valid_max_plane_size(display, mode, 1);

sys/dev/pci/drm/i915/display/intel_dsi_dcs_backlight.c

166

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dsi_dcs_backlight.c

176

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

108

struct intel_display *display = to_intel_display(&intel_dsi->base);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

114

drm_dbg_kms(display->drm, "\n");

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

126

if (drm_WARN_ON(display->drm, !intel_dsi->dsi_hosts[port]))

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

131

drm_dbg_kms(display->drm, "no dsi device for port %c\n",

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

156

drm_dbg_kms(display->drm, "Generic Read not yet implemented or used\n");

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

168

drm_dbg_kms(display->drm, "DCS Read not yet implemented or used\n");

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

175

if (DISPLAY_VER(display) < 11)

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

186

struct intel_display *display = to_intel_display(&intel_dsi->base);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

189

drm_dbg_kms(display->drm, "%d usecs\n", delay);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

202

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

210

gpio_desc = devm_gpiod_get_index(display->drm->dev, con_id, idx,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

213

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

252

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

257

drm_dbg_kms(display->drm, "SC gpio not supported\n");

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

261

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

276

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

296

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

302

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

333

static void icl_native_gpio_set_value(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

338

if (drm_WARN_ON(display->drm, DISPLAY_VER(display) == 11 && gpio >= MIPI_RESET_2))

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

355

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

356

intel_de_rmw(display, SHOTPLUG_CTL_DDI,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

360

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

366

intel_de_rmw(display, PP_CONTROL(display, index), PANEL_POWER_ON,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

373

intel_de_rmw(display, PP_CONTROL(display, index), EDP_BLC_ENABLE,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

380

intel_de_rmw(display, GPIO(display, index),

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

389

intel_de_rmw(display, GPIO(display, index),

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

401

struct intel_display *display = to_intel_display(&intel_dsi->base);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

406

bool native = DISPLAY_VER(display) >= 11;

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

427

drm_dbg_kms(display->drm, "GPIO index %u, number %u, source %u, native %s, set to %s\n",

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

431

icl_native_gpio_set_value(display, gpio_number, value);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

432

else if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

434

else if (display->platform.valleyview)

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

436

else if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

474

struct intel_display *display = to_intel_display(&intel_dsi->base);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

475

struct acpi_device *adev = ACPI_COMPANION(display->drm->dev);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

498

struct intel_display *display = to_intel_display(&intel_dsi->base);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

508

drm_dbg_kms(display->drm, "bus %d target-addr 0x%02x reg 0x%02x data %*ph\n",

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

518

drm_err(display->drm, "Cannot find a valid i2c bus for xfer\n");

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

536

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

550

struct intel_display *display = to_intel_display(&intel_dsi->base);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

552

drm_dbg_kms(display->drm, "Skipping SPI element execution\n");

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

559

struct intel_display *display = to_intel_display(&intel_dsi->base);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

575

drm_err(display->drm, "%s failed, error: %d\n", __func__, ret);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

577

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

627

struct intel_display *display = to_intel_display(&intel_dsi->base);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

632

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

640

drm_WARN_ON(display->drm, *data != seq_id);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

642

drm_dbg_kms(display->drm, "Starting MIPI sequence %d - %s\n",

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

672

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

678

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

684

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

713

struct intel_display *display = to_intel_display(&intel_dsi->base);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

714

struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

772

struct intel_display *display = to_intel_display(&intel_dsi->base);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

780

drm_dbg_kms(display->drm, "\n");

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

826

drm_err(display->drm, "Burst mode target is not set\n");

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

843

drm_err(display->drm, "Burst mode freq is less than computed\n");

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

913

struct intel_display *display = to_intel_display(&intel_dsi->base);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

923

if ((display->platform.valleyview || display->platform.cherryview) &&

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

929

if (display->platform.valleyview && mipi_config->pwm_blc == PPS_BLC_SOC) {

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

938

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

941

pinctrl = devm_pinctrl_get_select(display->drm->dev, "soc_pwm0");

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

943

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

951

intel_dsi->gpio_panel = devm_gpiod_get(display->drm->dev, "panel", flags);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

953

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

961

devm_gpiod_get(display->drm->dev, "backlight", flags);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

963

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_dvo.c

133

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_dvo.c

139

tmp = intel_de_read(display, DVO(port));

sys/dev/pci/drm/i915/display/intel_dvo.c

150

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dvo.c

154

tmp = intel_de_read(display, DVO(port));

sys/dev/pci/drm/i915/display/intel_dvo.c

164

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dvo.c

170

tmp = intel_de_read(display, DVO(port));

sys/dev/pci/drm/i915/display/intel_dvo.c

190

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dvo.c

196

intel_de_rmw(display, DVO(port), DVO_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_dvo.c

197

intel_de_posting_read(display, DVO(port));

sys/dev/pci/drm/i915/display/intel_dvo.c

205

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dvo.c

213

intel_de_rmw(display, DVO(port), 0, DVO_ENABLE);

sys/dev/pci/drm/i915/display/intel_dvo.c

214

intel_de_posting_read(display, DVO(port));

sys/dev/pci/drm/i915/display/intel_dvo.c

223

struct intel_display *display = to_intel_display(_connector->dev);

sys/dev/pci/drm/i915/display/intel_dvo.c

228

int max_dotclk = display->cdclk.max_dotclk_freq;

sys/dev/pci/drm/i915/display/intel_dvo.c

232

status = intel_cpu_transcoder_mode_valid(display, mode);

sys/dev/pci/drm/i915/display/intel_dvo.c

292

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_dvo.c

300

dvo_val = intel_de_read(display, DVO(port)) &

sys/dev/pci/drm/i915/display/intel_dvo.c

313

intel_de_write(display, DVO_SRCDIM(port),

sys/dev/pci/drm/i915/display/intel_dvo.c

316

intel_de_write(display, DVO(port), dvo_val);

sys/dev/pci/drm/i915/display/intel_dvo.c

322

struct intel_display *display = to_intel_display(_connector->dev);

sys/dev/pci/drm/i915/display/intel_dvo.c

326

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",

sys/dev/pci/drm/i915/display/intel_dvo.c

329

if (!intel_display_device_enabled(display))

sys/dev/pci/drm/i915/display/intel_dvo.c

332

if (!intel_display_driver_check_access(display))

sys/dev/pci/drm/i915/display/intel_dvo.c

340

struct intel_display *display = to_intel_display(_connector->dev);

sys/dev/pci/drm/i915/display/intel_dvo.c

344

if (!intel_display_driver_check_access(display))

sys/dev/pci/drm/i915/display/intel_dvo.c

417

static bool intel_dvo_init_dev(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dvo.c

432

if (intel_gmbus_is_valid_pin(display, dvo->gpio))

sys/dev/pci/drm/i915/display/intel_dvo.c

444

i2c = intel_gmbus_get_adapter(display, gpio);

sys/dev/pci/drm/i915/display/intel_dvo.c

460

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_dvo.c

461

dpll[pipe] = intel_de_rmw(display, DPLL(display, pipe), 0,

sys/dev/pci/drm/i915/display/intel_dvo.c

467

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_dvo.c

468

intel_de_write(display, DPLL(display, pipe), dpll[pipe]);

sys/dev/pci/drm/i915/display/intel_dvo.c

476

static bool intel_dvo_probe(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dvo.c

483

if (intel_dvo_init_dev(display, intel_dvo,

sys/dev/pci/drm/i915/display/intel_dvo.c

491

void intel_dvo_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_dvo.c

519

if (!intel_dvo_probe(display, intel_dvo)) {

sys/dev/pci/drm/i915/display/intel_dvo.c

525

assert_port_valid(display, intel_dvo->dev.port);

sys/dev/pci/drm/i915/display/intel_dvo.c

536

drm_encoder_init(display->drm, &encoder->base,

sys/dev/pci/drm/i915/display/intel_dvo.c

541

drm_dbg_kms(display->drm, "[ENCODER:%d:%s] detected %s\n",

sys/dev/pci/drm/i915/display/intel_dvo.c

550

drm_connector_init_with_ddc(display->drm, &connector->base,

sys/dev/pci/drm/i915/display/intel_dvo.c

553

intel_gmbus_get_adapter(display, GMBUS_PIN_DPC));

sys/dev/pci/drm/i915/display/intel_dvo.h

12

void intel_dvo_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_dvo.h

14

static inline void intel_dvo_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_encoder.c

100

drm_modeset_unlock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_encoder.c

102

for_each_intel_encoder(display->drm, encoder)

sys/dev/pci/drm/i915/display/intel_encoder.c

35

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_encoder.c

37

mod_delayed_work(display->wq.unordered,

sys/dev/pci/drm/i915/display/intel_encoder.c

41

void intel_encoder_unblock_all_hpds(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_encoder.c

45

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_encoder.c

48

for_each_intel_encoder(display->drm, encoder)

sys/dev/pci/drm/i915/display/intel_encoder.c

52

void intel_encoder_block_all_hpds(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_encoder.c

56

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_encoder.c

59

for_each_intel_encoder(display->drm, encoder)

sys/dev/pci/drm/i915/display/intel_encoder.c

63

void intel_encoder_suspend_all(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_encoder.c

67

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_encoder.c

74

drm_modeset_lock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_encoder.c

75

for_each_intel_encoder(display->drm, encoder)

sys/dev/pci/drm/i915/display/intel_encoder.c

78

drm_modeset_unlock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_encoder.c

80

for_each_intel_encoder(display->drm, encoder)

sys/dev/pci/drm/i915/display/intel_encoder.c

85

void intel_encoder_shutdown_all(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_encoder.c

89

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_encoder.c

96

drm_modeset_lock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_encoder.c

97

for_each_intel_encoder(display->drm, encoder)

sys/dev/pci/drm/i915/display/intel_encoder.h

18

void intel_encoder_suspend_all(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_encoder.h

19

void intel_encoder_shutdown_all(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_encoder.h

21

void intel_encoder_block_all_hpds(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_encoder.h

22

void intel_encoder_unblock_all_hpds(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_fb.c

1021

struct intel_display *display = to_intel_display(fb->dev);

sys/dev/pci/drm/i915/display/intel_fb.c

1024

drm_WARN_ON(display->drm, new_offset > old_offset);

sys/dev/pci/drm/i915/display/intel_fb.c

1030

tile_size = intel_tile_size(display);

sys/dev/pci/drm/i915/display/intel_fb.c

1080

static u32 intel_compute_aligned_offset(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fb.c

1095

tile_size = intel_tile_size(display);

sys/dev/pci/drm/i915/display/intel_fb.c

1139

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_fb.c

1146

return intel_compute_aligned_offset(display, x, y, fb, color_plane,

sys/dev/pci/drm/i915/display/intel_fb.c

1155

struct intel_display *display = to_intel_display(fb->dev);

sys/dev/pci/drm/i915/display/intel_fb.c

1159

alignment = intel_tile_size(display);

sys/dev/pci/drm/i915/display/intel_fb.c

1164

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fb.c

1176

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fb.c

1196

struct intel_display *display = to_intel_display(fb->dev);

sys/dev/pci/drm/i915/display/intel_fb.c

1230

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fb.c

1244

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_fb.c

1259

if (DISPLAY_VER(display) < 4)

sys/dev/pci/drm/i915/display/intel_fb.c

1271

unsigned int alignment = intel_tile_size(display) - 1;

sys/dev/pci/drm/i915/display/intel_fb.c

1284

struct intel_display *display = to_intel_display(fb->base.dev);

sys/dev/pci/drm/i915/display/intel_fb.c

1286

return (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) &&

sys/dev/pci/drm/i915/display/intel_fb.c

1292

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_fb.c

1295

return DISPLAY_VER(display) < 4 ||

sys/dev/pci/drm/i915/display/intel_fb.c

1341

struct intel_display *display = to_intel_display(fb->base.dev);

sys/dev/pci/drm/i915/display/intel_fb.c

1347

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fb.c

1368

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fb.c

1379

struct intel_display *display = to_intel_display(fb->base.dev);

sys/dev/pci/drm/i915/display/intel_fb.c

1380

unsigned int tile_size = intel_tile_size(display);

sys/dev/pci/drm/i915/display/intel_fb.c

1383

offset = intel_compute_aligned_offset(display, x, y, &fb->base, color_plane,

sys/dev/pci/drm/i915/display/intel_fb.c

1434

struct intel_display *display = to_intel_display(fb->base.dev);

sys/dev/pci/drm/i915/display/intel_fb.c

1437

if ((display->platform.alderlake_p || DISPLAY_VER(display) >= 14) &&

sys/dev/pci/drm/i915/display/intel_fb.c

1467

struct intel_display *display = to_intel_display(fb->base.dev);

sys/dev/pci/drm/i915/display/intel_fb.c

1473

return DIV_ROUND_UP(size, intel_tile_size(display));

sys/dev/pci/drm/i915/display/intel_fb.c

1476

#define assign_chk_ovf(display, var, val) ({ \

sys/dev/pci/drm/i915/display/intel_fb.c

1477

drm_WARN_ON((display)->drm, overflows_type(val, var)); \

sys/dev/pci/drm/i915/display/intel_fb.c

1481

#define assign_bfld_chk_ovf(display, var, val) ({ \

sys/dev/pci/drm/i915/display/intel_fb.c

1483

drm_WARN_ON((display)->drm, (var) != (val)); \

sys/dev/pci/drm/i915/display/intel_fb.c

1492

struct intel_display *display = to_intel_display(fb->base.dev);

sys/dev/pci/drm/i915/display/intel_fb.c

1497

unsigned int tile_size = intel_tile_size(display);

sys/dev/pci/drm/i915/display/intel_fb.c

1501

assign_bfld_chk_ovf(display, remap_info->offset, obj_offset);

sys/dev/pci/drm/i915/display/intel_fb.c

1506

assign_chk_ovf(display, remap_info->size,

sys/dev/pci/drm/i915/display/intel_fb.c

1511

assign_chk_ovf(display, remap_info->src_stride,

sys/dev/pci/drm/i915/display/intel_fb.c

1513

assign_chk_ovf(display, remap_info->width,

sys/dev/pci/drm/i915/display/intel_fb.c

1515

assign_chk_ovf(display, remap_info->height,

sys/dev/pci/drm/i915/display/intel_fb.c

1520

drm_WARN_ON(display->drm, remap_info->linear);

sys/dev/pci/drm/i915/display/intel_fb.c

1521

check_array_bounds(display, view->gtt.rotated.plane, color_plane);

sys/dev/pci/drm/i915/display/intel_fb.c

1523

assign_chk_ovf(display, remap_info->dst_stride,

sys/dev/pci/drm/i915/display/intel_fb.c

1544

drm_WARN_ON(display->drm, view->gtt.type != I915_GTT_VIEW_REMAPPED);

sys/dev/pci/drm/i915/display/intel_fb.c

1546

check_array_bounds(display, view->gtt.remapped.plane, color_plane);

sys/dev/pci/drm/i915/display/intel_fb.c

1580

assign_chk_ovf(display, remap_info->dst_stride, dst_stride);

sys/dev/pci/drm/i915/display/intel_fb.c

1638

static void intel_fb_view_init(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fb.c

1646

(display->platform.alderlake_p || DISPLAY_VER(display) >= 14))

sys/dev/pci/drm/i915/display/intel_fb.c

1652

struct intel_display *display = to_intel_display(fb->base.dev);

sys/dev/pci/drm/i915/display/intel_fb.c

1654

if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/intel_fb.c

1663

struct intel_display *display = to_intel_display(fb->dev);

sys/dev/pci/drm/i915/display/intel_fb.c

1667

for_each_intel_plane(display->drm, plane) {

sys/dev/pci/drm/i915/display/intel_fb.c

1675

drm_WARN_ON(display->drm, plane_min_alignment &&

sys/dev/pci/drm/i915/display/intel_fb.c

1689

struct intel_display *display = to_intel_display(fb->dev);

sys/dev/pci/drm/i915/display/intel_fb.c

1693

for_each_intel_plane(display->drm, plane) {

sys/dev/pci/drm/i915/display/intel_fb.c

1703

int intel_fill_fb_info(struct intel_display *display, struct intel_framebuffer *fb)

sys/dev/pci/drm/i915/display/intel_fb.c

1710

unsigned int tile_size = intel_tile_size(display);

sys/dev/pci/drm/i915/display/intel_fb.c

1712

intel_fb_view_init(display, &fb->normal_view, I915_GTT_VIEW_NORMAL);

sys/dev/pci/drm/i915/display/intel_fb.c

1714

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_fb.c

1719

intel_fb_view_init(display, &fb->rotated_view, I915_GTT_VIEW_ROTATED);

sys/dev/pci/drm/i915/display/intel_fb.c

1721

intel_fb_view_init(display, &fb->remapped_view, I915_GTT_VIEW_REMAPPED);

sys/dev/pci/drm/i915/display/intel_fb.c

1740

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fb.c

1747

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fb.c

1793

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fb.c

1838

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_fb.c

1847

intel_fb_view_init(display, &plane_state->view,

sys/dev/pci/drm/i915/display/intel_fb.c

1856

drm_WARN_ON(display->drm, intel_fb_is_ccs_modifier(fb->modifier));

sys/dev/pci/drm/i915/display/intel_fb.c

1977

u32 intel_fb_max_stride(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fb.c

1986

if (DISPLAY_VER(display) < 4 || intel_fb_is_ccs_modifier(modifier) ||

sys/dev/pci/drm/i915/display/intel_fb.c

1987

intel_fb_modifier_uses_dpt(display, modifier))

sys/dev/pci/drm/i915/display/intel_fb.c

1988

return intel_plane_fb_max_stride(display->drm, pixel_format, modifier);

sys/dev/pci/drm/i915/display/intel_fb.c

1989

else if (DISPLAY_VER(display) >= 7)

sys/dev/pci/drm/i915/display/intel_fb.c

1998

struct intel_display *display = to_intel_display(fb->dev);

sys/dev/pci/drm/i915/display/intel_fb.c

2002

unsigned int max_stride = intel_plane_fb_max_stride(display->drm,

sys/dev/pci/drm/i915/display/intel_fb.c

2012

return intel_tile_size(display);

sys/dev/pci/drm/i915/display/intel_fb.c

2023

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_fb.c

2034

else if ((DISPLAY_VER(display) == 9 || display->platform.geminilake) &&

sys/dev/pci/drm/i915/display/intel_fb.c

2043

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_fb.c

2065

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fb.c

2129

struct intel_display *display = to_intel_display(obj->dev);

sys/dev/pci/drm/i915/display/intel_fb.c

2132

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_fb.c

2216

struct intel_display *display = to_intel_display(obj->dev);

sys/dev/pci/drm/i915/display/intel_fb.c

2241

if (!drm_any_plane_has_format(display->drm,

sys/dev/pci/drm/i915/display/intel_fb.c

2244

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fb.c

2250

max_stride = intel_fb_max_stride(display, mode_cmd->pixel_format,

sys/dev/pci/drm/i915/display/intel_fb.c

2253

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fb.c

2263

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fb.c

2269

drm_helper_mode_fill_fb_struct(display->drm, fb, info, mode_cmd);

sys/dev/pci/drm/i915/display/intel_fb.c

2275

drm_dbg_kms(display->drm, "bad plane %d handle\n", i);

sys/dev/pci/drm/i915/display/intel_fb.c

2281

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fb.c

2291

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fb.c

2301

ret = intel_fill_fb_info(display, intel_fb);

sys/dev/pci/drm/i915/display/intel_fb.c

2310

drm_dbg_kms(display->drm, "failed to create DPT\n");

sys/dev/pci/drm/i915/display/intel_fb.c

2318

ret = drm_framebuffer_init(display->drm, fb, &intel_fb_funcs);

sys/dev/pci/drm/i915/display/intel_fb.c

2320

drm_err(display->drm, "framebuffer init failed %d\n", ret);

sys/dev/pci/drm/i915/display/intel_fb.c

26

#define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a))

sys/dev/pci/drm/i915/display/intel_fb.c

546

static bool plane_has_modifier(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fb.c

550

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_fb.c

552

if (!IS_DISPLAY_VER(display, md->display_ver.from, md->display_ver.until))

sys/dev/pci/drm/i915/display/intel_fb.c

567

(GRAPHICS_VER(i915) < 20 || !display->platform.dgfx))

sys/dev/pci/drm/i915/display/intel_fb.c

571

(GRAPHICS_VER(i915) < 20 || display->platform.dgfx))

sys/dev/pci/drm/i915/display/intel_fb.c

586

u64 *intel_fb_plane_get_modifiers(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fb.c

594

if (plane_has_modifier(display, plane_caps, &intel_modifiers[i]))

sys/dev/pci/drm/i915/display/intel_fb.c

599

if (drm_WARN_ON(display->drm, !list))

sys/dev/pci/drm/i915/display/intel_fb.c

604

if (plane_has_modifier(display, plane_caps, &intel_modifiers[i]))

sys/dev/pci/drm/i915/display/intel_fb.c

760

struct intel_display *display = to_intel_display(fb->dev);

sys/dev/pci/drm/i915/display/intel_fb.c

764

else if (DISPLAY_VER(display) < 11 &&

sys/dev/pci/drm/i915/display/intel_fb.c

771

unsigned int intel_tile_size(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fb.c

773

return DISPLAY_VER(display) == 2 ? 2048 : 4096;

sys/dev/pci/drm/i915/display/intel_fb.c

779

struct intel_display *display = to_intel_display(fb->dev);

sys/dev/pci/drm/i915/display/intel_fb.c

780

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_fb.c

785

return intel_tile_size(display);

sys/dev/pci/drm/i915/display/intel_fb.c

787

if (DISPLAY_VER(display) == 2)

sys/dev/pci/drm/i915/display/intel_fb.c

817

if (DISPLAY_VER(display) == 2 || HAS_128_BYTE_Y_TILING(i915))

sys/dev/pci/drm/i915/display/intel_fb.c

848

struct intel_display *display = to_intel_display(fb->dev);

sys/dev/pci/drm/i915/display/intel_fb.c

850

return intel_tile_size(display) /

sys/dev/pci/drm/i915/display/intel_fb.c

902

bool intel_fb_modifier_uses_dpt(struct intel_display *display, u64 modifier)

sys/dev/pci/drm/i915/display/intel_fb.c

904

return HAS_DPT(display) && modifier != DRM_FORMAT_MOD_LINEAR;

sys/dev/pci/drm/i915/display/intel_fb.c

909

struct intel_display *display = to_intel_display(fb->dev);

sys/dev/pci/drm/i915/display/intel_fb.c

911

return display->params.enable_dpt &&

sys/dev/pci/drm/i915/display/intel_fb.c

912

intel_fb_modifier_uses_dpt(display, fb->modifier);

sys/dev/pci/drm/i915/display/intel_fb.h

120

bool intel_fb_modifier_uses_dpt(struct intel_display *display, u64 modifier);

sys/dev/pci/drm/i915/display/intel_fb.h

45

u64 *intel_fb_plane_get_modifiers(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fb.h

62

unsigned int intel_tile_size(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_fb.h

88

int intel_fill_fb_info(struct intel_display *display, struct intel_framebuffer *fb);

sys/dev/pci/drm/i915/display/intel_fb_bo.c

26

struct intel_display *display = to_intel_display(obj->base.dev);

sys/dev/pci/drm/i915/display/intel_fb_bo.c

41

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fb_bo.c

49

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fb_bo.c

59

if (DISPLAY_VER(display) < 4 &&

sys/dev/pci/drm/i915/display/intel_fb_bo.c

61

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fb_bo.c

71

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fb_pin.c

104

atomic_dec(&display->restore.pending_fb_pin);

sys/dev/pci/drm/i915/display/intel_fb_pin.c

119

struct intel_display *display = to_intel_display(dev);

sys/dev/pci/drm/i915/display/intel_fb_pin.c

142

wakeref = intel_display_rpm_get(display);

sys/dev/pci/drm/i915/display/intel_fb_pin.c

144

atomic_inc(&display->restore.pending_fb_pin);

sys/dev/pci/drm/i915/display/intel_fb_pin.c

155

if (HAS_GMCH(display))

sys/dev/pci/drm/i915/display/intel_fb_pin.c

196

if (ret != 0 && DISPLAY_VER(display) < 4) {

sys/dev/pci/drm/i915/display/intel_fb_pin.c

220

atomic_dec(&display->restore.pending_fb_pin);

sys/dev/pci/drm/i915/display/intel_fb_pin.c

221

intel_display_rpm_put(display, wakeref);

sys/dev/pci/drm/i915/display/intel_fb_pin.c

264

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_fb_pin.c

308

drm_WARN_ON(display->drm, intel_dpt_offset(plane_state->dpt_vma));

sys/dev/pci/drm/i915/display/intel_fb_pin.c

31

struct intel_display *display = to_intel_display(dev);

sys/dev/pci/drm/i915/display/intel_fb_pin.c

49

atomic_inc(&display->restore.pending_fb_pin);

sys/dev/pci/drm/i915/display/intel_fbc.c

1017

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

1019

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_fbc.c

1021

else if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_fbc.c

1023

else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_fbc.c

1025

else if (DISPLAY_VER(display) == 4)

sys/dev/pci/drm/i915/display/intel_fbc.c

1033

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

1043

if (DISPLAY_VER(display) == 2)

sys/dev/pci/drm/i915/display/intel_fbc.c

1053

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

1062

if (display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_fbc.c

1088

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

1090

if (DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/intel_fbc.c

1092

else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_fbc.c

1122

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

1124

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_fbc.c

1126

else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_fbc.c

1132

static void intel_fbc_max_surface_size(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fbc.c

1135

if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/intel_fbc.c

1138

} else if (DISPLAY_VER(display) >= 10) {

sys/dev/pci/drm/i915/display/intel_fbc.c

1141

} else if (DISPLAY_VER(display) >= 7) {

sys/dev/pci/drm/i915/display/intel_fbc.c

1144

} else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) {

sys/dev/pci/drm/i915/display/intel_fbc.c

1161

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

1164

intel_fbc_max_surface_size(display, &max_w, &max_h);

sys/dev/pci/drm/i915/display/intel_fbc.c

1174

static void intel_fbc_max_plane_size(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fbc.c

1177

if (DISPLAY_VER(display) >= 10) {

sys/dev/pci/drm/i915/display/intel_fbc.c

1180

} else if (DISPLAY_VER(display) >= 8 || display->platform.haswell) {

sys/dev/pci/drm/i915/display/intel_fbc.c

1183

} else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) {

sys/dev/pci/drm/i915/display/intel_fbc.c

1194

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

1197

intel_fbc_max_plane_size(display, &max_w, &max_h);

sys/dev/pci/drm/i915/display/intel_fbc.c

1219

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

1221

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_fbc.c

1239

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

1241

drm_WARN_ON(display->drm, fbc_dirty_rect->y2 == 0);

sys/dev/pci/drm/i915/display/intel_fbc.c

1243

intel_de_write_dsb(display, dsb, XE3_FBC_DIRTY_RECT(fbc->id),

sys/dev/pci/drm/i915/display/intel_fbc.c

1265

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_fbc.c

1268

if (!HAS_FBC_DIRTY_RECT(display))

sys/dev/pci/drm/i915/display/intel_fbc.c

1299

struct intel_display *display = to_intel_display(state->base.dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

1317

drm_WARN_ON(display->drm, plane_state->flags & PLANE_HAS_FENCE &&

sys/dev/pci/drm/i915/display/intel_fbc.c

1318

!intel_fbc_has_fences(display));

sys/dev/pci/drm/i915/display/intel_fbc.c

1332

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

1346

return DISPLAY_VER(display) >= 9 ||

sys/dev/pci/drm/i915/display/intel_fbc.c

1398

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_fbc.c

1405

if (!HAS_FBC_DIRTY_RECT(display))

sys/dev/pci/drm/i915/display/intel_fbc.c

1427

struct intel_display *display = to_intel_display(state->base.dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

1428

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_fbc.c

1449

if (!display->params.enable_fbc) {

sys/dev/pci/drm/i915/display/intel_fbc.c

1459

if (intel_display_wa(display, 16023588340)) {

sys/dev/pci/drm/i915/display/intel_fbc.c

1465

if (i915_vtd_active(i915) && (display->platform.skylake || display->platform.broxton)) {

sys/dev/pci/drm/i915/display/intel_fbc.c

1494

if (DISPLAY_VER(display) >= 12 && crtc_state->has_sel_update) {

sys/dev/pci/drm/i915/display/intel_fbc.c

1500

if ((IS_DISPLAY_VER(display, 12, 13) ||

sys/dev/pci/drm/i915/display/intel_fbc.c

1501

IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_C0)) &&

sys/dev/pci/drm/i915/display/intel_fbc.c

1527

if (DISPLAY_VER(display) < 20 &&

sys/dev/pci/drm/i915/display/intel_fbc.c

1549

if (IS_DISPLAY_VER(display, 9, 12) &&

sys/dev/pci/drm/i915/display/intel_fbc.c

1556

if (IS_DISPLAY_VER(display, 9, 12) &&

sys/dev/pci/drm/i915/display/intel_fbc.c

1564

if (display->platform.haswell || display->platform.broadwell) {

sys/dev/pci/drm/i915/display/intel_fbc.c

158

static unsigned int skl_fbc_min_cfb_stride(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fbc.c

1632

struct intel_display *display = to_intel_display(state->base.dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

1658

if (fbc->activated && DISPLAY_VER(display) >= 10)

sys/dev/pci/drm/i915/display/intel_fbc.c

1692

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

1696

drm_WARN_ON(display->drm, fbc->active);

sys/dev/pci/drm/i915/display/intel_fbc.c

1698

drm_dbg_kms(display->drm, "Disabling FBC on [PLANE:%d:%s]\n",

sys/dev/pci/drm/i915/display/intel_fbc.c

1706

if (display->platform.dg2 || DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_fbc.c

172

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_fbc.c

1774

void intel_fbc_invalidate(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fbc.c

1781

for_each_intel_fbc(display, fbc, fbc_id)

sys/dev/pci/drm/i915/display/intel_fbc.c

1813

void intel_fbc_flush(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fbc.c

1820

for_each_intel_fbc(display, fbc, fbc_id)

sys/dev/pci/drm/i915/display/intel_fbc.c

1845

struct intel_display *display = to_intel_display(state->base.dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

186

static unsigned int _intel_fbc_cfb_stride(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fbc.c

1864

drm_WARN_ON(display->drm, fbc->active);

sys/dev/pci/drm/i915/display/intel_fbc.c

1886

drm_dbg_kms(display->drm, "Enabling FBC on [PLANE:%d:%s]\n",

sys/dev/pci/drm/i915/display/intel_fbc.c

1892

if (HAS_FBC_DIRTY_RECT(display))

sys/dev/pci/drm/i915/display/intel_fbc.c

1907

struct intel_display *display = to_intel_display(crtc->base.dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

1910

for_each_intel_plane(display->drm, plane) {

sys/dev/pci/drm/i915/display/intel_fbc.c

195

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_fbc.c

1955

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

196

return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(display, cpp, width));

sys/dev/pci/drm/i915/display/intel_fbc.c

1963

drm_dbg_kms(display->drm, "Disabling FBC due to FIFO underrun.\n");

sys/dev/pci/drm/i915/display/intel_fbc.c

1968

intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, fbc->state.plane->pipe));

sys/dev/pci/drm/i915/display/intel_fbc.c

1976

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

1983

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fbc.c

1999

void intel_fbc_reset_underrun(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fbc.c

2004

for_each_intel_fbc(display, fbc, fbc_id)

sys/dev/pci/drm/i915/display/intel_fbc.c

2010

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

2023

queue_work(display->wq.unordered, &fbc->underrun_work);

sys/dev/pci/drm/i915/display/intel_fbc.c

203

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

2040

void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fbc.c

2045

for_each_intel_fbc(display, fbc, fbc_id)

sys/dev/pci/drm/i915/display/intel_fbc.c

2058

static int intel_sanitize_fbc_option(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fbc.c

2060

if (display->params.enable_fbc >= 0)

sys/dev/pci/drm/i915/display/intel_fbc.c

2061

return !!display->params.enable_fbc;

sys/dev/pci/drm/i915/display/intel_fbc.c

2063

if (!HAS_FBC(display))

sys/dev/pci/drm/i915/display/intel_fbc.c

2066

if (display->platform.broadwell || DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_fbc.c

2077

static struct intel_fbc *intel_fbc_create(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fbc.c

208

return _intel_fbc_cfb_stride(display, cpp, width, stride);

sys/dev/pci/drm/i915/display/intel_fbc.c

2087

fbc->display = display;

sys/dev/pci/drm/i915/display/intel_fbc.c

2091

if (DISPLAY_VER(display) >= 7)

sys/dev/pci/drm/i915/display/intel_fbc.c

2093

else if (DISPLAY_VER(display) == 6)

sys/dev/pci/drm/i915/display/intel_fbc.c

2095

else if (DISPLAY_VER(display) == 5)

sys/dev/pci/drm/i915/display/intel_fbc.c

2097

else if (display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_fbc.c

2099

else if (DISPLAY_VER(display) == 4)

sys/dev/pci/drm/i915/display/intel_fbc.c

2113

void intel_fbc_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fbc.c

2117

display->params.enable_fbc = intel_sanitize_fbc_option(display);

sys/dev/pci/drm/i915/display/intel_fbc.c

2118

drm_dbg_kms(display->drm, "Sanitized enable_fbc value: %d\n",

sys/dev/pci/drm/i915/display/intel_fbc.c

2119

display->params.enable_fbc);

sys/dev/pci/drm/i915/display/intel_fbc.c

2121

for_each_fbc_id(display, fbc_id)

sys/dev/pci/drm/i915/display/intel_fbc.c

2122

display->fbc[fbc_id] = intel_fbc_create(display, fbc_id);

sys/dev/pci/drm/i915/display/intel_fbc.c

2133

void intel_fbc_sanitize(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fbc.c

2138

for_each_intel_fbc(display, fbc, fbc_id) {

sys/dev/pci/drm/i915/display/intel_fbc.c

2149

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

2153

drm_modeset_lock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_fbc.c

2155

wakeref = intel_display_rpm_get(display);

sys/dev/pci/drm/i915/display/intel_fbc.c

216

static unsigned int intel_fbc_max_cfb_height(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fbc.c

2166

for_each_intel_plane(display->drm, plane) {

sys/dev/pci/drm/i915/display/intel_fbc.c

218

if (DISPLAY_VER(display) >= 8)

sys/dev/pci/drm/i915/display/intel_fbc.c

2180

intel_display_rpm_put(display, wakeref);

sys/dev/pci/drm/i915/display/intel_fbc.c

2182

drm_modeset_unlock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_fbc.c

220

else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_fbc.c

2241

void intel_fbc_debugfs_register(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fbc.c

2245

fbc = display->fbc[INTEL_FBC_A];

sys/dev/pci/drm/i915/display/intel_fbc.c

2247

intel_fbc_debugfs_add(fbc, display->drm->debugfs_root);

sys/dev/pci/drm/i915/display/intel_fbc.c

226

static unsigned int _intel_fbc_cfb_size(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fbc.c

229

return min(height, intel_fbc_max_cfb_height(display)) * stride;

sys/dev/pci/drm/i915/display/intel_fbc.c

234

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

237

return _intel_fbc_cfb_size(display, height, intel_fbc_cfb_stride(plane_state));

sys/dev/pci/drm/i915/display/intel_fbc.c

242

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

257

(DISPLAY_VER(display) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR) ||

sys/dev/pci/drm/i915/display/intel_fbc.c

258

display->platform.battlemage)

sys/dev/pci/drm/i915/display/intel_fbc.c

264

static bool intel_fbc_has_fences(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fbc.c

266

struct drm_i915_private __maybe_unused *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_fbc.c

273

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

281

if (DISPLAY_VER(display) == 2)

sys/dev/pci/drm/i915/display/intel_fbc.c

290

if (display->platform.i945gm)

sys/dev/pci/drm/i915/display/intel_fbc.c

315

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

319

fbc_ctl = intel_de_read(display, FBC_CONTROL);

sys/dev/pci/drm/i915/display/intel_fbc.c

324

intel_de_write(display, FBC_CONTROL, fbc_ctl);

sys/dev/pci/drm/i915/display/intel_fbc.c

327

if (intel_de_wait_for_clear(display, FBC_STATUS,

sys/dev/pci/drm/i915/display/intel_fbc.c

329

drm_dbg_kms(display->drm, "FBC idle timed out\n");

sys/dev/pci/drm/i915/display/intel_fbc.c

336

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

342

intel_de_write(display, FBC_TAG(i), 0);

sys/dev/pci/drm/i915/display/intel_fbc.c

344

if (DISPLAY_VER(display) == 4) {

sys/dev/pci/drm/i915/display/intel_fbc.c

345

intel_de_write(display, FBC_CONTROL2,

sys/dev/pci/drm/i915/display/intel_fbc.c

347

intel_de_write(display, FBC_FENCE_OFF,

sys/dev/pci/drm/i915/display/intel_fbc.c

351

intel_de_write(display, FBC_CONTROL,

sys/dev/pci/drm/i915/display/intel_fbc.c

357

return intel_de_read(fbc->display, FBC_CONTROL) & FBC_CTL_EN;

sys/dev/pci/drm/i915/display/intel_fbc.c

362

return intel_de_read(fbc->display, FBC_STATUS) &

sys/dev/pci/drm/i915/display/intel_fbc.c

368

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

372

intel_de_write_fw(display, DSPADDR(display, i9xx_plane),

sys/dev/pci/drm/i915/display/intel_fbc.c

373

intel_de_read_fw(display, DSPADDR(display, i9xx_plane)));

sys/dev/pci/drm/i915/display/intel_fbc.c

378

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

379

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_fbc.c

381

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_fbc.c

385

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_fbc.c

389

intel_de_write(display, FBC_CFB_BASE,

sys/dev/pci/drm/i915/display/intel_fbc.c

391

intel_de_write(display, FBC_LL_BASE,

sys/dev/pci/drm/i915/display/intel_fbc.c

406

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

410

intel_de_write_fw(display, DSPSURF(display, i9xx_plane),

sys/dev/pci/drm/i915/display/intel_fbc.c

411

intel_de_read_fw(display, DSPSURF(display, i9xx_plane)));

sys/dev/pci/drm/i915/display/intel_fbc.c

440

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

447

if (display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_fbc.c

453

if (DISPLAY_VER(display) < 6)

sys/dev/pci/drm/i915/display/intel_fbc.c

462

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

465

intel_de_write(display, DPFC_FENCE_YOFF,

sys/dev/pci/drm/i915/display/intel_fbc.c

468

intel_de_write(display, DPFC_CONTROL,

sys/dev/pci/drm/i915/display/intel_fbc.c

474

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

478

dpfc_ctl = intel_de_read(display, DPFC_CONTROL);

sys/dev/pci/drm/i915/display/intel_fbc.c

481

intel_de_write(display, DPFC_CONTROL, dpfc_ctl);

sys/dev/pci/drm/i915/display/intel_fbc.c

487

return intel_de_read(fbc->display, DPFC_CONTROL) & DPFC_CTL_EN;

sys/dev/pci/drm/i915/display/intel_fbc.c

492

return intel_de_read(fbc->display, DPFC_STATUS) & DPFC_COMP_SEG_MASK;

sys/dev/pci/drm/i915/display/intel_fbc.c

497

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

499

intel_de_write(display, DPFC_CB_BASE,

sys/dev/pci/drm/i915/display/intel_fbc.c

514

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

517

intel_de_write(display, ILK_DPFC_FENCE_YOFF(fbc->id),

sys/dev/pci/drm/i915/display/intel_fbc.c

520

intel_de_write(display, ILK_DPFC_CONTROL(fbc->id),

sys/dev/pci/drm/i915/display/intel_fbc.c

527

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

529

if (display->platform.dg2)

sys/dev/pci/drm/i915/display/intel_fbc.c

530

intel_de_rmw(display, GEN9_CLKGATE_DIS_4, DG2_DPFC_GATING_DIS,

sys/dev/pci/drm/i915/display/intel_fbc.c

532

else if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_fbc.c

533

intel_de_rmw(display, MTL_PIPE_CLKGATE_DIS2(fbc->id),

sys/dev/pci/drm/i915/display/intel_fbc.c

540

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

543

if (HAS_FBC_DIRTY_RECT(display))

sys/dev/pci/drm/i915/display/intel_fbc.c

544

intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), 0);

sys/dev/pci/drm/i915/display/intel_fbc.c

547

dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id));

sys/dev/pci/drm/i915/display/intel_fbc.c

550

intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);

sys/dev/pci/drm/i915/display/intel_fbc.c

556

return intel_de_read(fbc->display, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN;

sys/dev/pci/drm/i915/display/intel_fbc.c

561

return intel_de_read(fbc->display, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;

sys/dev/pci/drm/i915/display/intel_fbc.c

566

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

568

intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id),

sys/dev/pci/drm/i915/display/intel_fbc.c

583

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

590

intel_de_write(display, SNB_DPFC_CTL_SA, ctl);

sys/dev/pci/drm/i915/display/intel_fbc.c

591

intel_de_write(display, SNB_DPFC_CPU_FENCE_OFFSET, fbc_state->fence_y_offset);

sys/dev/pci/drm/i915/display/intel_fbc.c

603

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

605

intel_de_write(display, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);

sys/dev/pci/drm/i915/display/intel_fbc.c

606

intel_de_posting_read(display, MSG_FBC_REND_STATE(fbc->id));

sys/dev/pci/drm/i915/display/intel_fbc.c

620

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

628

intel_de_write(display, GLK_FBC_STRIDE(fbc->id), val);

sys/dev/pci/drm/i915/display/intel_fbc.c

633

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

642

intel_de_rmw(display, CHICKEN_MISC_4,

sys/dev/pci/drm/i915/display/intel_fbc.c

649

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

655

if (display->platform.ivybridge)

sys/dev/pci/drm/i915/display/intel_fbc.c

658

if (DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/intel_fbc.c

672

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

675

if (DISPLAY_VER(display) >= 10)

sys/dev/pci/drm/i915/display/intel_fbc.c

677

else if (DISPLAY_VER(display) == 9)

sys/dev/pci/drm/i915/display/intel_fbc.c

680

if (intel_fbc_has_fences(display))

sys/dev/pci/drm/i915/display/intel_fbc.c

685

if (DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/intel_fbc.c

686

intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);

sys/dev/pci/drm/i915/display/intel_fbc.c

688

if (HAS_FBC_DIRTY_RECT(display))

sys/dev/pci/drm/i915/display/intel_fbc.c

689

intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id),

sys/dev/pci/drm/i915/display/intel_fbc.c

692

intel_de_write(display, ILK_DPFC_CONTROL(fbc->id),

sys/dev/pci/drm/i915/display/intel_fbc.c

698

return intel_de_read(fbc->display, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB;

sys/dev/pci/drm/i915/display/intel_fbc.c

704

intel_de_rmw(fbc->display, ILK_DPFC_CONTROL(fbc->id),

sys/dev/pci/drm/i915/display/intel_fbc.c

749

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

752

drm_WARN_ON(display->drm, fbc->flip_pending);

sys/dev/pci/drm/i915/display/intel_fbc.c

761

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

766

if (fbc->active && !intel_fbc_has_fences(display))

sys/dev/pci/drm/i915/display/intel_fbc.c

772

drm_WARN_ON(display->drm, fbc->active && HAS_FBC_DIRTY_RECT(display));

sys/dev/pci/drm/i915/display/intel_fbc.c

790

static u64 intel_fbc_cfb_base_max(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fbc.c

792

if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_fbc.c

798

static u64 intel_fbc_stolen_end(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fbc.c

800

struct drm_i915_private __maybe_unused *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_fbc.c

807

if (display->platform.broadwell ||

sys/dev/pci/drm/i915/display/intel_fbc.c

808

(DISPLAY_VER(display) == 9 && !display->platform.broxton))

sys/dev/pci/drm/i915/display/intel_fbc.c

813

return min(end, intel_fbc_cfb_base_max(display));

sys/dev/pci/drm/i915/display/intel_fbc.c

821

static int intel_fbc_max_limit(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fbc.c

824

if (display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_fbc.c

837

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

838

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_fbc.c

839

u64 end = intel_fbc_stolen_end(display);

sys/dev/pci/drm/i915/display/intel_fbc.c

850

for (; limit <= intel_fbc_max_limit(display); limit <<= 1) {

sys/dev/pci/drm/i915/display/intel_fbc.c

863

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

864

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_fbc.c

867

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_fbc.c

869

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_fbc.c

872

if (DISPLAY_VER(display) < 5 && !display->platform.g4x) {

sys/dev/pci/drm/i915/display/intel_fbc.c

883

drm_info_once(display->drm,

sys/dev/pci/drm/i915/display/intel_fbc.c

888

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fbc.c

898

drm_info_once(display->drm,

sys/dev/pci/drm/i915/display/intel_fbc.c

910

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

912

if (display->platform.skylake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/intel_fbc.c

917

intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id),

sys/dev/pci/drm/i915/display/intel_fbc.c

921

if (display->platform.skylake || display->platform.kabylake ||

sys/dev/pci/drm/i915/display/intel_fbc.c

922

display->platform.coffeelake || display->platform.cometlake) {

sys/dev/pci/drm/i915/display/intel_fbc.c

927

intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id),

sys/dev/pci/drm/i915/display/intel_fbc.c

932

if (IS_DISPLAY_VER(display, 11, 12))

sys/dev/pci/drm/i915/display/intel_fbc.c

933

intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id),

sys/dev/pci/drm/i915/display/intel_fbc.c

937

if (DISPLAY_VER(display) >= 11 && !display->platform.dg2)

sys/dev/pci/drm/i915/display/intel_fbc.c

938

intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id),

sys/dev/pci/drm/i915/display/intel_fbc.c

942

if (display->platform.dg2 || DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_fbc.c

948

struct intel_display *display = fbc->display;

sys/dev/pci/drm/i915/display/intel_fbc.c

949

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_fbc.c

960

void intel_fbc_cleanup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fbc.c

965

for_each_intel_fbc(display, fbc, fbc_id) {

sys/dev/pci/drm/i915/display/intel_fbc.c

98

struct intel_display *display;

sys/dev/pci/drm/i915/display/intel_fbc.h

35

void intel_fbc_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_fbc.h

36

void intel_fbc_cleanup(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_fbc.h

37

void intel_fbc_sanitize(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_fbc.h

41

void intel_fbc_invalidate(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fbc.h

44

void intel_fbc_flush(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fbc.h

47

void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_fbc.h

48

void intel_fbc_reset_underrun(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_fbc.h

50

void intel_fbc_debugfs_register(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_fbdev.c

234

__intel_fbdev_fb_alloc(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fbdev.c

242

fb = intel_fbdev_fb_alloc(display->drm, &mode_cmd);

sys/dev/pci/drm/i915/display/intel_fbdev.c

250

struct intel_display *display = to_intel_display(helper->dev);

sys/dev/pci/drm/i915/display/intel_fbdev.c

266

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fbdev.c

275

wakeref = intel_display_rpm_get(display);

sys/dev/pci/drm/i915/display/intel_fbdev.c

277

if (!fb || drm_WARN_ON(display->drm, !intel_fb_bo(&fb->base))) {

sys/dev/pci/drm/i915/display/intel_fbdev.c

278

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fbdev.c

281

fb = __intel_fbdev_fb_alloc(display, sizes);

sys/dev/pci/drm/i915/display/intel_fbdev.c

287

drm_dbg_kms(display->drm, "re-using BIOS fb\n");

sys/dev/pci/drm/i915/display/intel_fbdev.c

311

drm_err(display->drm, "Failed to allocate fb_info (%pe)\n", info);

sys/dev/pci/drm/i915/display/intel_fbdev.c

323

ret = intel_fbdev_fb_fill_info(display, info, obj, vma);

sys/dev/pci/drm/i915/display/intel_fbdev.c

327

drm_fb_helper_fill_info(info, display->drm->fb_helper, sizes);

sys/dev/pci/drm/i915/display/intel_fbdev.c

338

drm_dbg_kms(display->drm, "allocated %dx%d fb: 0x%08x\n",

sys/dev/pci/drm/i915/display/intel_fbdev.c

345

intel_display_rpm_put(display, wakeref);

sys/dev/pci/drm/i915/display/intel_fbdev.c

348

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_fbdev.c

382

intel_display_rpm_put(display, wakeref);

sys/dev/pci/drm/i915/display/intel_fbdev.c

396

static bool intel_fbdev_init_bios(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fbdev.c

404

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_fbdev.c

414

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fbdev.c

421

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fbdev.c

428

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fbdev.c

437

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fbdev.c

443

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_fbdev.c

451

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fbdev.c

457

drm_dbg_kms(display->drm, "checking [PLANE:%d:%s] for BIOS fb\n",

sys/dev/pci/drm/i915/display/intel_fbdev.c

468

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fbdev.c

479

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fbdev.c

488

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fbdev.c

496

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fbdev.c

503

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fbdev.c

513

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_fbdev.c

524

drm_WARN(display->drm, !plane_state->uapi.fb,

sys/dev/pci/drm/i915/display/intel_fbdev.c

530

drm_dbg_kms(display->drm, "using BIOS fb for initial console\n");

sys/dev/pci/drm/i915/display/intel_fbdev.c

555

void intel_fbdev_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fbdev.c

560

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_fbdev.c

563

ifbdev = drmm_kzalloc(display->drm, sizeof(*ifbdev), GFP_KERNEL);

sys/dev/pci/drm/i915/display/intel_fbdev.c

567

display->fbdev.fbdev = ifbdev;

sys/dev/pci/drm/i915/display/intel_fbdev.c

568

if (intel_fbdev_init_bios(display, ifbdev))

sys/dev/pci/drm/i915/display/intel_fbdev.c

573

drm_client_setup_with_color_mode(display->drm, preferred_bpp);

sys/dev/pci/drm/i915/display/intel_fbdev.c

70

struct intel_display *display = to_intel_display(fb_helper->client.dev);

sys/dev/pci/drm/i915/display/intel_fbdev.c

72

return display->fbdev.fbdev;

sys/dev/pci/drm/i915/display/intel_fbdev.h

23

void intel_fbdev_setup(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_fbdev.h

30

static inline void intel_fbdev_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fbdev_fb.c

104

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_fbdev_fb.c

19

struct intel_display *display = to_intel_display(drm);

sys/dev/pci/drm/i915/display/intel_fbdev_fb.c

41

if (!display->platform.meteorlake && size * 2 < dev_priv->dsm.usable_size)

sys/dev/pci/drm/i915/display/intel_fbdev_fb.c

69

int intel_fbdev_fb_fill_info(struct intel_display *display, struct fb_info *info,

sys/dev/pci/drm/i915/display/intel_fbdev_fb.c

72

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_fbdev_fb.h

18

int intel_fbdev_fb_fill_info(struct intel_display *display, struct fb_info *info,

sys/dev/pci/drm/i915/display/intel_fdi.c

100

static void assert_fdi_rx_pll(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fdi.c

1005

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

1008

temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;

sys/dev/pci/drm/i915/display/intel_fdi.c

1009

intel_de_write(display, reg, temp | FDI_RX_PLL_ENABLE);

sys/dev/pci/drm/i915/display/intel_fdi.c

1011

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

1015

intel_de_rmw(display, reg, 0, FDI_PCDCLK);

sys/dev/pci/drm/i915/display/intel_fdi.c

1016

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

1021

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

1023

intel_de_write(display, reg, temp | FDI_TX_PLL_ENABLE);

sys/dev/pci/drm/i915/display/intel_fdi.c

1025

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

1032

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_fdi.c

1036

intel_de_rmw(display, FDI_RX_CTL(pipe), FDI_PCDCLK, 0);

sys/dev/pci/drm/i915/display/intel_fdi.c

1039

intel_de_rmw(display, FDI_TX_CTL(pipe), FDI_TX_PLL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_fdi.c

1040

intel_de_posting_read(display, FDI_TX_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_fdi.c

1044

intel_de_rmw(display, FDI_RX_CTL(pipe), FDI_RX_PLL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_fdi.c

1045

intel_de_posting_read(display, FDI_RX_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_fdi.c

105

cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE;

sys/dev/pci/drm/i915/display/intel_fdi.c

1051

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_fdi.c

1057

intel_de_rmw(display, FDI_TX_CTL(pipe), FDI_TX_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_fdi.c

1058

intel_de_posting_read(display, FDI_TX_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_fdi.c

106

INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

sys/dev/pci/drm/i915/display/intel_fdi.c

1061

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

1063

temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;

sys/dev/pci/drm/i915/display/intel_fdi.c

1064

intel_de_write(display, reg, temp & ~FDI_RX_ENABLE);

sys/dev/pci/drm/i915/display/intel_fdi.c

1066

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

1070

if (HAS_PCH_IBX(display))

sys/dev/pci/drm/i915/display/intel_fdi.c

1071

intel_de_write(display, FDI_RX_CHICKEN(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

1075

intel_de_rmw(display, FDI_TX_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

1079

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

1080

if (HAS_PCH_CPT(display)) {

sys/dev/pci/drm/i915/display/intel_fdi.c

1089

temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;

sys/dev/pci/drm/i915/display/intel_fdi.c

1090

intel_de_write(display, reg, temp);

sys/dev/pci/drm/i915/display/intel_fdi.c

1092

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

1109

intel_fdi_init_hook(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fdi.c

111

void assert_fdi_rx_pll_enabled(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_fdi.c

1111

if (display->platform.ironlake) {

sys/dev/pci/drm/i915/display/intel_fdi.c

1112

display->funcs.fdi = &ilk_funcs;

sys/dev/pci/drm/i915/display/intel_fdi.c

1113

} else if (display->platform.sandybridge) {

sys/dev/pci/drm/i915/display/intel_fdi.c

1114

display->funcs.fdi = &gen6_funcs;

sys/dev/pci/drm/i915/display/intel_fdi.c

1115

} else if (display->platform.ivybridge) {

sys/dev/pci/drm/i915/display/intel_fdi.c

1117

display->funcs.fdi = &ivb_funcs;

sys/dev/pci/drm/i915/display/intel_fdi.c

113

assert_fdi_rx_pll(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_fdi.c

116

void assert_fdi_rx_pll_disabled(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_fdi.c

118

assert_fdi_rx_pll(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_fdi.c

124

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_fdi.c

126

display->funcs.fdi->fdi_link_train(crtc, crtc_state);

sys/dev/pci/drm/i915/display/intel_fdi.c

142

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_fdi.c

147

if (!display->platform.ivybridge || INTEL_NUM_PIPES(display) != 3)

sys/dev/pci/drm/i915/display/intel_fdi.c

150

crtc = intel_crtc_for_pipe(display, PIPE_C);

sys/dev/pci/drm/i915/display/intel_fdi.c

162

crtc = intel_crtc_for_pipe(display, PIPE_B);

sys/dev/pci/drm/i915/display/intel_fdi.c

185

static int ilk_check_fdi_lanes(struct intel_display *display, enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_fdi.c

195

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fdi.c

199

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fdi.c

205

if (display->platform.haswell || display->platform.broadwell) {

sys/dev/pci/drm/i915/display/intel_fdi.c

207

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fdi.c

216

if (INTEL_NUM_PIPES(display) == 2)

sys/dev/pci/drm/i915/display/intel_fdi.c

227

other_crtc = intel_crtc_for_pipe(display, PIPE_C);

sys/dev/pci/drm/i915/display/intel_fdi.c

234

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fdi.c

242

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fdi.c

248

other_crtc = intel_crtc_for_pipe(display, PIPE_B);

sys/dev/pci/drm/i915/display/intel_fdi.c

255

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fdi.c

269

void intel_fdi_pll_freq_update(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fdi.c

271

if (display->platform.ironlake) {

sys/dev/pci/drm/i915/display/intel_fdi.c

274

fdi_pll_clk = intel_de_read(display, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;

sys/dev/pci/drm/i915/display/intel_fdi.c

276

display->fdi.pll_freq = (fdi_pll_clk + 2) * 10000;

sys/dev/pci/drm/i915/display/intel_fdi.c

277

} else if (display->platform.sandybridge || display->platform.ivybridge) {

sys/dev/pci/drm/i915/display/intel_fdi.c

278

display->fdi.pll_freq = 270000;

sys/dev/pci/drm/i915/display/intel_fdi.c

283

drm_dbg(display->drm, "FDI PLL freq=%d\n", display->fdi.pll_freq);

sys/dev/pci/drm/i915/display/intel_fdi.c

286

int intel_fdi_link_freq(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fdi.c

289

if (HAS_DDI(display))

sys/dev/pci/drm/i915/display/intel_fdi.c

29

static void assert_fdi_tx(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fdi.c

292

return display->fdi.pll_freq;

sys/dev/pci/drm/i915/display/intel_fdi.c

298

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_fdi.c

309

link_bw = intel_fdi_link_freq(display, pipe_config);

sys/dev/pci/drm/i915/display/intel_fdi.c

332

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_fdi.c

336

ret = ilk_check_fdi_lanes(display, crtc->pipe, pipe_config,

sys/dev/pci/drm/i915/display/intel_fdi.c

34

if (HAS_DDI(display)) {

sys/dev/pci/drm/i915/display/intel_fdi.c

389

static void cpt_set_fdi_bc_bifurcation(struct intel_display *display, bool enable)

sys/dev/pci/drm/i915/display/intel_fdi.c

393

temp = intel_de_read(display, SOUTH_CHICKEN1);

sys/dev/pci/drm/i915/display/intel_fdi.c

397

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_fdi.c

398

intel_de_read(display, FDI_RX_CTL(PIPE_B)) &

sys/dev/pci/drm/i915/display/intel_fdi.c

400

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_fdi.c

401

intel_de_read(display, FDI_RX_CTL(PIPE_C)) &

sys/dev/pci/drm/i915/display/intel_fdi.c

408

drm_dbg_kms(display->drm, "%sabling fdi C rx\n",

sys/dev/pci/drm/i915/display/intel_fdi.c

410

intel_de_write(display, SOUTH_CHICKEN1, temp);

sys/dev/pci/drm/i915/display/intel_fdi.c

411

intel_de_posting_read(display, SOUTH_CHICKEN1);

sys/dev/pci/drm/i915/display/intel_fdi.c

416

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_fdi.c

42

cur_state = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_fdi.c

424

cpt_set_fdi_bc_bifurcation(display, false);

sys/dev/pci/drm/i915/display/intel_fdi.c

426

cpt_set_fdi_bc_bifurcation(display, true);

sys/dev/pci/drm/i915/display/intel_fdi.c

43

TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE;

sys/dev/pci/drm/i915/display/intel_fdi.c

430

cpt_set_fdi_bc_bifurcation(display, true);

sys/dev/pci/drm/i915/display/intel_fdi.c

440

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_fdi.c

447

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

448

if (display->platform.ivybridge) {

sys/dev/pci/drm/i915/display/intel_fdi.c

45

cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE;

sys/dev/pci/drm/i915/display/intel_fdi.c

455

intel_de_write(display, reg, temp);

sys/dev/pci/drm/i915/display/intel_fdi.c

458

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

459

if (HAS_PCH_CPT(display)) {

sys/dev/pci/drm/i915/display/intel_fdi.c

466

intel_de_write(display, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);

sys/dev/pci/drm/i915/display/intel_fdi.c

469

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

47

INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

sys/dev/pci/drm/i915/display/intel_fdi.c

473

if (display->platform.ivybridge)

sys/dev/pci/drm/i915/display/intel_fdi.c

474

intel_de_rmw(display, reg, 0, FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);

sys/dev/pci/drm/i915/display/intel_fdi.c

481

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_fdi.c

490

intel_de_write(display, FDI_RX_TUSIZE1(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

491

intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);

sys/dev/pci/drm/i915/display/intel_fdi.c

494

assert_transcoder_enabled(display, crtc_state->cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_fdi.c

499

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

502

intel_de_write(display, reg, temp);

sys/dev/pci/drm/i915/display/intel_fdi.c

503

intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

508

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

513

intel_de_write(display, reg, temp | FDI_TX_ENABLE);

sys/dev/pci/drm/i915/display/intel_fdi.c

516

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

519

intel_de_write(display, reg, temp | FDI_RX_ENABLE);

sys/dev/pci/drm/i915/display/intel_fdi.c

52

void assert_fdi_tx_enabled(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_fdi.c

521

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

525

intel_de_write(display, FDI_RX_CHICKEN(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

527

intel_de_write(display, FDI_RX_CHICKEN(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

532

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

533

drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);

sys/dev/pci/drm/i915/display/intel_fdi.c

536

drm_dbg_kms(display->drm, "FDI train 1 done.\n");

sys/dev/pci/drm/i915/display/intel_fdi.c

537

intel_de_write(display, reg, temp | FDI_RX_BIT_LOCK);

sys/dev/pci/drm/i915/display/intel_fdi.c

54

assert_fdi_tx(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_fdi.c

542

drm_err(display->drm, "FDI train 1 fail!\n");

sys/dev/pci/drm/i915/display/intel_fdi.c

545

intel_de_rmw(display, FDI_TX_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

547

intel_de_rmw(display, FDI_RX_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

549

intel_de_posting_read(display, FDI_RX_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_fdi.c

554

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

555

drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);

sys/dev/pci/drm/i915/display/intel_fdi.c

558

intel_de_write(display, reg,

sys/dev/pci/drm/i915/display/intel_fdi.c

560

drm_dbg_kms(display->drm, "FDI train 2 done.\n");

sys/dev/pci/drm/i915/display/intel_fdi.c

565

drm_err(display->drm, "FDI train 2 fail!\n");

sys/dev/pci/drm/i915/display/intel_fdi.c

567

drm_dbg_kms(display->drm, "FDI train done\n");

sys/dev/pci/drm/i915/display/intel_fdi.c

57

void assert_fdi_tx_disabled(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_fdi.c

582

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_fdi.c

59

assert_fdi_tx(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_fdi.c

591

intel_de_write(display, FDI_RX_TUSIZE1(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

592

intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);

sys/dev/pci/drm/i915/display/intel_fdi.c

597

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

600

intel_de_write(display, reg, temp);

sys/dev/pci/drm/i915/display/intel_fdi.c

602

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

607

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

615

intel_de_write(display, reg, temp | FDI_TX_ENABLE);

sys/dev/pci/drm/i915/display/intel_fdi.c

617

intel_de_write(display, FDI_RX_MISC(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

62

static void assert_fdi_rx(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fdi.c

621

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

622

if (HAS_PCH_CPT(display)) {

sys/dev/pci/drm/i915/display/intel_fdi.c

629

intel_de_write(display, reg, temp | FDI_RX_ENABLE);

sys/dev/pci/drm/i915/display/intel_fdi.c

631

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

635

intel_de_rmw(display, FDI_TX_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

637

intel_de_posting_read(display, FDI_TX_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_fdi.c

642

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

643

drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);

sys/dev/pci/drm/i915/display/intel_fdi.c

645

intel_de_write(display, reg,

sys/dev/pci/drm/i915/display/intel_fdi.c

647

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fdi.c

657

drm_err(display->drm, "FDI train 1 fail!\n");

sys/dev/pci/drm/i915/display/intel_fdi.c

661

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

664

if (display->platform.sandybridge) {

sys/dev/pci/drm/i915/display/intel_fdi.c

669

intel_de_write(display, reg, temp);

sys/dev/pci/drm/i915/display/intel_fdi.c

67

cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE;

sys/dev/pci/drm/i915/display/intel_fdi.c

672

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

673

if (HAS_PCH_CPT(display)) {

sys/dev/pci/drm/i915/display/intel_fdi.c

68

INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

sys/dev/pci/drm/i915/display/intel_fdi.c

680

intel_de_write(display, reg, temp);

sys/dev/pci/drm/i915/display/intel_fdi.c

682

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

686

intel_de_rmw(display, FDI_TX_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

688

intel_de_posting_read(display, FDI_TX_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_fdi.c

693

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

694

drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);

sys/dev/pci/drm/i915/display/intel_fdi.c

696

intel_de_write(display, reg,

sys/dev/pci/drm/i915/display/intel_fdi.c

698

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fdi.c

708

drm_err(display->drm, "FDI train 2 fail!\n");

sys/dev/pci/drm/i915/display/intel_fdi.c

710

drm_dbg_kms(display->drm, "FDI train done.\n");

sys/dev/pci/drm/i915/display/intel_fdi.c

717

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_fdi.c

728

intel_de_write(display, FDI_RX_TUSIZE1(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

729

intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);

sys/dev/pci/drm/i915/display/intel_fdi.c

73

void assert_fdi_rx_enabled(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_fdi.c

734

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

737

intel_de_write(display, reg, temp);

sys/dev/pci/drm/i915/display/intel_fdi.c

739

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

742

drm_dbg_kms(display->drm, "FDI_RX_IIR before link train 0x%x\n",

sys/dev/pci/drm/i915/display/intel_fdi.c

743

intel_de_read(display, FDI_RX_IIR(pipe)));

sys/dev/pci/drm/i915/display/intel_fdi.c

749

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

75

assert_fdi_rx(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_fdi.c

752

intel_de_write(display, reg, temp);

sys/dev/pci/drm/i915/display/intel_fdi.c

755

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

759

intel_de_write(display, reg, temp);

sys/dev/pci/drm/i915/display/intel_fdi.c

763

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

770

intel_de_write(display, reg, temp | FDI_TX_ENABLE);

sys/dev/pci/drm/i915/display/intel_fdi.c

772

intel_de_write(display, FDI_RX_MISC(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

776

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

779

intel_de_write(display, reg, temp | FDI_RX_ENABLE);

sys/dev/pci/drm/i915/display/intel_fdi.c

78

void assert_fdi_rx_disabled(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_fdi.c

781

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

786

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

787

drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);

sys/dev/pci/drm/i915/display/intel_fdi.c

790

(intel_de_read(display, reg) & FDI_RX_BIT_LOCK)) {

sys/dev/pci/drm/i915/display/intel_fdi.c

791

intel_de_write(display, reg,

sys/dev/pci/drm/i915/display/intel_fdi.c

793

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fdi.c

80

assert_fdi_rx(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_fdi.c

801

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fdi.c

807

intel_de_rmw(display, FDI_TX_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

810

intel_de_rmw(display, FDI_RX_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

813

intel_de_posting_read(display, FDI_RX_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_fdi.c

818

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

819

drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);

sys/dev/pci/drm/i915/display/intel_fdi.c

822

(intel_de_read(display, reg) & FDI_RX_SYMBOL_LOCK)) {

sys/dev/pci/drm/i915/display/intel_fdi.c

823

intel_de_write(display, reg,

sys/dev/pci/drm/i915/display/intel_fdi.c

825

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fdi.c

83

void assert_fdi_tx_pll_enabled(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_fdi.c

833

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fdi.c

838

drm_dbg_kms(display->drm, "FDI train done.\n");

sys/dev/pci/drm/i915/display/intel_fdi.c

852

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_fdi.c

867

intel_de_write(display, FDI_RX_MISC(PIPE_A),

sys/dev/pci/drm/i915/display/intel_fdi.c

874

rx_ctl_val = display->fdi.rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |

sys/dev/pci/drm/i915/display/intel_fdi.c

877

intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);

sys/dev/pci/drm/i915/display/intel_fdi.c

878

intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));

sys/dev/pci/drm/i915/display/intel_fdi.c

88

if (display->platform.ironlake)

sys/dev/pci/drm/i915/display/intel_fdi.c

883

intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);

sys/dev/pci/drm/i915/display/intel_fdi.c

886

drm_WARN_ON(display->drm, crtc_state->intel_dpll->info->id != DPLL_ID_SPLL);

sys/dev/pci/drm/i915/display/intel_fdi.c

893

intel_de_write(display, DP_TP_CTL(PORT_E),

sys/dev/pci/drm/i915/display/intel_fdi.c

903

intel_de_write(display, DDI_BUF_CTL(PORT_E),

sys/dev/pci/drm/i915/display/intel_fdi.c

907

intel_de_posting_read(display, DDI_BUF_CTL(PORT_E));

sys/dev/pci/drm/i915/display/intel_fdi.c

912

intel_de_write(display, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));

sys/dev/pci/drm/i915/display/intel_fdi.c

916

intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);

sys/dev/pci/drm/i915/display/intel_fdi.c

917

intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));

sys/dev/pci/drm/i915/display/intel_fdi.c

92

if (HAS_DDI(display))

sys/dev/pci/drm/i915/display/intel_fdi.c

923

intel_de_rmw(display, FDI_RX_MISC(PIPE_A),

sys/dev/pci/drm/i915/display/intel_fdi.c

925

intel_de_posting_read(display, FDI_RX_MISC(PIPE_A));

sys/dev/pci/drm/i915/display/intel_fdi.c

930

temp = intel_de_read(display, DP_TP_STATUS(PORT_E));

sys/dev/pci/drm/i915/display/intel_fdi.c

932

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_fdi.c

942

drm_err(display->drm, "FDI link training failed!\n");

sys/dev/pci/drm/i915/display/intel_fdi.c

947

intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);

sys/dev/pci/drm/i915/display/intel_fdi.c

948

intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));

sys/dev/pci/drm/i915/display/intel_fdi.c

95

cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_PLL_ENABLE;

sys/dev/pci/drm/i915/display/intel_fdi.c

950

intel_de_rmw(display, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_fdi.c

951

intel_de_posting_read(display, DDI_BUF_CTL(PORT_E));

sys/dev/pci/drm/i915/display/intel_fdi.c

954

intel_de_rmw(display, DP_TP_CTL(PORT_E), DP_TP_CTL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_fdi.c

955

intel_de_posting_read(display, DP_TP_CTL(PORT_E));

sys/dev/pci/drm/i915/display/intel_fdi.c

957

intel_wait_ddi_buf_idle(display, PORT_E);

sys/dev/pci/drm/i915/display/intel_fdi.c

96

INTEL_DISPLAY_STATE_WARN(display, !cur_state,

sys/dev/pci/drm/i915/display/intel_fdi.c

960

intel_de_rmw(display, FDI_RX_MISC(PIPE_A),

sys/dev/pci/drm/i915/display/intel_fdi.c

963

intel_de_posting_read(display, FDI_RX_MISC(PIPE_A));

sys/dev/pci/drm/i915/display/intel_fdi.c

967

intel_de_write(display, DP_TP_CTL(PORT_E),

sys/dev/pci/drm/i915/display/intel_fdi.c

976

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_fdi.c

984

intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_RX_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_fdi.c

985

intel_de_rmw(display, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_fdi.c

986

intel_wait_ddi_buf_idle(display, PORT_E);

sys/dev/pci/drm/i915/display/intel_fdi.c

988

intel_de_rmw(display, FDI_RX_MISC(PIPE_A),

sys/dev/pci/drm/i915/display/intel_fdi.c

991

intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_PCDCLK, 0);

sys/dev/pci/drm/i915/display/intel_fdi.c

992

intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_RX_PLL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_fdi.c

997

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_fdi.h

21

int intel_fdi_link_freq(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fdi.h

31

void intel_fdi_init_hook(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_fdi.h

35

void intel_fdi_pll_freq_update(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_fdi.h

40

void assert_fdi_tx_enabled(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_fdi.h

41

void assert_fdi_tx_disabled(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_fdi.h

42

void assert_fdi_rx_enabled(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_fdi.h

43

void assert_fdi_rx_disabled(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_fdi.h

44

void assert_fdi_tx_pll_enabled(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_fdi.h

45

void assert_fdi_rx_pll_enabled(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_fdi.h

46

void assert_fdi_rx_pll_disabled(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

100

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

102

if ((intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

105

enable_mask = i915_pipestat_enable_mask(display, crtc->pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

106

intel_de_write(display, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

107

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

109

trace_intel_cpu_fifo_underrun(display, crtc->pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

110

drm_err(display->drm, "pipe %c underrun\n", pipe_name(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

113

static void i9xx_set_fifo_underrun_reporting(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

117

i915_reg_t reg = PIPESTAT(display, pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

119

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

122

u32 enable_mask = i915_pipestat_enable_mask(display, pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

124

intel_de_write(display, reg,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

126

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

128

if (old && intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

129

drm_err(display->drm, "pipe %c underrun\n",

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

134

static void ilk_set_fifo_underrun_reporting(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

141

ilk_enable_display_irq(display, bit);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

143

ilk_disable_display_irq(display, bit);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

148

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

150

u32 err_int = intel_de_read(display, GEN7_ERR_INT);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

152

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

157

intel_de_write(display, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

158

intel_de_posting_read(display, GEN7_ERR_INT);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

160

trace_intel_cpu_fifo_underrun(display, pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

161

drm_err(display->drm, "fifo underrun on pipe %c\n", pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

164

static void ivb_set_fifo_underrun_reporting(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

169

intel_de_write(display, GEN7_ERR_INT,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

172

if (!ivb_can_enable_err_int(display))

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

175

ilk_enable_display_irq(display, DE_ERR_INT_IVB);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

177

ilk_disable_display_irq(display, DE_ERR_INT_IVB);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

180

intel_de_read(display, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

181

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

188

static void bdw_set_fifo_underrun_reporting(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

192

bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_FIFO_UNDERRUN);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

194

bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_FIFO_UNDERRUN);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

197

static void ibx_set_fifo_underrun_reporting(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

205

ibx_enable_display_interrupt(display, bit);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

207

ibx_disable_display_interrupt(display, bit);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

212

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

214

u32 serr_int = intel_de_read(display, SERR_INT);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

216

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

221

intel_de_write(display, SERR_INT,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

223

intel_de_posting_read(display, SERR_INT);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

225

trace_intel_pch_fifo_underrun(display, pch_transcoder);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

226

drm_err(display->drm, "pch fifo underrun on pch transcoder %c\n",

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

230

static void cpt_set_fifo_underrun_reporting(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

235

intel_de_write(display, SERR_INT,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

238

if (!cpt_can_enable_serr_int(display))

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

241

ibx_enable_display_interrupt(display, SDE_ERROR_CPT);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

243

ibx_disable_display_interrupt(display, SDE_ERROR_CPT);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

245

if (old && intel_de_read(display, SERR_INT) &

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

247

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

254

static bool __intel_set_cpu_fifo_underrun_reporting(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

257

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

260

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

265

if (HAS_GMCH(display))

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

266

i9xx_set_fifo_underrun_reporting(display, pipe, enable, old);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

267

else if (display->platform.ironlake || display->platform.sandybridge)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

268

ilk_set_fifo_underrun_reporting(display, pipe, enable);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

269

else if (DISPLAY_VER(display) == 7)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

270

ivb_set_fifo_underrun_reporting(display, pipe, enable, old);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

271

else if (DISPLAY_VER(display) >= 8)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

272

bdw_set_fifo_underrun_reporting(display, pipe, enable);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

293

bool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

299

spin_lock_irqsave(&display->irq.lock, flags);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

300

ret = __intel_set_cpu_fifo_underrun_reporting(display, pipe, enable);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

301

spin_unlock_irqrestore(&display->irq.lock, flags);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

320

bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

324

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pch_transcoder);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

337

spin_lock_irqsave(&display->irq.lock, flags);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

342

if (HAS_PCH_IBX(display))

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

343

ibx_set_fifo_underrun_reporting(display,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

347

cpt_set_fifo_underrun_reporting(display,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

351

spin_unlock_irqrestore(&display->irq.lock, flags);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

364

void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

367

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

374

if (HAS_GMCH(display) &&

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

378

if (intel_set_cpu_fifo_underrun_reporting(display, pipe, false)) {

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

379

trace_intel_cpu_fifo_underrun(display, pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

381

drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

384

intel_fbc_handle_fifo_underrun_irq(display);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

396

void intel_pch_fifo_underrun_irq_handler(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

399

if (intel_set_pch_fifo_underrun_reporting(display, pch_transcoder,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

401

trace_intel_pch_fifo_underrun(display, pch_transcoder);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

402

drm_err(display->drm, "PCH transcoder %c FIFO underrun\n",

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

416

void intel_check_cpu_fifo_underruns(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

420

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

422

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

426

if (HAS_GMCH(display))

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

428

else if (DISPLAY_VER(display) == 7)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

432

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

443

void intel_check_pch_fifo_underruns(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

447

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

449

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

453

if (HAS_PCH_CPT(display))

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

457

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

460

void intel_init_fifo_underrun_reporting(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

475

if (intel_has_pch_trancoder(display, crtc->pipe))

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

60

static bool ivb_can_enable_err_int(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

65

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

67

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

68

crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

77

static bool cpt_can_enable_serr_int(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

82

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

84

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

85

crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

96

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

97

i915_reg_t reg = PIPESTAT(display, crtc->pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.h

15

void intel_init_fifo_underrun_reporting(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.h

17

bool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.h

19

bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.h

22

void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.h

24

void intel_pch_fifo_underrun_irq_handler(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.h

26

void intel_check_cpu_fifo_underruns(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.h

27

void intel_check_pch_fifo_underruns(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_flipq.c

107

drm_dbg_kms(display->drm, "[CRTC:%d:%s] FQ %d: start 0x%x\n",

sys/dev/pci/drm/i915/display/intel_flipq.c

113

bool intel_flipq_supported(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_flipq.c

115

if (!display->params.enable_flipq)

sys/dev/pci/drm/i915/display/intel_flipq.c

118

if (!display->dmc.dmc)

sys/dev/pci/drm/i915/display/intel_flipq.c

121

if (DISPLAY_VER(display) == 20)

sys/dev/pci/drm/i915/display/intel_flipq.c

125

return DISPLAY_VER(display) >= 30 && intel_vrr_always_use_vrr_tg(display);

sys/dev/pci/drm/i915/display/intel_flipq.c

128

void intel_flipq_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_flipq.c

132

intel_dmc_wait_fw_load(display);

sys/dev/pci/drm/i915/display/intel_flipq.c

134

for_each_intel_crtc(display->drm, crtc)

sys/dev/pci/drm/i915/display/intel_flipq.c

138

static int cdclk_factor(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_flipq.c

140

if (DISPLAY_VER(display) >= 30)

sys/dev/pci/drm/i915/display/intel_flipq.c

146

int intel_flipq_exec_time_us(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_flipq.c

149

DIV_ROUND_UP(display->cdclk.hw.cdclk * cdclk_factor(display), 540000) +

sys/dev/pci/drm/i915/display/intel_flipq.c

150

display->sagv.block_time_us;

sys/dev/pci/drm/i915/display/intel_flipq.c

153

static int intel_flipq_preempt_timeout_ms(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_flipq.c

155

return DIV_ROUND_UP(intel_flipq_exec_time_us(display), 1000);

sys/dev/pci/drm/i915/display/intel_flipq.c

160

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_flipq.c

162

intel_de_rmw(display, PIPEDMC_FQ_CTRL(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_flipq.c

166

intel_de_wait_for_clear(display,

sys/dev/pci/drm/i915/display/intel_flipq.c

169

intel_flipq_preempt_timeout_ms(display)))

sys/dev/pci/drm/i915/display/intel_flipq.c

170

drm_err(display->drm, "[CRTC:%d:%s] flip queue preempt timeout\n",

sys/dev/pci/drm/i915/display/intel_flipq.c

176

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_flipq.c

178

return intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id));

sys/dev/pci/drm/i915/display/intel_flipq.c

183

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_flipq.c

185

intel_de_write(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_flipq.c

195

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_flipq.c

197

intel_de_write(display, PIPEDMC_FPQ_CTL1(crtc->pipe), PIPEDMC_SW_DMC_WAKE);

sys/dev/pci/drm/i915/display/intel_flipq.c

202

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_flipq.c

205

intel_flipq_exec_time_us(display));

sys/dev/pci/drm/i915/display/intel_flipq.c

211

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_flipq.c

215

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_flipq.c

221

intel_de_read(display, PIPEDMC_FQ_RAM(flipq->start_mmioaddr, i)));

sys/dev/pci/drm/i915/display/intel_flipq.c

226

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_flipq.c

229

intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id)),

sys/dev/pci/drm/i915/display/intel_flipq.c

230

intel_de_read(display, PIPEDMC_FPQ_HP(crtc->pipe, flipq_id)));

sys/dev/pci/drm/i915/display/intel_flipq.c

232

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_flipq.c

237

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_flipq.c

240

intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe)));

sys/dev/pci/drm/i915/display/intel_flipq.c

242

tmp = intel_de_read(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_flipq.c

244

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_flipq.c

254

void intel_flipq_reset(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_flipq.c

256

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_flipq.c

259

intel_de_write(display, PIPEDMC_FQ_CTRL(pipe), 0);

sys/dev/pci/drm/i915/display/intel_flipq.c

261

intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(pipe), 0);

sys/dev/pci/drm/i915/display/intel_flipq.c

262

intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(pipe), 0);

sys/dev/pci/drm/i915/display/intel_flipq.c

267

intel_de_write(display, PIPEDMC_FPQ_HP(pipe, flipq_id), 0);

sys/dev/pci/drm/i915/display/intel_flipq.c

268

intel_de_write(display, PIPEDMC_FPQ_CHP(pipe, flipq_id), 0);

sys/dev/pci/drm/i915/display/intel_flipq.c

273

intel_de_write(display, PIPEDMC_FPQ_ATOMIC_TP(pipe), 0);

sys/dev/pci/drm/i915/display/intel_flipq.c

276

static enum pipedmc_event_id flipq_event_id(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_flipq.c

278

if (DISPLAY_VER(display) >= 30)

sys/dev/pci/drm/i915/display/intel_flipq.c

286

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_flipq.c

292

if (DISPLAY_VER(display) >= 30) {

sys/dev/pci/drm/i915/display/intel_flipq.c

296

intel_de_write(display, PTL_PIPEDMC_EXEC_TIME_LINES(start_mmioaddr),

sys/dev/pci/drm/i915/display/intel_flipq.c

298

intel_de_write(display, PTL_PIPEDMC_END_OF_EXEC_GB(start_mmioaddr),

sys/dev/pci/drm/i915/display/intel_flipq.c

302

intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_flipq.c

304

intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_flipq.c

308

intel_pipedmc_enable_event(crtc, flipq_event_id(display));

sys/dev/pci/drm/i915/display/intel_flipq.c

310

intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe), PIPEDMC_FQ_CTRL_ENABLE);

sys/dev/pci/drm/i915/display/intel_flipq.c

315

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_flipq.c

320

intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe), 0);

sys/dev/pci/drm/i915/display/intel_flipq.c

322

intel_pipedmc_disable_event(crtc, flipq_event_id(display));

sys/dev/pci/drm/i915/display/intel_flipq.c

324

intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(crtc->pipe), 0);

sys/dev/pci/drm/i915/display/intel_flipq.c

325

intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(crtc->pipe), 0);

sys/dev/pci/drm/i915/display/intel_flipq.c

331

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_flipq.c

337

return !drm_WARN(display->drm,

sys/dev/pci/drm/i915/display/intel_flipq.c

344

static void intel_flipq_write(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_flipq.c

347

intel_de_write(display, PIPEDMC_FQ_RAM(flipq->start_mmioaddr, flipq->tail *

sys/dev/pci/drm/i915/display/intel_flipq.c

351

static void lnl_flipq_add(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_flipq.c

361

intel_flipq_write(display, flipq, pts, i++);

sys/dev/pci/drm/i915/display/intel_flipq.c

362

intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++);

sys/dev/pci/drm/i915/display/intel_flipq.c

363

intel_flipq_write(display, flipq, LNL_FQ_INTERRUPT |

sys/dev/pci/drm/i915/display/intel_flipq.c

366

intel_flipq_write(display, flipq, 0, i++);

sys/dev/pci/drm/i915/display/intel_flipq.c

367

intel_flipq_write(display, flipq, 0, i++); /* head for second DSB */

sys/dev/pci/drm/i915/display/intel_flipq.c

368

intel_flipq_write(display, flipq, 0, i++); /* DSB engine + size for second DSB */

sys/dev/pci/drm/i915/display/intel_flipq.c

373

intel_flipq_write(display, flipq, pts, i++);

sys/dev/pci/drm/i915/display/intel_flipq.c

374

intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++);

sys/dev/pci/drm/i915/display/intel_flipq.c

375

intel_flipq_write(display, flipq, LNL_FQ_INTERRUPT |

sys/dev/pci/drm/i915/display/intel_flipq.c

378

intel_flipq_write(display, flipq, 0, i++);

sys/dev/pci/drm/i915/display/intel_flipq.c

386

static void ptl_flipq_add(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_flipq.c

396

intel_flipq_write(display, flipq, pts, i++);

sys/dev/pci/drm/i915/display/intel_flipq.c

397

intel_flipq_write(display, flipq, 0, i++);

sys/dev/pci/drm/i915/display/intel_flipq.c

398

intel_flipq_write(display, flipq, PTL_FQ_INTERRUPT |

sys/dev/pci/drm/i915/display/intel_flipq.c

401

intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++);

sys/dev/pci/drm/i915/display/intel_flipq.c

402

intel_flipq_write(display, flipq, 0, i++); /* DSB engine + size for second DSB */

sys/dev/pci/drm/i915/display/intel_flipq.c

403

intel_flipq_write(display, flipq, 0, i++); /* head for second DSB */

sys/dev/pci/drm/i915/display/intel_flipq.c

408

intel_flipq_write(display, flipq, pts, i++);

sys/dev/pci/drm/i915/display/intel_flipq.c

409

intel_flipq_write(display, flipq, 0, i++);

sys/dev/pci/drm/i915/display/intel_flipq.c

410

intel_flipq_write(display, flipq, PTL_FQ_INTERRUPT |

sys/dev/pci/drm/i915/display/intel_flipq.c

413

intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++);

sys/dev/pci/drm/i915/display/intel_flipq.c

427

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_flipq.c

433

pts += intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_flipq.c

437

if (DISPLAY_VER(display) >= 30)

sys/dev/pci/drm/i915/display/intel_flipq.c

438

ptl_flipq_add(display, flipq, pts, dsb_id, dsb);

sys/dev/pci/drm/i915/display/intel_flipq.c

440

lnl_flipq_add(display, flipq, pts, dsb_id, dsb);

sys/dev/pci/drm/i915/display/intel_flipq.c

451

static bool need_dmc_halt_wa(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_flipq.c

453

return DISPLAY_VER(display) == 20 ||

sys/dev/pci/drm/i915/display/intel_flipq.c

454

(display->platform.pantherlake &&

sys/dev/pci/drm/i915/display/intel_flipq.c

455

IS_DISPLAY_STEP(display, STEP_A0, STEP_B0));

sys/dev/pci/drm/i915/display/intel_flipq.c

460

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_flipq.c

462

if (need_dmc_halt_wa(display))

sys/dev/pci/drm/i915/display/intel_flipq.c

468

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_flipq.c

470

if (need_dmc_halt_wa(display))

sys/dev/pci/drm/i915/display/intel_flipq.c

98

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_flipq.h

19

bool intel_flipq_supported(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_flipq.h

20

void intel_flipq_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_flipq.h

21

void intel_flipq_reset(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_flipq.h

31

int intel_flipq_exec_time_us(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

100

intel_drrs_flush(display, frontbuffer_bits);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

101

intel_psr_flush(display, frontbuffer_bits, origin);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

102

intel_fbc_flush(display, frontbuffer_bits, origin);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

117

void intel_frontbuffer_flip_prepare(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

120

spin_lock(&display->fb_tracking.lock);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

121

display->fb_tracking.flip_bits |= frontbuffer_bits;

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

123

display->fb_tracking.busy_bits &= ~frontbuffer_bits;

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

124

spin_unlock(&display->fb_tracking.lock);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

137

void intel_frontbuffer_flip_complete(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

140

spin_lock(&display->fb_tracking.lock);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

142

frontbuffer_bits &= display->fb_tracking.flip_bits;

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

143

display->fb_tracking.flip_bits &= ~frontbuffer_bits;

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

144

spin_unlock(&display->fb_tracking.lock);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

147

frontbuffer_flush(display, frontbuffer_bits, ORIGIN_FLIP);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

161

void intel_frontbuffer_flip(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

164

spin_lock(&display->fb_tracking.lock);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

166

display->fb_tracking.busy_bits &= ~frontbuffer_bits;

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

167

spin_unlock(&display->fb_tracking.lock);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

169

frontbuffer_flush(display, frontbuffer_bits, ORIGIN_FLIP);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

176

struct intel_display *display = to_intel_display(front->obj->dev);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

179

spin_lock(&display->fb_tracking.lock);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

180

display->fb_tracking.busy_bits |= frontbuffer_bits;

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

181

display->fb_tracking.flip_bits &= ~frontbuffer_bits;

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

182

spin_unlock(&display->fb_tracking.lock);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

185

trace_intel_frontbuffer_invalidate(display, frontbuffer_bits, origin);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

188

intel_psr_invalidate(display, frontbuffer_bits, origin);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

189

intel_drrs_invalidate(display, frontbuffer_bits);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

190

intel_fbc_invalidate(display, frontbuffer_bits, origin);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

197

struct intel_display *display = to_intel_display(front->obj->dev);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

200

spin_lock(&display->fb_tracking.lock);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

202

frontbuffer_bits &= display->fb_tracking.busy_bits;

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

203

display->fb_tracking.busy_bits &= ~frontbuffer_bits;

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

204

spin_unlock(&display->fb_tracking.lock);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

208

frontbuffer_flush(display, frontbuffer_bits, origin);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

262

struct intel_display *display = to_intel_display(obj->dev);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

264

drm_WARN_ON(display->drm, atomic_read(&front->bits));

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

269

drm_WARN_ON(display->drm, ret);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

270

spin_unlock(&display->fb_tracking.lock);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

281

struct intel_display *display = to_intel_display(obj->dev);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

303

spin_lock(&display->fb_tracking.lock);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

305

spin_unlock(&display->fb_tracking.lock);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

348

struct intel_display *display = to_intel_display(old->obj->dev);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

350

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

356

struct intel_display *display = to_intel_display(new->obj->dev);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

358

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

84

static void frontbuffer_flush(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

89

spin_lock(&display->fb_tracking.lock);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

90

frontbuffer_bits &= ~display->fb_tracking.busy_bits;

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

91

spin_unlock(&display->fb_tracking.lock);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

96

trace_intel_frontbuffer_flush(display, frontbuffer_bits, origin);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

99

intel_td_flush(display);

sys/dev/pci/drm/i915/display/intel_frontbuffer.h

71

void intel_frontbuffer_flip_prepare(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_frontbuffer.h

73

void intel_frontbuffer_flip_complete(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_frontbuffer.h

75

void intel_frontbuffer_flip(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_global_state.c

111

void intel_atomic_global_obj_init(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_global_state.c

124

list_add_tail(&obj->head, &display->global.obj_list);

sys/dev/pci/drm/i915/display/intel_global_state.c

127

void intel_atomic_global_obj_cleanup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_global_state.c

131

list_for_each_entry_safe(obj, next, &display->global.obj_list, head) {

sys/dev/pci/drm/i915/display/intel_global_state.c

134

drm_WARN_ON(display->drm, kref_read(&obj->state->ref) != 1);

sys/dev/pci/drm/i915/display/intel_global_state.c

139

static void assert_global_state_write_locked(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_global_state.c

143

for_each_intel_crtc(display->drm, crtc)

sys/dev/pci/drm/i915/display/intel_global_state.c

162

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_global_state.c

166

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_global_state.c

171

drm_WARN(display->drm, 1, "Global state not read locked\n");

sys/dev/pci/drm/i915/display/intel_global_state.c

178

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_global_state.c

229

drm_dbg_atomic(display->drm, "Added new global object %p state %p to %p\n",

sys/dev/pci/drm/i915/display/intel_global_state.c

263

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_global_state.c

270

drm_WARN_ON(display->drm, obj->state != old_obj_state);

sys/dev/pci/drm/i915/display/intel_global_state.c

279

assert_global_state_write_locked(display);

sys/dev/pci/drm/i915/display/intel_global_state.c

310

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_global_state.c

313

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_global_state.c

343

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_global_state.c

346

for_each_intel_crtc(display->drm, crtc)

sys/dev/pci/drm/i915/display/intel_global_state.c

389

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_global_state.c

403

drm_err(display->drm, "global state timed out\n");

sys/dev/pci/drm/i915/display/intel_global_state.h

38

void intel_atomic_global_obj_init(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_global_state.h

42

void intel_atomic_global_obj_cleanup(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_gmbus.c

1000

mutex_unlock(&display->gmbus.mutex);

sys/dev/pci/drm/i915/display/intel_gmbus.c

1013

int intel_gmbus_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_gmbus.c

1016

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

sys/dev/pci/drm/i915/display/intel_gmbus.c

1021

if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_gmbus.c

1022

display->gmbus.mmio_base = VLV_DISPLAY_BASE;

sys/dev/pci/drm/i915/display/intel_gmbus.c

1023

else if (!HAS_GMCH(display))

sys/dev/pci/drm/i915/display/intel_gmbus.c

1028

display->gmbus.mmio_base = PCH_DISPLAY_BASE;

sys/dev/pci/drm/i915/display/intel_gmbus.c

1030

rw_init(&display->gmbus.mutex, "gmbus");

sys/dev/pci/drm/i915/display/intel_gmbus.c

1031

init_waitqueue_head(&display->gmbus.wait_queue);

sys/dev/pci/drm/i915/display/intel_gmbus.c

1033

for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) {

sys/dev/pci/drm/i915/display/intel_gmbus.c

1037

gmbus_pin = get_gmbus_pin(display, pin);

sys/dev/pci/drm/i915/display/intel_gmbus.c

1057

bus->display = display;

sys/dev/pci/drm/i915/display/intel_gmbus.c

1072

if (display->platform.i830)

sys/dev/pci/drm/i915/display/intel_gmbus.c

1075

intel_gpio_setup(bus, GPIO(display, gmbus_pin->gpio));

sys/dev/pci/drm/i915/display/intel_gmbus.c

1083

display->gmbus.bus[pin] = bus;

sys/dev/pci/drm/i915/display/intel_gmbus.c

1086

intel_gmbus_reset(display);

sys/dev/pci/drm/i915/display/intel_gmbus.c

1091

intel_gmbus_teardown(display);

sys/dev/pci/drm/i915/display/intel_gmbus.c

1096

struct i2c_adapter *intel_gmbus_get_adapter(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_gmbus.c

1099

if (drm_WARN_ON(display->drm, pin >= ARRAY_SIZE(display->gmbus.bus) ||

sys/dev/pci/drm/i915/display/intel_gmbus.c

1100

!display->gmbus.bus[pin]))

sys/dev/pci/drm/i915/display/intel_gmbus.c

1103

return &display->gmbus.bus[pin]->adapter;

sys/dev/pci/drm/i915/display/intel_gmbus.c

1109

struct intel_display *display = bus->display;

sys/dev/pci/drm/i915/display/intel_gmbus.c

1111

mutex_lock(&display->gmbus.mutex);

sys/dev/pci/drm/i915/display/intel_gmbus.c

1114

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_gmbus.c

1119

mutex_unlock(&display->gmbus.mutex);

sys/dev/pci/drm/i915/display/intel_gmbus.c

1129

void intel_gmbus_teardown(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_gmbus.c

1133

for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) {

sys/dev/pci/drm/i915/display/intel_gmbus.c

1136

bus = display->gmbus.bus[pin];

sys/dev/pci/drm/i915/display/intel_gmbus.c

1143

display->gmbus.bus[pin] = NULL;

sys/dev/pci/drm/i915/display/intel_gmbus.c

1147

void intel_gmbus_irq_handler(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_gmbus.c

1149

wake_up_all(&display->gmbus.wait_queue);

sys/dev/pci/drm/i915/display/intel_gmbus.c

158

static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_gmbus.c

164

if (INTEL_PCH_TYPE(display) >= PCH_MTL) {

sys/dev/pci/drm/i915/display/intel_gmbus.c

167

} else if (INTEL_PCH_TYPE(display) >= PCH_DG2) {

sys/dev/pci/drm/i915/display/intel_gmbus.c

170

} else if (INTEL_PCH_TYPE(display) >= PCH_DG1) {

sys/dev/pci/drm/i915/display/intel_gmbus.c

173

} else if (INTEL_PCH_TYPE(display) >= PCH_ICP) {

sys/dev/pci/drm/i915/display/intel_gmbus.c

176

} else if (HAS_PCH_CNP(display)) {

sys/dev/pci/drm/i915/display/intel_gmbus.c

179

} else if (display->platform.geminilake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/intel_gmbus.c

182

} else if (DISPLAY_VER(display) == 9) {

sys/dev/pci/drm/i915/display/intel_gmbus.c

185

} else if (display->platform.broadwell) {

sys/dev/pci/drm/i915/display/intel_gmbus.c

199

bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin)

sys/dev/pci/drm/i915/display/intel_gmbus.c

201

return get_gmbus_pin(display, pin);

sys/dev/pci/drm/i915/display/intel_gmbus.c

215

intel_gmbus_reset(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_gmbus.c

217

intel_de_write(display, GMBUS0(display), 0);

sys/dev/pci/drm/i915/display/intel_gmbus.c

218

intel_de_write(display, GMBUS4(display), 0);

sys/dev/pci/drm/i915/display/intel_gmbus.c

221

static void pnv_gmbus_clock_gating(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_gmbus.c

225

intel_de_rmw(display, DSPCLK_GATE_D,

sys/dev/pci/drm/i915/display/intel_gmbus.c

230

static void pch_gmbus_clock_gating(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_gmbus.c

233

intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,

sys/dev/pci/drm/i915/display/intel_gmbus.c

238

static void bxt_gmbus_clock_gating(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_gmbus.c

241

intel_de_rmw(display, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS,

sys/dev/pci/drm/i915/display/intel_gmbus.c

247

struct intel_display *display = bus->display;

sys/dev/pci/drm/i915/display/intel_gmbus.c

250

if (display->platform.i830 || display->platform.i845g)

sys/dev/pci/drm/i915/display/intel_gmbus.c

257

if (intel_display_wa(display, 16025573575))

sys/dev/pci/drm/i915/display/intel_gmbus.c

261

return intel_de_read_notrace(display, bus->gpio_reg) & preserve_bits;

sys/dev/pci/drm/i915/display/intel_gmbus.c

267

struct intel_display *display = bus->display;

sys/dev/pci/drm/i915/display/intel_gmbus.c

270

intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);

sys/dev/pci/drm/i915/display/intel_gmbus.c

271

intel_de_write_notrace(display, bus->gpio_reg, reserved);

sys/dev/pci/drm/i915/display/intel_gmbus.c

273

return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;

sys/dev/pci/drm/i915/display/intel_gmbus.c

279

struct intel_display *display = bus->display;

sys/dev/pci/drm/i915/display/intel_gmbus.c

282

intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);

sys/dev/pci/drm/i915/display/intel_gmbus.c

283

intel_de_write_notrace(display, bus->gpio_reg, reserved);

sys/dev/pci/drm/i915/display/intel_gmbus.c

285

return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;

sys/dev/pci/drm/i915/display/intel_gmbus.c

291

struct intel_display *display = bus->display;

sys/dev/pci/drm/i915/display/intel_gmbus.c

301

intel_de_write_notrace(display, bus->gpio_reg, reserved | clock_bits);

sys/dev/pci/drm/i915/display/intel_gmbus.c

302

intel_de_posting_read(display, bus->gpio_reg);

sys/dev/pci/drm/i915/display/intel_gmbus.c

308

struct intel_display *display = bus->display;

sys/dev/pci/drm/i915/display/intel_gmbus.c

318

intel_de_write_notrace(display, bus->gpio_reg, reserved | data_bits);

sys/dev/pci/drm/i915/display/intel_gmbus.c

319

intel_de_posting_read(display, bus->gpio_reg);

sys/dev/pci/drm/i915/display/intel_gmbus.c

325

struct intel_display *display = bus->display;

sys/dev/pci/drm/i915/display/intel_gmbus.c

326

u32 reg_val = intel_de_read_notrace(display, bus->gpio_reg);

sys/dev/pci/drm/i915/display/intel_gmbus.c

334

intel_de_write_notrace(display, bus->gpio_reg, reg_val);

sys/dev/pci/drm/i915/display/intel_gmbus.c

335

intel_de_posting_read(display, bus->gpio_reg);

sys/dev/pci/drm/i915/display/intel_gmbus.c

342

struct intel_display *display = bus->display;

sys/dev/pci/drm/i915/display/intel_gmbus.c

344

intel_gmbus_reset(display);

sys/dev/pci/drm/i915/display/intel_gmbus.c

346

if (display->platform.pineview)

sys/dev/pci/drm/i915/display/intel_gmbus.c

347

pnv_gmbus_clock_gating(display, false);

sys/dev/pci/drm/i915/display/intel_gmbus.c

349

if (intel_display_wa(display, 16025573575))

sys/dev/pci/drm/i915/display/intel_gmbus.c

362

struct intel_display *display = bus->display;

sys/dev/pci/drm/i915/display/intel_gmbus.c

367

if (display->platform.pineview)

sys/dev/pci/drm/i915/display/intel_gmbus.c

368

pnv_gmbus_clock_gating(display, true);

sys/dev/pci/drm/i915/display/intel_gmbus.c

370

if (intel_display_wa(display, 16025573575))

sys/dev/pci/drm/i915/display/intel_gmbus.c

499

static bool has_gmbus_irq(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_gmbus.c

501

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_gmbus.c

506

return HAS_GMBUS_IRQ(display) && intel_irqs_enabled(i915);

sys/dev/pci/drm/i915/display/intel_gmbus.c

509

static int gmbus_wait(struct intel_display *display, u32 status, u32 irq_en)

sys/dev/pci/drm/i915/display/intel_gmbus.c

519

if (!has_gmbus_irq(display) || cold)

sys/dev/pci/drm/i915/display/intel_gmbus.c

522

add_wait_queue(&display->gmbus.wait_queue, &wait);

sys/dev/pci/drm/i915/display/intel_gmbus.c

523

intel_de_write_fw(display, GMBUS4(display), irq_en);

sys/dev/pci/drm/i915/display/intel_gmbus.c

527

ret = poll_timeout_us_atomic(gmbus2 = intel_de_read_fw(display, GMBUS2(display)),

sys/dev/pci/drm/i915/display/intel_gmbus.c

531

ret = poll_timeout_us(gmbus2 = intel_de_read_fw(display, GMBUS2(display)),

sys/dev/pci/drm/i915/display/intel_gmbus.c

535

intel_de_write_fw(display, GMBUS4(display), 0);

sys/dev/pci/drm/i915/display/intel_gmbus.c

536

remove_wait_queue(&display->gmbus.wait_queue, &wait);

sys/dev/pci/drm/i915/display/intel_gmbus.c

54

struct intel_display *display;

sys/dev/pci/drm/i915/display/intel_gmbus.c

545

gmbus_wait_idle(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_gmbus.c

553

if (has_gmbus_irq(display) && !cold)

sys/dev/pci/drm/i915/display/intel_gmbus.c

556

add_wait_queue(&display->gmbus.wait_queue, &wait);

sys/dev/pci/drm/i915/display/intel_gmbus.c

557

intel_de_write_fw(display, GMBUS4(display), irq_enable);

sys/dev/pci/drm/i915/display/intel_gmbus.c

559

ret = intel_de_wait_fw(display, GMBUS2(display), GMBUS_ACTIVE, 0, 10, NULL);

sys/dev/pci/drm/i915/display/intel_gmbus.c

561

intel_de_write_fw(display, GMBUS4(display), 0);

sys/dev/pci/drm/i915/display/intel_gmbus.c

562

remove_wait_queue(&display->gmbus.wait_queue, &wait);

sys/dev/pci/drm/i915/display/intel_gmbus.c

567

static unsigned int gmbus_max_xfer_size(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_gmbus.c

569

return DISPLAY_VER(display) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :

sys/dev/pci/drm/i915/display/intel_gmbus.c

574

gmbus_xfer_read_chunk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_gmbus.c

579

bool burst_read = len > gmbus_max_xfer_size(display);

sys/dev/pci/drm/i915/display/intel_gmbus.c

592

intel_de_write_fw(display, GMBUS0(display),

sys/dev/pci/drm/i915/display/intel_gmbus.c

596

intel_de_write_fw(display, GMBUS1(display),

sys/dev/pci/drm/i915/display/intel_gmbus.c

602

ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);

sys/dev/pci/drm/i915/display/intel_gmbus.c

606

val = intel_de_read_fw(display, GMBUS3(display));

sys/dev/pci/drm/i915/display/intel_gmbus.c

619

intel_de_write_fw(display, GMBUS0(display), gmbus0_reg);

sys/dev/pci/drm/i915/display/intel_gmbus.c

636

gmbus_xfer_read(struct intel_display *display, struct i2c_msg *msg,

sys/dev/pci/drm/i915/display/intel_gmbus.c

645

if (HAS_GMBUS_BURST_READ(display))

sys/dev/pci/drm/i915/display/intel_gmbus.c

648

len = min(rx_size, gmbus_max_xfer_size(display));

sys/dev/pci/drm/i915/display/intel_gmbus.c

650

ret = gmbus_xfer_read_chunk(display, msg->addr, buf, len,

sys/dev/pci/drm/i915/display/intel_gmbus.c

663

gmbus_xfer_write_chunk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_gmbus.c

676

intel_de_write_fw(display, GMBUS3(display), val);

sys/dev/pci/drm/i915/display/intel_gmbus.c

677

intel_de_write_fw(display, GMBUS1(display),

sys/dev/pci/drm/i915/display/intel_gmbus.c

687

intel_de_write_fw(display, GMBUS3(display), val);

sys/dev/pci/drm/i915/display/intel_gmbus.c

689

ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);

sys/dev/pci/drm/i915/display/intel_gmbus.c

698

gmbus_xfer_write(struct intel_display *display, struct i2c_msg *msg,

sys/dev/pci/drm/i915/display/intel_gmbus.c

707

len = min(tx_size, gmbus_max_xfer_size(display));

sys/dev/pci/drm/i915/display/intel_gmbus.c

709

ret = gmbus_xfer_write_chunk(display, msg->addr, buf, len,

sys/dev/pci/drm/i915/display/intel_gmbus.c

736

gmbus_index_xfer(struct intel_display *display, struct i2c_msg *msgs,

sys/dev/pci/drm/i915/display/intel_gmbus.c

752

intel_de_write_fw(display, GMBUS5(display), gmbus5);

sys/dev/pci/drm/i915/display/intel_gmbus.c

755

ret = gmbus_xfer_read(display, &msgs[1], gmbus0_reg,

sys/dev/pci/drm/i915/display/intel_gmbus.c

758

ret = gmbus_xfer_write(display, &msgs[1], gmbus1_index);

sys/dev/pci/drm/i915/display/intel_gmbus.c

762

intel_de_write_fw(display, GMBUS5(display), 0);

sys/dev/pci/drm/i915/display/intel_gmbus.c

772

struct intel_display *display = bus->display;

sys/dev/pci/drm/i915/display/intel_gmbus.c

777

if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_gmbus.c

778

bxt_gmbus_clock_gating(display, false);

sys/dev/pci/drm/i915/display/intel_gmbus.c

779

else if (HAS_PCH_SPT(display) || HAS_PCH_CNP(display))

sys/dev/pci/drm/i915/display/intel_gmbus.c

780

pch_gmbus_clock_gating(display, false);

sys/dev/pci/drm/i915/display/intel_gmbus.c

783

intel_de_write_fw(display, GMBUS0(display), gmbus0_source | bus->reg0);

sys/dev/pci/drm/i915/display/intel_gmbus.c

788

ret = gmbus_index_xfer(display, &msgs[i],

sys/dev/pci/drm/i915/display/intel_gmbus.c

792

ret = gmbus_xfer_read(display, &msgs[i],

sys/dev/pci/drm/i915/display/intel_gmbus.c

795

ret = gmbus_xfer_write(display, &msgs[i], 0);

sys/dev/pci/drm/i915/display/intel_gmbus.c

799

ret = gmbus_wait(display,

sys/dev/pci/drm/i915/display/intel_gmbus.c

811

intel_de_write_fw(display, GMBUS1(display), GMBUS_CYCLE_STOP | GMBUS_SW_RDY);

sys/dev/pci/drm/i915/display/intel_gmbus.c

817

if (gmbus_wait_idle(display)) {

sys/dev/pci/drm/i915/display/intel_gmbus.c

818

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_gmbus.c

823

intel_de_write_fw(display, GMBUS0(display), 0);

sys/dev/pci/drm/i915/display/intel_gmbus.c

842

if (gmbus_wait_idle(display)) {

sys/dev/pci/drm/i915/display/intel_gmbus.c

843

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_gmbus.c

853

intel_de_write_fw(display, GMBUS1(display), GMBUS_SW_CLR_INT);

sys/dev/pci/drm/i915/display/intel_gmbus.c

854

intel_de_write_fw(display, GMBUS1(display), 0);

sys/dev/pci/drm/i915/display/intel_gmbus.c

855

intel_de_write_fw(display, GMBUS0(display), 0);

sys/dev/pci/drm/i915/display/intel_gmbus.c

857

drm_dbg_kms(display->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",

sys/dev/pci/drm/i915/display/intel_gmbus.c

868

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_gmbus.c

877

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_gmbus.c

880

intel_de_write_fw(display, GMBUS0(display), 0);

sys/dev/pci/drm/i915/display/intel_gmbus.c

890

if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_gmbus.c

891

bxt_gmbus_clock_gating(display, true);

sys/dev/pci/drm/i915/display/intel_gmbus.c

892

else if (HAS_PCH_SPT(display) || HAS_PCH_CNP(display))

sys/dev/pci/drm/i915/display/intel_gmbus.c

893

pch_gmbus_clock_gating(display, true);

sys/dev/pci/drm/i915/display/intel_gmbus.c

902

struct intel_display *display = bus->display;

sys/dev/pci/drm/i915/display/intel_gmbus.c

906

wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS);

sys/dev/pci/drm/i915/display/intel_gmbus.c

918

intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref);

sys/dev/pci/drm/i915/display/intel_gmbus.c

926

struct intel_display *display = bus->display;

sys/dev/pci/drm/i915/display/intel_gmbus.c

946

wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS);

sys/dev/pci/drm/i915/display/intel_gmbus.c

947

mutex_lock(&display->gmbus.mutex);

sys/dev/pci/drm/i915/display/intel_gmbus.c

956

mutex_unlock(&display->gmbus.mutex);

sys/dev/pci/drm/i915/display/intel_gmbus.c

957

intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref);

sys/dev/pci/drm/i915/display/intel_gmbus.c

980

struct intel_display *display = bus->display;

sys/dev/pci/drm/i915/display/intel_gmbus.c

982

mutex_lock(&display->gmbus.mutex);

sys/dev/pci/drm/i915/display/intel_gmbus.c

989

struct intel_display *display = bus->display;

sys/dev/pci/drm/i915/display/intel_gmbus.c

991

return mutex_trylock(&display->gmbus.mutex);

sys/dev/pci/drm/i915/display/intel_gmbus.c

998

struct intel_display *display = bus->display;

sys/dev/pci/drm/i915/display/intel_gmbus.h

37

int intel_gmbus_setup(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_gmbus.h

38

void intel_gmbus_teardown(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_gmbus.h

39

bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin);

sys/dev/pci/drm/i915/display/intel_gmbus.h

43

intel_gmbus_get_adapter(struct intel_display *display, unsigned int pin);

sys/dev/pci/drm/i915/display/intel_gmbus.h

46

void intel_gmbus_reset(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_gmbus.h

48

void intel_gmbus_irq_handler(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1003

drm_dbg_kms(display->drm, "HDCP 1.4 transcoder: %s stream encryption disabled\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

1015

intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 0);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1016

if (intel_de_wait_for_clear(display,

sys/dev/pci/drm/i915/display/intel_hdcp.c

1017

HDCP_STATUS(display, cpu_transcoder, port),

sys/dev/pci/drm/i915/display/intel_hdcp.c

1019

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

1024

repeater_ctl = intel_hdcp_get_repeater_ctl(display, cpu_transcoder,

sys/dev/pci/drm/i915/display/intel_hdcp.c

1026

intel_de_rmw(display, HDCP_REP_CTL, repeater_ctl, 0);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1030

drm_err(display->drm, "Failed to disable HDCP signalling\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

1034

drm_dbg_kms(display->drm, "HDCP is disabled\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

1040

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1044

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP is being enabled...\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

1047

if (!hdcp_key_loadable(display)) {

sys/dev/pci/drm/i915/display/intel_hdcp.c

1048

drm_err(display->drm, "HDCP key Load is not possible\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

1053

ret = intel_hdcp_load_keys(display);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1056

intel_hdcp_clear_keys(display);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1059

drm_err(display->drm, "Could not load HDCP keys, (%d)\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

1074

drm_dbg_kms(display->drm, "HDCP Auth failure (%d)\n", ret);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1080

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

1093

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1097

drm_WARN_ON(display->drm, !mutex_is_locked(&hdcp->mutex));

sys/dev/pci/drm/i915/display/intel_hdcp.c

1102

drm_WARN_ON(display->drm, !mutex_is_locked(&dig_port->hdcp.mutex));

sys/dev/pci/drm/i915/display/intel_hdcp.c

1105

if (!drm_WARN_ON(display->drm, dig_port->hdcp.num_streams == 0))

sys/dev/pci/drm/i915/display/intel_hdcp.c

1114

if (!queue_work(display->wq.unordered, &hdcp->prop_work))

sys/dev/pci/drm/i915/display/intel_hdcp.c

1122

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1141

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

1142

!intel_hdcp_in_use(display, cpu_transcoder, port))) {

sys/dev/pci/drm/i915/display/intel_hdcp.c

1143

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

1146

intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)));

sys/dev/pci/drm/i915/display/intel_hdcp.c

115

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1162

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

1168

drm_err(display->drm, "Failed to disable hdcp (%d)\n", ret);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1177

drm_err(display->drm, "Failed to enable hdcp (%d)\n", ret);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1195

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1197

drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1210

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1215

bool is_hdcp_supported(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_hdcp.c

1217

return DISPLAY_RUNTIME_INFO(display)->has_hdcp &&

sys/dev/pci/drm/i915/display/intel_hdcp.c

1218

(DISPLAY_VER(display) >= 12 || port < PORT_E);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1225

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1231

mutex_lock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1232

arbiter = display->hdcp.arbiter;

sys/dev/pci/drm/i915/display/intel_hdcp.c

1235

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1241

drm_dbg_kms(display->drm, "Prepare_ake_init failed. %d\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

1243

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1255

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1261

mutex_lock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1262

arbiter = display->hdcp.arbiter;

sys/dev/pci/drm/i915/display/intel_hdcp.c

1265

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1273

drm_dbg_kms(display->drm, "Verify rx_cert failed. %d\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

1275

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1283

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1289

mutex_lock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1290

arbiter = display->hdcp.arbiter;

sys/dev/pci/drm/i915/display/intel_hdcp.c

1293

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1299

drm_dbg_kms(display->drm, "Verify hprime failed. %d\n", ret);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1300

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1309

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

131

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1315

mutex_lock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1316

arbiter = display->hdcp.arbiter;

sys/dev/pci/drm/i915/display/intel_hdcp.c

1319

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1325

drm_dbg_kms(display->drm, "Store pairing info failed. %d\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

1327

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1336

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1342

mutex_lock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1343

arbiter = display->hdcp.arbiter;

sys/dev/pci/drm/i915/display/intel_hdcp.c

1346

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1352

drm_dbg_kms(display->drm, "Prepare lc_init failed. %d\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

1354

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1363

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1369

mutex_lock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1370

arbiter = display->hdcp.arbiter;

sys/dev/pci/drm/i915/display/intel_hdcp.c

1373

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1379

drm_dbg_kms(display->drm, "Verify L_Prime failed. %d\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

1381

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1389

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1395

mutex_lock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1396

arbiter = display->hdcp.arbiter;

sys/dev/pci/drm/i915/display/intel_hdcp.c

1399

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1405

drm_dbg_kms(display->drm, "Get session key failed. %d\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

1407

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1418

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1424

mutex_lock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1425

arbiter = display->hdcp.arbiter;

sys/dev/pci/drm/i915/display/intel_hdcp.c

1428

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1437

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

1439

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1448

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1454

mutex_lock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1455

arbiter = display->hdcp.arbiter;

sys/dev/pci/drm/i915/display/intel_hdcp.c

1458

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1464

drm_dbg_kms(display->drm, "Verify mprime failed. %d\n", ret);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1465

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1472

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1478

mutex_lock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1479

arbiter = display->hdcp.arbiter;

sys/dev/pci/drm/i915/display/intel_hdcp.c

1482

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1488

drm_dbg_kms(display->drm, "Enable hdcp auth failed. %d\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

1490

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1497

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1502

mutex_lock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1503

arbiter = display->hdcp.arbiter;

sys/dev/pci/drm/i915/display/intel_hdcp.c

1506

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1512

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1525

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

153

if (drm_WARN_ON(display->drm, data->k > INTEL_NUM_PIPES(display) || data->k == 0))

sys/dev/pci/drm/i915/display/intel_hdcp.c

1588

drm_dbg_kms(display->drm, "cert.rx_caps dont claim HDCP2.2\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

1594

if (drm_hdcp_check_ksvs_revoked(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

1597

drm_err(display->drm, "Receiver ID is revoked\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

1748

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1769

drm_dbg_kms(display->drm, "Topology Max Size Exceeded\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

1782

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

1792

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

1799

drm_dbg_kms(display->drm, "Seq_num_v roll over.\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

1805

if (drm_hdcp_check_ksvs_revoked(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

1808

drm_err(display->drm, "Revoked receiver ID(s) is in list\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

1829

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1836

drm_dbg_kms(display->drm, "AKE Failed. Err : %d\n", ret);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1842

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

1849

drm_dbg_kms(display->drm, "SKE Failed. Err : %d\n", ret);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1864

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

1875

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1883

if (!(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &

sys/dev/pci/drm/i915/display/intel_hdcp.c

1885

drm_err(display->drm, "[CONNECTOR:%d:%s] HDCP 2.2 Link is not encrypted\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

1894

drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 2.2 stream enc\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

1898

drm_dbg_kms(display->drm, "HDCP 2.2 transcoder: %s stream encrypted\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

1906

drm_dbg_kms(display->drm, "Port deauth failed.\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

1916

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1923

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

1924

intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &

sys/dev/pci/drm/i915/display/intel_hdcp.c

1930

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

1937

if (intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &

sys/dev/pci/drm/i915/display/intel_hdcp.c

1940

intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port),

sys/dev/pci/drm/i915/display/intel_hdcp.c

1943

ret = intel_de_wait_for_set(display,

sys/dev/pci/drm/i915/display/intel_hdcp.c

1944

HDCP2_STATUS(display, cpu_transcoder,

sys/dev/pci/drm/i915/display/intel_hdcp.c

1955

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1962

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

1963

!(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &

sys/dev/pci/drm/i915/display/intel_hdcp.c

1966

intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port),

sys/dev/pci/drm/i915/display/intel_hdcp.c

1969

ret = intel_de_wait_for_clear(display,

sys/dev/pci/drm/i915/display/intel_hdcp.c

1970

HDCP2_STATUS(display, cpu_transcoder,

sys/dev/pci/drm/i915/display/intel_hdcp.c

1975

drm_dbg_kms(display->drm, "Disable Encryption Timedout");

sys/dev/pci/drm/i915/display/intel_hdcp.c

1981

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

1994

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2007

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

201

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2012

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

2023

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2032

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

2040

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

2049

drm_dbg_kms(display->drm, "HDCP2 port auth failed.(%d)\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

2054

drm_dbg_kms(display->drm, "HDCP2.2 Auth %d of %d Failed.(%d)\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

2057

drm_dbg_kms(display->drm, "Port deauth failed.\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

2068

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

2071

drm_dbg_kms(display->drm, "Port deauth failed.\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

2084

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2088

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being enabled. Type: %d\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

2096

drm_dbg_kms(display->drm, "HDCP2 Type%d Enabling Failed. (%d)\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

2101

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is enabled. Type %d\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

2112

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2118

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being Disabled\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

2124

drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 2.2 stream enc\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

2128

drm_dbg_kms(display->drm, "HDCP 2.2 transcoder: %s stream encryption disabled\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

213

drm_dbg_kms(display->drm, "Bksv is invalid\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

2138

drm_dbg_kms(display->drm, "Port deauth failed.\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

2150

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2168

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

2169

!intel_hdcp2_in_use(display, cpu_transcoder, port))) {

sys/dev/pci/drm/i915/display/intel_hdcp.c

2170

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

2172

intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)));

sys/dev/pci/drm/i915/display/intel_hdcp.c

2195

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

2206

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

2211

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

2218

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

2240

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2246

queue_delayed_work(display->wq.unordered, &hdcp->check_work,

sys/dev/pci/drm/i915/display/intel_hdcp.c

2249

queue_delayed_work(display->wq.unordered, &hdcp->check_work,

sys/dev/pci/drm/i915/display/intel_hdcp.c

2257

struct intel_display *display = to_intel_display(drv_kdev);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2259

drm_dbg(display->drm, "I915 HDCP comp bind\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

2260

mutex_lock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2261

display->hdcp.arbiter = (struct i915_hdcp_arbiter *)data;

sys/dev/pci/drm/i915/display/intel_hdcp.c

2262

display->hdcp.arbiter->hdcp_dev = mei_kdev;

sys/dev/pci/drm/i915/display/intel_hdcp.c

2263

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2271

struct intel_display *display = to_intel_display(drv_kdev);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2273

drm_dbg(display->drm, "I915 HDCP comp unbind\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

2274

mutex_lock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2275

display->hdcp.arbiter = NULL;

sys/dev/pci/drm/i915/display/intel_hdcp.c

2276

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2313

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2317

if (DISPLAY_VER(display) < 12)

sys/dev/pci/drm/i915/display/intel_hdcp.c

2337

data->streams = kcalloc(INTEL_NUM_PIPES(display),

sys/dev/pci/drm/i915/display/intel_hdcp.c

2341

drm_err(display->drm, "Out of Memory\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

2349

static bool is_hdcp2_supported(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hdcp.c

2351

if (USE_HDCP_GSC(display))

sys/dev/pci/drm/i915/display/intel_hdcp.c

2357

return DISPLAY_VER(display) >= 10 ||

sys/dev/pci/drm/i915/display/intel_hdcp.c

2358

display->platform.kabylake ||

sys/dev/pci/drm/i915/display/intel_hdcp.c

2359

display->platform.coffeelake ||

sys/dev/pci/drm/i915/display/intel_hdcp.c

2360

display->platform.cometlake;

sys/dev/pci/drm/i915/display/intel_hdcp.c

2363

void intel_hdcp_component_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hdcp.c

2367

if (!is_hdcp2_supported(display))

sys/dev/pci/drm/i915/display/intel_hdcp.c

2371

mutex_lock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2372

drm_WARN_ON(display->drm, display->hdcp.comp_added);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2374

display->hdcp.comp_added = true;

sys/dev/pci/drm/i915/display/intel_hdcp.c

2375

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2376

if (USE_HDCP_GSC(display))

sys/dev/pci/drm/i915/display/intel_hdcp.c

2377

ret = intel_hdcp_gsc_init(display);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2379

ret = component_add_typed(display->drm->dev, &i915_hdcp_ops,

sys/dev/pci/drm/i915/display/intel_hdcp.c

2383

drm_dbg_kms(display->drm, "Failed at fw component add(%d)\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

2385

mutex_lock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2386

display->hdcp.comp_added = false;

sys/dev/pci/drm/i915/display/intel_hdcp.c

2387

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2397

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2403

drm_dbg_kms(display->drm, "Mei hdcp data init failed\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

2414

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2421

if (is_hdcp2_supported(display))

sys/dev/pci/drm/i915/display/intel_hdcp.c

2449

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2462

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

2474

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_hdcp.c

2490

drm_dbg_kms(display->drm, "Forcing HDCP 1.4\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

2502

queue_delayed_work(display->wq.unordered, &hdcp->check_work,

sys/dev/pci/drm/i915/display/intel_hdcp.c

252

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2574

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

260

if (USE_HDCP_GSC(display)) {

sys/dev/pci/drm/i915/display/intel_hdcp.c

2601

if (!queue_work(display->wq.unordered, &hdcp->prop_work))

sys/dev/pci/drm/i915/display/intel_hdcp.c

261

if (!intel_hdcp_gsc_check_status(display->drm))

sys/dev/pci/drm/i915/display/intel_hdcp.c

2619

if (!queue_work(display->wq.unordered, &hdcp->prop_work))

sys/dev/pci/drm/i915/display/intel_hdcp.c

2638

void intel_hdcp_component_fini(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hdcp.c

2640

mutex_lock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2641

if (!display->hdcp.comp_added) {

sys/dev/pci/drm/i915/display/intel_hdcp.c

2642

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2646

display->hdcp.comp_added = false;

sys/dev/pci/drm/i915/display/intel_hdcp.c

2647

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2649

if (USE_HDCP_GSC(display))

sys/dev/pci/drm/i915/display/intel_hdcp.c

2650

intel_hdcp_gsc_fini(display);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2652

component_del(display->drm->dev, &i915_hdcp_ops);

sys/dev/pci/drm/i915/display/intel_hdcp.c

266

mutex_lock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

267

if (!display->hdcp.comp_added || !display->hdcp.arbiter) {

sys/dev/pci/drm/i915/display/intel_hdcp.c

268

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

271

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2742

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2750

queue_delayed_work(display->wq.unordered, &hdcp->check_work, 0);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2797

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2800

ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2815

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2847

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2856

ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2869

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp.c

307

static bool intel_hdcp_in_use(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hdcp.c

310

return intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_hdcp.c

311

HDCP_STATUS(display, cpu_transcoder, port)) &

sys/dev/pci/drm/i915/display/intel_hdcp.c

315

static bool intel_hdcp2_in_use(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hdcp.c

318

return intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_hdcp.c

319

HDCP2_STATUS(display, cpu_transcoder, port)) &

sys/dev/pci/drm/i915/display/intel_hdcp.c

341

static bool hdcp_key_loadable(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hdcp.c

350

if (display->platform.haswell || display->platform.broadwell)

sys/dev/pci/drm/i915/display/intel_hdcp.c

356

with_intel_display_rpm(display)

sys/dev/pci/drm/i915/display/intel_hdcp.c

357

enabled = intel_display_power_well_is_enabled(display, id);

sys/dev/pci/drm/i915/display/intel_hdcp.c

368

static void intel_hdcp_clear_keys(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hdcp.c

370

intel_de_write(display, HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER);

sys/dev/pci/drm/i915/display/intel_hdcp.c

371

intel_de_write(display, HDCP_KEY_STATUS,

sys/dev/pci/drm/i915/display/intel_hdcp.c

375

static int intel_hdcp_load_keys(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hdcp.c

380

val = intel_de_read(display, HDCP_KEY_STATUS);

sys/dev/pci/drm/i915/display/intel_hdcp.c

388

if (display->platform.haswell || display->platform.broadwell)

sys/dev/pci/drm/i915/display/intel_hdcp.c

389

if (!(intel_de_read(display, HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE))

sys/dev/pci/drm/i915/display/intel_hdcp.c

400

if (DISPLAY_VER(display) == 9 && !display->platform.broxton) {

sys/dev/pci/drm/i915/display/intel_hdcp.c

401

ret = intel_pcode_write(display->drm, SKL_PCODE_LOAD_HDCP_KEYS, 1);

sys/dev/pci/drm/i915/display/intel_hdcp.c

403

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

409

intel_de_write(display, HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER);

sys/dev/pci/drm/i915/display/intel_hdcp.c

413

ret = intel_de_wait_custom(display, HDCP_KEY_STATUS,

sys/dev/pci/drm/i915/display/intel_hdcp.c

422

intel_de_write(display, HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER);

sys/dev/pci/drm/i915/display/intel_hdcp.c

428

static int intel_write_sha_text(struct intel_display *display, u32 sha_text)

sys/dev/pci/drm/i915/display/intel_hdcp.c

430

intel_de_write(display, HDCP_SHA_TEXT, sha_text);

sys/dev/pci/drm/i915/display/intel_hdcp.c

431

if (intel_de_wait_for_set(display, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) {

sys/dev/pci/drm/i915/display/intel_hdcp.c

432

drm_err(display->drm, "Timed out waiting for SHA1 ready\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

439

u32 intel_hdcp_get_repeater_ctl(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hdcp.c

442

if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_hdcp.c

457

drm_err(display->drm, "Unknown transcoder %d\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

475

drm_err(display->drm, "Unknown port %d\n", port);

sys/dev/pci/drm/i915/display/intel_hdcp.c

485

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

49

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdcp.c

497

intel_de_write(display, HDCP_SHA_V_PRIME(i), vprime);

sys/dev/pci/drm/i915/display/intel_hdcp.c

513

rep_ctl = intel_hdcp_get_repeater_ctl(display, cpu_transcoder, port);

sys/dev/pci/drm/i915/display/intel_hdcp.c

514

intel_de_write(display, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);

sys/dev/pci/drm/i915/display/intel_hdcp.c

526

ret = intel_write_sha_text(display, sha_text);

sys/dev/pci/drm/i915/display/intel_hdcp.c

533

intel_de_write(display, HDCP_REP_CTL,

sys/dev/pci/drm/i915/display/intel_hdcp.c

550

ret = intel_write_sha_text(display, sha_text);

sys/dev/pci/drm/i915/display/intel_hdcp.c

566

intel_de_write(display, HDCP_REP_CTL,

sys/dev/pci/drm/i915/display/intel_hdcp.c

568

ret = intel_write_sha_text(display,

sys/dev/pci/drm/i915/display/intel_hdcp.c

57

if (DISPLAY_VER(display) >= 30) {

sys/dev/pci/drm/i915/display/intel_hdcp.c

575

intel_de_write(display, HDCP_REP_CTL,

sys/dev/pci/drm/i915/display/intel_hdcp.c

577

ret = intel_write_sha_text(display, 0);

sys/dev/pci/drm/i915/display/intel_hdcp.c

58

rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_hdcp.c

583

intel_de_write(display, HDCP_REP_CTL,

sys/dev/pci/drm/i915/display/intel_hdcp.c

585

ret = intel_write_sha_text(display, 0);

sys/dev/pci/drm/i915/display/intel_hdcp.c

592

intel_de_write(display, HDCP_REP_CTL,

sys/dev/pci/drm/i915/display/intel_hdcp.c

597

ret = intel_write_sha_text(display, sha_text);

sys/dev/pci/drm/i915/display/intel_hdcp.c

60

} else if (IS_DISPLAY_VERx100_STEP(display, 1401, STEP_B0, STEP_FOREVER) ||

sys/dev/pci/drm/i915/display/intel_hdcp.c

603

intel_de_write(display, HDCP_REP_CTL,

sys/dev/pci/drm/i915/display/intel_hdcp.c

605

ret = intel_write_sha_text(display, 0);

sys/dev/pci/drm/i915/display/intel_hdcp.c

61

IS_DISPLAY_VERx100_STEP(display, 2000, STEP_B0, STEP_FOREVER)) {

sys/dev/pci/drm/i915/display/intel_hdcp.c

611

intel_de_write(display, HDCP_REP_CTL,

sys/dev/pci/drm/i915/display/intel_hdcp.c

613

ret = intel_write_sha_text(display, 0);

sys/dev/pci/drm/i915/display/intel_hdcp.c

62

rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_hdcp.c

620

intel_de_write(display, HDCP_REP_CTL,

sys/dev/pci/drm/i915/display/intel_hdcp.c

623

ret = intel_write_sha_text(display, sha_text);

sys/dev/pci/drm/i915/display/intel_hdcp.c

629

intel_de_write(display, HDCP_REP_CTL,

sys/dev/pci/drm/i915/display/intel_hdcp.c

632

ret = intel_write_sha_text(display, 0);

sys/dev/pci/drm/i915/display/intel_hdcp.c

64

} else if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_D0, STEP_FOREVER)) {

sys/dev/pci/drm/i915/display/intel_hdcp.c

642

intel_de_write(display, HDCP_REP_CTL,

sys/dev/pci/drm/i915/display/intel_hdcp.c

645

ret = intel_write_sha_text(display, sha_text);

sys/dev/pci/drm/i915/display/intel_hdcp.c

65

rekey_reg = CHICKEN_TRANS(display, hdcp->cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_hdcp.c

651

intel_de_write(display, HDCP_REP_CTL,

sys/dev/pci/drm/i915/display/intel_hdcp.c

654

ret = intel_write_sha_text(display, sha_text);

sys/dev/pci/drm/i915/display/intel_hdcp.c

660

intel_de_write(display, HDCP_REP_CTL,

sys/dev/pci/drm/i915/display/intel_hdcp.c

662

ret = intel_write_sha_text(display, bstatus[1]);

sys/dev/pci/drm/i915/display/intel_hdcp.c

668

intel_de_write(display, HDCP_REP_CTL,

sys/dev/pci/drm/i915/display/intel_hdcp.c

670

ret = intel_write_sha_text(display, 0);

sys/dev/pci/drm/i915/display/intel_hdcp.c

676

intel_de_write(display, HDCP_REP_CTL,

sys/dev/pci/drm/i915/display/intel_hdcp.c

678

ret = intel_write_sha_text(display, 0);

sys/dev/pci/drm/i915/display/intel_hdcp.c

683

drm_dbg_kms(display->drm, "Invalid number of leftovers %d\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

688

intel_de_write(display, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);

sys/dev/pci/drm/i915/display/intel_hdcp.c

691

ret = intel_write_sha_text(display, 0);

sys/dev/pci/drm/i915/display/intel_hdcp.c

70

intel_de_rmw(display, rekey_reg, rekey_bit, enable ? 0 : rekey_bit);

sys/dev/pci/drm/i915/display/intel_hdcp.c

703

ret = intel_write_sha_text(display, sha_text);

sys/dev/pci/drm/i915/display/intel_hdcp.c

708

intel_de_write(display, HDCP_REP_CTL,

sys/dev/pci/drm/i915/display/intel_hdcp.c

710

if (intel_de_wait_for_set(display, HDCP_REP_CTL,

sys/dev/pci/drm/i915/display/intel_hdcp.c

712

drm_err(display->drm, "Timed out waiting for SHA1 complete\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

715

if (!(intel_de_read(display, HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) {

sys/dev/pci/drm/i915/display/intel_hdcp.c

716

drm_dbg_kms(display->drm, "SHA-1 mismatch, HDCP failed\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

727

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

735

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

746

drm_dbg_kms(display->drm, "Max Topology Limit Exceeded\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

759

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

766

drm_dbg_kms(display->drm, "Out of mem: ksv_fifo\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

774

if (drm_hdcp_check_ksvs_revoked(display->drm, ksv_fifo,

sys/dev/pci/drm/i915/display/intel_hdcp.c

776

drm_err(display->drm, "Revoked Ksv(s) in ksv_fifo\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

794

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

799

drm_dbg_kms(display->drm, "HDCP is enabled (%d downstream devices)\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

810

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

844

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

852

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_hdcp.c

853

HDCP_ANINIT(display, cpu_transcoder, port),

sys/dev/pci/drm/i915/display/intel_hdcp.c

855

intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port),

sys/dev/pci/drm/i915/display/intel_hdcp.c

859

if (intel_de_wait_for_set(display,

sys/dev/pci/drm/i915/display/intel_hdcp.c

860

HDCP_STATUS(display, cpu_transcoder, port),

sys/dev/pci/drm/i915/display/intel_hdcp.c

862

drm_err(display->drm, "Timed out waiting for An\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

866

an.reg[0] = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_hdcp.c

867

HDCP_ANLO(display, cpu_transcoder, port));

sys/dev/pci/drm/i915/display/intel_hdcp.c

868

an.reg[1] = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_hdcp.c

869

HDCP_ANHI(display, cpu_transcoder, port));

sys/dev/pci/drm/i915/display/intel_hdcp.c

882

if (drm_hdcp_check_ksvs_revoked(display->drm, bksv.shim, 1) > 0) {

sys/dev/pci/drm/i915/display/intel_hdcp.c

883

drm_err(display->drm, "BKSV is revoked\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

887

intel_de_write(display, HDCP_BKSVLO(display, cpu_transcoder, port),

sys/dev/pci/drm/i915/display/intel_hdcp.c

889

intel_de_write(display, HDCP_BKSVHI(display, cpu_transcoder, port),

sys/dev/pci/drm/i915/display/intel_hdcp.c

896

intel_de_write(display, HDCP_REP_CTL,

sys/dev/pci/drm/i915/display/intel_hdcp.c

897

intel_hdcp_get_repeater_ctl(display, cpu_transcoder, port));

sys/dev/pci/drm/i915/display/intel_hdcp.c

903

intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port),

sys/dev/pci/drm/i915/display/intel_hdcp.c

907

ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)),

sys/dev/pci/drm/i915/display/intel_hdcp.c

911

drm_err(display->drm, "Timed out waiting for R0 ready\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

937

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_hdcp.c

938

HDCP_RPRIME(display, cpu_transcoder, port),

sys/dev/pci/drm/i915/display/intel_hdcp.c

942

ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)),

sys/dev/pci/drm/i915/display/intel_hdcp.c

950

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdcp.c

956

if (intel_de_wait_for_set(display,

sys/dev/pci/drm/i915/display/intel_hdcp.c

957

HDCP_STATUS(display, cpu_transcoder, port),

sys/dev/pci/drm/i915/display/intel_hdcp.c

960

drm_err(display->drm, "Timed out waiting for encryption\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

968

drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 1.4 stream enc\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

972

drm_dbg_kms(display->drm, "HDCP 1.4 transcoder: %s stream encrypted\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

979

drm_dbg_kms(display->drm, "HDCP is enabled (no repeater present)\n");

sys/dev/pci/drm/i915/display/intel_hdcp.c

985

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdcp.c

993

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP is being disabled...\n",

sys/dev/pci/drm/i915/display/intel_hdcp.c

999

drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 1.4 stream enc\n",

sys/dev/pci/drm/i915/display/intel_hdcp.h

41

bool is_hdcp_supported(struct intel_display *display, enum port port);

sys/dev/pci/drm/i915/display/intel_hdcp.h

42

void intel_hdcp_component_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_hdcp.h

43

void intel_hdcp_component_fini(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

100

gsc_context = display->hdcp.gsc_context;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

121

drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed: %zd\n", byte);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

126

drm_dbg_kms(display->drm, "FW cmd 0x%08X Failed. Status: 0x%X\n",

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

158

struct intel_display *display;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

164

display = to_intel_display(dev);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

165

if (!display) {

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

169

gsc_context = display->hdcp.gsc_context;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

188

drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

193

drm_dbg_kms(display->drm, "FW cmd 0x%08X Failed. Status: 0x%X\n",

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

212

struct intel_display *display;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

218

display = to_intel_display(dev);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

219

if (!display) {

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

223

gsc_context = display->hdcp.gsc_context;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

243

drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

248

drm_dbg_kms(display->drm, "FW cmd 0x%08X failed. Status: 0x%X\n",

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

26

struct intel_display *display;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

269

struct intel_display *display;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

275

display = to_intel_display(dev);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

276

if (!display) {

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

280

gsc_context = display->hdcp.gsc_context;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

294

drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

299

drm_dbg_kms(display->drm, "FW cmd 0x%08X Failed. status: 0x%X\n",

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

32

display = to_intel_display(dev);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

321

struct intel_display *display;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

327

display = to_intel_display(dev);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

328

if (!display) {

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

33

if (!display) {

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

332

gsc_context = display->hdcp.gsc_context;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

352

drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

357

drm_dbg_kms(display->drm, "FW cmd 0x%08X failed. status: 0x%X\n",

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

37

gsc_context = display->hdcp.gsc_context;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

378

struct intel_display *display;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

384

display = to_intel_display(dev);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

385

if (!display) {

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

389

gsc_context = display->hdcp.gsc_context;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

403

drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

408

drm_dbg_kms(display->drm, "FW cmd 0x%08X failed. status: 0x%X\n",

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

436

struct intel_display *display;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

442

display = to_intel_display(dev);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

443

if (!display) {

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

447

gsc_context = display->hdcp.gsc_context;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

473

drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

478

drm_dbg_kms(display->drm, "FW cmd 0x%08X failed. status: 0x%X\n",

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

503

struct intel_display *display;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

510

display = to_intel_display(dev);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

511

if (!display) {

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

515

gsc_context = display->hdcp.gsc_context;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

547

drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

55

drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

552

drm_dbg_kms(display->drm, "FW cmd 0x%08X failed. status: 0x%X\n",

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

571

struct intel_display *display;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

577

display = to_intel_display(dev);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

578

if (!display) {

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

582

gsc_context = display->hdcp.gsc_context;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

599

drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

60

drm_dbg_kms(display->drm, "FW cmd 0x%08X Failed. Status: 0x%X\n",

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

604

drm_dbg_kms(display->drm, "FW cmd 0x%08X failed. status: 0x%X\n",

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

622

struct intel_display *display;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

628

display = to_intel_display(dev);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

629

if (!display) {

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

633

gsc_context = display->hdcp.gsc_context;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

650

drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

655

drm_dbg_kms(display->drm, "Session Close Failed. status: 0x%X\n",

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

680

int intel_hdcp_gsc_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

690

mutex_lock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

692

gsc_context = intel_hdcp_gsc_context_alloc(display->drm);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

699

display->hdcp.arbiter = arbiter;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

700

display->hdcp.arbiter->hdcp_dev = display->drm->dev;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

701

display->hdcp.arbiter->ops = &gsc_hdcp_ops;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

702

display->hdcp.gsc_context = gsc_context;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

705

mutex_unlock(&display->hdcp.hdcp_mutex);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

710

void intel_hdcp_gsc_fini(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

712

intel_hdcp_gsc_context_free(display->hdcp.gsc_context);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

713

display->hdcp.gsc_context = NULL;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

714

kfree(display->hdcp.arbiter);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

715

display->hdcp.arbiter = NULL;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

89

struct intel_display *display;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

95

display = to_intel_display(dev);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

96

if (!display) {

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.h

11

int intel_hdcp_gsc_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.h

12

void intel_hdcp_gsc_fini(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1000

intel_de_write(display, reg, crtc_state->infoframes.gcp);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1008

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1016

if (HAS_DDI(display))

sys/dev/pci/drm/i915/display/intel_hdmi.c

1017

reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1018

else if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1020

else if (HAS_PCH_SPLIT(display))

sys/dev/pci/drm/i915/display/intel_hdmi.c

1025

crtc_state->infoframes.gcp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1032

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1034

if (display->platform.g4x || !crtc_state->has_infoframe)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1055

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1060

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1074

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1075

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1080

drm_WARN(display->drm, val & VIDEO_DIP_ENABLE,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1095

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1096

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1114

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1118

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1131

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1132

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1144

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1145

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1163

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1167

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1181

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1182

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1187

drm_WARN(display->drm, val & VIDEO_DIP_ENABLE,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1202

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1203

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1220

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1221

i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1223

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1232

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1233

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1245

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1246

i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1248

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1250

assert_hdmi_transcoder_func_disabled(display,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1259

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1260

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1267

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1268

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1286

struct intel_display *display = to_intel_display(hdmi);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1292

drm_dbg_kms(display->drm, "%s DP dual mode adaptor TMDS output\n",

sys/dev/pci/drm/i915/display/intel_hdmi.c

1295

drm_dp_dual_mode_set_tmds_output(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1361

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1369

drm_dbg_kms(display->drm, "Write An over DDC failed (%d)\n",

sys/dev/pci/drm/i915/display/intel_hdmi.c

1376

drm_dbg_kms(display->drm, "Failed to output aksv (%d)\n", ret);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1385

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1391

drm_dbg_kms(display->drm, "Read Bksv over DDC failed (%d)\n",

sys/dev/pci/drm/i915/display/intel_hdmi.c

1400

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1406

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1416

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1422

drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n",

sys/dev/pci/drm/i915/display/intel_hdmi.c

1434

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1440

drm_dbg_kms(display->drm, "Read Ri' over DDC failed (%d)\n",

sys/dev/pci/drm/i915/display/intel_hdmi.c

1449

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1455

drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n",

sys/dev/pci/drm/i915/display/intel_hdmi.c

1467

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1472

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1483

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1492

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1501

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1508

scanline = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1509

PIPEDSL(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_hdmi.c

1518

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1526

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1539

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1551

drm_err(display->drm, "%s HDCP signalling failed (%d)\n",

sys/dev/pci/drm/i915/display/intel_hdmi.c

1560

if (display->platform.kabylake && enable)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1571

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1584

intel_de_write(display, HDCP_RPRIME(display, cpu_transcoder, port), ri.reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1587

ret = intel_de_wait_for_set(display, HDCP_STATUS(display, cpu_transcoder, port),

sys/dev/pci/drm/i915/display/intel_hdmi.c

1590

drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n",

sys/dev/pci/drm/i915/display/intel_hdmi.c

1591

intel_de_read(display, HDCP_STATUS(display, cpu_transcoder,

sys/dev/pci/drm/i915/display/intel_hdmi.c

164

hsw_dip_data_reg(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1658

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1664

drm_dbg_kms(display->drm, "rx_status read failed. Err %d\n",

sys/dev/pci/drm/i915/display/intel_hdmi.c

1685

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1699

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

171

return HSW_TVIDEO_DIP_GMP_DATA(display, cpu_transcoder, i);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1721

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdmi.c

173

return HSW_TVIDEO_DIP_VSC_DATA(display, cpu_transcoder, i);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1738

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1747

drm_dbg_kms(display->drm, "Failed to read msg_id: %d(%zd)\n",

sys/dev/pci/drm/i915/display/intel_hdmi.c

175

return ADL_TVIDEO_DIP_AS_SDP_DATA(display, cpu_transcoder, i);

sys/dev/pci/drm/i915/display/intel_hdmi.c

177

return ICL_VIDEO_DIP_PPS_DATA(display, cpu_transcoder, i);

sys/dev/pci/drm/i915/display/intel_hdmi.c

179

return HSW_TVIDEO_DIP_AVI_DATA(display, cpu_transcoder, i);

sys/dev/pci/drm/i915/display/intel_hdmi.c

181

return HSW_TVIDEO_DIP_SPD_DATA(display, cpu_transcoder, i);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1813

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1816

if (DISPLAY_VER(display) >= 13 || display->platform.alderlake_s)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1818

else if (DISPLAY_VER(display) >= 10)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1820

else if (DISPLAY_VER(display) >= 8 || display->platform.haswell)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1822

else if (DISPLAY_VER(display) >= 5)

sys/dev/pci/drm/i915/display/intel_hdmi.c

183

return HSW_TVIDEO_DIP_VS_DATA(display, cpu_transcoder, i);

sys/dev/pci/drm/i915/display/intel_hdmi.c

185

return GLK_TVIDEO_DIP_DRM_DATA(display, cpu_transcoder, i);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1878

struct intel_display *display = to_intel_display(hdmi);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1888

if (display->platform.geminilake && clock > 446666 && clock < 480000)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1892

if ((display->platform.geminilake || display->platform.broxton) &&

sys/dev/pci/drm/i915/display/intel_hdmi.c

1897

if (display->platform.cherryview && clock > 216000 && clock < 240000)

sys/dev/pci/drm/i915/display/intel_hdmi.c

192

static int hsw_dip_data_size(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1926

static bool intel_hdmi_source_bpc_possible(struct intel_display *display, int bpc)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1930

return !HAS_GMCH(display);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1932

return DISPLAY_VER(display) >= 11;

sys/dev/pci/drm/i915/display/intel_hdmi.c

1980

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1993

if (!intel_hdmi_source_bpc_possible(display, bpc))

sys/dev/pci/drm/i915/display/intel_hdmi.c

2006

drm_WARN_ON(display->drm, status == MODE_OK);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2016

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2020

int max_dotclk = display->cdclk.max_dotclk_freq;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2025

status = intel_cpu_transcoder_mode_valid(display, mode);

sys/dev/pci/drm/i915/display/intel_hdmi.c

203

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2057

status = intel_pfit_mode_valid(display, mode, sink_format, 0);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2075

return intel_mode_valid_max_plane_size(display, mode, 1);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2100

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2104

if (!intel_hdmi_source_bpc_possible(display, bpc))

sys/dev/pci/drm/i915/display/intel_hdmi.c

2109

bpc == 10 && DISPLAY_VER(display) == 11 &&

sys/dev/pci/drm/i915/display/intel_hdmi.c

2156

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

217

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2179

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

219

u32 val = intel_de_read(display, VIDEO_DIP_CTL);

sys/dev/pci/drm/i915/display/intel_hdmi.c

222

drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),

sys/dev/pci/drm/i915/display/intel_hdmi.c

2256

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2267

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

230

intel_de_write(display, VIDEO_DIP_CTL, val);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2328

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

233

intel_de_write(display, VIDEO_DIP_DATA, *data);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2364

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

238

intel_de_write(display, VIDEO_DIP_DATA, 0);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2401

drm_dbg_kms(display->drm, "bad AVI infoframe\n");

sys/dev/pci/drm/i915/display/intel_hdmi.c

2406

drm_dbg_kms(display->drm, "bad SPD infoframe\n");

sys/dev/pci/drm/i915/display/intel_hdmi.c

2411

drm_dbg_kms(display->drm, "bad HDMI infoframe\n");

sys/dev/pci/drm/i915/display/intel_hdmi.c

2416

drm_dbg_kms(display->drm, "bad DRM infoframe\n");

sys/dev/pci/drm/i915/display/intel_hdmi.c

244

intel_de_write(display, VIDEO_DIP_CTL, val);

sys/dev/pci/drm/i915/display/intel_hdmi.c

245

intel_de_posting_read(display, VIDEO_DIP_CTL);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2451

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2457

type = drm_dp_dual_mode_detect(display->drm, ddc);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2471

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

2484

drm_dp_dual_mode_max_tmds_clock(display->drm, type, ddc);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2486

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

2492

if ((DISPLAY_VER(display) >= 8 || display->platform.haswell) &&

sys/dev/pci/drm/i915/display/intel_hdmi.c

2494

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

2504

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2511

wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2516

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

253

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2534

intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2546

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2552

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",

sys/dev/pci/drm/i915/display/intel_hdmi.c

2555

if (!intel_display_device_enabled(display))

sys/dev/pci/drm/i915/display/intel_hdmi.c

2558

if (!intel_display_driver_check_access(display))

sys/dev/pci/drm/i915/display/intel_hdmi.c

2561

wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2563

if (DISPLAY_VER(display) >= 11 &&

sys/dev/pci/drm/i915/display/intel_hdmi.c

257

intel_de_rmw(display, VIDEO_DIP_CTL,

sys/dev/pci/drm/i915/display/intel_hdmi.c

2573

intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2585

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2587

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",

sys/dev/pci/drm/i915/display/intel_hdmi.c

2590

if (!intel_display_driver_check_access(display))

sys/dev/pci/drm/i915/display/intel_hdmi.c

261

*data++ = intel_de_read(display, VIDEO_DIP_DATA);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2649

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2651

if (HAS_DDI(display))

sys/dev/pci/drm/i915/display/intel_hdmi.c

2667

struct intel_display *display = to_intel_display(intel_hdmi);

sys/dev/pci/drm/i915/display/intel_hdmi.c

267

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2676

if (DISPLAY_VER(display) >= 10)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2679

if (!HAS_GMCH(display))

sys/dev/pci/drm/i915/display/intel_hdmi.c

268

u32 val = intel_de_read(display, VIDEO_DIP_CTL);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2707

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2714

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

2795

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2803

drm_WARN(display->drm, 1, "Unknown port:%c\n", port_name(port));

sys/dev/pci/drm/i915/display/intel_hdmi.c

2832

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2843

if (INTEL_PCH_TYPE(display) >= PCH_TGP && phy >= PHY_C)

sys/dev/pci/drm/i915/display/intel_hdmi.c

285

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2851

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2854

drm_WARN_ON(display->drm, encoder->port == PORT_A);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2862

if (INTEL_PCH_TYPE(display) >= PCH_TGP && phy >= PHY_C)

sys/dev/pci/drm/i915/display/intel_hdmi.c

289

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2914

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2917

if (display->platform.alderlake_s)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2919

else if (INTEL_PCH_TYPE(display) >= PCH_DG1)

sys/dev/pci/drm/i915/display/intel_hdmi.c

292

drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),

sys/dev/pci/drm/i915/display/intel_hdmi.c

2921

else if (display->platform.rocketlake)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2923

else if (DISPLAY_VER(display) == 9 && HAS_PCH_TGP(display))

sys/dev/pci/drm/i915/display/intel_hdmi.c

2925

else if ((display->platform.jasperlake || display->platform.elkhartlake) &&

sys/dev/pci/drm/i915/display/intel_hdmi.c

2926

HAS_PCH_TGP(display))

sys/dev/pci/drm/i915/display/intel_hdmi.c

2928

else if (INTEL_PCH_TYPE(display) >= PCH_ICP)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2930

else if (HAS_PCH_CNP(display))

sys/dev/pci/drm/i915/display/intel_hdmi.c

2932

else if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2934

else if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2945

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2948

for_each_intel_encoder(display->drm, other) {

sys/dev/pci/drm/i915/display/intel_hdmi.c

2959

if (connector && connector->base.ddc == intel_gmbus_get_adapter(display, ddc_pin))

sys/dev/pci/drm/i915/display/intel_hdmi.c

2968

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2981

if (!intel_gmbus_is_valid_pin(display, ddc_pin)) {

sys/dev/pci/drm/i915/display/intel_hdmi.c

2982

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

2990

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

2997

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

300

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_hdmi.c

3007

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_hdmi.c

3009

if (display->platform.valleyview || display->platform.cherryview) {

sys/dev/pci/drm/i915/display/intel_hdmi.c

3014

} else if (display->platform.g4x) {

sys/dev/pci/drm/i915/display/intel_hdmi.c

3019

} else if (HAS_DDI(display)) {

sys/dev/pci/drm/i915/display/intel_hdmi.c

303

intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_hdmi.c

3031

} else if (HAS_PCH_IBX(display)) {

sys/dev/pci/drm/i915/display/intel_hdmi.c

3047

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_hdmi.c

3056

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

3060

if (DISPLAY_VER(display) < 12 && drm_WARN_ON(dev, port == PORT_A))

sys/dev/pci/drm/i915/display/intel_hdmi.c

3076

intel_gmbus_get_adapter(display, ddc_pin));

sys/dev/pci/drm/i915/display/intel_hdmi.c

3080

if (DISPLAY_VER(display) < 12)

sys/dev/pci/drm/i915/display/intel_hdmi.c

3085

if (DISPLAY_VER(display) >= 10)

sys/dev/pci/drm/i915/display/intel_hdmi.c

309

intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0);

sys/dev/pci/drm/i915/display/intel_hdmi.c

3091

if (HAS_DDI(display))

sys/dev/pci/drm/i915/display/intel_hdmi.c

3101

if (is_hdcp_supported(display, port)) {

sys/dev/pci/drm/i915/display/intel_hdmi.c

3105

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

3115

drm_dbg_kms(display->drm, "CEC notifier get failed\n");

sys/dev/pci/drm/i915/display/intel_hdmi.c

315

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_hdmi.c

316

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

324

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

329

intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_hdmi.c

333

*data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_hdmi.c

339

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

342

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

360

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

364

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

367

drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),

sys/dev/pci/drm/i915/display/intel_hdmi.c

378

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_hdmi.c

381

intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_hdmi.c

387

intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0);

sys/dev/pci/drm/i915/display/intel_hdmi.c

393

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_hdmi.c

394

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

402

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

407

intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_hdmi.c

411

*data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_hdmi.c

417

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

419

u32 val = intel_de_read(display, TVIDEO_DIP_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_hdmi.c

434

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

438

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

441

drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),

sys/dev/pci/drm/i915/display/intel_hdmi.c

449

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_hdmi.c

452

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_hdmi.c

458

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_hdmi.c

465

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_hdmi.c

466

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

474

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

479

intel_de_rmw(display, VLV_TVIDEO_DIP_CTL(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_hdmi.c

483

*data++ = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_hdmi.c

490

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

492

u32 val = intel_de_read(display, VLV_TVIDEO_DIP_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_hdmi.c

510

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

513

i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

516

u32 val = intel_de_read(display, ctl_reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

518

data_size = hsw_dip_data_size(display, type);

sys/dev/pci/drm/i915/display/intel_hdmi.c

520

drm_WARN_ON(display->drm, len > data_size);

sys/dev/pci/drm/i915/display/intel_hdmi.c

523

intel_de_write(display, ctl_reg, val);

sys/dev/pci/drm/i915/display/intel_hdmi.c

526

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_hdmi.c

527

hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2),

sys/dev/pci/drm/i915/display/intel_hdmi.c

533

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_hdmi.c

534

hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2),

sys/dev/pci/drm/i915/display/intel_hdmi.c

538

if (!(IS_DISPLAY_VER(display, 13, 14) && crtc_state->has_psr &&

sys/dev/pci/drm/i915/display/intel_hdmi.c

545

intel_de_write(display, ctl_reg, val);

sys/dev/pci/drm/i915/display/intel_hdmi.c

546

intel_de_posting_read(display, ctl_reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

553

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

559

*data++ = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_hdmi.c

560

hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2));

sys/dev/pci/drm/i915/display/intel_hdmi.c

566

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

567

u32 val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_hdmi.c

568

HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_hdmi.c

575

if (DISPLAY_VER(display) >= 10)

sys/dev/pci/drm/i915/display/intel_hdmi.c

578

if (HAS_AS_SDP(display))

sys/dev/pci/drm/i915/display/intel_hdmi.c

610

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

621

if (HAS_DDI(display)) {

sys/dev/pci/drm/i915/display/intel_hdmi.c

74

struct intel_display *display = to_intel_display(intel_hdmi);

sys/dev/pci/drm/i915/display/intel_hdmi.c

77

enabled_bits = HAS_DDI(display) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;

sys/dev/pci/drm/i915/display/intel_hdmi.c

774

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_hdmi.c

784

if (display->platform.dgfx)

sys/dev/pci/drm/i915/display/intel_hdmi.c

79

drm_WARN(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

80

intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits,

sys/dev/pci/drm/i915/display/intel_hdmi.c

836

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

840

if (DISPLAY_VER(display) < 10)

sys/dev/pci/drm/i915/display/intel_hdmi.c

85

assert_hdmi_transcoder_func_disabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hdmi.c

854

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

860

if (drm_WARN_ON(display->drm, ret))

sys/dev/pci/drm/i915/display/intel_hdmi.c

871

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

875

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

88

drm_WARN(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

89

intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) &

sys/dev/pci/drm/i915/display/intel_hdmi.c

895

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

902

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_hdmi.c

903

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

909

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hdmi.c

922

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_hdmi.c

923

intel_de_posting_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

983

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

991

if (HAS_DDI(display))

sys/dev/pci/drm/i915/display/intel_hdmi.c

992

reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_hdmi.c

993

else if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_hdmi.c

995

else if (HAS_PCH_SPLIT(display))

sys/dev/pci/drm/i915/display/intel_hotplug.c

1001

blocked_hpd_pin_mask = get_blocked_hpd_pin_mask(display);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1006

switch (display->hotplug.stats[pin].state) {

sys/dev/pci/drm/i915/display/intel_hotplug.c

1014

MISSING_CASE(display->hotplug.stats[pin].state);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1022

queue_delayed_detection_work(display, &display->hotplug.hotplug_work, 0);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1025

static bool block_hpd_pin(struct intel_display *display, enum hpd_pin pin)

sys/dev/pci/drm/i915/display/intel_hotplug.c

1027

struct intel_hotplug *hotplug = &display->hotplug;

sys/dev/pci/drm/i915/display/intel_hotplug.c

1029

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1036

static bool unblock_hpd_pin(struct intel_display *display, enum hpd_pin pin)

sys/dev/pci/drm/i915/display/intel_hotplug.c

1038

struct intel_hotplug *hotplug = &display->hotplug;

sys/dev/pci/drm/i915/display/intel_hotplug.c

1040

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1042

if (drm_WARN_ON(display->drm, hotplug->stats[pin].blocked_count == 0))

sys/dev/pci/drm/i915/display/intel_hotplug.c

1076

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1077

struct intel_hotplug *hotplug = &display->hotplug;

sys/dev/pci/drm/i915/display/intel_hotplug.c

1083

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1085

if (block_hpd_pin(display, encoder->hpd_pin))

sys/dev/pci/drm/i915/display/intel_hotplug.c

1088

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1090

if (do_flush && hpd_pin_has_pulse(display, encoder->hpd_pin))

sys/dev/pci/drm/i915/display/intel_hotplug.c

1105

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1110

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1112

if (unblock_hpd_pin(display, encoder->hpd_pin))

sys/dev/pci/drm/i915/display/intel_hotplug.c

1113

queue_work_for_missed_irqs(display);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1115

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1128

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1129

struct intel_hotplug *hotplug = &display->hotplug;

sys/dev/pci/drm/i915/display/intel_hotplug.c

1135

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1137

if (unblock_hpd_pin(display, pin)) {

sys/dev/pci/drm/i915/display/intel_hotplug.c

1144

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1147

void intel_hpd_enable_detection_work(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug.c

1149

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1150

display->hotplug.detection_work_enabled = true;

sys/dev/pci/drm/i915/display/intel_hotplug.c

1151

queue_work_for_missed_irqs(display);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1152

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1155

void intel_hpd_disable_detection_work(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug.c

1157

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1158

display->hotplug.detection_work_enabled = false;

sys/dev/pci/drm/i915/display/intel_hotplug.c

1159

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1161

cancel_all_detection_work(display);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1164

bool intel_hpd_schedule_detection(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug.c

1169

spin_lock_irqsave(&display->irq.lock, flags);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1170

ret = queue_delayed_detection_work(display, &display->hotplug.hotplug_work, 0);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1171

spin_unlock_irqrestore(&display->irq.lock, flags);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1178

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/intel_hotplug.c

1179

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1180

struct intel_hotplug *hotplug = &display->hotplug;

sys/dev/pci/drm/i915/display/intel_hotplug.c

1186

flush_work(&display->hotplug.dig_port_work);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1187

flush_delayed_work(&display->hotplug.hotplug_work);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1203

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/intel_hotplug.c

1204

struct intel_hotplug *hotplug = &display->hotplug;

sys/dev/pci/drm/i915/display/intel_hotplug.c

1229

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hotplug.c

1233

drm_dbg_kms(display->drm, "Disabling HPD storm detection\n");

sys/dev/pci/drm/i915/display/intel_hotplug.c

1235

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1240

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1243

flush_delayed_work(&display->hotplug.reenable_work);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1264

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/intel_hotplug.c

1267

str_yes_no(display->hotplug.hpd_short_storm_enabled));

sys/dev/pci/drm/i915/display/intel_hotplug.c

1284

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/intel_hotplug.c

1285

struct intel_hotplug *hotplug = &display->hotplug;

sys/dev/pci/drm/i915/display/intel_hotplug.c

1306

new_state = !HAS_DP_MST(display);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1310

drm_dbg_kms(display->drm, "%sabling HPD short storm detection\n",

sys/dev/pci/drm/i915/display/intel_hotplug.c

1313

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1318

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1321

flush_delayed_work(&display->hotplug.reenable_work);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1337

void intel_hpd_debugfs_register(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug.c

1339

struct dentry *debugfs_root = display->drm->debugfs_root;

sys/dev/pci/drm/i915/display/intel_hotplug.c

1342

display, &i915_hpd_storm_ctl_fops);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1344

display, &i915_hpd_short_storm_ctl_fops);

sys/dev/pci/drm/i915/display/intel_hotplug.c

1346

&display->hotplug.ignore_long_hpd);

sys/dev/pci/drm/i915/display/intel_hotplug.c

152

static bool intel_hpd_irq_storm_detect(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hotplug.c

155

struct intel_hotplug *hpd = &display->hotplug;

sys/dev/pci/drm/i915/display/intel_hotplug.c

163

(!long_hpd && !display->hotplug.hpd_short_storm_enabled))

sys/dev/pci/drm/i915/display/intel_hotplug.c

174

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hotplug.c

178

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hotplug.c

187

static bool detection_work_enabled(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug.c

189

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

191

return display->hotplug.detection_work_enabled;

sys/dev/pci/drm/i915/display/intel_hotplug.c

195

mod_delayed_detection_work(struct intel_display *display, struct delayed_work *work, int delay)

sys/dev/pci/drm/i915/display/intel_hotplug.c

197

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

199

if (!detection_work_enabled(display))

sys/dev/pci/drm/i915/display/intel_hotplug.c

202

return mod_delayed_work(display->wq.unordered, work, delay);

sys/dev/pci/drm/i915/display/intel_hotplug.c

206

queue_delayed_detection_work(struct intel_display *display, struct delayed_work *work, int delay)

sys/dev/pci/drm/i915/display/intel_hotplug.c

208

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

210

if (!detection_work_enabled(display))

sys/dev/pci/drm/i915/display/intel_hotplug.c

213

return queue_delayed_work(display->wq.unordered, work, delay);

sys/dev/pci/drm/i915/display/intel_hotplug.c

217

queue_detection_work(struct intel_display *display, struct work_struct *work)

sys/dev/pci/drm/i915/display/intel_hotplug.c

219

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

221

if (!detection_work_enabled(display))

sys/dev/pci/drm/i915/display/intel_hotplug.c

224

return queue_work(display->wq.unordered, work);

sys/dev/pci/drm/i915/display/intel_hotplug.c

228

intel_hpd_irq_storm_switch_to_polling(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug.c

234

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

236

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_hotplug.c

245

display->hotplug.stats[pin].state != HPD_MARK_DISABLED)

sys/dev/pci/drm/i915/display/intel_hotplug.c

248

drm_info(display->drm,

sys/dev/pci/drm/i915/display/intel_hotplug.c

253

display->hotplug.stats[pin].state = HPD_DISABLED;

sys/dev/pci/drm/i915/display/intel_hotplug.c

262

drm_kms_helper_poll_reschedule(display->drm);

sys/dev/pci/drm/i915/display/intel_hotplug.c

263

mod_delayed_detection_work(display,

sys/dev/pci/drm/i915/display/intel_hotplug.c

264

&display->hotplug.reenable_work,

sys/dev/pci/drm/i915/display/intel_hotplug.c

271

struct intel_display *display =

sys/dev/pci/drm/i915/display/intel_hotplug.c

272

container_of(work, typeof(*display), hotplug.reenable_work.work);

sys/dev/pci/drm/i915/display/intel_hotplug.c

278

wakeref = intel_display_rpm_get(display);

sys/dev/pci/drm/i915/display/intel_hotplug.c

280

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

282

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_hotplug.c

286

display->hotplug.stats[pin].state != HPD_DISABLED)

sys/dev/pci/drm/i915/display/intel_hotplug.c

290

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_hotplug.c

298

if (display->hotplug.stats[pin].state == HPD_DISABLED)

sys/dev/pci/drm/i915/display/intel_hotplug.c

299

display->hotplug.stats[pin].state = HPD_ENABLED;

sys/dev/pci/drm/i915/display/intel_hotplug.c

302

intel_hpd_irq_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug.c

304

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

306

intel_display_rpm_put(display, wakeref);

sys/dev/pci/drm/i915/display/intel_hotplug.c

355

static bool hpd_pin_has_pulse(struct intel_display *display, enum hpd_pin pin)

sys/dev/pci/drm/i915/display/intel_hotplug.c

359

for_each_intel_encoder(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_hotplug.c

370

static bool hpd_pin_is_blocked(struct intel_display *display, enum hpd_pin pin)

sys/dev/pci/drm/i915/display/intel_hotplug.c

372

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

374

return display->hotplug.stats[pin].blocked_count;

sys/dev/pci/drm/i915/display/intel_hotplug.c

377

static u32 get_blocked_hpd_pin_mask(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug.c

383

if (hpd_pin_is_blocked(display, pin))

sys/dev/pci/drm/i915/display/intel_hotplug.c

392

struct intel_display *display =

sys/dev/pci/drm/i915/display/intel_hotplug.c

394

struct intel_hotplug *hotplug = &display->hotplug;

sys/dev/pci/drm/i915/display/intel_hotplug.c

400

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

402

blocked_hpd_pin_mask = get_blocked_hpd_pin_mask(display);

sys/dev/pci/drm/i915/display/intel_hotplug.c

408

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

410

for_each_intel_encoder(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_hotplug.c

435

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

436

display->hotplug.event_bits |= old_bits;

sys/dev/pci/drm/i915/display/intel_hotplug.c

437

queue_delayed_detection_work(display,

sys/dev/pci/drm/i915/display/intel_hotplug.c

438

&display->hotplug.hotplug_work, 0);

sys/dev/pci/drm/i915/display/intel_hotplug.c

439

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

452

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_hotplug.c

453

struct intel_hotplug *hotplug = &display->hotplug;

sys/dev/pci/drm/i915/display/intel_hotplug.c

456

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

459

if (!hpd_pin_is_blocked(display, encoder->hpd_pin))

sys/dev/pci/drm/i915/display/intel_hotplug.c

462

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

470

struct intel_display *display =

sys/dev/pci/drm/i915/display/intel_hotplug.c

472

struct intel_hotplug *hotplug = &display->hotplug;

sys/dev/pci/drm/i915/display/intel_hotplug.c

482

mutex_lock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/intel_hotplug.c

483

drm_dbg_kms(display->drm, "running encoder hotplug functions\n");

sys/dev/pci/drm/i915/display/intel_hotplug.c

485

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

487

blocked_hpd_pin_mask = get_blocked_hpd_pin_mask(display);

sys/dev/pci/drm/i915/display/intel_hotplug.c

494

intel_hpd_irq_storm_switch_to_polling(display);

sys/dev/pci/drm/i915/display/intel_hotplug.c

496

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

499

if (display->hotplug.ignore_long_hpd) {

sys/dev/pci/drm/i915/display/intel_hotplug.c

500

drm_dbg_kms(display->drm, "Ignore HPD flag on - skip encoder hotplug handlers\n");

sys/dev/pci/drm/i915/display/intel_hotplug.c

501

mutex_unlock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/intel_hotplug.c

505

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_hotplug.c

524

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hotplug.c

547

mutex_unlock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/intel_hotplug.c

552

drm_kms_helper_hotplug_event(display->drm);

sys/dev/pci/drm/i915/display/intel_hotplug.c

560

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

561

display->hotplug.retry_bits |= retry;

sys/dev/pci/drm/i915/display/intel_hotplug.c

563

mod_delayed_detection_work(display,

sys/dev/pci/drm/i915/display/intel_hotplug.c

564

&display->hotplug.hotplug_work,

sys/dev/pci/drm/i915/display/intel_hotplug.c

566

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

587

void intel_hpd_irq_handler(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hotplug.c

600

spin_lock(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

608

for_each_intel_encoder(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_hotplug.c

620

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_hotplug.c

625

if (!hpd_pin_is_blocked(display, pin))

sys/dev/pci/drm/i915/display/intel_hotplug.c

630

display->hotplug.long_hpd_pin_mask |= BIT(pin);

sys/dev/pci/drm/i915/display/intel_hotplug.c

633

display->hotplug.short_hpd_pin_mask |= BIT(pin);

sys/dev/pci/drm/i915/display/intel_hotplug.c

644

if (display->hotplug.stats[pin].state == HPD_DISABLED) {

sys/dev/pci/drm/i915/display/intel_hotplug.c

651

drm_WARN_ONCE(display->drm, !HAS_GMCH(display),

sys/dev/pci/drm/i915/display/intel_hotplug.c

657

if (display->hotplug.stats[pin].state != HPD_ENABLED)

sys/dev/pci/drm/i915/display/intel_hotplug.c

668

display->hotplug.event_bits |= BIT(pin);

sys/dev/pci/drm/i915/display/intel_hotplug.c

671

if (!hpd_pin_is_blocked(display, pin))

sys/dev/pci/drm/i915/display/intel_hotplug.c

675

if (intel_hpd_irq_storm_detect(display, pin, long_hpd)) {

sys/dev/pci/drm/i915/display/intel_hotplug.c

676

display->hotplug.event_bits &= ~BIT(pin);

sys/dev/pci/drm/i915/display/intel_hotplug.c

687

intel_hpd_irq_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug.c

696

queue_work(display->hotplug.dp_wq, &display->hotplug.dig_port_work);

sys/dev/pci/drm/i915/display/intel_hotplug.c

698

queue_delayed_detection_work(display,

sys/dev/pci/drm/i915/display/intel_hotplug.c

699

&display->hotplug.hotplug_work, 0);

sys/dev/pci/drm/i915/display/intel_hotplug.c

701

spin_unlock(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

718

void intel_hpd_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug.c

722

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_hotplug.c

726

display->hotplug.stats[i].count = 0;

sys/dev/pci/drm/i915/display/intel_hotplug.c

727

display->hotplug.stats[i].state = HPD_ENABLED;

sys/dev/pci/drm/i915/display/intel_hotplug.c

734

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

735

intel_hpd_irq_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug.c

736

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

739

static void i915_hpd_poll_detect_connectors(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug.c

746

mutex_lock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/intel_hotplug.c

748

if (!display->drm->mode_config.poll_enabled)

sys/dev/pci/drm/i915/display/intel_hotplug.c

751

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_hotplug.c

769

mutex_unlock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/intel_hotplug.c

777

drm_kms_helper_hotplug_event(display->drm);

sys/dev/pci/drm/i915/display/intel_hotplug.c

784

struct intel_display *display =

sys/dev/pci/drm/i915/display/intel_hotplug.c

785

container_of(work, typeof(*display), hotplug.poll_init_work);

sys/dev/pci/drm/i915/display/intel_hotplug.c

791

mutex_lock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/intel_hotplug.c

793

enabled = READ_ONCE(display->hotplug.poll_enabled);

sys/dev/pci/drm/i915/display/intel_hotplug.c

801

wakeref = intel_display_power_get(display,

sys/dev/pci/drm/i915/display/intel_hotplug.c

803

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_hotplug.c

804

READ_ONCE(display->hotplug.poll_enabled));

sys/dev/pci/drm/i915/display/intel_hotplug.c

805

cancel_work(&display->hotplug.poll_init_work);

sys/dev/pci/drm/i915/display/intel_hotplug.c

808

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

810

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_hotplug.c

818

if (display->hotplug.stats[pin].state == HPD_DISABLED)

sys/dev/pci/drm/i915/display/intel_hotplug.c

829

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

832

drm_kms_helper_poll_reschedule(display->drm);

sys/dev/pci/drm/i915/display/intel_hotplug.c

834

mutex_unlock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/intel_hotplug.c

841

i915_hpd_poll_detect_connectors(display);

sys/dev/pci/drm/i915/display/intel_hotplug.c

843

intel_display_power_put(display,

sys/dev/pci/drm/i915/display/intel_hotplug.c

865

void intel_hpd_poll_enable(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug.c

867

if (!HAS_DISPLAY(display) || !intel_display_device_enabled(display))

sys/dev/pci/drm/i915/display/intel_hotplug.c

870

WRITE_ONCE(display->hotplug.poll_enabled, true);

sys/dev/pci/drm/i915/display/intel_hotplug.c

878

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

879

queue_detection_work(display,

sys/dev/pci/drm/i915/display/intel_hotplug.c

880

&display->hotplug.poll_init_work);

sys/dev/pci/drm/i915/display/intel_hotplug.c

881

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

903

void intel_hpd_poll_disable(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug.c

907

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_hotplug.c

910

for_each_intel_dp(display->drm, encoder)

sys/dev/pci/drm/i915/display/intel_hotplug.c

913

WRITE_ONCE(display->hotplug.poll_enabled, false);

sys/dev/pci/drm/i915/display/intel_hotplug.c

915

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

916

queue_detection_work(display,

sys/dev/pci/drm/i915/display/intel_hotplug.c

917

&display->hotplug.poll_init_work);

sys/dev/pci/drm/i915/display/intel_hotplug.c

918

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

921

void intel_hpd_poll_fini(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug.c

927

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_hotplug.c

935

void intel_hpd_init_early(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug.c

937

INIT_DELAYED_WORK(&display->hotplug.hotplug_work,

sys/dev/pci/drm/i915/display/intel_hotplug.c

939

INIT_WORK(&display->hotplug.dig_port_work, i915_digport_work_func);

sys/dev/pci/drm/i915/display/intel_hotplug.c

940

INIT_WORK(&display->hotplug.poll_init_work, i915_hpd_poll_init_work);

sys/dev/pci/drm/i915/display/intel_hotplug.c

941

INIT_DELAYED_WORK(&display->hotplug.reenable_work,

sys/dev/pci/drm/i915/display/intel_hotplug.c

944

display->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;

sys/dev/pci/drm/i915/display/intel_hotplug.c

951

display->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(display);

sys/dev/pci/drm/i915/display/intel_hotplug.c

954

static bool cancel_all_detection_work(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug.c

958

if (cancel_delayed_work_sync(&display->hotplug.hotplug_work))

sys/dev/pci/drm/i915/display/intel_hotplug.c

960

if (cancel_work_sync(&display->hotplug.poll_init_work))

sys/dev/pci/drm/i915/display/intel_hotplug.c

962

if (cancel_delayed_work_sync(&display->hotplug.reenable_work))

sys/dev/pci/drm/i915/display/intel_hotplug.c

968

void intel_hpd_cancel_work(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug.c

970

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_hotplug.c

973

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

975

display->hotplug.long_hpd_pin_mask = 0;

sys/dev/pci/drm/i915/display/intel_hotplug.c

976

display->hotplug.short_hpd_pin_mask = 0;

sys/dev/pci/drm/i915/display/intel_hotplug.c

977

display->hotplug.event_bits = 0;

sys/dev/pci/drm/i915/display/intel_hotplug.c

978

display->hotplug.retry_bits = 0;

sys/dev/pci/drm/i915/display/intel_hotplug.c

980

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.c

982

cancel_work_sync(&display->hotplug.dig_port_work);

sys/dev/pci/drm/i915/display/intel_hotplug.c

988

if (cancel_all_detection_work(display))

sys/dev/pci/drm/i915/display/intel_hotplug.c

989

drm_dbg_kms(display->drm, "Hotplug detection work still active\n");

sys/dev/pci/drm/i915/display/intel_hotplug.c

992

static void queue_work_for_missed_irqs(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug.c

994

struct intel_hotplug *hotplug = &display->hotplug;

sys/dev/pci/drm/i915/display/intel_hotplug.c

999

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug.h

17

void intel_hpd_poll_enable(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_hotplug.h

18

void intel_hpd_poll_disable(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_hotplug.h

19

void intel_hpd_poll_fini(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_hotplug.h

22

void intel_hpd_irq_handler(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hotplug.h

25

void intel_hpd_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_hotplug.h

26

void intel_hpd_init_early(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_hotplug.h

27

void intel_hpd_cancel_work(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_hotplug.h

32

void intel_hpd_debugfs_register(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_hotplug.h

34

void intel_hpd_enable_detection_work(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_hotplug.h

35

void intel_hpd_disable_detection_work(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_hotplug.h

36

bool intel_hpd_schedule_detection(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1001

static void mtp_ddi_hpd_detection_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1003

intel_de_rmw(display, SHOTPLUG_CTL_DDI,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1004

intel_hpd_hotplug_mask(display, mtp_ddi_hotplug_mask),

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1005

intel_hpd_hotplug_enables(display, mtp_ddi_hotplug_enables));

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1010

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1012

intel_de_rmw(display, SHOTPLUG_CTL_DDI,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1017

static void mtp_tc_hpd_detection_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1019

intel_de_rmw(display, SHOTPLUG_CTL_TC,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1020

intel_hpd_hotplug_mask(display, mtp_tc_hotplug_mask),

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1021

intel_hpd_hotplug_enables(display, mtp_tc_hotplug_enables));

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1026

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1028

intel_de_rmw(display, SHOTPLUG_CTL_TC,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1033

static void mtp_hpd_invert(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1044

intel_de_rmw(display, SOUTH_CHICKEN1, 0, val);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1049

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1051

mtp_hpd_invert(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1056

static void mtp_hpd_irq_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1060

enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1061

hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1067

intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1069

mtp_hpd_invert(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1070

ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1072

mtp_ddi_hpd_detection_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1073

mtp_tc_hpd_detection_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1076

static void xe2lpd_sde_hpd_irq_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1080

enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1081

hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1083

ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1085

mtp_ddi_hpd_detection_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1086

mtp_tc_hpd_detection_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1094

static void _xelpdp_pica_hpd_detection_setup(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1103

intel_de_rmw(display, XELPDP_PORT_HOTPLUG_CTL(hpd_pin),

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1109

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1111

_xelpdp_pica_hpd_detection_setup(display, encoder->hpd_pin, true);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1114

static void xelpdp_pica_hpd_detection_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1122

for_each_intel_encoder(display->drm, encoder)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1126

_xelpdp_pica_hpd_detection_setup(display, pin, available_pins & BIT(pin));

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1135

static void xelpdp_hpd_irq_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1139

enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1140

hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1142

intel_de_rmw(display, PICAINTERRUPT_IMR, hotplug_irqs,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1144

intel_de_posting_read(display, PICAINTERRUPT_IMR);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1146

xelpdp_pica_hpd_detection_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1148

if (INTEL_PCH_TYPE(display) >= PCH_LNL)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1149

xe2lpd_sde_hpd_irq_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1150

else if (INTEL_PCH_TYPE(display) >= PCH_MTL)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1151

mtp_hpd_irq_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1190

static void spt_hpd_detection_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1193

if (HAS_PCH_CNP(display)) {

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1194

intel_de_rmw(display, SOUTH_CHICKEN1, CHASSIS_CLK_REQ_DURATION_MASK,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1199

intel_de_rmw(display, PCH_PORT_HOTPLUG,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1200

intel_hpd_hotplug_mask(display, spt_hotplug_mask),

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1201

intel_hpd_hotplug_enables(display, spt_hotplug_enables));

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1203

intel_de_rmw(display, PCH_PORT_HOTPLUG2,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1204

intel_hpd_hotplug_mask(display, spt_hotplug2_mask),

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1205

intel_hpd_hotplug_enables(display, spt_hotplug2_enables));

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1210

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1213

if (HAS_PCH_CNP(display)) {

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1214

intel_de_rmw(display, SOUTH_CHICKEN1,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1219

intel_de_rmw(display, PCH_PORT_HOTPLUG,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1223

intel_de_rmw(display, PCH_PORT_HOTPLUG2,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1228

static void spt_hpd_irq_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1232

if (INTEL_PCH_TYPE(display) >= PCH_CNP)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1233

intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1235

enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1236

hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1238

ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1240

spt_hpd_detection_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1265

static void ilk_hpd_detection_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1272

intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1273

intel_hpd_hotplug_mask(display, ilk_hotplug_mask),

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1274

intel_hpd_hotplug_enables(display, ilk_hotplug_enables));

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1279

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1281

intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1288

static void ilk_hpd_irq_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1292

enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1293

hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1295

if (DISPLAY_VER(display) >= 8)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1296

bdw_update_port_irq(display, hotplug_irqs, enabled_irqs);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1298

ilk_update_display_irq(display, hotplug_irqs, enabled_irqs);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1300

ilk_hpd_detection_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1302

ibx_hpd_irq_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1344

static void bxt_hpd_detection_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1346

intel_de_rmw(display, PCH_PORT_HOTPLUG,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1347

intel_hpd_hotplug_mask(display, bxt_hotplug_mask),

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1348

intel_hpd_hotplug_enables(display, bxt_hotplug_enables));

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1353

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1355

intel_de_rmw(display, PCH_PORT_HOTPLUG,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1360

static void bxt_hpd_irq_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1364

enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1365

hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1367

bdw_update_port_irq(display, hotplug_irqs, enabled_irqs);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1369

bxt_hpd_detection_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

137

static void intel_hpd_init_pins(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1372

static void g45_hpd_peg_band_gap_wa(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1379

intel_de_rmw(display, PEG_BAND_GAP_DATA, 0xf, 0xd);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1384

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1387

if (display->platform.g45)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1388

g45_hpd_peg_band_gap_wa(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

139

struct intel_hotplug *hpd = &display->hotplug;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1391

i915_hotplug_interrupt_update(display, hotplug_en, hotplug_en);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1394

static void i915_hpd_irq_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1398

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1404

hotplug_en = intel_hpd_enabled_irqs(display, hpd_mask_i915);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1409

if (display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

141

if (HAS_GMCH(display)) {

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1413

if (display->platform.g45)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1414

g45_hpd_peg_band_gap_wa(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1417

i915_hotplug_interrupt_update_locked(display,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

142

if (display->platform.g4x || display->platform.valleyview ||

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1426

void (*hpd_irq_setup)(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

143

display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1449

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1451

if (display->funcs.hotplug)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1452

display->funcs.hotplug->hpd_enable_detection(encoder);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1455

void intel_hpd_irq_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1457

if ((display->platform.valleyview || display->platform.cherryview) &&

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1458

!display->irq.vlv_display_irqs_enabled)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1461

if (display->funcs.hotplug)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1462

display->funcs.hotplug->hpd_irq_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1465

void intel_hotplug_irq_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1467

intel_hpd_init_pins(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1469

intel_hpd_init_early(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1471

if (HAS_GMCH(display)) {

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1472

if (HAS_HOTPLUG(display))

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1473

display->funcs.hotplug = &i915_hpd_funcs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1475

if (HAS_PCH_DG2(display))

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1476

display->funcs.hotplug = &icp_hpd_funcs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1477

else if (HAS_PCH_DG1(display))

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1478

display->funcs.hotplug = &dg1_hpd_funcs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1479

else if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1480

display->funcs.hotplug = &xelpdp_hpd_funcs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1481

else if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1482

display->funcs.hotplug = &gen11_hpd_funcs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1483

else if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1484

display->funcs.hotplug = &bxt_hpd_funcs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1485

else if (INTEL_PCH_TYPE(display) >= PCH_ICP)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1486

display->funcs.hotplug = &icp_hpd_funcs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1487

else if (INTEL_PCH_TYPE(display) >= PCH_SPT)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1488

display->funcs.hotplug = &spt_hpd_funcs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1490

display->funcs.hotplug = &ilk_hpd_funcs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

150

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

152

else if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

154

else if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

156

else if (DISPLAY_VER(display) == 9)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

158

else if (DISPLAY_VER(display) >= 8)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

160

else if (DISPLAY_VER(display) >= 7)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

165

if ((INTEL_PCH_TYPE(display) < PCH_DG1) &&

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

166

(!HAS_PCH_SPLIT(display) || HAS_PCH_NOP(display)))

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

169

if (INTEL_PCH_TYPE(display) >= PCH_MTL)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

171

else if (INTEL_PCH_TYPE(display) >= PCH_DG1)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

173

else if (INTEL_PCH_TYPE(display) >= PCH_ICP)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

175

else if (HAS_PCH_CNP(display) || HAS_PCH_SPT(display))

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

177

else if (HAS_PCH_LPT(display) || HAS_PCH_CPT(display))

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

179

else if (HAS_PCH_IBX(display))

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

182

MISSING_CASE(INTEL_PCH_TYPE(display));

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

186

void i915_hotplug_interrupt_update_locked(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

189

lockdep_assert_held(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

190

drm_WARN_ON(display->drm, bits & ~mask);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

192

intel_de_rmw(display, PORT_HOTPLUG_EN(display), mask, bits);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

207

void i915_hotplug_interrupt_update(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

211

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

212

i915_hotplug_interrupt_update_locked(display, mask, bits);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

213

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

344

static void intel_get_hpd_pins(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

364

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

369

static u32 intel_hpd_enabled_irqs(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

375

for_each_intel_encoder(display->drm, encoder)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

376

if (display->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

382

static u32 intel_hpd_hotplug_irqs(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

388

for_each_intel_encoder(display->drm, encoder)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

394

static u32 intel_hpd_hotplug_mask(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

406

static u32 intel_hpd_hotplug_enables(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

412

for_each_intel_encoder(display->drm, encoder)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

418

u32 i9xx_hpd_irq_ack(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

423

if (display->platform.g4x ||

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

424

display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

440

u32 tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

441

PORT_HOTPLUG_STAT(display)) & hotplug_status_mask;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

447

intel_de_write(display, PORT_HOTPLUG_STAT(display),

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

451

drm_WARN_ONCE(display->drm, 1,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

453

intel_de_read(display, PORT_HOTPLUG_STAT(display)));

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

458

void i9xx_hpd_irq_handler(struct intel_display *display, u32 hotplug_status)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

463

if (display->platform.g4x ||

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

464

display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

470

intel_get_hpd_pins(display, &pin_mask, &long_mask,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

472

display->hotplug.hpd,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

475

intel_hpd_irq_handler(display, pin_mask, long_mask);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

478

if ((display->platform.g4x ||

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

479

display->platform.valleyview || display->platform.cherryview) &&

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

481

intel_dp_aux_irq_handler(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

484

void ibx_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

494

dig_hotplug_reg = intel_de_read(display, PCH_PORT_HOTPLUG);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

503

intel_de_write(display, PCH_PORT_HOTPLUG, dig_hotplug_reg);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

507

intel_get_hpd_pins(display, &pin_mask, &long_mask,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

509

display->hotplug.pch_hpd,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

512

intel_hpd_irq_handler(display, pin_mask, long_mask);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

515

void xelpdp_pica_irq_handler(struct intel_display *display, u32 iir)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

522

if (DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

528

if (!(display->hotplug.hpd[pin] & hotplug_trigger))

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

533

val = intel_de_read(display, XELPDP_PORT_HOTPLUG_CTL(pin));

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

534

intel_de_write(display, XELPDP_PORT_HOTPLUG_CTL(pin), val);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

541

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

545

intel_hpd_irq_handler(display, pin_mask, long_mask);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

549

intel_dp_aux_irq_handler(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

552

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

556

void icp_irq_handler(struct intel_display *display, u32 pch_iir)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

566

spin_lock(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

567

dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_DDI, 0, 0);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

568

spin_unlock(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

570

intel_get_hpd_pins(display, &pin_mask, &long_mask,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

572

display->hotplug.pch_hpd,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

579

dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_TC, 0, 0);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

581

intel_get_hpd_pins(display, &pin_mask, &long_mask,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

583

display->hotplug.pch_hpd,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

588

intel_hpd_irq_handler(display, pin_mask, long_mask);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

591

intel_gmbus_irq_handler(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

594

void spt_irq_handler(struct intel_display *display, u32 pch_iir)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

604

dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG, 0, 0);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

606

intel_get_hpd_pins(display, &pin_mask, &long_mask,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

608

display->hotplug.pch_hpd,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

615

dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG2, 0, 0);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

617

intel_get_hpd_pins(display, &pin_mask, &long_mask,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

619

display->hotplug.pch_hpd,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

624

intel_hpd_irq_handler(display, pin_mask, long_mask);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

627

intel_gmbus_irq_handler(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

630

void ilk_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

634

dig_hotplug_reg = intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL, 0, 0);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

636

intel_get_hpd_pins(display, &pin_mask, &long_mask,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

638

display->hotplug.hpd,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

641

intel_hpd_irq_handler(display, pin_mask, long_mask);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

644

void bxt_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

648

dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG, 0, 0);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

650

intel_get_hpd_pins(display, &pin_mask, &long_mask,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

652

display->hotplug.hpd,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

655

intel_hpd_irq_handler(display, pin_mask, long_mask);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

658

void gen11_hpd_irq_handler(struct intel_display *display, u32 iir)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

667

dig_hotplug_reg = intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL, 0, 0);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

669

intel_get_hpd_pins(display, &pin_mask, &long_mask,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

671

display->hotplug.hpd,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

678

dig_hotplug_reg = intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL, 0, 0);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

680

intel_get_hpd_pins(display, &pin_mask, &long_mask,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

682

display->hotplug.hpd,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

687

intel_hpd_irq_handler(display, pin_mask, long_mask);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

689

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

711

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

719

return HAS_PCH_LPT_LP(display) ?

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

735

static void ibx_hpd_detection_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

742

intel_de_rmw(display, PCH_PORT_HOTPLUG,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

743

intel_hpd_hotplug_mask(display, ibx_hotplug_mask),

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

744

intel_hpd_hotplug_enables(display, ibx_hotplug_enables));

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

749

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

751

intel_de_rmw(display, PCH_PORT_HOTPLUG,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

756

static void ibx_hpd_irq_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

760

enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

761

hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

763

ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

765

ibx_hpd_detection_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

806

static void icp_ddi_hpd_detection_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

808

intel_de_rmw(display, SHOTPLUG_CTL_DDI,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

809

intel_hpd_hotplug_mask(display, icp_ddi_hotplug_mask),

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

810

intel_hpd_hotplug_enables(display, icp_ddi_hotplug_enables));

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

815

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

817

intel_de_rmw(display, SHOTPLUG_CTL_DDI,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

822

static void icp_tc_hpd_detection_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

824

intel_de_rmw(display, SHOTPLUG_CTL_TC,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

825

intel_hpd_hotplug_mask(display, icp_tc_hotplug_mask),

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

826

intel_hpd_hotplug_enables(display, icp_tc_hotplug_enables));

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

831

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

833

intel_de_rmw(display, SHOTPLUG_CTL_TC,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

844

static void icp_hpd_irq_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

848

enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

849

hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

855

intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

857

ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

859

icp_ddi_hpd_detection_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

860

icp_tc_hpd_detection_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

883

static void dg1_hpd_invert(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

889

intel_de_rmw(display, SOUTH_CHICKEN1, 0, val);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

894

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

896

dg1_hpd_invert(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

900

static void dg1_hpd_irq_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

902

dg1_hpd_invert(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

903

icp_hpd_irq_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

906

static void gen11_tc_hpd_detection_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

908

intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

909

intel_hpd_hotplug_mask(display, gen11_hotplug_mask),

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

910

intel_hpd_hotplug_enables(display, gen11_hotplug_enables));

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

915

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

917

intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

922

static void gen11_tbt_hpd_detection_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

924

intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

925

intel_hpd_hotplug_mask(display, gen11_hotplug_mask),

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

926

intel_hpd_hotplug_enables(display, gen11_hotplug_enables));

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

931

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

933

intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

940

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

945

if (INTEL_PCH_TYPE(display) >= PCH_ICP)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

949

static void gen11_hpd_irq_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

953

enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

954

hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

956

intel_de_rmw(display, GEN11_DE_HPD_IMR, hotplug_irqs,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

958

intel_de_posting_read(display, GEN11_DE_HPD_IMR);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

960

gen11_tc_hpd_detection_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

961

gen11_tbt_hpd_detection_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

963

if (INTEL_PCH_TYPE(display) >= PCH_ICP)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

964

icp_hpd_irq_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

14

u32 i9xx_hpd_irq_ack(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

16

void i9xx_hpd_irq_handler(struct intel_display *display, u32 hotplug_status);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

17

void ibx_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

18

void ilk_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

19

void gen11_hpd_irq_handler(struct intel_display *display, u32 iir);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

20

void bxt_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

21

void xelpdp_pica_irq_handler(struct intel_display *display, u32 iir);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

22

void icp_irq_handler(struct intel_display *display, u32 pch_iir);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

23

void spt_irq_handler(struct intel_display *display, u32 pch_iir);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

25

void i915_hotplug_interrupt_update_locked(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

27

void i915_hotplug_interrupt_update(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

31

void intel_hpd_irq_setup(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

33

void intel_hotplug_irq_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_hti.c

14

void intel_hti_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hti.c

20

if (DISPLAY_INFO(display)->has_hti)

sys/dev/pci/drm/i915/display/intel_hti.c

21

display->hti.state = intel_de_read(display, HDPORT_STATE);

sys/dev/pci/drm/i915/display/intel_hti.c

24

bool intel_hti_uses_phy(struct intel_display *display, enum phy phy)

sys/dev/pci/drm/i915/display/intel_hti.c

26

if (drm_WARN_ON(display->drm, phy == PHY_NONE))

sys/dev/pci/drm/i915/display/intel_hti.c

29

return display->hti.state & HDPORT_ENABLED &&

sys/dev/pci/drm/i915/display/intel_hti.c

30

display->hti.state & HDPORT_DDI_USED(phy);

sys/dev/pci/drm/i915/display/intel_hti.c

33

u32 intel_hti_dpll_mask(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_hti.c

35

if (!(display->hti.state & HDPORT_ENABLED))

sys/dev/pci/drm/i915/display/intel_hti.c

42

return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, display->hti.state);

sys/dev/pci/drm/i915/display/intel_hti.h

14

void intel_hti_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_hti.h

15

bool intel_hti_uses_phy(struct intel_display *display, enum phy phy);

sys/dev/pci/drm/i915/display/intel_hti.h

16

u32 intel_hti_dpll_mask(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_link_bw.c

105

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_link_bw.c

110

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {

sys/dev/pci/drm/i915/display/intel_link_bw.c

219

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_link_bw.c

228

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_link_bw.c

261

assert_link_limit_change_valid(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_link_bw.c

269

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_link_bw.c

274

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_link_bw.c

276

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_link_bw.c

287

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_link_bw.c

315

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_link_bw.c

323

if (!assert_link_limit_change_valid(display, &old_limits, new_limits))

sys/dev/pci/drm/i915/display/intel_link_bw.c

422

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_link_bw.c

429

return HAS_DSC_MST(display);

sys/dev/pci/drm/i915/display/intel_link_bw.c

431

return HAS_DSC(display);

sys/dev/pci/drm/i915/display/intel_link_bw.c

444

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_link_bw.c

461

bpp_x16 > fxp_q4_from_int(intel_display_max_pipe_bpp(display))))

sys/dev/pci/drm/i915/display/intel_link_bw.c

464

err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_link_bw.c

470

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_link_bw.c

482

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_link_bw.c

494

if (HAS_FDI(display))

sys/dev/pci/drm/i915/display/intel_link_bw.c

55

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_link_bw.c

60

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_link_bw.c

61

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_load_detect.c

114

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_load_detect.c

121

state = drm_atomic_state_alloc(display->drm);

sys/dev/pci/drm/i915/display/intel_load_detect.c

122

restore_state = drm_atomic_state_alloc(display->drm);

sys/dev/pci/drm/i915/display/intel_load_detect.c

167

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_load_detect.c

175

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_load_detect.c

207

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_load_detect.c

213

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",

sys/dev/pci/drm/i915/display/intel_load_detect.c

222

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_load_detect.c

52

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_load_detect.c

57

struct drm_mode_config *config = &display->drm->mode_config;

sys/dev/pci/drm/i915/display/intel_load_detect.c

63

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",

sys/dev/pci/drm/i915/display/intel_load_detect.c

67

drm_WARN_ON(display->drm, !drm_modeset_is_locked(&config->connection_mutex));

sys/dev/pci/drm/i915/display/intel_load_detect.c

92

for_each_intel_crtc(display->drm, possible_crtc) {

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

104

rsc[0].start = display->audio.lpe.irq;

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

105

rsc[0].end = display->audio.lpe.irq;

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

116

pinfo.parent = display->drm->dev;

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

125

pdata->num_pipes = INTEL_NUM_PIPES(display);

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

126

pdata->num_ports = display->platform.cherryview ? 3 : 2; /* B,C,D or B,C */

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

137

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

148

static void lpe_audio_platdev_destroy(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

159

platform_device_unregister(display->audio.lpe.platdev);

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

179

static int lpe_audio_irq_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

184

int irq = display->audio.lpe.irq;

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

194

static bool lpe_audio_detect(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

200

if (display->platform.valleyview || display->platform.cherryview) {

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

210

drm_info(display->drm,

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

219

static int lpe_audio_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

226

display->audio.lpe.irq = irq_alloc_desc(0);

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

227

if (display->audio.lpe.irq < 0) {

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

228

drm_err(display->drm, "Failed to allocate IRQ desc: %d\n",

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

229

display->audio.lpe.irq);

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

230

ret = display->audio.lpe.irq;

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

234

drm_dbg(display->drm, "irq = %d\n", display->audio.lpe.irq);

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

236

ret = lpe_audio_irq_init(display);

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

239

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

245

display->audio.lpe.platdev = lpe_audio_platdev_create(display);

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

247

if (IS_ERR(display->audio.lpe.platdev)) {

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

248

ret = PTR_ERR(display->audio.lpe.platdev);

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

249

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

258

intel_de_write(display, VLV_AUD_CHICKEN_BIT_REG,

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

263

irq_free_desc(display->audio.lpe.irq);

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

265

display->audio.lpe.irq = -1;

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

266

display->audio.lpe.platdev = NULL;

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

278

void intel_lpe_audio_irq_handler(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

284

if (!HAS_LPE_AUDIO(display))

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

287

ret = generic_handle_irq(display->audio.lpe.irq);

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

289

drm_err_ratelimited(display->drm,

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

302

int intel_lpe_audio_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

306

if (lpe_audio_detect(display)) {

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

307

ret = lpe_audio_setup(display);

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

309

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

322

void intel_lpe_audio_teardown(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

326

if (!HAS_LPE_AUDIO(display))

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

329

lpe_audio_platdev_destroy(display);

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

331

irq_free_desc(display->audio.lpe.irq);

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

333

display->audio.lpe.irq = -1;

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

334

display->audio.lpe.platdev = NULL;

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

350

void intel_lpe_audio_notify(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

360

if (!HAS_LPE_AUDIO(display))

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

363

pdata = dev_get_platdata(&display->audio.lpe.platdev->dev);

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

368

audio_enable = intel_de_read(display, VLV_AUD_PORT_EN_DBG(port));

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

377

intel_de_write(display, VLV_AUD_PORT_EN_DBG(port),

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

386

intel_de_write(display, VLV_AUD_PORT_EN_DBG(port),

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

391

pdata->notify_audio_lpe(display->audio.lpe.platdev, port - PORT_B);

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

80

#define HAS_LPE_AUDIO(display) ((display)->audio.lpe.platdev)

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

83

lpe_audio_platdev_create(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

88

struct pci_dev *pdev = to_pci_dev(display->drm->dev);

sys/dev/pci/drm/i915/display/intel_lpe_audio.h

16

int intel_lpe_audio_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_lpe_audio.h

17

void intel_lpe_audio_teardown(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_lpe_audio.h

18

void intel_lpe_audio_irq_handler(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_lpe_audio.h

19

void intel_lpe_audio_notify(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_lpe_audio.h

23

static inline int intel_lpe_audio_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_lpe_audio.h

27

static inline void intel_lpe_audio_teardown(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_lpe_audio.h

30

static inline void intel_lpe_audio_irq_handler(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_lpe_audio.h

33

static inline void intel_lpe_audio_notify(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_lspcon.c

108

drm_dbg_kms(display->drm, "Vendor: Mega Chips\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

113

drm_dbg_kms(display->drm, "Vendor: Parade Tech\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

117

drm_err(display->drm, "Invalid/Unknown vendor OUI\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

136

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_lspcon.c

144

drm_dbg_kms(display->drm, "HDR capability detection failed\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

147

drm_dbg_kms(display->drm, "LSPCON capable of HDR\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

157

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_lspcon.c

162

drm_dbg_kms(display->drm, "Error reading LSPCON mode\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

184

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_lspcon.c

193

drm_dbg_kms(display->drm, "Waiting for LSPCON mode %s to settle\n",

sys/dev/pci/drm/i915/display/intel_lspcon.c

202

drm_err(display->drm, "LSPCON mode hasn't settled\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

205

drm_dbg_kms(display->drm, "Current LSPCON mode %s\n",

sys/dev/pci/drm/i915/display/intel_lspcon.c

215

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_lspcon.c

222

drm_err(display->drm, "Error reading LSPCON mode\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

227

drm_dbg_kms(display->drm, "Current mode = desired LSPCON mode\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

234

drm_err(display->drm, "LSPCON mode change failed\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

239

drm_dbg_kms(display->drm, "LSPCON mode changed done\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

246

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_lspcon.c

251

drm_dbg_kms(display->drm, "Native AUX CH down\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

255

drm_dbg_kms(display->drm, "Native AUX CH up, DPCD version: %d.%d\n",

sys/dev/pci/drm/i915/display/intel_lspcon.c

264

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_lspcon.c

284

drm_dbg_kms(display->drm, "No LSPCON detected, found %s\n",

sys/dev/pci/drm/i915/display/intel_lspcon.c

290

drm_dbg_kms(display->drm, "LSPCON detected\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

300

drm_err(display->drm, "LSPCON mode change to PCON failed\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

310

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_lspcon.c

316

drm_dbg_kms(display->drm, "LSPCON recovering in PCON mode after %u ms\n",

sys/dev/pci/drm/i915/display/intel_lspcon.c

327

drm_dbg_kms(display->drm, "LSPCON DP descriptor mismatch after resume\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

498

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_lspcon.c

513

drm_dbg_kms(display->drm, "Update HDR metadata for lspcon\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

522

drm_err(display->drm, "Failed to write infoframes\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

543

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_lspcon.c

553

drm_err(display->drm, "Writing infoframes while LSPCON disabled ?\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

563

drm_err(display->drm, "couldn't fill AVI infoframe\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

604

drm_err(display->drm, "Failed to pack AVI IF\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

645

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_lspcon.c

661

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_lspcon.c

662

HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_lspcon.c

681

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_lspcon.c

690

drm_err(display->drm, "Failed to probe lspcon\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

695

drm_err(display->drm, "LSPCON DPCD read failed\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

700

drm_err(display->drm, "LSPCON vendor detection failed\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

706

drm_dbg_kms(display->drm, "Success: LSPCON init\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

727

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_lspcon.c

736

drm_err(display->drm, "LSPCON init failed on port %c\n",

sys/dev/pci/drm/i915/display/intel_lspcon.c

753

drm_err(display->drm, "LSPCON resume failed\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

755

drm_dbg_kms(display->drm, "LSPCON resume success\n");

sys/dev/pci/drm/i915/display/intel_lspcon.c

92

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_lspcon.c

97

drm_err(display->drm, "Can't read description\n");

sys/dev/pci/drm/i915/display/intel_lvds.c

1002

drm_dbg_kms(display->drm, "detected %s-link lvds configuration\n",

sys/dev/pci/drm/i915/display/intel_lvds.c

1010

drm_dbg_kms(display->drm, "No LVDS modes found, disabling.\n");

sys/dev/pci/drm/i915/display/intel_lvds.c

106

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_lvds.c

111

wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain);

sys/dev/pci/drm/i915/display/intel_lvds.c

115

ret = intel_lvds_port_enabled(display, lvds_encoder->reg, pipe);

sys/dev/pci/drm/i915/display/intel_lvds.c

117

intel_display_power_put(display, encoder->power_domain, wakeref);

sys/dev/pci/drm/i915/display/intel_lvds.c

125

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_lvds.c

131

tmp = intel_de_read(display, lvds_encoder->reg);

sys/dev/pci/drm/i915/display/intel_lvds.c

143

if (DISPLAY_VER(display) < 5)

sys/dev/pci/drm/i915/display/intel_lvds.c

148

if (DISPLAY_VER(display) < 4) {

sys/dev/pci/drm/i915/display/intel_lvds.c

149

tmp = intel_de_read(display, PFIT_CONTROL(display));

sys/dev/pci/drm/i915/display/intel_lvds.c

157

static void intel_lvds_pps_get_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_lvds.c

162

pps->powerdown_on_reset = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_lvds.c

163

PP_CONTROL(display, 0)) & PANEL_POWER_RESET;

sys/dev/pci/drm/i915/display/intel_lvds.c

165

val = intel_de_read(display, PP_ON_DELAYS(display, 0));

sys/dev/pci/drm/i915/display/intel_lvds.c

170

val = intel_de_read(display, PP_OFF_DELAYS(display, 0));

sys/dev/pci/drm/i915/display/intel_lvds.c

174

val = intel_de_read(display, PP_DIVISOR(display, 0));

sys/dev/pci/drm/i915/display/intel_lvds.c

187

if (DISPLAY_VER(display) < 5 &&

sys/dev/pci/drm/i915/display/intel_lvds.c

192

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_lvds.c

203

drm_dbg(display->drm, "LVDS PPS:power_up %d power_down %d power_cycle %d backlight_on %d backlight_off %d "

sys/dev/pci/drm/i915/display/intel_lvds.c

211

static void intel_lvds_pps_init_hw(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_lvds.c

216

val = intel_de_read(display, PP_CONTROL(display, 0));

sys/dev/pci/drm/i915/display/intel_lvds.c

217

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_lvds.c

221

intel_de_write(display, PP_CONTROL(display, 0), val);

sys/dev/pci/drm/i915/display/intel_lvds.c

223

intel_de_write(display, PP_ON_DELAYS(display, 0),

sys/dev/pci/drm/i915/display/intel_lvds.c

228

intel_de_write(display, PP_OFF_DELAYS(display, 0),

sys/dev/pci/drm/i915/display/intel_lvds.c

232

intel_de_write(display, PP_DIVISOR(display, 0),

sys/dev/pci/drm/i915/display/intel_lvds.c

243

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_lvds.c

250

if (HAS_PCH_SPLIT(display)) {

sys/dev/pci/drm/i915/display/intel_lvds.c

251

assert_fdi_rx_pll_disabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_lvds.c

252

assert_dpll_disabled(display, crtc_state->intel_dpll);

sys/dev/pci/drm/i915/display/intel_lvds.c

254

assert_pll_disabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_lvds.c

257

intel_lvds_pps_init_hw(display, &lvds_encoder->init_pps);

sys/dev/pci/drm/i915/display/intel_lvds.c

262

if (HAS_PCH_CPT(display)) {

sys/dev/pci/drm/i915/display/intel_lvds.c

297

if (DISPLAY_VER(display) == 4) {

sys/dev/pci/drm/i915/display/intel_lvds.c

313

intel_de_write(display, lvds_encoder->reg, temp);

sys/dev/pci/drm/i915/display/intel_lvds.c

324

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_lvds.c

327

intel_de_rmw(display, lvds_encoder->reg, 0, LVDS_PORT_EN);

sys/dev/pci/drm/i915/display/intel_lvds.c

329

intel_de_rmw(display, PP_CONTROL(display, 0), 0, PANEL_POWER_ON);

sys/dev/pci/drm/i915/display/intel_lvds.c

330

intel_de_posting_read(display, lvds_encoder->reg);

sys/dev/pci/drm/i915/display/intel_lvds.c

332

if (intel_de_wait_for_set(display, PP_STATUS(display, 0), PP_ON, 5000))

sys/dev/pci/drm/i915/display/intel_lvds.c

333

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_lvds.c

344

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_lvds.c

347

intel_de_rmw(display, PP_CONTROL(display, 0), PANEL_POWER_ON, 0);

sys/dev/pci/drm/i915/display/intel_lvds.c

348

if (intel_de_wait_for_clear(display, PP_STATUS(display, 0), PP_ON, 1000))

sys/dev/pci/drm/i915/display/intel_lvds.c

349

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_lvds.c

352

intel_de_rmw(display, lvds_encoder->reg, LVDS_PORT_EN, 0);

sys/dev/pci/drm/i915/display/intel_lvds.c

353

intel_de_posting_read(display, lvds_encoder->reg);

sys/dev/pci/drm/i915/display/intel_lvds.c

385

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_lvds.c

387

if (intel_de_wait_for_clear(display, PP_STATUS(display, 0), PP_CYCLE_DELAY_ACTIVE, 5000))

sys/dev/pci/drm/i915/display/intel_lvds.c

388

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_lvds.c

396

struct intel_display *display = to_intel_display(_connector->dev);

sys/dev/pci/drm/i915/display/intel_lvds.c

400

int max_pixclk = display->cdclk.max_dotclk_freq;

sys/dev/pci/drm/i915/display/intel_lvds.c

403

status = intel_cpu_transcoder_mode_valid(display, mode);

sys/dev/pci/drm/i915/display/intel_lvds.c

421

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_lvds.c

430

if (DISPLAY_VER(display) < 4 && crtc->pipe == 0) {

sys/dev/pci/drm/i915/display/intel_lvds.c

431

drm_err(display->drm, "Can't support LVDS on pipe A\n");

sys/dev/pci/drm/i915/display/intel_lvds.c

435

if (HAS_PCH_SPLIT(display)) {

sys/dev/pci/drm/i915/display/intel_lvds.c

448

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_lvds.c

776

struct intel_encoder *intel_get_lvds_encoder(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_lvds.c

780

for_each_intel_encoder(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_lvds.c

788

bool intel_is_dual_link_lvds(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_lvds.c

790

struct intel_encoder *encoder = intel_get_lvds_encoder(display);

sys/dev/pci/drm/i915/display/intel_lvds.c

797

struct intel_display *display = to_intel_display(&lvds_encoder->base);

sys/dev/pci/drm/i915/display/intel_lvds.c

804

if (display->params.lvds_channel_mode > 0)

sys/dev/pci/drm/i915/display/intel_lvds.c

805

return display->params.lvds_channel_mode == 2;

sys/dev/pci/drm/i915/display/intel_lvds.c

820

val = intel_de_read(display, lvds_encoder->reg);

sys/dev/pci/drm/i915/display/intel_lvds.c

821

if (HAS_PCH_CPT(display))

sys/dev/pci/drm/i915/display/intel_lvds.c

843

void intel_lvds_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_lvds.c

855

drm_WARN(display->drm, !display->vbt.int_lvds_support,

sys/dev/pci/drm/i915/display/intel_lvds.c

860

if (!display->vbt.int_lvds_support) {

sys/dev/pci/drm/i915/display/intel_lvds.c

861

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_lvds.c

866

if (HAS_PCH_SPLIT(display))

sys/dev/pci/drm/i915/display/intel_lvds.c

87

bool intel_lvds_port_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_lvds.c

871

lvds = intel_de_read(display, lvds_reg);

sys/dev/pci/drm/i915/display/intel_lvds.c

873

if (HAS_PCH_SPLIT(display)) {

sys/dev/pci/drm/i915/display/intel_lvds.c

879

if (!intel_bios_is_lvds_present(display, &ddc_pin)) {

sys/dev/pci/drm/i915/display/intel_lvds.c

881

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_lvds.c

885

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_lvds.c

902

drm_connector_init_with_ddc(display->drm, &connector->base,

sys/dev/pci/drm/i915/display/intel_lvds.c

905

intel_gmbus_get_adapter(display, ddc_pin));

sys/dev/pci/drm/i915/display/intel_lvds.c

907

drm_encoder_init(display->drm, &encoder->base, &intel_lvds_enc_funcs,

sys/dev/pci/drm/i915/display/intel_lvds.c

913

if (HAS_PCH_SPLIT(display)) {

sys/dev/pci/drm/i915/display/intel_lvds.c

92

val = intel_de_read(display, lvds_reg);

sys/dev/pci/drm/i915/display/intel_lvds.c

931

if (DISPLAY_VER(display) < 4)

sys/dev/pci/drm/i915/display/intel_lvds.c

943

intel_lvds_pps_get_hw_state(display, &lvds_encoder->init_pps);

sys/dev/pci/drm/i915/display/intel_lvds.c

95

if (HAS_PCH_CPT(display))

sys/dev/pci/drm/i915/display/intel_lvds.c

958

mutex_lock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/intel_lvds.c

973

intel_bios_init_panel_late(display, &connector->panel, NULL,

sys/dev/pci/drm/i915/display/intel_lvds.c

991

mutex_unlock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/intel_lvds.h

17

bool intel_lvds_port_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_lvds.h

19

void intel_lvds_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_lvds.h

20

struct intel_encoder *intel_get_lvds_encoder(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_lvds.h

21

bool intel_is_dual_link_lvds(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_lvds.h

23

static inline bool intel_lvds_port_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_lvds.h

28

static inline void intel_lvds_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_lvds.h

31

static inline struct intel_encoder *intel_get_lvds_encoder(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_lvds.h

35

static inline bool intel_is_dual_link_lvds(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

1002

intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

1004

intel_power_domains_sanitize_state(display);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

123

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

125

to_intel_pmdemand_state(display->pmdemand.obj.state);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

129

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

135

intel_pmdemand_update_phys_mask(display, encoder,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

148

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

151

for_each_encoder_on_crtc(display->drm, &crtc->base, encoder) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

159

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

161

to_intel_pmdemand_state(display->pmdemand.obj.state);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

173

intel_update_watermarks(display);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

175

intel_display_power_put_all_in_set(display, &crtc->enabled_power_domains);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

181

intel_pmdemand_update_port_clock(display, pmdemand_state, pipe, 0);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

188

static u8 get_transcoder_pipes(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

194

for_each_intel_crtc(display->drm, temp_crtc) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

218

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

237

*master_pipe_mask = get_transcoder_pipes(display, BIT(master_transcoder));

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

238

drm_WARN_ON(display->drm, !is_power_of_2(*master_pipe_mask));

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

240

master_crtc = intel_crtc_for_pipe(display, ffs(*master_pipe_mask) - 1);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

242

*slave_pipes_mask = get_transcoder_pipes(display, master_crtc_state->sync_mode_slaves_mask);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

245

static u8 get_joiner_secondary_pipes(struct intel_display *display, u8 primary_pipes_mask)

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

250

for_each_intel_crtc_in_pipe_mask(display->drm, primary_crtc, primary_pipes_mask) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

263

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

271

joiner_secondaries_mask = get_joiner_secondary_pipes(display,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

275

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

280

for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc, joiner_secondaries_mask)

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

283

for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc, portsync_slaves_mask)

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

286

for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc, portsync_master_mask)

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

289

for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

296

static void intel_modeset_update_connector_atomic_state(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

301

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

323

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

336

if (DISPLAY_INFO(display)->color.degamma_lut_size) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

351

drm_WARN_ON(display->drm, crtc_state->post_csc_lut &&

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

370

intel_sanitize_plane_mapping(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

374

if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

377

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

389

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

393

plane_crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

426

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

43

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

431

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

445

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

461

intel_init_fifo_underrun_reporting(display, crtc,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

463

!HAS_GMCH(display));

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

469

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

477

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

518

static void intel_sanitize_all_crtcs(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

533

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

54

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

546

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

556

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

568

return display->platform.sandybridge &&

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

576

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

582

to_intel_pmdemand_state(display->pmdemand.obj.state);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

593

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

601

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

607

intel_pmdemand_update_phys_mask(display, encoder,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

618

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

62

state = drm_atomic_state_alloc(display->drm);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

64

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

652

if (HAS_DDI(display))

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

657

static void readout_plane_state(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

662

for_each_intel_plane(display->drm, plane) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

671

crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

676

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

682

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

690

static void intel_modeset_readout_hw_state(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

693

to_intel_pmdemand_state(display->pmdemand.obj.state);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

700

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

715

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

721

readout_plane_state(display);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

723

for_each_intel_encoder(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

729

crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

74

for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

742

for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

751

intel_pmdemand_update_phys_mask(display, encoder,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

755

intel_pmdemand_update_phys_mask(display, encoder,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

765

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

772

intel_dpll_readout_hw_state(display);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

774

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

808

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

815

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

83

drm_WARN_ON(display->drm, IS_ERR(temp_crtc_state) || ret);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

838

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

854

if (crtc_state->double_wide || DISPLAY_VER(display) >= 10)

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

86

display->funcs.display->crtc_disable(to_intel_atomic_state(state), crtc);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

861

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

867

intel_pmdemand_update_port_clock(display, pmdemand_state, pipe,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

872

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

873

intel_wm_get_hw_state(display);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

875

intel_bw_update_hw_state(display);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

876

intel_cdclk_update_hw_state(display);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

878

intel_pmdemand_init_pmdemand_params(display, pmdemand_state);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

882

get_encoder_power_domains(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

886

for_each_intel_encoder(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

90

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

904

static void intel_early_display_was(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

910

if (IS_DISPLAY_VER(display, 10, 12))

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

911

intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, DARBF_GATING_DIS);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

917

if (display->platform.haswell)

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

918

intel_de_rmw(display, CHICKEN_PAR1_1, 0, FORCE_ARB_IDLE_PLANES);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

920

if (display->platform.kabylake || display->platform.coffeelake ||

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

921

display->platform.cometlake) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

923

intel_de_rmw(display, CHICKEN_PAR1_1,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

925

intel_de_rmw(display, CHICKEN_MISC_2,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

931

void intel_modeset_setup_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

938

wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

940

intel_early_display_was(display);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

941

intel_vga_disable(display);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

943

intel_modeset_readout_hw_state(display);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

946

get_encoder_power_domains(display);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

948

intel_pch_sanitize(display);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

950

intel_cmtg_sanitize(display);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

956

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

970

intel_fbc_sanitize(display);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

972

intel_sanitize_plane_mapping(display);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

974

for_each_intel_encoder(display->drm, encoder)

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

981

intel_modeset_update_connector_atomic_state(display);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

983

intel_sanitize_all_crtcs(display, ctx);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

985

intel_dpll_sanitize_state(display);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

988

if (DISPLAY_VER(display) < 9)

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

989

intel_wm_get_hw_state(display);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

990

intel_wm_sanitize(display);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

992

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

998

if (drm_WARN_ON(display->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))

sys/dev/pci/drm/i915/display/intel_modeset_setup.h

12

void intel_modeset_setup_hw_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

105

drm_WARN(display->drm, abs(fdi_dotclock - dotclock) > 1,

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

114

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

120

for_each_intel_encoder(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

124

drm_dbg_kms(display->drm, "[ENCODER:%d:%s]\n",

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

139

INTEL_DISPLAY_STATE_WARN(display,

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

147

INTEL_DISPLAY_STATE_WARN(display, !!encoder->base.crtc != enabled,

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

155

INTEL_DISPLAY_STATE_WARN(display, active,

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

166

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

177

drm_dbg_kms(display->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

185

if (display->platform.i830 && hw_crtc_state->hw.active)

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

188

INTEL_DISPLAY_STATE_WARN(display,

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

193

INTEL_DISPLAY_STATE_WARN(display, crtc->active != sw_crtc_state->hw.active,

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

199

for_each_encoder_on_crtc(display->drm, &primary_crtc->base, encoder) {

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

204

INTEL_DISPLAY_STATE_WARN(display, active != sw_crtc_state->hw.active,

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

209

INTEL_DISPLAY_STATE_WARN(display, active && primary_crtc->pipe != pipe,

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

224

INTEL_DISPLAY_STATE_WARN(display, 1, "pipe state doesn't match!\n");

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

31

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

33

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

39

INTEL_DISPLAY_STATE_WARN(display, !crtc_state,

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

45

INTEL_DISPLAY_STATE_WARN(display, !crtc_state->hw.active,

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

51

INTEL_DISPLAY_STATE_WARN(display,

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

55

INTEL_DISPLAY_STATE_WARN(display, conn_state->crtc != encoder->base.crtc,

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

58

INTEL_DISPLAY_STATE_WARN(display, crtc_state && crtc_state->hw.active,

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

60

INTEL_DISPLAY_STATE_WARN(display, !crtc_state && conn_state->best_encoder,

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

69

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

86

INTEL_DISPLAY_STATE_WARN(display, new_conn_state->best_encoder != encoder,

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

93

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

96

int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(display, crtc_state),

sys/dev/pci/drm/i915/display/intel_opregion.c

1003

drm_WARN_ON(display->drm, rvda < OPREGION_SIZE);

sys/dev/pci/drm/i915/display/intel_opregion.c

1022

if (intel_bios_is_valid_vbt(display, vbt, vbt_size)) {

sys/dev/pci/drm/i915/display/intel_opregion.c

1023

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_opregion.c

1029

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_opregion.c

1052

if (intel_bios_is_valid_vbt(display, vbt, vbt_size)) {

sys/dev/pci/drm/i915/display/intel_opregion.c

1053

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_opregion.c

1058

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_opregion.c

1073

display->opregion = NULL;

sys/dev/pci/drm/i915/display/intel_opregion.c

1096

intel_opregion_get_panel_type(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.c

1101

ret = swsci(display, SWSCI_GBDA_PANEL_DETAILS, 0x0, &panel_details);

sys/dev/pci/drm/i915/display/intel_opregion.c

1107

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_opregion.c

1114

drm_dbg_kms(display->drm, "No panel type in OpRegion\n");

sys/dev/pci/drm/i915/display/intel_opregion.c

1124

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_opregion.c

1145

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_opregion.c

1146

struct intel_opregion *opregion = display->opregion;

sys/dev/pci/drm/i915/display/intel_opregion.c

1164

drm_dbg_kms(display->drm, "Invalid EDID in ACPI OpRegion (Mailbox #5)\n");

sys/dev/pci/drm/i915/display/intel_opregion.c

1172

bool intel_opregion_vbt_present(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.c

1174

struct intel_opregion *opregion = display->opregion;

sys/dev/pci/drm/i915/display/intel_opregion.c

1182

const void *intel_opregion_get_vbt(struct intel_display *display, size_t *size)

sys/dev/pci/drm/i915/display/intel_opregion.c

1184

struct intel_opregion *opregion = display->opregion;

sys/dev/pci/drm/i915/display/intel_opregion.c

1195

bool intel_opregion_headless_sku(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.c

1197

struct intel_opregion *opregion = display->opregion;

sys/dev/pci/drm/i915/display/intel_opregion.c

1212

void intel_opregion_register(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.c

1214

struct intel_opregion *opregion = display->opregion;

sys/dev/pci/drm/i915/display/intel_opregion.c

1227

intel_opregion_resume(display);

sys/dev/pci/drm/i915/display/intel_opregion.c

1230

static void intel_opregion_resume_display(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.c

1232

struct intel_opregion *opregion = display->opregion;

sys/dev/pci/drm/i915/display/intel_opregion.c

1236

intel_didl_outputs(display);

sys/dev/pci/drm/i915/display/intel_opregion.c

1237

intel_setup_cadls(display);

sys/dev/pci/drm/i915/display/intel_opregion.c

1255

intel_dsm_get_bios_data_funcs_supported(display);

sys/dev/pci/drm/i915/display/intel_opregion.c

1258

void intel_opregion_resume(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.c

1260

struct intel_opregion *opregion = display->opregion;

sys/dev/pci/drm/i915/display/intel_opregion.c

1265

if (HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_opregion.c

1266

intel_opregion_resume_display(display);

sys/dev/pci/drm/i915/display/intel_opregion.c

1268

intel_opregion_notify_adapter(display, PCI_D0);

sys/dev/pci/drm/i915/display/intel_opregion.c

1271

static void intel_opregion_suspend_display(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.c

1273

struct intel_opregion *opregion = display->opregion;

sys/dev/pci/drm/i915/display/intel_opregion.c

1284

void intel_opregion_suspend(struct intel_display *display, pci_power_t state)

sys/dev/pci/drm/i915/display/intel_opregion.c

1286

struct intel_opregion *opregion = display->opregion;

sys/dev/pci/drm/i915/display/intel_opregion.c

1291

intel_opregion_notify_adapter(display, state);

sys/dev/pci/drm/i915/display/intel_opregion.c

1293

if (HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_opregion.c

1294

intel_opregion_suspend_display(display);

sys/dev/pci/drm/i915/display/intel_opregion.c

1297

void intel_opregion_unregister(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.c

1299

struct intel_opregion *opregion = display->opregion;

sys/dev/pci/drm/i915/display/intel_opregion.c

1301

intel_opregion_suspend(display, PCI_D1);

sys/dev/pci/drm/i915/display/intel_opregion.c

1312

void intel_opregion_cleanup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.c

1314

struct intel_opregion *opregion = display->opregion;

sys/dev/pci/drm/i915/display/intel_opregion.c

1315

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_opregion.c

1331

display->opregion = NULL;

sys/dev/pci/drm/i915/display/intel_opregion.c

1336

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/intel_opregion.c

1337

struct intel_opregion *opregion = display->opregion;

sys/dev/pci/drm/i915/display/intel_opregion.c

1347

void intel_opregion_debugfs_register(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.c

1349

debugfs_create_file("i915_opregion", 0444, display->drm->debugfs_root,

sys/dev/pci/drm/i915/display/intel_opregion.c

1350

display, &intel_opregion_fops);

sys/dev/pci/drm/i915/display/intel_opregion.c

260

struct intel_display *display;

sys/dev/pci/drm/i915/display/intel_opregion.c

276

static int check_swsci_function(struct intel_display *display, u32 function)

sys/dev/pci/drm/i915/display/intel_opregion.c

278

struct intel_opregion *opregion = display->opregion;

sys/dev/pci/drm/i915/display/intel_opregion.c

308

static int swsci(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_opregion.c

312

struct pci_dev *pdev = display->drm->pdev;

sys/dev/pci/drm/i915/display/intel_opregion.c

317

ret = check_swsci_function(display, function);

sys/dev/pci/drm/i915/display/intel_opregion.c

321

swsci = display->opregion->swsci;

sys/dev/pci/drm/i915/display/intel_opregion.c

339

drm_dbg(display->drm, "SWSCI request already in progress\n");

sys/dev/pci/drm/i915/display/intel_opregion.c

365

drm_dbg(display->drm, "SWSCI request timed out\n");

sys/dev/pci/drm/i915/display/intel_opregion.c

374

drm_dbg(display->drm, "SWSCI request error %u\n", scic);

sys/dev/pci/drm/i915/display/intel_opregion.c

394

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_opregion.c

401

if (!HAS_DDI(display))

sys/dev/pci/drm/i915/display/intel_opregion.c

405

ret = check_swsci_function(display, SWSCI_SBCB_DISPLAY_POWER_STATE);

sys/dev/pci/drm/i915/display/intel_opregion.c

429

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_opregion.c

454

drm_WARN_ONCE(display->drm, 1,

sys/dev/pci/drm/i915/display/intel_opregion.c

462

return swsci(display, SWSCI_SBCB_DISPLAY_POWER_STATE, parm, NULL);

sys/dev/pci/drm/i915/display/intel_opregion.c

476

int intel_opregion_notify_adapter(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_opregion.c

481

if (!HAS_DDI(display))

sys/dev/pci/drm/i915/display/intel_opregion.c

486

return swsci(display, SWSCI_SBCB_ADAPTER_POWER_STATE,

sys/dev/pci/drm/i915/display/intel_opregion.c

493

static u32 asle_set_backlight(struct intel_display *display, u32 bclp)

sys/dev/pci/drm/i915/display/intel_opregion.c

497

struct opregion_asle *asle = display->opregion->asle;

sys/dev/pci/drm/i915/display/intel_opregion.c

499

drm_dbg(display->drm, "bclp = 0x%08x\n", bclp);

sys/dev/pci/drm/i915/display/intel_opregion.c

502

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_opregion.c

514

drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL);

sys/dev/pci/drm/i915/display/intel_opregion.c

520

drm_dbg_kms(display->drm, "updating opregion backlight %d/255\n",

sys/dev/pci/drm/i915/display/intel_opregion.c

522

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_opregion.c

528

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_opregion.c

534

static u32 asle_set_als_illum(struct intel_display *display, u32 alsi)

sys/dev/pci/drm/i915/display/intel_opregion.c

538

drm_dbg(display->drm, "Illum is not supported\n");

sys/dev/pci/drm/i915/display/intel_opregion.c

542

static u32 asle_set_pwm_freq(struct intel_display *display, u32 pfmb)

sys/dev/pci/drm/i915/display/intel_opregion.c

544

drm_dbg(display->drm, "PWM freq is not supported\n");

sys/dev/pci/drm/i915/display/intel_opregion.c

548

static u32 asle_set_pfit(struct intel_display *display, u32 pfit)

sys/dev/pci/drm/i915/display/intel_opregion.c

552

drm_dbg(display->drm, "Pfit is not supported\n");

sys/dev/pci/drm/i915/display/intel_opregion.c

556

static u32 asle_set_supported_rotation_angles(struct intel_display *display, u32 srot)

sys/dev/pci/drm/i915/display/intel_opregion.c

558

drm_dbg(display->drm, "SROT is not supported\n");

sys/dev/pci/drm/i915/display/intel_opregion.c

562

static u32 asle_set_button_array(struct intel_display *display, u32 iuer)

sys/dev/pci/drm/i915/display/intel_opregion.c

565

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_opregion.c

568

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_opregion.c

571

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_opregion.c

574

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_opregion.c

577

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_opregion.c

580

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_opregion.c

586

static u32 asle_set_convertible(struct intel_display *display, u32 iuer)

sys/dev/pci/drm/i915/display/intel_opregion.c

589

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_opregion.c

592

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_opregion.c

598

static u32 asle_set_docking(struct intel_display *display, u32 iuer)

sys/dev/pci/drm/i915/display/intel_opregion.c

601

drm_dbg(display->drm, "Docking is not supported (docked)\n");

sys/dev/pci/drm/i915/display/intel_opregion.c

603

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_opregion.c

609

static u32 asle_isct_state(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.c

611

drm_dbg(display->drm, "ISCT is not supported\n");

sys/dev/pci/drm/i915/display/intel_opregion.c

619

struct intel_display *display = opregion->display;

sys/dev/pci/drm/i915/display/intel_opregion.c

630

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_opregion.c

636

aslc_stat |= asle_set_als_illum(display, asle->alsi);

sys/dev/pci/drm/i915/display/intel_opregion.c

639

aslc_stat |= asle_set_backlight(display, asle->bclp);

sys/dev/pci/drm/i915/display/intel_opregion.c

642

aslc_stat |= asle_set_pfit(display, asle->pfit);

sys/dev/pci/drm/i915/display/intel_opregion.c

645

aslc_stat |= asle_set_pwm_freq(display, asle->pfmb);

sys/dev/pci/drm/i915/display/intel_opregion.c

648

aslc_stat |= asle_set_supported_rotation_angles(display,

sys/dev/pci/drm/i915/display/intel_opregion.c

652

aslc_stat |= asle_set_button_array(display, asle->iuer);

sys/dev/pci/drm/i915/display/intel_opregion.c

655

aslc_stat |= asle_set_convertible(display, asle->iuer);

sys/dev/pci/drm/i915/display/intel_opregion.c

658

aslc_stat |= asle_set_docking(display, asle->iuer);

sys/dev/pci/drm/i915/display/intel_opregion.c

661

aslc_stat |= asle_isct_state(display);

sys/dev/pci/drm/i915/display/intel_opregion.c

666

bool intel_opregion_asle_present(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.c

668

return display->opregion && display->opregion->asle;

sys/dev/pci/drm/i915/display/intel_opregion.c

671

void intel_opregion_asle_intr(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.c

673

struct intel_opregion *opregion = display->opregion;

sys/dev/pci/drm/i915/display/intel_opregion.c

676

queue_work(display->wq.unordered, &opregion->asle_work);

sys/dev/pci/drm/i915/display/intel_opregion.c

732

static void intel_didl_outputs(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.c

734

struct intel_opregion *opregion = display->opregion;

sys/dev/pci/drm/i915/display/intel_opregion.c

749

intel_acpi_device_id_update(display);

sys/dev/pci/drm/i915/display/intel_opregion.c

751

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_opregion.c

759

drm_dbg_kms(display->drm, "%d outputs detected\n", i);

sys/dev/pci/drm/i915/display/intel_opregion.c

762

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_opregion.c

771

static void intel_setup_cadls(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.c

773

struct intel_opregion *opregion = display->opregion;

sys/dev/pci/drm/i915/display/intel_opregion.c

788

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_opregion.c

803

static void swsci_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.c

805

struct intel_opregion *opregion = display->opregion;

sys/dev/pci/drm/i915/display/intel_opregion.c

814

if (swsci(display, SWSCI_GBDA_SUPPORTED_CALLS, 0, &tmp) == 0) {

sys/dev/pci/drm/i915/display/intel_opregion.c

825

if (swsci(display, SWSCI_GBDA_REQUESTED_CALLBACKS, 0, &tmp) == 0) {

sys/dev/pci/drm/i915/display/intel_opregion.c

836

if (swsci(display, SWSCI_SBCB_SUPPORTED_CALLBACKS, 0, &tmp) == 0) {

sys/dev/pci/drm/i915/display/intel_opregion.c

846

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_opregion.c

856

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_opregion.c

881

int intel_opregion_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.c

884

struct pci_dev *pdev = display->drm->pdev;

sys/dev/pci/drm/i915/display/intel_opregion.c

885

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_opregion.c

900

drm_dbg(display->drm, "graphic opregion physical addr: 0x%x\n",

sys/dev/pci/drm/i915/display/intel_opregion.c

903

drm_dbg(display->drm, "ACPI OpRegion not supported!\n");

sys/dev/pci/drm/i915/display/intel_opregion.c

911

opregion->display = display;

sys/dev/pci/drm/i915/display/intel_opregion.c

912

display->opregion = opregion;

sys/dev/pci/drm/i915/display/intel_opregion.c

934

drm_dbg(display->drm, "opregion signature mismatch\n");

sys/dev/pci/drm/i915/display/intel_opregion.c

940

drm_dbg(display->drm, "ACPI OpRegion version %u.%u.%u\n",

sys/dev/pci/drm/i915/display/intel_opregion.c

947

drm_dbg(display->drm, "Public ACPI methods supported\n");

sys/dev/pci/drm/i915/display/intel_opregion.c

962

drm_err(display->drm, "SWSCI Mailbox #2 present for opregion v3.x, ignoring\n");

sys/dev/pci/drm/i915/display/intel_opregion.c

965

drm_dbg(display->drm, "SWSCI Mailbox #2 present for opregion v2.x\n");

sys/dev/pci/drm/i915/display/intel_opregion.c

966

drm_dbg(display->drm, "SWSCI supported\n");

sys/dev/pci/drm/i915/display/intel_opregion.c

968

swsci_setup(display);

sys/dev/pci/drm/i915/display/intel_opregion.c

973

drm_dbg(display->drm, "ASLE supported\n");

sys/dev/pci/drm/i915/display/intel_opregion.c

980

drm_dbg(display->drm, "ASLE extension supported\n");

sys/dev/pci/drm/i915/display/intel_opregion.c

985

drm_dbg(display->drm, "Mailbox #2 for backlight present\n");

sys/dev/pci/drm/i915/display/intel_opregion.h

107

intel_opregion_notify_adapter(struct intel_display *display, pci_power_t state)

sys/dev/pci/drm/i915/display/intel_opregion.h

112

static inline int intel_opregion_get_panel_type(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.h

123

static inline bool intel_opregion_vbt_present(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.h

129

intel_opregion_get_vbt(struct intel_display *display, size_t *size)

sys/dev/pci/drm/i915/display/intel_opregion.h

134

static inline bool intel_opregion_headless_sku(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.h

139

static inline void intel_opregion_debugfs_register(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.h

37

int intel_opregion_setup(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_opregion.h

38

void intel_opregion_cleanup(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_opregion.h

40

void intel_opregion_register(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_opregion.h

41

void intel_opregion_unregister(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_opregion.h

43

void intel_opregion_resume(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_opregion.h

44

void intel_opregion_suspend(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_opregion.h

47

bool intel_opregion_asle_present(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_opregion.h

48

void intel_opregion_asle_intr(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_opregion.h

51

int intel_opregion_notify_adapter(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_opregion.h

53

int intel_opregion_get_panel_type(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_opregion.h

56

bool intel_opregion_vbt_present(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_opregion.h

57

const void *intel_opregion_get_vbt(struct intel_display *display, size_t *size);

sys/dev/pci/drm/i915/display/intel_opregion.h

59

bool intel_opregion_headless_sku(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_opregion.h

61

void intel_opregion_debugfs_register(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_opregion.h

65

static inline int intel_opregion_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.h

70

static inline void intel_opregion_cleanup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.h

74

static inline void intel_opregion_register(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.h

78

static inline void intel_opregion_unregister(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.h

82

static inline void intel_opregion_resume(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.h

86

static inline void intel_opregion_suspend(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_opregion.h

91

static inline bool intel_opregion_asle_present(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_opregion.h

96

static inline void intel_opregion_asle_intr(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_overlay.c

1010

static int check_overlay_src(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_overlay.c

1021

if (display->platform.i845g || display->platform.i830) {

sys/dev/pci/drm/i915/display/intel_overlay.c

1073

if (display->platform.i830 || display->platform.i845g)

sys/dev/pci/drm/i915/display/intel_overlay.c

1080

if (DISPLAY_VER(display) == 4 && rec->stride_Y < 512)

sys/dev/pci/drm/i915/display/intel_overlay.c

1124

struct intel_display *display = to_intel_display(dev);

sys/dev/pci/drm/i915/display/intel_overlay.c

1132

overlay = display->overlay;

sys/dev/pci/drm/i915/display/intel_overlay.c

1134

drm_dbg(display->drm, "userspace bug: no overlay\n");

sys/dev/pci/drm/i915/display/intel_overlay.c

1158

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_overlay.c

1207

ret = check_overlay_src(display, params, new_bo);

sys/dev/pci/drm/i915/display/intel_overlay.c

1287

struct intel_display *display = to_intel_display(dev);

sys/dev/pci/drm/i915/display/intel_overlay.c

1292

overlay = display->overlay;

sys/dev/pci/drm/i915/display/intel_overlay.c

1294

drm_dbg(display->drm, "userspace bug: no overlay\n");

sys/dev/pci/drm/i915/display/intel_overlay.c

1307

if (DISPLAY_VER(display) != 2) {

sys/dev/pci/drm/i915/display/intel_overlay.c

1308

attrs->gamma0 = intel_de_read(display, OGAMC0);

sys/dev/pci/drm/i915/display/intel_overlay.c

1309

attrs->gamma1 = intel_de_read(display, OGAMC1);

sys/dev/pci/drm/i915/display/intel_overlay.c

1310

attrs->gamma2 = intel_de_read(display, OGAMC2);

sys/dev/pci/drm/i915/display/intel_overlay.c

1311

attrs->gamma3 = intel_de_read(display, OGAMC3);

sys/dev/pci/drm/i915/display/intel_overlay.c

1312

attrs->gamma4 = intel_de_read(display, OGAMC4);

sys/dev/pci/drm/i915/display/intel_overlay.c

1313

attrs->gamma5 = intel_de_read(display, OGAMC5);

sys/dev/pci/drm/i915/display/intel_overlay.c

1331

if (DISPLAY_VER(display) == 2)

sys/dev/pci/drm/i915/display/intel_overlay.c

1343

intel_de_write(display, OGAMC0, attrs->gamma0);

sys/dev/pci/drm/i915/display/intel_overlay.c

1344

intel_de_write(display, OGAMC1, attrs->gamma1);

sys/dev/pci/drm/i915/display/intel_overlay.c

1345

intel_de_write(display, OGAMC2, attrs->gamma2);

sys/dev/pci/drm/i915/display/intel_overlay.c

1346

intel_de_write(display, OGAMC3, attrs->gamma3);

sys/dev/pci/drm/i915/display/intel_overlay.c

1347

intel_de_write(display, OGAMC4, attrs->gamma4);

sys/dev/pci/drm/i915/display/intel_overlay.c

1348

intel_de_write(display, OGAMC5, attrs->gamma5);

sys/dev/pci/drm/i915/display/intel_overlay.c

1362

struct intel_display *display = overlay->display;

sys/dev/pci/drm/i915/display/intel_overlay.c

1363

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_overlay.c

1368

if (!display->platform.meteorlake) /* Wa_22018444074 */

sys/dev/pci/drm/i915/display/intel_overlay.c

1401

void intel_overlay_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_overlay.c

1403

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_overlay.c

1408

if (!HAS_OVERLAY(display))

sys/dev/pci/drm/i915/display/intel_overlay.c

1419

overlay->display = display;

sys/dev/pci/drm/i915/display/intel_overlay.c

1430

ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(display));

sys/dev/pci/drm/i915/display/intel_overlay.c

1438

display->overlay = overlay;

sys/dev/pci/drm/i915/display/intel_overlay.c

1439

drm_info(display->drm, "Initialized overlay support.\n");

sys/dev/pci/drm/i915/display/intel_overlay.c

1446

bool intel_overlay_available(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_overlay.c

1448

return display->overlay;

sys/dev/pci/drm/i915/display/intel_overlay.c

1451

void intel_overlay_cleanup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_overlay.c

1455

overlay = fetch_and_zero(&display->overlay);

sys/dev/pci/drm/i915/display/intel_overlay.c

1464

drm_WARN_ON(display->drm, overlay->active);

sys/dev/pci/drm/i915/display/intel_overlay.c

1482

intel_overlay_snapshot_capture(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_overlay.c

1484

struct intel_overlay *overlay = display->overlay;

sys/dev/pci/drm/i915/display/intel_overlay.c

1494

error->dovsta = intel_de_read(display, DOVSTA);

sys/dev/pci/drm/i915/display/intel_overlay.c

1495

error->isr = intel_de_read(display, GEN2_ISR);

sys/dev/pci/drm/i915/display/intel_overlay.c

190

struct intel_display *display;

sys/dev/pci/drm/i915/display/intel_overlay.c

212

static void i830_overlay_clock_gating(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_overlay.c

215

struct pci_dev *pdev = display->drm->pdev;

sys/dev/pci/drm/i915/display/intel_overlay.c

220

intel_de_write(display, DSPCLK_GATE_D, 0);

sys/dev/pci/drm/i915/display/intel_overlay.c

222

intel_de_write(display, DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);

sys/dev/pci/drm/i915/display/intel_overlay.c

259

struct intel_display *display = overlay->display;

sys/dev/pci/drm/i915/display/intel_overlay.c

263

drm_WARN_ON(display->drm, overlay->active);

sys/dev/pci/drm/i915/display/intel_overlay.c

277

if (display->platform.i830)

sys/dev/pci/drm/i915/display/intel_overlay.c

278

i830_overlay_clock_gating(display, false);

sys/dev/pci/drm/i915/display/intel_overlay.c

294

struct intel_display *display = overlay->display;

sys/dev/pci/drm/i915/display/intel_overlay.c

298

drm_WARN_ON(display->drm, overlay->old_vma);

sys/dev/pci/drm/i915/display/intel_overlay.c

310

intel_frontbuffer_flip_prepare(display, INTEL_FRONTBUFFER_OVERLAY(pipe));

sys/dev/pci/drm/i915/display/intel_overlay.c

324

struct intel_display *display = overlay->display;

sys/dev/pci/drm/i915/display/intel_overlay.c

329

drm_WARN_ON(display->drm, !overlay->active);

sys/dev/pci/drm/i915/display/intel_overlay.c

335

tmp = intel_de_read(display, DOVSTA);

sys/dev/pci/drm/i915/display/intel_overlay.c

337

drm_dbg(display->drm, "overlay underrun, DOVSTA: %x\n", tmp);

sys/dev/pci/drm/i915/display/intel_overlay.c

361

struct intel_display *display = overlay->display;

sys/dev/pci/drm/i915/display/intel_overlay.c

365

if (drm_WARN_ON(display->drm, !vma))

sys/dev/pci/drm/i915/display/intel_overlay.c

368

intel_frontbuffer_flip_complete(display, INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));

sys/dev/pci/drm/i915/display/intel_overlay.c

382

struct intel_display *display = overlay->display;

sys/dev/pci/drm/i915/display/intel_overlay.c

390

if (display->platform.i830)

sys/dev/pci/drm/i915/display/intel_overlay.c

391

i830_overlay_clock_gating(display, true);

sys/dev/pci/drm/i915/display/intel_overlay.c

406

struct intel_display *display = overlay->display;

sys/dev/pci/drm/i915/display/intel_overlay.c

410

drm_WARN_ON(display->drm, !overlay->active);

sys/dev/pci/drm/i915/display/intel_overlay.c

464

struct intel_display *display = overlay->display;

sys/dev/pci/drm/i915/display/intel_overlay.c

475

if (!(intel_de_read(display, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) {

sys/dev/pci/drm/i915/display/intel_overlay.c

499

void intel_overlay_reset(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_overlay.c

501

struct intel_overlay *overlay = display->overlay;

sys/dev/pci/drm/i915/display/intel_overlay.c

562

static u32 calc_swidthsw(struct intel_display *display, u32 offset, u32 width)

sys/dev/pci/drm/i915/display/intel_overlay.c

566

if (DISPLAY_VER(display) == 2)

sys/dev/pci/drm/i915/display/intel_overlay.c

801

struct intel_display *display = overlay->display;

sys/dev/pci/drm/i915/display/intel_overlay.c

809

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_overlay.c

810

!drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));

sys/dev/pci/drm/i915/display/intel_overlay.c

816

atomic_inc(&display->restore.pending_fb_pin);

sys/dev/pci/drm/i915/display/intel_overlay.c

836

if (DISPLAY_VER(display) == 4)

sys/dev/pci/drm/i915/display/intel_overlay.c

857

swidthsw = calc_swidthsw(display, params->offset_Y, tmp_width);

sys/dev/pci/drm/i915/display/intel_overlay.c

870

tmp_U = calc_swidthsw(display, params->offset_U,

sys/dev/pci/drm/i915/display/intel_overlay.c

872

tmp_V = calc_swidthsw(display, params->offset_V,

sys/dev/pci/drm/i915/display/intel_overlay.c

904

atomic_dec(&display->restore.pending_fb_pin);

sys/dev/pci/drm/i915/display/intel_overlay.c

911

struct intel_display *display = overlay->display;

sys/dev/pci/drm/i915/display/intel_overlay.c

914

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_overlay.c

915

!drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));

sys/dev/pci/drm/i915/display/intel_overlay.c

948

struct intel_display *display = overlay->display;

sys/dev/pci/drm/i915/display/intel_overlay.c

954

if (DISPLAY_VER(display) >= 4) {

sys/dev/pci/drm/i915/display/intel_overlay.c

955

u32 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));

sys/dev/pci/drm/i915/display/intel_overlay.c

962

if (intel_de_read(display, PFIT_CONTROL(display)) & PFIT_VERT_AUTO_SCALE)

sys/dev/pci/drm/i915/display/intel_overlay.c

963

tmp = intel_de_read(display, PFIT_AUTO_RATIOS(display));

sys/dev/pci/drm/i915/display/intel_overlay.c

965

tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));

sys/dev/pci/drm/i915/display/intel_overlay.h

20

void intel_overlay_setup(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_overlay.h

21

bool intel_overlay_available(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_overlay.h

22

void intel_overlay_cleanup(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_overlay.h

28

void intel_overlay_reset(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_overlay.h

30

static inline void intel_overlay_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_overlay.h

33

static inline bool intel_overlay_available(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_overlay.h

37

static inline void intel_overlay_cleanup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_overlay.h

54

static inline void intel_overlay_reset(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_overlay.h

61

intel_overlay_snapshot_capture(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_overlay.h

66

intel_overlay_snapshot_capture(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_panel.c

252

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_panel.c

261

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_panel.c

272

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_panel.c

290

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_panel.c

303

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_panel.c

307

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_panel.c

312

drm_mode_destroy(display->drm, mode);

sys/dev/pci/drm/i915/display/intel_panel.c

329

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_panel.c

340

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] using %s fixed mode: " DRM_MODE_FMT "\n",

sys/dev/pci/drm/i915/display/intel_panel.c

349

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_panel.c

357

drm_mode_duplicate(display->drm, mode),

sys/dev/pci/drm/i915/display/intel_panel.c

363

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_panel.c

371

drm_mode_duplicate(display->drm, mode),

sys/dev/pci/drm/i915/display/intel_panel.c

386

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_panel.c

388

if (!intel_display_device_enabled(display))

sys/dev/pci/drm/i915/display/intel_panel.c

391

if (!intel_display_driver_check_access(display))

sys/dev/pci/drm/i915/display/intel_panel.c

47

bool intel_panel_use_ssc(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_panel.c

478

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_panel.c

483

ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL);

sys/dev/pci/drm/i915/display/intel_panel.c

49

if (display->params.panel_use_ssc >= 0)

sys/dev/pci/drm/i915/display/intel_panel.c

496

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Panel prepare\n",

sys/dev/pci/drm/i915/display/intel_panel.c

50

return display->params.panel_use_ssc != 0;

sys/dev/pci/drm/i915/display/intel_panel.c

502

drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

sys/dev/pci/drm/i915/display/intel_panel.c

51

return display->vbt.lvds_use_ssc &&

sys/dev/pci/drm/i915/display/intel_panel.c

510

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_panel.c

52

!intel_has_quirk(display, QUIRK_LVDS_SSC_DISABLE);

sys/dev/pci/drm/i915/display/intel_panel.c

528

if (drm_WARN_ON(display->drm, !dev))

sys/dev/pci/drm/i915/display/intel_panel.c

557

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Registered panel device '%s', has fwnode: %s\n",

sys/dev/pci/drm/i915/display/intel_panel.h

30

bool intel_panel_use_ssc(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_pch.c

100

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pch.c

101

!display->platform.haswell_ult &&

sys/dev/pci/drm/i915/display/intel_pch.c

102

!display->platform.broadwell_ult);

sys/dev/pci/drm/i915/display/intel_pch.c

105

drm_dbg_kms(display->drm, "Found WildcatPoint PCH\n");

sys/dev/pci/drm/i915/display/intel_pch.c

106

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pch.c

107

!display->platform.haswell &&

sys/dev/pci/drm/i915/display/intel_pch.c

108

!display->platform.broadwell);

sys/dev/pci/drm/i915/display/intel_pch.c

109

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pch.c

110

display->platform.haswell_ult ||

sys/dev/pci/drm/i915/display/intel_pch.c

111

display->platform.broadwell_ult);

sys/dev/pci/drm/i915/display/intel_pch.c

115

drm_dbg_kms(display->drm, "Found WildcatPoint LP PCH\n");

sys/dev/pci/drm/i915/display/intel_pch.c

116

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pch.c

117

!display->platform.haswell &&

sys/dev/pci/drm/i915/display/intel_pch.c

118

!display->platform.broadwell);

sys/dev/pci/drm/i915/display/intel_pch.c

119

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pch.c

120

!display->platform.haswell_ult &&

sys/dev/pci/drm/i915/display/intel_pch.c

121

!display->platform.broadwell_ult);

sys/dev/pci/drm/i915/display/intel_pch.c

125

drm_dbg_kms(display->drm, "Found SunrisePoint PCH\n");

sys/dev/pci/drm/i915/display/intel_pch.c

126

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pch.c

127

!display->platform.skylake &&

sys/dev/pci/drm/i915/display/intel_pch.c

128

!display->platform.kabylake &&

sys/dev/pci/drm/i915/display/intel_pch.c

129

!display->platform.coffeelake);

sys/dev/pci/drm/i915/display/intel_pch.c

132

drm_dbg_kms(display->drm, "Found SunrisePoint LP PCH\n");

sys/dev/pci/drm/i915/display/intel_pch.c

133

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pch.c

134

!display->platform.skylake &&

sys/dev/pci/drm/i915/display/intel_pch.c

135

!display->platform.kabylake &&

sys/dev/pci/drm/i915/display/intel_pch.c

136

!display->platform.coffeelake &&

sys/dev/pci/drm/i915/display/intel_pch.c

137

!display->platform.cometlake);

sys/dev/pci/drm/i915/display/intel_pch.c

140

drm_dbg_kms(display->drm, "Found Kaby Lake PCH (KBP)\n");

sys/dev/pci/drm/i915/display/intel_pch.c

141

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pch.c

142

!display->platform.skylake &&

sys/dev/pci/drm/i915/display/intel_pch.c

143

!display->platform.kabylake &&

sys/dev/pci/drm/i915/display/intel_pch.c

144

!display->platform.coffeelake &&

sys/dev/pci/drm/i915/display/intel_pch.c

145

!display->platform.cometlake);

sys/dev/pci/drm/i915/display/intel_pch.c

149

drm_dbg_kms(display->drm, "Found Cannon Lake PCH (CNP)\n");

sys/dev/pci/drm/i915/display/intel_pch.c

150

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pch.c

151

!display->platform.coffeelake &&

sys/dev/pci/drm/i915/display/intel_pch.c

152

!display->platform.cometlake);

sys/dev/pci/drm/i915/display/intel_pch.c

155

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pch.c

157

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pch.c

158

!display->platform.coffeelake &&

sys/dev/pci/drm/i915/display/intel_pch.c

159

!display->platform.cometlake);

sys/dev/pci/drm/i915/display/intel_pch.c

163

drm_dbg_kms(display->drm, "Found Comet Lake PCH (CMP)\n");

sys/dev/pci/drm/i915/display/intel_pch.c

164

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pch.c

165

!display->platform.coffeelake &&

sys/dev/pci/drm/i915/display/intel_pch.c

166

!display->platform.cometlake &&

sys/dev/pci/drm/i915/display/intel_pch.c

167

!display->platform.rocketlake);

sys/dev/pci/drm/i915/display/intel_pch.c

171

drm_dbg_kms(display->drm, "Found Comet Lake V PCH (CMP-V)\n");

sys/dev/pci/drm/i915/display/intel_pch.c

172

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pch.c

173

!display->platform.coffeelake &&

sys/dev/pci/drm/i915/display/intel_pch.c

174

!display->platform.cometlake);

sys/dev/pci/drm/i915/display/intel_pch.c

179

drm_dbg_kms(display->drm, "Found Ice Lake PCH\n");

sys/dev/pci/drm/i915/display/intel_pch.c

180

drm_WARN_ON(display->drm, !display->platform.icelake);

sys/dev/pci/drm/i915/display/intel_pch.c

183

drm_dbg_kms(display->drm, "Found Mule Creek Canyon PCH\n");

sys/dev/pci/drm/i915/display/intel_pch.c

184

drm_WARN_ON(display->drm, !(display->platform.jasperlake ||

sys/dev/pci/drm/i915/display/intel_pch.c

185

display->platform.elkhartlake));

sys/dev/pci/drm/i915/display/intel_pch.c

190

drm_dbg_kms(display->drm, "Found Tiger Lake LP PCH\n");

sys/dev/pci/drm/i915/display/intel_pch.c

191

drm_WARN_ON(display->drm, !display->platform.tigerlake &&

sys/dev/pci/drm/i915/display/intel_pch.c

192

!display->platform.rocketlake &&

sys/dev/pci/drm/i915/display/intel_pch.c

193

!display->platform.skylake &&

sys/dev/pci/drm/i915/display/intel_pch.c

194

!display->platform.kabylake &&

sys/dev/pci/drm/i915/display/intel_pch.c

195

!display->platform.coffeelake &&

sys/dev/pci/drm/i915/display/intel_pch.c

196

!display->platform.cometlake);

sys/dev/pci/drm/i915/display/intel_pch.c

199

drm_dbg_kms(display->drm, "Found Jasper Lake PCH\n");

sys/dev/pci/drm/i915/display/intel_pch.c

200

drm_WARN_ON(display->drm, !(display->platform.jasperlake ||

sys/dev/pci/drm/i915/display/intel_pch.c

201

display->platform.elkhartlake));

sys/dev/pci/drm/i915/display/intel_pch.c

208

drm_dbg_kms(display->drm, "Found Alder Lake PCH\n");

sys/dev/pci/drm/i915/display/intel_pch.c

209

drm_WARN_ON(display->drm, !display->platform.alderlake_s &&

sys/dev/pci/drm/i915/display/intel_pch.c

210

!display->platform.alderlake_p);

sys/dev/pci/drm/i915/display/intel_pch.c

228

intel_virt_detect_pch(const struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pch.c

240

if (display->platform.alderlake_s || display->platform.alderlake_p)

sys/dev/pci/drm/i915/display/intel_pch.c

242

else if (display->platform.tigerlake || display->platform.rocketlake)

sys/dev/pci/drm/i915/display/intel_pch.c

244

else if (display->platform.jasperlake || display->platform.elkhartlake)

sys/dev/pci/drm/i915/display/intel_pch.c

246

else if (display->platform.icelake)

sys/dev/pci/drm/i915/display/intel_pch.c

248

else if (display->platform.coffeelake ||

sys/dev/pci/drm/i915/display/intel_pch.c

249

display->platform.cometlake)

sys/dev/pci/drm/i915/display/intel_pch.c

251

else if (display->platform.kabylake || display->platform.skylake)

sys/dev/pci/drm/i915/display/intel_pch.c

253

else if (display->platform.haswell_ult ||

sys/dev/pci/drm/i915/display/intel_pch.c

254

display->platform.broadwell_ult)

sys/dev/pci/drm/i915/display/intel_pch.c

256

else if (display->platform.haswell || display->platform.broadwell)

sys/dev/pci/drm/i915/display/intel_pch.c

258

else if (DISPLAY_VER(display) == 6 || display->platform.ivybridge)

sys/dev/pci/drm/i915/display/intel_pch.c

260

else if (DISPLAY_VER(display) == 5)

sys/dev/pci/drm/i915/display/intel_pch.c

264

drm_dbg_kms(display->drm, "Assuming PCH ID %04x\n", id);

sys/dev/pci/drm/i915/display/intel_pch.c

266

drm_dbg_kms(display->drm, "Assuming no PCH\n");

sys/dev/pci/drm/i915/display/intel_pch.c

268

*pch_type = intel_pch_type(display, id);

sys/dev/pci/drm/i915/display/intel_pch.c

271

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pch.c

288

void intel_pch_detect(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pch.c

295

pch_type = intel_pch_fake_for_south_display(display);

sys/dev/pci/drm/i915/display/intel_pch.c

297

display->pch_type = pch_type;

sys/dev/pci/drm/i915/display/intel_pch.c

298

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pch.c

319

pch_type = intel_pch_type(display, id);

sys/dev/pci/drm/i915/display/intel_pch.c

321

display->pch_type = pch_type;

sys/dev/pci/drm/i915/display/intel_pch.c

324

intel_virt_detect_pch(display, &id, &pch_type);

sys/dev/pci/drm/i915/display/intel_pch.c

325

display->pch_type = pch_type;

sys/dev/pci/drm/i915/display/intel_pch.c

333

if (pci_find_device(&pa, intel_pch_match) && !HAS_DISPLAY(display)) {

sys/dev/pci/drm/i915/display/intel_pch.c

334

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pch.c

336

display->pch_type = PCH_NOP;

sys/dev/pci/drm/i915/display/intel_pch.c

338

if (i915_run_as_guest() && HAS_DISPLAY(display)) {

sys/dev/pci/drm/i915/display/intel_pch.c

339

intel_virt_detect_pch(display, &id, &pch_type);

sys/dev/pci/drm/i915/display/intel_pch.c

340

display->pch_type = pch_type;

sys/dev/pci/drm/i915/display/intel_pch.c

342

drm_dbg_kms(display->drm, "No PCH found.\n");

sys/dev/pci/drm/i915/display/intel_pch.c

48

static enum intel_pch intel_pch_fake_for_south_display(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pch.c

52

if (DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/intel_pch.c

54

else if (display->platform.battlemage || display->platform.meteorlake)

sys/dev/pci/drm/i915/display/intel_pch.c

56

else if (display->platform.dg2)

sys/dev/pci/drm/i915/display/intel_pch.c

58

else if (display->platform.dg1)

sys/dev/pci/drm/i915/display/intel_pch.c

66

intel_pch_type(const struct intel_display *display, unsigned short id)

sys/dev/pci/drm/i915/display/intel_pch.c

70

drm_dbg_kms(display->drm, "Found Ibex Peak PCH\n");

sys/dev/pci/drm/i915/display/intel_pch.c

71

drm_WARN_ON(display->drm, DISPLAY_VER(display) != 5);

sys/dev/pci/drm/i915/display/intel_pch.c

74

drm_dbg_kms(display->drm, "Found CougarPoint PCH\n");

sys/dev/pci/drm/i915/display/intel_pch.c

75

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pch.c

76

DISPLAY_VER(display) != 6 &&

sys/dev/pci/drm/i915/display/intel_pch.c

77

!display->platform.ivybridge);

sys/dev/pci/drm/i915/display/intel_pch.c

80

drm_dbg_kms(display->drm, "Found PantherPoint PCH\n");

sys/dev/pci/drm/i915/display/intel_pch.c

81

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pch.c

82

DISPLAY_VER(display) != 6 &&

sys/dev/pci/drm/i915/display/intel_pch.c

83

!display->platform.ivybridge);

sys/dev/pci/drm/i915/display/intel_pch.c

87

drm_dbg_kms(display->drm, "Found LynxPoint PCH\n");

sys/dev/pci/drm/i915/display/intel_pch.c

88

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pch.c

89

!display->platform.haswell &&

sys/dev/pci/drm/i915/display/intel_pch.c

90

!display->platform.broadwell);

sys/dev/pci/drm/i915/display/intel_pch.c

91

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pch.c

92

display->platform.haswell_ult ||

sys/dev/pci/drm/i915/display/intel_pch.c

93

display->platform.broadwell_ult);

sys/dev/pci/drm/i915/display/intel_pch.c

96

drm_dbg_kms(display->drm, "Found LynxPoint LP PCH\n");

sys/dev/pci/drm/i915/display/intel_pch.c

97

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pch.c

98

!display->platform.haswell &&

sys/dev/pci/drm/i915/display/intel_pch.c

99

!display->platform.broadwell);

sys/dev/pci/drm/i915/display/intel_pch.h

38

#define HAS_PCH_DG2(display) (INTEL_PCH_TYPE(display) == PCH_DG2)

sys/dev/pci/drm/i915/display/intel_pch.h

39

#define HAS_PCH_ADP(display) (INTEL_PCH_TYPE(display) == PCH_ADP)

sys/dev/pci/drm/i915/display/intel_pch.h

40

#define HAS_PCH_DG1(display) (INTEL_PCH_TYPE(display) == PCH_DG1)

sys/dev/pci/drm/i915/display/intel_pch.h

41

#define HAS_PCH_TGP(display) (INTEL_PCH_TYPE(display) == PCH_TGP)

sys/dev/pci/drm/i915/display/intel_pch.h

42

#define HAS_PCH_ICP(display) (INTEL_PCH_TYPE(display) == PCH_ICP)

sys/dev/pci/drm/i915/display/intel_pch.h

43

#define HAS_PCH_CNP(display) (INTEL_PCH_TYPE(display) == PCH_CNP)

sys/dev/pci/drm/i915/display/intel_pch.h

44

#define HAS_PCH_SPT(display) (INTEL_PCH_TYPE(display) == PCH_SPT)

sys/dev/pci/drm/i915/display/intel_pch.h

45

#define HAS_PCH_LPT_H(display) (INTEL_PCH_TYPE(display) == PCH_LPT_H)

sys/dev/pci/drm/i915/display/intel_pch.h

46

#define HAS_PCH_LPT_LP(display) (INTEL_PCH_TYPE(display) == PCH_LPT_LP)

sys/dev/pci/drm/i915/display/intel_pch.h

47

#define HAS_PCH_LPT(display) (INTEL_PCH_TYPE(display) == PCH_LPT_H || \

sys/dev/pci/drm/i915/display/intel_pch.h

48

INTEL_PCH_TYPE(display) == PCH_LPT_LP)

sys/dev/pci/drm/i915/display/intel_pch.h

49

#define HAS_PCH_CPT(display) (INTEL_PCH_TYPE(display) == PCH_CPT)

sys/dev/pci/drm/i915/display/intel_pch.h

50

#define HAS_PCH_IBX(display) (INTEL_PCH_TYPE(display) == PCH_IBX)

sys/dev/pci/drm/i915/display/intel_pch.h

51

#define HAS_PCH_NOP(display) (INTEL_PCH_TYPE(display) == PCH_NOP)

sys/dev/pci/drm/i915/display/intel_pch.h

52

#define HAS_PCH_SPLIT(display) (INTEL_PCH_TYPE(display) != PCH_NONE)

sys/dev/pci/drm/i915/display/intel_pch.h

54

void intel_pch_detect(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_pch_display.c

100

assert_pch_hdmi_disabled(display, pipe, PORT_B, PCH_HDMIB);

sys/dev/pci/drm/i915/display/intel_pch_display.c

101

assert_pch_hdmi_disabled(display, pipe, PORT_C, PCH_HDMIC);

sys/dev/pci/drm/i915/display/intel_pch_display.c

102

assert_pch_hdmi_disabled(display, pipe, PORT_D, PCH_HDMID);

sys/dev/pci/drm/i915/display/intel_pch_display.c

105

static void assert_pch_transcoder_disabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pch_display.c

111

val = intel_de_read(display, PCH_TRANSCONF(pipe));

sys/dev/pci/drm/i915/display/intel_pch_display.c

113

INTEL_DISPLAY_STATE_WARN(display, enabled,

sys/dev/pci/drm/i915/display/intel_pch_display.c

118

static void ibx_sanitize_pch_hdmi_port(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pch_display.c

121

u32 val = intel_de_read(display, hdmi_reg);

sys/dev/pci/drm/i915/display/intel_pch_display.c

127

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pch_display.c

134

intel_de_write(display, hdmi_reg, val);

sys/dev/pci/drm/i915/display/intel_pch_display.c

137

static void ibx_sanitize_pch_dp_port(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pch_display.c

140

u32 val = intel_de_read(display, dp_reg);

sys/dev/pci/drm/i915/display/intel_pch_display.c

146

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pch_display.c

153

intel_de_write(display, dp_reg, val);

sys/dev/pci/drm/i915/display/intel_pch_display.c

156

static void ibx_sanitize_pch_ports(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pch_display.c

169

ibx_sanitize_pch_dp_port(display, PORT_B, PCH_DP_B);

sys/dev/pci/drm/i915/display/intel_pch_display.c

170

ibx_sanitize_pch_dp_port(display, PORT_C, PCH_DP_C);

sys/dev/pci/drm/i915/display/intel_pch_display.c

171

ibx_sanitize_pch_dp_port(display, PORT_D, PCH_DP_D);

sys/dev/pci/drm/i915/display/intel_pch_display.c

174

ibx_sanitize_pch_hdmi_port(display, PORT_B, PCH_HDMIB);

sys/dev/pci/drm/i915/display/intel_pch_display.c

175

ibx_sanitize_pch_hdmi_port(display, PORT_C, PCH_HDMIC);

sys/dev/pci/drm/i915/display/intel_pch_display.c

176

ibx_sanitize_pch_hdmi_port(display, PORT_D, PCH_HDMID);

sys/dev/pci/drm/i915/display/intel_pch_display.c

182

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_pch_display.c

185

intel_set_m_n(display, m_n,

sys/dev/pci/drm/i915/display/intel_pch_display.c

193

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_pch_display.c

196

intel_set_m_n(display, m_n,

sys/dev/pci/drm/i915/display/intel_pch_display.c

204

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_pch_display.c

207

intel_get_m_n(display, m_n,

sys/dev/pci/drm/i915/display/intel_pch_display.c

215

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_pch_display.c

218

intel_get_m_n(display, m_n,

sys/dev/pci/drm/i915/display/intel_pch_display.c

226

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_pch_display.c

229

intel_de_write(display, PCH_TRANS_HTOTAL(pch_transcoder),

sys/dev/pci/drm/i915/display/intel_pch_display.c

230

intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder)));

sys/dev/pci/drm/i915/display/intel_pch_display.c

231

intel_de_write(display, PCH_TRANS_HBLANK(pch_transcoder),

sys/dev/pci/drm/i915/display/intel_pch_display.c

232

intel_de_read(display, TRANS_HBLANK(display, cpu_transcoder)));

sys/dev/pci/drm/i915/display/intel_pch_display.c

233

intel_de_write(display, PCH_TRANS_HSYNC(pch_transcoder),

sys/dev/pci/drm/i915/display/intel_pch_display.c

234

intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder)));

sys/dev/pci/drm/i915/display/intel_pch_display.c

236

intel_de_write(display, PCH_TRANS_VTOTAL(pch_transcoder),

sys/dev/pci/drm/i915/display/intel_pch_display.c

237

intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder)));

sys/dev/pci/drm/i915/display/intel_pch_display.c

238

intel_de_write(display, PCH_TRANS_VBLANK(pch_transcoder),

sys/dev/pci/drm/i915/display/intel_pch_display.c

239

intel_de_read(display, TRANS_VBLANK(display, cpu_transcoder)));

sys/dev/pci/drm/i915/display/intel_pch_display.c

240

intel_de_write(display, PCH_TRANS_VSYNC(pch_transcoder),

sys/dev/pci/drm/i915/display/intel_pch_display.c

241

intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder)));

sys/dev/pci/drm/i915/display/intel_pch_display.c

242

intel_de_write(display, PCH_TRANS_VSYNCSHIFT(pch_transcoder),

sys/dev/pci/drm/i915/display/intel_pch_display.c

243

intel_de_read(display, TRANS_VSYNCSHIFT(display, cpu_transcoder)));

sys/dev/pci/drm/i915/display/intel_pch_display.c

248

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_pch_display.c

25

bool intel_has_pch_trancoder(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pch_display.c

255

assert_dpll_enabled(display, crtc_state->intel_dpll);

sys/dev/pci/drm/i915/display/intel_pch_display.c

258

assert_fdi_tx_enabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

259

assert_fdi_rx_enabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

261

if (HAS_PCH_CPT(display)) {

sys/dev/pci/drm/i915/display/intel_pch_display.c

263

val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_pch_display.c

272

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_pch_display.c

276

val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_pch_display.c

277

pipeconf_val = intel_de_read(display, TRANSCONF(display, pipe));

sys/dev/pci/drm/i915/display/intel_pch_display.c

279

if (HAS_PCH_IBX(display)) {

sys/dev/pci/drm/i915/display/intel_pch_display.c

28

return HAS_PCH_IBX(display) || HAS_PCH_CPT(display) ||

sys/dev/pci/drm/i915/display/intel_pch_display.c

29

(HAS_PCH_LPT_H(display) && pch_transcoder == PIPE_A);

sys/dev/pci/drm/i915/display/intel_pch_display.c

298

if (HAS_PCH_IBX(display) &&

sys/dev/pci/drm/i915/display/intel_pch_display.c

307

intel_de_write(display, reg, val | TRANS_ENABLE);

sys/dev/pci/drm/i915/display/intel_pch_display.c

308

if (intel_de_wait_for_set(display, reg, TRANS_STATE_ENABLE, 100))

sys/dev/pci/drm/i915/display/intel_pch_display.c

309

drm_err(display->drm, "failed to enable transcoder %c\n",

sys/dev/pci/drm/i915/display/intel_pch_display.c

315

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_pch_display.c

320

assert_fdi_tx_disabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

321

assert_fdi_rx_disabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

324

assert_pch_ports_disabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

327

intel_de_rmw(display, reg, TRANS_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_pch_display.c

329

if (intel_de_wait_for_clear(display, reg, TRANS_STATE_ENABLE, 50))

sys/dev/pci/drm/i915/display/intel_pch_display.c

330

drm_err(display->drm, "failed to disable transcoder %c\n",

sys/dev/pci/drm/i915/display/intel_pch_display.c

333

if (HAS_PCH_CPT(display))

sys/dev/pci/drm/i915/display/intel_pch_display.c

335

intel_de_rmw(display, TRANS_CHICKEN2(pipe),

sys/dev/pci/drm/i915/display/intel_pch_display.c

34

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_pch_display.c

36

if (HAS_PCH_LPT(display))

sys/dev/pci/drm/i915/display/intel_pch_display.c

364

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_pch_display.c

370

assert_pch_transcoder_disabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

379

if (HAS_PCH_CPT(display)) {

sys/dev/pci/drm/i915/display/intel_pch_display.c

382

temp = intel_de_read(display, PCH_DPLL_SEL);

sys/dev/pci/drm/i915/display/intel_pch_display.c

386

intel_get_dpll_by_id(display, DPLL_ID_PCH_PLL_B))

sys/dev/pci/drm/i915/display/intel_pch_display.c

390

intel_de_write(display, PCH_DPLL_SEL, temp);

sys/dev/pci/drm/i915/display/intel_pch_display.c

405

assert_pps_unlocked(display, pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

415

if (HAS_PCH_CPT(display) &&

sys/dev/pci/drm/i915/display/intel_pch_display.c

419

u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe))

sys/dev/pci/drm/i915/display/intel_pch_display.c

42

static void assert_pch_dp_disabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pch_display.c

424

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_pch_display.c

438

drm_WARN_ON(display->drm, port < PORT_B || port > PORT_D);

sys/dev/pci/drm/i915/display/intel_pch_display.c

441

intel_de_write(display, reg, temp);

sys/dev/pci/drm/i915/display/intel_pch_display.c

456

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_pch_display.c

463

if (HAS_PCH_CPT(display)) {

sys/dev/pci/drm/i915/display/intel_pch_display.c

465

intel_de_rmw(display, TRANS_DP_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_pch_display.c

470

intel_de_rmw(display, PCH_DPLL_SEL,

sys/dev/pci/drm/i915/display/intel_pch_display.c

481

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_pch_display.c

49

state = g4x_dp_port_enabled(display, dp_reg, port, &port_pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

492

intel_dotclock_calculate(intel_fdi_link_freq(display, crtc_state),

sys/dev/pci/drm/i915/display/intel_pch_display.c

498

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_pch_display.c

506

if ((intel_de_read(display, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)

sys/dev/pci/drm/i915/display/intel_pch_display.c

51

INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe,

sys/dev/pci/drm/i915/display/intel_pch_display.c

511

tmp = intel_de_read(display, FDI_RX_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_pch_display.c

518

if (HAS_PCH_IBX(display)) {

sys/dev/pci/drm/i915/display/intel_pch_display.c

525

tmp = intel_de_read(display, PCH_DPLL_SEL);

sys/dev/pci/drm/i915/display/intel_pch_display.c

532

crtc_state->intel_dpll = intel_get_dpll_by_id(display, pll_id);

sys/dev/pci/drm/i915/display/intel_pch_display.c

535

pll_active = intel_dpll_get_hw_state(display, pll,

sys/dev/pci/drm/i915/display/intel_pch_display.c

537

drm_WARN_ON(display->drm, !pll_active);

sys/dev/pci/drm/i915/display/intel_pch_display.c

549

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_pch_display.c

55

INTEL_DISPLAY_STATE_WARN(display,

sys/dev/pci/drm/i915/display/intel_pch_display.c

554

assert_fdi_tx_enabled(display, (enum pipe)cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_pch_display.c

555

assert_fdi_rx_enabled(display, PIPE_A);

sys/dev/pci/drm/i915/display/intel_pch_display.c

557

val = intel_de_read(display, TRANS_CHICKEN2(PIPE_A));

sys/dev/pci/drm/i915/display/intel_pch_display.c

56

HAS_PCH_IBX(display) && !state && port_pipe == PIPE_B,

sys/dev/pci/drm/i915/display/intel_pch_display.c

563

intel_de_write(display, TRANS_CHICKEN2(PIPE_A), val);

sys/dev/pci/drm/i915/display/intel_pch_display.c

566

pipeconf_val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_pch_display.c

567

TRANSCONF(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_pch_display.c

574

intel_de_write(display, LPT_TRANSCONF, val);

sys/dev/pci/drm/i915/display/intel_pch_display.c

575

if (intel_de_wait_for_set(display, LPT_TRANSCONF,

sys/dev/pci/drm/i915/display/intel_pch_display.c

577

drm_err(display->drm, "Failed to enable PCH transcoder\n");

sys/dev/pci/drm/i915/display/intel_pch_display.c

580

static void lpt_disable_pch_transcoder(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pch_display.c

582

intel_de_rmw(display, LPT_TRANSCONF, TRANS_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_pch_display.c

584

if (intel_de_wait_for_clear(display, LPT_TRANSCONF,

sys/dev/pci/drm/i915/display/intel_pch_display.c

586

drm_err(display->drm, "Failed to disable PCH transcoder\n");

sys/dev/pci/drm/i915/display/intel_pch_display.c

589

intel_de_rmw(display, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0);

sys/dev/pci/drm/i915/display/intel_pch_display.c

595

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_pch_display.c

599

assert_pch_transcoder_disabled(display, PIPE_A);

sys/dev/pci/drm/i915/display/intel_pch_display.c

61

static void assert_pch_hdmi_disabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pch_display.c

612

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_pch_display.c

614

lpt_disable_pch_transcoder(display);

sys/dev/pci/drm/i915/display/intel_pch_display.c

616

lpt_disable_iclkip(display);

sys/dev/pci/drm/i915/display/intel_pch_display.c

621

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_pch_display.c

625

if ((intel_de_read(display, LPT_TRANSCONF) & TRANS_ENABLE) == 0)

sys/dev/pci/drm/i915/display/intel_pch_display.c

630

tmp = intel_de_read(display, FDI_RX_CTL(PIPE_A));

sys/dev/pci/drm/i915/display/intel_pch_display.c

637

crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(display);

sys/dev/pci/drm/i915/display/intel_pch_display.c

640

void intel_pch_sanitize(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pch_display.c

642

if (HAS_PCH_IBX(display))

sys/dev/pci/drm/i915/display/intel_pch_display.c

643

ibx_sanitize_pch_ports(display);

sys/dev/pci/drm/i915/display/intel_pch_display.c

68

state = intel_sdvo_port_enabled(display, hdmi_reg, &port_pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

70

INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe,

sys/dev/pci/drm/i915/display/intel_pch_display.c

74

INTEL_DISPLAY_STATE_WARN(display,

sys/dev/pci/drm/i915/display/intel_pch_display.c

75

HAS_PCH_IBX(display) && !state && port_pipe == PIPE_B,

sys/dev/pci/drm/i915/display/intel_pch_display.c

80

static void assert_pch_ports_disabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pch_display.c

85

assert_pch_dp_disabled(display, pipe, PORT_B, PCH_DP_B);

sys/dev/pci/drm/i915/display/intel_pch_display.c

86

assert_pch_dp_disabled(display, pipe, PORT_C, PCH_DP_C);

sys/dev/pci/drm/i915/display/intel_pch_display.c

87

assert_pch_dp_disabled(display, pipe, PORT_D, PCH_DP_D);

sys/dev/pci/drm/i915/display/intel_pch_display.c

89

INTEL_DISPLAY_STATE_WARN(display,

sys/dev/pci/drm/i915/display/intel_pch_display.c

90

intel_crt_port_enabled(display, PCH_ADPA, &port_pipe) && port_pipe == pipe,

sys/dev/pci/drm/i915/display/intel_pch_display.c

94

INTEL_DISPLAY_STATE_WARN(display,

sys/dev/pci/drm/i915/display/intel_pch_display.c

95

intel_lvds_port_enabled(display, PCH_LVDS, &port_pipe) && port_pipe == pipe,

sys/dev/pci/drm/i915/display/intel_pch_display.h

19

bool intel_has_pch_trancoder(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pch_display.h

44

void intel_pch_sanitize(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_pch_display.h

46

static inline bool intel_has_pch_trancoder(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pch_display.h

93

static inline void intel_pch_sanitize(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

101

tmp = intel_sbi_read(display, 0x21C4, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

103

intel_sbi_write(display, 0x21C4, tmp, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

105

tmp = intel_sbi_read(display, 0x20EC, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

108

intel_sbi_write(display, 0x20EC, tmp, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

110

tmp = intel_sbi_read(display, 0x21EC, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

113

intel_sbi_write(display, 0x21EC, tmp, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

116

void lpt_disable_iclkip(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

120

intel_de_write(display, PIXCLK_GATE, PIXCLK_GATE_GATE);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

122

intel_sbi_lock(display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

124

temp = intel_sbi_read(display, SBI_SSCCTL6, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

126

intel_sbi_write(display, SBI_SSCCTL6, temp, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

128

intel_sbi_unlock(display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

18

static void lpt_fdi_reset_mphy(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

188

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

193

lpt_disable_iclkip(display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

196

drm_WARN_ON(display->drm, lpt_iclkip_freq(&p) != clock);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

199

drm_WARN_ON(display->drm, SBI_SSCDIVINTPHASE_DIVSEL(p.divsel) &

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

201

drm_WARN_ON(display->drm, SBI_SSCDIVINTPHASE_DIR(p.phasedir) &

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

204

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

208

intel_sbi_lock(display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

211

temp = intel_sbi_read(display, SBI_SSCDIVINTPHASE6, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

218

intel_sbi_write(display, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

22

intel_de_rmw(display, SOUTH_CHICKEN2, 0, FDI_MPHY_IOSFSB_RESET_CTL);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

221

temp = intel_sbi_read(display, SBI_SSCAUXDIV6, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

224

intel_sbi_write(display, SBI_SSCAUXDIV6, temp, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

227

temp = intel_sbi_read(display, SBI_SSCCTL6, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

229

intel_sbi_write(display, SBI_SSCCTL6, temp, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

231

intel_sbi_unlock(display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

236

intel_de_write(display, PIXCLK_GATE, PIXCLK_GATE_UNGATE);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

239

int lpt_get_iclkip(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

24

ret = intel_de_wait_custom(display, SOUTH_CHICKEN2,

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

244

if ((intel_de_read(display, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

249

intel_sbi_lock(display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

251

temp = intel_sbi_read(display, SBI_SSCCTL6, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

253

intel_sbi_unlock(display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

257

temp = intel_sbi_read(display, SBI_SSCDIVINTPHASE6, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

263

temp = intel_sbi_read(display, SBI_SSCAUXDIV6, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

267

intel_sbi_unlock(display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

28

drm_err(display->drm, "FDI mPHY reset assert timeout\n");

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

280

static void lpt_enable_clkout_dp(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

285

if (drm_WARN(display->drm, with_fdi && !with_spread,

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

288

if (drm_WARN(display->drm, HAS_PCH_LPT_LP(display) &&

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

292

intel_sbi_lock(display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

294

tmp = intel_sbi_read(display, SBI_SSCCTL, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

297

intel_sbi_write(display, SBI_SSCCTL, tmp, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

30

intel_de_rmw(display, SOUTH_CHICKEN2, FDI_MPHY_IOSFSB_RESET_CTL, 0);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

302

tmp = intel_sbi_read(display, SBI_SSCCTL, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

304

intel_sbi_write(display, SBI_SSCCTL, tmp, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

307

lpt_fdi_program_mphy(display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

310

reg = HAS_PCH_LPT_LP(display) ? SBI_GEN0 : SBI_DBUFF0;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

311

tmp = intel_sbi_read(display, reg, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

313

intel_sbi_write(display, reg, tmp, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

315

intel_sbi_unlock(display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

319

void lpt_disable_clkout_dp(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

32

ret = intel_de_wait_custom(display, SOUTH_CHICKEN2,

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

323

intel_sbi_lock(display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

325

reg = HAS_PCH_LPT_LP(display) ? SBI_GEN0 : SBI_DBUFF0;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

326

tmp = intel_sbi_read(display, reg, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

328

intel_sbi_write(display, reg, tmp, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

330

tmp = intel_sbi_read(display, SBI_SSCCTL, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

334

intel_sbi_write(display, SBI_SSCCTL, tmp, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

338

intel_sbi_write(display, SBI_SSCCTL, tmp, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

341

intel_sbi_unlock(display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

36

drm_err(display->drm, "FDI mPHY reset de-assert timeout\n");

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

376

static void lpt_bend_clkout_dp(struct intel_display *display, int steps)

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

381

if (drm_WARN_ON(display->drm, steps % 5 != 0))

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

384

if (drm_WARN_ON(display->drm, idx >= ARRAY_SIZE(sscdivintphase)))

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

387

intel_sbi_lock(display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

393

intel_sbi_write(display, SBI_SSCDITHPHASE, tmp, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

395

tmp = intel_sbi_read(display, SBI_SSCDIVINTPHASE, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

398

intel_sbi_write(display, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

40

static void lpt_fdi_program_mphy(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

400

intel_sbi_unlock(display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

405

static bool spll_uses_pch_ssc(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

407

u32 fuse_strap = intel_de_read(display, FUSE_STRAP);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

408

u32 ctl = intel_de_read(display, SPLL_CTL);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

417

if (display->platform.broadwell &&

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

424

static bool wrpll_uses_pch_ssc(struct intel_display *display, enum intel_dpll_id id)

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

426

u32 fuse_strap = intel_de_read(display, FUSE_STRAP);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

427

u32 ctl = intel_de_read(display, WRPLL_CTL(id));

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

435

if ((display->platform.broadwell || display->platform.haswell_ult) &&

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

44

lpt_fdi_reset_mphy(display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

443

static void lpt_init_pch_refclk(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

448

for_each_intel_encoder(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

46

tmp = intel_sbi_read(display, 0x8008, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

473

display->dpll.pch_ssc_use = 0;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

475

if (spll_uses_pch_ssc(display)) {

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

476

drm_dbg_kms(display->drm, "SPLL using PCH SSC\n");

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

477

display->dpll.pch_ssc_use |= BIT(DPLL_ID_SPLL);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

480

if (wrpll_uses_pch_ssc(display, DPLL_ID_WRPLL1)) {

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

481

drm_dbg_kms(display->drm, "WRPLL1 using PCH SSC\n");

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

482

display->dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL1);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

485

if (wrpll_uses_pch_ssc(display, DPLL_ID_WRPLL2)) {

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

486

drm_dbg_kms(display->drm, "WRPLL2 using PCH SSC\n");

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

487

display->dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL2);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

49

intel_sbi_write(display, 0x8008, tmp, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

490

if (display->dpll.pch_ssc_use)

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

494

lpt_bend_clkout_dp(display, 0);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

495

lpt_enable_clkout_dp(display, true, true);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

497

lpt_disable_clkout_dp(display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

501

static void ilk_init_pch_refclk(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

51

tmp = intel_sbi_read(display, 0x2008, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

515

for_each_intel_encoder(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

53

intel_sbi_write(display, 0x2008, tmp, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

531

if (HAS_PCH_IBX(display)) {

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

532

has_ck505 = display->vbt.display_clock_mode;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

540

for_each_dpll(display, pll, i) {

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

543

temp = intel_de_read(display, PCH_DPLL(pll->info->id));

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

55

tmp = intel_sbi_read(display, 0x2108, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

555

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

564

val = intel_de_read(display, PCH_DREF_CONTROL);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

57

intel_sbi_write(display, 0x2108, tmp, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

584

if (intel_panel_use_ssc(display) && can_ssc)

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

588

if (intel_panel_use_ssc(display) && can_ssc)

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

59

tmp = intel_sbi_read(display, 0x206C, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

61

intel_sbi_write(display, 0x206C, tmp, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

616

if (intel_panel_use_ssc(display) && can_ssc) {

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

617

drm_dbg_kms(display->drm, "Using SSC on panel\n");

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

624

intel_de_write(display, PCH_DREF_CONTROL, val);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

625

intel_de_posting_read(display, PCH_DREF_CONTROL);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

63

tmp = intel_sbi_read(display, 0x216C, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

632

if (intel_panel_use_ssc(display) && can_ssc) {

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

633

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

643

intel_de_write(display, PCH_DREF_CONTROL, val);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

644

intel_de_posting_read(display, PCH_DREF_CONTROL);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

647

drm_dbg_kms(display->drm, "Disabling CPU source output\n");

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

65

intel_sbi_write(display, 0x216C, tmp, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

654

intel_de_write(display, PCH_DREF_CONTROL, val);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

655

intel_de_posting_read(display, PCH_DREF_CONTROL);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

659

drm_dbg_kms(display->drm, "Disabling SSC source\n");

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

668

intel_de_write(display, PCH_DREF_CONTROL, val);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

669

intel_de_posting_read(display, PCH_DREF_CONTROL);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

67

tmp = intel_sbi_read(display, 0x2080, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

674

drm_WARN_ON(display->drm, val != final);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

680

void intel_init_pch_refclk(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

682

if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display))

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

683

ilk_init_pch_refclk(display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

684

else if (HAS_PCH_LPT(display))

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

685

lpt_init_pch_refclk(display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

70

intel_sbi_write(display, 0x2080, tmp, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

72

tmp = intel_sbi_read(display, 0x2180, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

75

intel_sbi_write(display, 0x2180, tmp, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

77

tmp = intel_sbi_read(display, 0x208C, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

80

intel_sbi_write(display, 0x208C, tmp, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

82

tmp = intel_sbi_read(display, 0x218C, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

85

intel_sbi_write(display, 0x218C, tmp, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

87

tmp = intel_sbi_read(display, 0x2098, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

90

intel_sbi_write(display, 0x2098, tmp, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

92

tmp = intel_sbi_read(display, 0x2198, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

95

intel_sbi_write(display, 0x2198, tmp, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

97

tmp = intel_sbi_read(display, 0x20C4, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

99

intel_sbi_write(display, 0x20C4, tmp, SBI_MPHY);

sys/dev/pci/drm/i915/display/intel_pch_refclk.h

16

void lpt_disable_iclkip(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.h

17

int lpt_get_iclkip(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.h

20

void intel_init_pch_refclk(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.h

21

void lpt_disable_clkout_dp(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_pch_refclk.h

26

static inline void lpt_disable_iclkip(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pch_refclk.h

29

static inline int lpt_get_iclkip(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pch_refclk.h

37

static inline void intel_init_pch_refclk(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pch_refclk.h

40

static inline void lpt_disable_clkout_dp(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pfit.c

110

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_pfit.c

122

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pfit.c

132

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pfit.c

145

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_pfit.c

151

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pfit.c

163

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_pfit.c

175

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pfit.c

188

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_pfit.c

21

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_pfit.c

260

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_pfit.c

33

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pfit.c

421

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_pfit.c

427

if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/intel_pfit.c

433

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pfit.c

441

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pfit.c

454

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_pfit.c

471

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pfit.c

478

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pfit.c

497

if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/intel_pfit.c

50

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pfit.c

511

if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/intel_pfit.c

527

if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/intel_pfit.c

537

if (DISPLAY_VER(display) < 4 && crtc_state->pipe_bpp == 18)

sys/dev/pci/drm/i915/display/intel_pfit.c

551

intel_pfit_mode_valid(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pfit.c

556

return skl_scaler_mode_valid(display, mode, output_format,

sys/dev/pci/drm/i915/display/intel_pfit.c

563

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_pfit.c

565

if (HAS_GMCH(display))

sys/dev/pci/drm/i915/display/intel_pfit.c

573

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_pfit.c

589

if (display->platform.ivybridge || display->platform.haswell)

sys/dev/pci/drm/i915/display/intel_pfit.c

590

intel_de_write_fw(display, PF_CTL(pipe), PF_ENABLE |

sys/dev/pci/drm/i915/display/intel_pfit.c

593

intel_de_write_fw(display, PF_CTL(pipe), PF_ENABLE |

sys/dev/pci/drm/i915/display/intel_pfit.c

595

intel_de_write_fw(display, PF_WIN_POS(pipe),

sys/dev/pci/drm/i915/display/intel_pfit.c

597

intel_de_write_fw(display, PF_WIN_SZ(pipe),

sys/dev/pci/drm/i915/display/intel_pfit.c

603

struct intel_display *display = to_intel_display(old_crtc_state);

sys/dev/pci/drm/i915/display/intel_pfit.c

61

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pfit.c

614

intel_de_write_fw(display, PF_CTL(pipe), 0);

sys/dev/pci/drm/i915/display/intel_pfit.c

615

intel_de_write_fw(display, PF_WIN_POS(pipe), 0);

sys/dev/pci/drm/i915/display/intel_pfit.c

616

intel_de_write_fw(display, PF_WIN_SZ(pipe), 0);

sys/dev/pci/drm/i915/display/intel_pfit.c

621

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_pfit.c

626

ctl = intel_de_read(display, PF_CTL(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_pfit.c

630

if (display->platform.ivybridge || display->platform.haswell)

sys/dev/pci/drm/i915/display/intel_pfit.c

637

pos = intel_de_read(display, PF_WIN_POS(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_pfit.c

638

size = intel_de_read(display, PF_WIN_SZ(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_pfit.c

651

drm_WARN_ON(display->drm, pipe != crtc->pipe);

sys/dev/pci/drm/i915/display/intel_pfit.c

656

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_pfit.c

666

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pfit.c

667

intel_de_read(display, PFIT_CONTROL(display)) & PFIT_ENABLE);

sys/dev/pci/drm/i915/display/intel_pfit.c

668

assert_transcoder_disabled(display, crtc_state->cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_pfit.c

670

intel_de_write(display, PFIT_PGM_RATIOS(display),

sys/dev/pci/drm/i915/display/intel_pfit.c

672

intel_de_write(display, PFIT_CONTROL(display),

sys/dev/pci/drm/i915/display/intel_pfit.c

679

intel_de_write(display, BCLRPAT(display, crtc->pipe), 0);

sys/dev/pci/drm/i915/display/intel_pfit.c

684

struct intel_display *display = to_intel_display(old_crtc_state);

sys/dev/pci/drm/i915/display/intel_pfit.c

689

assert_transcoder_disabled(display, old_crtc_state->cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_pfit.c

691

drm_dbg_kms(display->drm, "disabling pfit, current: 0x%08x\n",

sys/dev/pci/drm/i915/display/intel_pfit.c

692

intel_de_read(display, PFIT_CONTROL(display)));

sys/dev/pci/drm/i915/display/intel_pfit.c

693

intel_de_write(display, PFIT_CONTROL(display), 0);

sys/dev/pci/drm/i915/display/intel_pfit.c

696

static bool i9xx_has_pfit(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pfit.c

698

if (display->platform.i830)

sys/dev/pci/drm/i915/display/intel_pfit.c

701

return DISPLAY_VER(display) >= 4 ||

sys/dev/pci/drm/i915/display/intel_pfit.c

702

display->platform.pineview || display->platform.mobile;

sys/dev/pci/drm/i915/display/intel_pfit.c

707

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_pfit.c

712

if (!i9xx_has_pfit(display))

sys/dev/pci/drm/i915/display/intel_pfit.c

715

tmp = intel_de_read(display, PFIT_CONTROL(display));

sys/dev/pci/drm/i915/display/intel_pfit.c

72

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_pfit.c

720

if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/intel_pfit.c

730

intel_de_read(display, PFIT_PGM_RATIOS(display));

sys/dev/pci/drm/i915/display/intel_pfit.c

78

if (DISPLAY_VER(display) >= 8) {

sys/dev/pci/drm/i915/display/intel_pfit.c

81

} else if (DISPLAY_VER(display) >= 7) {

sys/dev/pci/drm/i915/display/intel_pfit.c

98

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pfit.h

25

intel_pfit_mode_valid(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

116

drm_WARN(display->drm, 1, "nonexisting DP port %c\n",

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

125

drm_modeset_unlock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

128

static int vlv_pipe_crc_ctl_reg(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

136

i9xx_pipe_crc_auto_source(display, pipe, source);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

151

if (!display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

173

u32 tmp = intel_de_read(display, PORT_DFT2_G4X(display));

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

189

intel_de_write(display, PORT_DFT2_G4X(display), tmp);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

195

static int i9xx_pipe_crc_ctl_reg(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

201

i9xx_pipe_crc_auto_source(display, pipe, source);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

208

if (!SUPPORTS_TV(display))

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

232

static void vlv_undo_pipe_scramble_reset(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

235

u32 tmp = intel_de_read(display, PORT_DFT2_G4X(display));

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

252

intel_de_write(display, PORT_DFT2_G4X(display), tmp);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

284

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

290

if (display->platform.i945gm || display->platform.i915gm)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

291

i915gm_irq_cstate_wa(display, enable);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

295

state = drm_atomic_state_alloc(display->drm);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

314

if (display->platform.haswell &&

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

330

drm_WARN(display->drm, ret,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

336

static int ivb_pipe_crc_ctl_reg(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

364

static int skl_pipe_crc_ctl_reg(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

407

static int get_new_crc_ctl_reg(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

411

if (DISPLAY_VER(display) == 2)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

413

else if (DISPLAY_VER(display) < 5)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

414

return i9xx_pipe_crc_ctl_reg(display, pipe, source, val);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

415

else if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

416

return vlv_pipe_crc_ctl_reg(display, pipe, source, val);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

417

else if (display->platform.ironlake || display->platform.sandybridge)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

419

else if (DISPLAY_VER(display) < 9)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

420

return ivb_pipe_crc_ctl_reg(display, pipe, source, val);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

422

return skl_pipe_crc_ctl_reg(display, pipe, source, val);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

450

static int i8xx_crc_source_valid(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

462

static int i9xx_crc_source_valid(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

475

static int vlv_crc_source_valid(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

490

static int ilk_crc_source_valid(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

504

static int ivb_crc_source_valid(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

518

static int skl_crc_source_valid(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

538

intel_is_valid_crc_source(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

541

if (DISPLAY_VER(display) == 2)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

542

return i8xx_crc_source_valid(display, source);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

543

else if (DISPLAY_VER(display) < 5)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

544

return i9xx_crc_source_valid(display, source);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

545

else if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

546

return vlv_crc_source_valid(display, source);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

547

else if (display->platform.ironlake || display->platform.sandybridge)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

548

return ilk_crc_source_valid(display, source);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

549

else if (DISPLAY_VER(display) < 9)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

550

return ivb_crc_source_valid(display, source);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

552

return skl_crc_source_valid(display, source);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

565

struct intel_display *display = to_intel_display(crtc->dev);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

569

drm_dbg_kms(display->drm, "unknown source %s\n", source_name);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

574

intel_is_valid_crc_source(display, source) == 0) {

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

585

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

596

drm_dbg_kms(display->drm, "unknown source %s\n", source_name);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

601

wakeref = intel_display_power_get_if_enabled(display, power_domain);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

603

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

612

ret = get_new_crc_ctl_reg(display, pipe, &source, &val);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

617

intel_de_write(display, PIPE_CRC_CTL(display, pipe), val);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

618

intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe));

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

621

if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

622

vlv_undo_pipe_scramble_reset(display, pipe);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

631

intel_display_power_put(display, power_domain, wakeref);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

638

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

646

if (get_new_crc_ctl_reg(display, pipe, &pipe_crc->source, &val) < 0)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

652

intel_de_write(display, PIPE_CRC_CTL(display, pipe), val);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

653

intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe));

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

658

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

659

struct drm_i915_private *dev_priv = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

668

intel_de_write(display, PIPE_CRC_CTL(display, pipe), 0);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

669

intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe));

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

78

static void i9xx_pipe_crc_auto_source(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

88

drm_modeset_lock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

89

for_each_intel_encoder(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_plane.c

1001

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_plane.c

1021

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_plane.c

1038

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_plane.c

1053

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_plane.c

1087

} else if (DISPLAY_VER(display) >= 20 &&

sys/dev/pci/drm/i915/display/intel_plane.c

1097

if ((DISPLAY_VERx100(display) == 2000 ||

sys/dev/pci/drm/i915/display/intel_plane.c

1098

DISPLAY_VERx100(display) == 3000 ||

sys/dev/pci/drm/i915/display/intel_plane.c

1099

DISPLAY_VERx100(display) == 3002) &&

sys/dev/pci/drm/i915/display/intel_plane.c

1111

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_plane.c

1119

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_plane.c

1182

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_plane.c

1244

intel_display_rps_mark_interactive(display, state, true);

sys/dev/pci/drm/i915/display/intel_plane.c

1265

struct intel_display *display = to_intel_display(plane->dev);

sys/dev/pci/drm/i915/display/intel_plane.c

1275

intel_display_rps_mark_interactive(display, state, false);

sys/dev/pci/drm/i915/display/intel_plane.c

1330

struct intel_display *display = to_intel_display(iplane);

sys/dev/pci/drm/i915/display/intel_plane.c

1338

intel_psr2_panic_force_full_update(display, crtc_state);

sys/dev/pci/drm/i915/display/intel_plane.c

1342

if (intel_fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) {

sys/dev/pci/drm/i915/display/intel_plane.c

1345

intel_fbdev_get_map(display->fbdev.fbdev, &map);

sys/dev/pci/drm/i915/display/intel_plane.c

1391

struct intel_display *display = to_intel_display(plane->dev);

sys/dev/pci/drm/i915/display/intel_plane.c

1404

if (intel_fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) {

sys/dev/pci/drm/i915/display/intel_plane.c

1405

intel_fbdev_get_map(display->fbdev.fbdev, &sb->map[0]);

sys/dev/pci/drm/i915/display/intel_plane.c

1467

struct intel_display *display = to_intel_display(uv_plane_state);

sys/dev/pci/drm/i915/display/intel_plane.c

1471

drm_dbg_kms(display->drm, "UV plane [PLANE:%d:%s] using Y plane [PLANE:%d:%s]\n",

sys/dev/pci/drm/i915/display/intel_plane.c

1503

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_plane.c

1514

drm_WARN_ON(display->drm, plane_state->uapi.visible);

sys/dev/pci/drm/i915/display/intel_plane.c

1528

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_plane.c

1535

if (DISPLAY_VER(display) < 11)

sys/dev/pci/drm/i915/display/intel_plane.c

1562

for_each_intel_plane_on_crtc(display->drm, crtc, y_plane) {

sys/dev/pci/drm/i915/display/intel_plane.c

1563

if (!icl_is_nv12_y_plane(display, y_plane->id))

sys/dev/pci/drm/i915/display/intel_plane.c

1577

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_plane.c

1594

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_plane.c

1597

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/intel_plane.c

1624

static bool active_planes_affects_min_cdclk(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_plane.c

1627

return display->platform.broadwell || display->platform.haswell ||

sys/dev/pci/drm/i915/display/intel_plane.c

1628

display->platform.cherryview || display->platform.valleyview ||

sys/dev/pci/drm/i915/display/intel_plane.c

1629

display->platform.ivybridge;

sys/dev/pci/drm/i915/display/intel_plane.c

1708

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_plane.c

1722

drm_dbg_atomic(display->drm,

sys/dev/pci/drm/i915/display/intel_plane.c

1742

if (!active_planes_affects_min_cdclk(display))

sys/dev/pci/drm/i915/display/intel_plane.c

175

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_plane.c

178

DISPLAY_INFO(display)->cursor_needs_physical;

sys/dev/pci/drm/i915/display/intel_plane.c

299

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_plane.c

344

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_plane.c

368

struct intel_display *display = to_intel_display(new_plane_state);

sys/dev/pci/drm/i915/display/intel_plane.c

372

if (DISPLAY_VER(display) < 12)

sys/dev/pci/drm/i915/display/intel_plane.c

462

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_plane.c

483

return DISPLAY_VER(display) < 9 || old_crtc_state->uapi.async_flip;

sys/dev/pci/drm/i915/display/intel_plane.c

587

struct intel_display *display = to_intel_display(new_crtc_state);

sys/dev/pci/drm/i915/display/intel_plane.c

596

if (DISPLAY_VER(display) >= 9 && plane->id != PLANE_CURSOR) {

sys/dev/pci/drm/i915/display/intel_plane.c

605

if (!was_crtc_enabled && drm_WARN_ON(display->drm, was_visible))

sys/dev/pci/drm/i915/display/intel_plane.c

629

drm_dbg_atomic(display->drm,

sys/dev/pci/drm/i915/display/intel_plane.c

639

if (HAS_GMCH(display) &&

sys/dev/pci/drm/i915/display/intel_plane.c

643

if ((display->platform.ironlake || display->platform.sandybridge || display->platform.ivybridge) &&

sys/dev/pci/drm/i915/display/intel_plane.c

736

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_plane.c

739

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/intel_plane.c

750

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_plane.c

757

struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe);

sys/dev/pci/drm/i915/display/intel_plane.c

988

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_plane.c

990

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_plane_initial.c

101

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_plane_initial.c

108

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_plane_initial.c

114

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_plane_initial.c

125

initial_plane_vma(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_plane_initial.c

128

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_plane_initial.c

140

if (!initial_plane_phys(display, plane_config))

sys/dev/pci/drm/i915/display/intel_plane_initial.c

159

drm_dbg_kms(display->drm, "Initial FB size exceeds half of stolen, discarding\n");

sys/dev/pci/drm/i915/display/intel_plane_initial.c

167

drm_dbg_kms(display->drm, "Failed to preallocate initial FB in %s\n",

sys/dev/pci/drm/i915/display/intel_plane_initial.c

245

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_plane_initial.c

262

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_plane_initial.c

274

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_plane_initial.c

280

vma = initial_plane_vma(display, plane_config);

sys/dev/pci/drm/i915/display/intel_plane_initial.c

29

struct intel_display *display = to_intel_display(this);

sys/dev/pci/drm/i915/display/intel_plane_initial.c

294

drm_dbg_kms(display->drm, "intel fb init failed\n");

sys/dev/pci/drm/i915/display/intel_plane_initial.c

32

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_plane_initial.c

403

void intel_initial_plane_config(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_plane_initial.c

408

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/intel_plane_initial.c

422

display->funcs.display->get_initial_plane_config(crtc, plane_config);

sys/dev/pci/drm/i915/display/intel_plane_initial.c

430

if (display->funcs.display->fixup_initial_plane_config(crtc, plane_config))

sys/dev/pci/drm/i915/display/intel_plane_initial.c

57

initial_plane_memory_type(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_plane_initial.c

59

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_plane_initial.c

61

if (display->platform.dgfx)

sys/dev/pci/drm/i915/display/intel_plane_initial.c

70

initial_plane_phys(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_plane_initial.c

73

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_plane_initial.c

81

mem_type = initial_plane_memory_type(display);

sys/dev/pci/drm/i915/display/intel_plane_initial.c

84

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_plane_initial.c

95

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_plane_initial.h

12

void intel_initial_plane_config(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

108

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

111

&display->pmdemand.obj);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

119

int intel_pmdemand_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pmdemand.c

127

intel_atomic_global_obj_init(display, &display->pmdemand.obj,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

131

if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_C0))

sys/dev/pci/drm/i915/display/intel_pmdemand.c

133

intel_de_rmw(display, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

138

void intel_pmdemand_init_early(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pmdemand.c

140

rw_init(&display->pmdemand.lock, "pmdem");

sys/dev/pci/drm/i915/display/intel_pmdemand.c

141

init_waitqueue_head(&display->pmdemand.waitqueue);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

145

intel_pmdemand_update_phys_mask(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

152

if (DISPLAY_VER(display) < 14)

sys/dev/pci/drm/i915/display/intel_pmdemand.c

170

intel_pmdemand_update_port_clock(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

174

if (DISPLAY_VER(display) < 14)

sys/dev/pci/drm/i915/display/intel_pmdemand.c

181

intel_pmdemand_update_max_ddiclk(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

191

intel_pmdemand_update_port_clock(display, pmdemand_state,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

202

intel_pmdemand_update_connector_phys(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

223

intel_pmdemand_update_phys_mask(display, encoder, pmdemand_state,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

228

intel_pmdemand_update_active_non_tc_phys(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

243

intel_pmdemand_update_connector_phys(display, state,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

248

intel_pmdemand_update_connector_phys(display, state,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

259

intel_pmdemand_encoder_has_tc_phy(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

268

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

285

(intel_pmdemand_encoder_has_tc_phy(display, old_encoder) &&

sys/dev/pci/drm/i915/display/intel_pmdemand.c

286

intel_pmdemand_encoder_has_tc_phy(display, new_encoder)))

sys/dev/pci/drm/i915/display/intel_pmdemand.c

320

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

326

if (DISPLAY_VER(display) < 14)

sys/dev/pci/drm/i915/display/intel_pmdemand.c

348

if (DISPLAY_VER(display) < 30) {

sys/dev/pci/drm/i915/display/intel_pmdemand.c

355

min_t(u8, intel_dbuf_num_active_pipes(new_dbuf_state), INTEL_NUM_PIPES(display));

sys/dev/pci/drm/i915/display/intel_pmdemand.c

367

intel_pmdemand_update_max_ddiclk(display, state, new_pmdemand_state);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

369

intel_pmdemand_update_active_non_tc_phys(display, state, new_pmdemand_state);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

390

static bool intel_pmdemand_check_prev_transaction(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pmdemand.c

392

return !(intel_de_wait_for_clear(display,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

395

intel_de_wait_for_clear(display,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

401

intel_pmdemand_init_pmdemand_params(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

406

if (DISPLAY_VER(display) < 14)

sys/dev/pci/drm/i915/display/intel_pmdemand.c

409

mutex_lock(&display->pmdemand.lock);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

410

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

411

!intel_pmdemand_check_prev_transaction(display))) {

sys/dev/pci/drm/i915/display/intel_pmdemand.c

417

reg1 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0));

sys/dev/pci/drm/i915/display/intel_pmdemand.c

419

reg2 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1));

sys/dev/pci/drm/i915/display/intel_pmdemand.c

435

if (DISPLAY_VER(display) >= 30) {

sys/dev/pci/drm/i915/display/intel_pmdemand.c

449

mutex_unlock(&display->pmdemand.lock);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

452

static bool intel_pmdemand_req_complete(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pmdemand.c

454

return !(intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &

sys/dev/pci/drm/i915/display/intel_pmdemand.c

458

static void intel_pmdemand_poll(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pmdemand.c

464

ret = intel_de_wait_custom(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1),

sys/dev/pci/drm/i915/display/intel_pmdemand.c

469

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

474

static void intel_pmdemand_wait(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pmdemand.c

477

if (DISPLAY_VER(display) == 20) {

sys/dev/pci/drm/i915/display/intel_pmdemand.c

478

intel_pmdemand_poll(display);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

480

if (!wait_event_timeout(display->pmdemand.waitqueue,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

481

intel_pmdemand_req_complete(display),

sys/dev/pci/drm/i915/display/intel_pmdemand.c

483

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

489

void intel_pmdemand_program_dbuf(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

495

if (DISPLAY_VER(display) >= 30)

sys/dev/pci/drm/i915/display/intel_pmdemand.c

498

mutex_lock(&display->pmdemand.lock);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

499

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

500

!intel_pmdemand_check_prev_transaction(display)))

sys/dev/pci/drm/i915/display/intel_pmdemand.c

503

intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0),

sys/dev/pci/drm/i915/display/intel_pmdemand.c

506

intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

509

intel_pmdemand_wait(display);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

512

mutex_unlock(&display->pmdemand.lock);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

516

intel_pmdemand_update_params(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

559

if (DISPLAY_VER(display) >= 30) {

sys/dev/pci/drm/i915/display/intel_pmdemand.c

572

intel_pmdemand_program_params(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

581

mutex_lock(&display->pmdemand.lock);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

582

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

583

!intel_pmdemand_check_prev_transaction(display)))

sys/dev/pci/drm/i915/display/intel_pmdemand.c

586

reg1 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0));

sys/dev/pci/drm/i915/display/intel_pmdemand.c

589

reg2 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1));

sys/dev/pci/drm/i915/display/intel_pmdemand.c

592

intel_pmdemand_update_params(display, new, old, &mod_reg1, &mod_reg2,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

596

intel_de_write(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0),

sys/dev/pci/drm/i915/display/intel_pmdemand.c

602

intel_de_write(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1),

sys/dev/pci/drm/i915/display/intel_pmdemand.c

611

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

615

intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

618

intel_pmdemand_wait(display);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

621

mutex_unlock(&display->pmdemand.lock);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

633

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

639

if (DISPLAY_VER(display) < 14)

sys/dev/pci/drm/i915/display/intel_pmdemand.c

649

intel_pmdemand_program_params(display, new_pmdemand_state,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

656

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

662

if (DISPLAY_VER(display) < 14)

sys/dev/pci/drm/i915/display/intel_pmdemand.c

672

intel_pmdemand_program_params(display, new_pmdemand_state, NULL,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

80

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

83

&display->pmdemand.obj);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

94

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

97

&display->pmdemand.obj);

sys/dev/pci/drm/i915/display/intel_pmdemand.h

22

void intel_pmdemand_init_early(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_pmdemand.h

23

int intel_pmdemand_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_pmdemand.h

24

void intel_pmdemand_init_pmdemand_params(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pmdemand.h

26

void intel_pmdemand_update_port_clock(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pmdemand.h

29

void intel_pmdemand_update_phys_mask(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pmdemand.h

33

void intel_pmdemand_program_dbuf(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pps.c

1001

if (IS_DISPLAY_VER(display, 13, 14))

sys/dev/pci/drm/i915/display/intel_pps.c

1002

intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,

sys/dev/pci/drm/i915/display/intel_pps.c

1006

if (!display->platform.ironlake)

sys/dev/pci/drm/i915/display/intel_pps.c

1009

intel_de_write(display, pp_ctrl_reg, pp);

sys/dev/pci/drm/i915/display/intel_pps.c

1010

intel_de_posting_read(display, pp_ctrl_reg);

sys/dev/pci/drm/i915/display/intel_pps.c

1015

if (IS_DISPLAY_VER(display, 13, 14))

sys/dev/pci/drm/i915/display/intel_pps.c

1016

intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,

sys/dev/pci/drm/i915/display/intel_pps.c

1019

if (display->platform.ironlake) {

sys/dev/pci/drm/i915/display/intel_pps.c

1021

intel_de_write(display, pp_ctrl_reg, pp);

sys/dev/pci/drm/i915/display/intel_pps.c

1022

intel_de_posting_read(display, pp_ctrl_reg);

sys/dev/pci/drm/i915/display/intel_pps.c

1039

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

1044

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

1049

drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power off\n",

sys/dev/pci/drm/i915/display/intel_pps.c

105

if (drm_WARN(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

1053

drm_WARN(display->drm, !intel_dp->pps.want_panel_vdd,

sys/dev/pci/drm/i915/display/intel_pps.c

106

intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN,

sys/dev/pci/drm/i915/display/intel_pps.c

1068

intel_de_write(display, pp_ctrl_reg, pp);

sys/dev/pci/drm/i915/display/intel_pps.c

1069

intel_de_posting_read(display, pp_ctrl_reg);

sys/dev/pci/drm/i915/display/intel_pps.c

1077

intel_display_power_put(display,

sys/dev/pci/drm/i915/display/intel_pps.c

1096

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

1114

intel_de_write(display, pp_ctrl_reg, pp);

sys/dev/pci/drm/i915/display/intel_pps.c

1115

intel_de_posting_read(display, pp_ctrl_reg);

sys/dev/pci/drm/i915/display/intel_pps.c

112

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

1122

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

1135

intel_de_write(display, pp_ctrl_reg, pp);

sys/dev/pci/drm/i915/display/intel_pps.c

1136

intel_de_posting_read(display, pp_ctrl_reg);

sys/dev/pci/drm/i915/display/intel_pps.c

1149

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_pps.c

1160

drm_dbg_kms(display->drm, "panel power control backlight %s\n",

sys/dev/pci/drm/i915/display/intel_pps.c

1171

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

1174

i915_reg_t pp_on_reg = PP_ON_DELAYS(display, pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

1176

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);

sys/dev/pci/drm/i915/display/intel_pps.c

1178

if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))

sys/dev/pci/drm/i915/display/intel_pps.c

1192

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

1196

intel_de_write(display, pp_on_reg, 0);

sys/dev/pci/drm/i915/display/intel_pps.c

1197

intel_de_posting_read(display, pp_on_reg);

sys/dev/pci/drm/i915/display/intel_pps.c

120

DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;

sys/dev/pci/drm/i915/display/intel_pps.c

1202

static void vlv_steal_power_sequencer(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pps.c

1207

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

1209

for_each_intel_dp(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_pps.c

1212

drm_WARN(display->drm, intel_dp->pps.vlv_active_pipe == pipe,

sys/dev/pci/drm/i915/display/intel_pps.c

1220

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

1232

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

1236

if (g4x_dp_port_enabled(display, intel_dp->output_reg,

sys/dev/pci/drm/i915/display/intel_pps.c

125

if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_pps.c

1283

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_pps.c

1287

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

1289

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);

sys/dev/pci/drm/i915/display/intel_pps.c

130

pll_enabled = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;

sys/dev/pci/drm/i915/display/intel_pps.c

1305

vlv_steal_power_sequencer(display, crtc->pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

1315

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

1339

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

1342

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

1353

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

1357

drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);

sys/dev/pci/drm/i915/display/intel_pps.c

1358

intel_dp->pps.vdd_wakeref = intel_display_power_get(display,

sys/dev/pci/drm/i915/display/intel_pps.c

137

release_cl_override = display->platform.cherryview &&

sys/dev/pci/drm/i915/display/intel_pps.c

138

!chv_phy_powergate_ch(display, phy, ch, true);

sys/dev/pci/drm/i915/display/intel_pps.c

1391

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

140

if (vlv_force_pll_on(display, pipe, vlv_get_dpll(display))) {

sys/dev/pci/drm/i915/display/intel_pps.c

1400

if (!HAS_DDI(display))

sys/dev/pci/drm/i915/display/intel_pps.c

1401

intel_de_write(display, regs.pp_ctrl, pp_ctl);

sys/dev/pci/drm/i915/display/intel_pps.c

1403

pp_on = intel_de_read(display, regs.pp_on);

sys/dev/pci/drm/i915/display/intel_pps.c

1404

pp_off = intel_de_read(display, regs.pp_off);

sys/dev/pci/drm/i915/display/intel_pps.c

141

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

1415

pp_div = intel_de_read(display, regs.pp_div);

sys/dev/pci/drm/i915/display/intel_pps.c

1430

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

1432

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

1441

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

1452

drm_err(display->drm, "PPS state mismatch\n");

sys/dev/pci/drm/i915/display/intel_pps.c

1479

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

1481

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

1494

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

1508

if (intel_has_quirk(display, QUIRK_INCREASE_T12_DELAY)) {

sys/dev/pci/drm/i915/display/intel_pps.c

1510

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

1521

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

1523

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

1537

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

154

intel_de_write(display, intel_dp->output_reg, DP);

sys/dev/pci/drm/i915/display/intel_pps.c

1541

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

155

intel_de_posting_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/intel_pps.c

1569

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

157

intel_de_write(display, intel_dp->output_reg, DP | DP_PORT_EN);

sys/dev/pci/drm/i915/display/intel_pps.c

1575

drm_dbg_kms(display->drm, "backlight on delay %d, off delay %d\n",

sys/dev/pci/drm/i915/display/intel_pps.c

158

intel_de_posting_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/intel_pps.c

1599

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

160

intel_de_write(display, intel_dp->output_reg, DP & ~DP_PORT_EN);

sys/dev/pci/drm/i915/display/intel_pps.c

1601

int div = DISPLAY_RUNTIME_INFO(display)->rawclk_freq / 1000;

sys/dev/pci/drm/i915/display/intel_pps.c

1606

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

161

intel_de_posting_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/intel_pps.c

1625

drm_WARN(display->drm, pp & PANEL_POWER_ON,

sys/dev/pci/drm/i915/display/intel_pps.c

1629

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

1634

intel_de_write(display, regs.pp_ctrl, pp);

sys/dev/pci/drm/i915/display/intel_pps.c

164

vlv_force_pll_off(display, pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

1644

if (display->platform.valleyview || display->platform.cherryview) {

sys/dev/pci/drm/i915/display/intel_pps.c

1646

} else if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display)) {

sys/dev/pci/drm/i915/display/intel_pps.c

1665

intel_de_write(display, regs.pp_on, pp_on);

sys/dev/pci/drm/i915/display/intel_pps.c

1666

intel_de_write(display, regs.pp_off, pp_off);

sys/dev/pci/drm/i915/display/intel_pps.c

167

chv_phy_powergate_ch(display, phy, ch, false);

sys/dev/pci/drm/i915/display/intel_pps.c

1672

intel_de_write(display, regs.pp_div,

sys/dev/pci/drm/i915/display/intel_pps.c

1678

intel_de_rmw(display, regs.pp_ctrl, BXT_POWER_CYCLE_DELAY_MASK,

sys/dev/pci/drm/i915/display/intel_pps.c

1682

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

1684

intel_de_read(display, regs.pp_on),

sys/dev/pci/drm/i915/display/intel_pps.c

1685

intel_de_read(display, regs.pp_off),

sys/dev/pci/drm/i915/display/intel_pps.c

1687

intel_de_read(display, regs.pp_div) :

sys/dev/pci/drm/i915/display/intel_pps.c

1688

(intel_de_read(display, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));

sys/dev/pci/drm/i915/display/intel_pps.c

1693

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

1704

if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_pps.c

171

static enum pipe vlv_find_free_pps(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pps.c

1739

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

1743

if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_pps.c

1746

if (intel_num_pps(display) < 2)

sys/dev/pci/drm/i915/display/intel_pps.c

1749

drm_WARN(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

1779

void intel_pps_unlock_regs_wa(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pps.c

1784

if (!HAS_DISPLAY(display) || HAS_DDI(display))

sys/dev/pci/drm/i915/display/intel_pps.c

1790

pps_num = intel_num_pps(display);

sys/dev/pci/drm/i915/display/intel_pps.c

1793

intel_de_rmw(display, PP_CONTROL(display, pps_idx),

sys/dev/pci/drm/i915/display/intel_pps.c

1797

void intel_pps_setup(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pps.c

1799

if (HAS_PCH_SPLIT(display) || display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_pps.c

180

for_each_intel_dp(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_pps.c

1800

display->pps.mmio_base = PCH_PPS_BASE;

sys/dev/pci/drm/i915/display/intel_pps.c

1801

else if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_pps.c

1802

display->pps.mmio_base = VLV_PPS_BASE;

sys/dev/pci/drm/i915/display/intel_pps.c

1804

display->pps.mmio_base = PPS_BASE;

sys/dev/pci/drm/i915/display/intel_pps.c

184

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

1840

void assert_pps_unlocked(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_pps.c

1847

if (drm_WARN_ON(display->drm, HAS_DDI(display)))

sys/dev/pci/drm/i915/display/intel_pps.c

1850

if (HAS_PCH_SPLIT(display)) {

sys/dev/pci/drm/i915/display/intel_pps.c

1853

pp_reg = PP_CONTROL(display, 0);

sys/dev/pci/drm/i915/display/intel_pps.c

1854

port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) &

sys/dev/pci/drm/i915/display/intel_pps.c

1859

intel_lvds_port_enabled(display, PCH_LVDS, &panel_pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

1862

g4x_dp_port_enabled(display, DP_A, PORT_A, &panel_pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

1865

g4x_dp_port_enabled(display, PCH_DP_C, PORT_C, &panel_pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

1868

g4x_dp_port_enabled(display, PCH_DP_D, PORT_D, &panel_pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

1874

} else if (display->platform.valleyview || display->platform.cherryview) {

sys/dev/pci/drm/i915/display/intel_pps.c

1876

pp_reg = PP_CONTROL(display, pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

1881

pp_reg = PP_CONTROL(display, 0);

sys/dev/pci/drm/i915/display/intel_pps.c

1882

port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) &

sys/dev/pci/drm/i915/display/intel_pps.c

1885

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

1887

intel_lvds_port_enabled(display, LVDS, &panel_pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

1890

val = intel_de_read(display, pp_reg);

sys/dev/pci/drm/i915/display/intel_pps.c

1895

INTEL_DISPLAY_STATE_WARN(display, panel_pipe == pipe && locked,

sys/dev/pci/drm/i915/display/intel_pps.c

192

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

209

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

213

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

216

drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp));

sys/dev/pci/drm/i915/display/intel_pps.c

218

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE &&

sys/dev/pci/drm/i915/display/intel_pps.c

224

pipe = vlv_find_free_pps(display);

sys/dev/pci/drm/i915/display/intel_pps.c

230

if (drm_WARN_ON(display->drm, pipe == INVALID_PIPE))

sys/dev/pci/drm/i915/display/intel_pps.c

233

vlv_steal_power_sequencer(display, pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

236

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

257

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

260

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

263

drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp));

sys/dev/pci/drm/i915/display/intel_pps.c

27

static void vlv_steal_power_sequencer(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pps.c

279

typedef bool (*pps_check)(struct intel_display *display, int pps_idx);

sys/dev/pci/drm/i915/display/intel_pps.c

281

static bool pps_has_pp_on(struct intel_display *display, int pps_idx)

sys/dev/pci/drm/i915/display/intel_pps.c

283

return intel_de_read(display, PP_STATUS(display, pps_idx)) & PP_ON;

sys/dev/pci/drm/i915/display/intel_pps.c

286

static bool pps_has_vdd_on(struct intel_display *display, int pps_idx)

sys/dev/pci/drm/i915/display/intel_pps.c

288

return intel_de_read(display, PP_CONTROL(display, pps_idx)) & EDP_FORCE_VDD;

sys/dev/pci/drm/i915/display/intel_pps.c

291

static bool pps_any(struct intel_display *display, int pps_idx)

sys/dev/pci/drm/i915/display/intel_pps.c

297

vlv_initial_pps_pipe(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_pps.c

303

u32 port_sel = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_pps.c

304

PP_ON_DELAYS(display, pipe)) &

sys/dev/pci/drm/i915/display/intel_pps.c

310

if (!check(display, pipe))

sys/dev/pci/drm/i915/display/intel_pps.c

322

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

326

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

330

intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,

sys/dev/pci/drm/i915/display/intel_pps.c

334

intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,

sys/dev/pci/drm/i915/display/intel_pps.c

338

intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,

sys/dev/pci/drm/i915/display/intel_pps.c

343

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

349

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

35

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

355

static int intel_num_pps(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pps.c

357

if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_pps.c

360

if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_pps.c

363

if (INTEL_PCH_TYPE(display) >= PCH_MTL)

sys/dev/pci/drm/i915/display/intel_pps.c

366

if (INTEL_PCH_TYPE(display) >= PCH_DG1)

sys/dev/pci/drm/i915/display/intel_pps.c

369

if (INTEL_PCH_TYPE(display) >= PCH_ICP)

sys/dev/pci/drm/i915/display/intel_pps.c

377

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

38

if (display->platform.valleyview || display->platform.cherryview) {

sys/dev/pci/drm/i915/display/intel_pps.c

380

INTEL_PCH_TYPE(display) >= PCH_ICP &&

sys/dev/pci/drm/i915/display/intel_pps.c

381

INTEL_PCH_TYPE(display) <= PCH_ADP)

sys/dev/pci/drm/i915/display/intel_pps.c

382

return intel_de_read(display, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;

sys/dev/pci/drm/i915/display/intel_pps.c

388

bxt_initial_pps_idx(struct intel_display *display, pps_check check)

sys/dev/pci/drm/i915/display/intel_pps.c

390

int pps_idx, pps_num = intel_num_pps(display);

sys/dev/pci/drm/i915/display/intel_pps.c

393

if (check(display, pps_idx))

sys/dev/pci/drm/i915/display/intel_pps.c

403

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

407

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

409

if (display->platform.valleyview || display->platform.cherryview) {

sys/dev/pci/drm/i915/display/intel_pps.c

415

if (intel_num_pps(display) > 1)

sys/dev/pci/drm/i915/display/intel_pps.c

420

if (drm_WARN_ON(display->drm, intel_dp->pps.pps_idx >= intel_num_pps(display)))

sys/dev/pci/drm/i915/display/intel_pps.c

425

intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_pp_on);

sys/dev/pci/drm/i915/display/intel_pps.c

428

intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_vdd_on);

sys/dev/pci/drm/i915/display/intel_pps.c

431

intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_any);

sys/dev/pci/drm/i915/display/intel_pps.c

433

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

438

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

447

void vlv_pps_reset_all(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pps.c

451

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_pps.c

464

for_each_intel_dp(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_pps.c

467

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);

sys/dev/pci/drm/i915/display/intel_pps.c

474

void bxt_pps_reset_all(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pps.c

478

if (!HAS_DISPLAY(display))

sys/dev/pci/drm/i915/display/intel_pps.c

483

for_each_intel_dp(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_pps.c

502

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

507

if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_pps.c

509

else if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/intel_pps.c

514

regs->pp_ctrl = PP_CONTROL(display, pps_idx);

sys/dev/pci/drm/i915/display/intel_pps.c

515

regs->pp_stat = PP_STATUS(display, pps_idx);

sys/dev/pci/drm/i915/display/intel_pps.c

516

regs->pp_on = PP_ON_DELAYS(display, pps_idx);

sys/dev/pci/drm/i915/display/intel_pps.c

517

regs->pp_off = PP_OFF_DELAYS(display, pps_idx);

sys/dev/pci/drm/i915/display/intel_pps.c

520

if (display->platform.geminilake || display->platform.broxton ||

sys/dev/pci/drm/i915/display/intel_pps.c

521

INTEL_PCH_TYPE(display) >= PCH_CNP)

sys/dev/pci/drm/i915/display/intel_pps.c

524

regs->pp_div = PP_DIVISOR(display, pps_idx);

sys/dev/pci/drm/i915/display/intel_pps.c

549

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

551

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

553

if ((display->platform.valleyview || display->platform.cherryview) &&

sys/dev/pci/drm/i915/display/intel_pps.c

557

return (intel_de_read(display, _pp_stat_reg(intel_dp)) & PP_ON) != 0;

sys/dev/pci/drm/i915/display/intel_pps.c

562

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

564

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

566

if ((display->platform.valleyview || display->platform.cherryview) &&

sys/dev/pci/drm/i915/display/intel_pps.c

570

return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;

sys/dev/pci/drm/i915/display/intel_pps.c

575

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

582

drm_WARN(display->drm, 1,

sys/dev/pci/drm/i915/display/intel_pps.c

586

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

590

intel_de_read(display, _pp_stat_reg(intel_dp)),

sys/dev/pci/drm/i915/display/intel_pps.c

591

intel_de_read(display, _pp_ctrl_reg(intel_dp)));

sys/dev/pci/drm/i915/display/intel_pps.c

609

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

615

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

622

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

627

intel_de_read(display, pp_stat_reg),

sys/dev/pci/drm/i915/display/intel_pps.c

628

intel_de_read(display, pp_ctrl_reg));

sys/dev/pci/drm/i915/display/intel_pps.c

630

ret = poll_timeout_us(val = intel_de_read(display, pp_stat_reg),

sys/dev/pci/drm/i915/display/intel_pps.c

634

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

638

intel_de_read(display, pp_stat_reg),

sys/dev/pci/drm/i915/display/intel_pps.c

639

intel_de_read(display, pp_ctrl_reg));

sys/dev/pci/drm/i915/display/intel_pps.c

643

drm_dbg_kms(display->drm, "Wait complete\n");

sys/dev/pci/drm/i915/display/intel_pps.c

648

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

651

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

660

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

663

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

672

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

684

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

71

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

726

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

729

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

731

control = intel_de_read(display, _pp_ctrl_reg(intel_dp));

sys/dev/pci/drm/i915/display/intel_pps.c

732

if (drm_WARN_ON(display->drm, !HAS_DDI(display) &&

sys/dev/pci/drm/i915/display/intel_pps.c

747

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

756

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

764

drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);

sys/dev/pci/drm/i915/display/intel_pps.c

765

intel_dp->pps.vdd_wakeref = intel_display_power_get(display,

sys/dev/pci/drm/i915/display/intel_pps.c

77

wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE);

sys/dev/pci/drm/i915/display/intel_pps.c

771

drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD on\n",

sys/dev/pci/drm/i915/display/intel_pps.c

78

mutex_lock(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

781

intel_de_write(display, pp_ctrl_reg, pp);

sys/dev/pci/drm/i915/display/intel_pps.c

782

intel_de_posting_read(display, pp_ctrl_reg);

sys/dev/pci/drm/i915/display/intel_pps.c

783

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

787

intel_de_read(display, pp_stat_reg),

sys/dev/pci/drm/i915/display/intel_pps.c

788

intel_de_read(display, pp_ctrl_reg));

sys/dev/pci/drm/i915/display/intel_pps.c

793

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

812

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

822

INTEL_DISPLAY_STATE_WARN(display, !vdd, "[ENCODER:%d:%s] %s VDD already requested on\n",

sys/dev/pci/drm/i915/display/intel_pps.c

830

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

835

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

837

drm_WARN_ON(display->drm, intel_dp->pps.want_panel_vdd);

sys/dev/pci/drm/i915/display/intel_pps.c

842

drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD off\n",

sys/dev/pci/drm/i915/display/intel_pps.c

852

intel_de_write(display, pp_ctrl_reg, pp);

sys/dev/pci/drm/i915/display/intel_pps.c

853

intel_de_posting_read(display, pp_ctrl_reg);

sys/dev/pci/drm/i915/display/intel_pps.c

856

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_pps.c

86

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

860

intel_de_read(display, pp_stat_reg),

sys/dev/pci/drm/i915/display/intel_pps.c

861

intel_de_read(display, pp_ctrl_reg));

sys/dev/pci/drm/i915/display/intel_pps.c

868

intel_display_power_put(display,

sys/dev/pci/drm/i915/display/intel_pps.c

88

mutex_unlock(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

89

intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);

sys/dev/pci/drm/i915/display/intel_pps.c

904

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

920

queue_delayed_work(display->wq.unordered,

sys/dev/pci/drm/i915/display/intel_pps.c

931

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

936

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

938

INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd,

sys/dev/pci/drm/i915/display/intel_pps.c

965

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

969

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

97

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

974

drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power on\n",

sys/dev/pci/drm/i915/display/intel_pps.c

979

if (drm_WARN(display->drm, edp_have_panel_power(intel_dp),

sys/dev/pci/drm/i915/display/intel_pps.c

990

if (display->platform.ironlake) {

sys/dev/pci/drm/i915/display/intel_pps.c

993

intel_de_write(display, pp_ctrl_reg, pp);

sys/dev/pci/drm/i915/display/intel_pps.c

994

intel_de_posting_read(display, pp_ctrl_reg);

sys/dev/pci/drm/i915/display/intel_pps.h

55

void vlv_pps_reset_all(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_pps.h

56

void bxt_pps_reset_all(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_pps.h

58

void intel_pps_unlock_regs_wa(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_pps.h

59

void intel_pps_setup(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_pps.h

63

void assert_pps_unlocked(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_pps_regs.h

16

#define _MMIO_PPS(display, pps_idx, reg) \

sys/dev/pci/drm/i915/display/intel_pps_regs.h

17

_MMIO((display)->pps.mmio_base - PPS_BASE + (reg) + (pps_idx) * 0x100)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

20

#define PP_STATUS(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_STATUS)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

47

#define PP_CONTROL(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_CONTROL)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

57

#define PP_ON_DELAYS(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_ON_DELAYS)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

68

#define PP_OFF_DELAYS(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_OFF_DELAYS)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

73

#define PP_DIVISOR(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_DIVISOR)

sys/dev/pci/drm/i915/display/intel_psr.c

1009

intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_psr.c

1013

intel_de_rmw(display,

sys/dev/pci/drm/i915/display/intel_psr.c

1014

PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder),

sys/dev/pci/drm/i915/display/intel_psr.c

1017

intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,

sys/dev/pci/drm/i915/display/intel_psr.c

1023

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

1030

if ((DISPLAY_VER(display) == 20 ||

sys/dev/pci/drm/i915/display/intel_psr.c

1031

IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&

sys/dev/pci/drm/i915/display/intel_psr.c

1038

if (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p)

sys/dev/pci/drm/i915/display/intel_psr.c

1041

if (DISPLAY_VER(display) >= 10 && DISPLAY_VER(display) < 13)

sys/dev/pci/drm/i915/display/intel_psr.c

1048

if (DISPLAY_VER(display) >= 12 && DISPLAY_VER(display) < 20) {

sys/dev/pci/drm/i915/display/intel_psr.c

1056

if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_E0)) {

sys/dev/pci/drm/i915/display/intel_psr.c

1079

} else if (DISPLAY_VER(display) >= 20) {

sys/dev/pci/drm/i915/display/intel_psr.c

1081

} else if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_psr.c

1084

} else if (DISPLAY_VER(display) >= 9) {

sys/dev/pci/drm/i915/display/intel_psr.c

1092

if (DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/intel_psr.c

1098

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_psr.c

1099

PSR2_MAN_TRK_CTL(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_psr.c

1100

drm_WARN_ON(display->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));

sys/dev/pci/drm/i915/display/intel_psr.c

1101

} else if (HAS_PSR2_SEL_FETCH(display)) {

sys/dev/pci/drm/i915/display/intel_psr.c

1102

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_psr.c

1103

PSR2_MAN_TRK_CTL(display, cpu_transcoder), 0);

sys/dev/pci/drm/i915/display/intel_psr.c

1113

intel_de_write(display, psr_ctl_reg(display, cpu_transcoder), psr_val);

sys/dev/pci/drm/i915/display/intel_psr.c

1115

intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), val);

sys/dev/pci/drm/i915/display/intel_psr.c

1119

transcoder_has_psr2(struct intel_display *display, enum transcoder cpu_transcoder)

sys/dev/pci/drm/i915/display/intel_psr.c

1121

if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_psr.c

1123

else if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_psr.c

1125

else if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_psr.c

1143

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

1146

intel_de_rmw(display, EDP_PSR2_CTL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_psr.c

1153

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

1156

intel_display_power_set_target_dc_state(display, DC_STATE_EN_DC3CO);

sys/dev/pci/drm/i915/display/intel_psr.c

1161

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

1163

intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);

sys/dev/pci/drm/i915/display/intel_psr.c

1196

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

1201

if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_psr.c

1211

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

1213

struct i915_power_domains *power_domains = &display->power.domains;

sys/dev/pci/drm/i915/display/intel_psr.c

1237

if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0))

sys/dev/pci/drm/i915/display/intel_psr.c

1247

if (drm_WARN_ON(display->drm, exit_scanlines > crtc_vdisplay))

sys/dev/pci/drm/i915/display/intel_psr.c

1256

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

1258

if (!display->params.enable_psr2_sel_fetch &&

sys/dev/pci/drm/i915/display/intel_psr.c

1260

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1271

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

1293

if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_psr.c

1314

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

1328

if (DISPLAY_VER(display) < 14 || intel_dp->edp_dpcd[0] < DP_EDP_14b)

sys/dev/pci/drm/i915/display/intel_psr.c

1338

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

1343

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1351

if (DISPLAY_VER(display) >= 20) {

sys/dev/pci/drm/i915/display/intel_psr.c

1354

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1358

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1372

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

1380

wake_lines = DISPLAY_VER(display) < 20 ?

sys/dev/pci/drm/i915/display/intel_psr.c

1398

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

1401

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1407

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1418

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

1423

if (!intel_dp->psr.sink_psr2_support || display->params.enable_psr == 1)

sys/dev/pci/drm/i915/display/intel_psr.c

1427

if (display->platform.jasperlake || display->platform.elkhartlake) {

sys/dev/pci/drm/i915/display/intel_psr.c

1428

drm_dbg_kms(display->drm, "PSR2 not supported by phy\n");

sys/dev/pci/drm/i915/display/intel_psr.c

1433

if (display->platform.rocketlake || display->platform.alderlake_s ||

sys/dev/pci/drm/i915/display/intel_psr.c

1434

display->platform.dg2) {

sys/dev/pci/drm/i915/display/intel_psr.c

1435

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1440

if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {

sys/dev/pci/drm/i915/display/intel_psr.c

1441

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1446

if (!transcoder_has_psr2(display, crtc_state->cpu_transcoder)) {

sys/dev/pci/drm/i915/display/intel_psr.c

1447

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1459

(DISPLAY_VER(display) < 14 && !display->platform.alderlake_p)) {

sys/dev/pci/drm/i915/display/intel_psr.c

1460

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1465

if (DISPLAY_VER(display) >= 20) {

sys/dev/pci/drm/i915/display/intel_psr.c

1469

} else if (IS_DISPLAY_VER(display, 12, 14)) {

sys/dev/pci/drm/i915/display/intel_psr.c

1473

} else if (IS_DISPLAY_VER(display, 10, 11)) {

sys/dev/pci/drm/i915/display/intel_psr.c

1477

} else if (DISPLAY_VER(display) == 9) {

sys/dev/pci/drm/i915/display/intel_psr.c

1484

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1492

display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {

sys/dev/pci/drm/i915/display/intel_psr.c

1493

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1503

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1518

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

1520

if (HAS_PSR2_SEL_FETCH(display) &&

sys/dev/pci/drm/i915/display/intel_psr.c

1522

!HAS_PSR_HW_TRACKING(display)) {

sys/dev/pci/drm/i915/display/intel_psr.c

1523

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1529

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1538

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1543

if (crtc_state->has_panel_replay && (DISPLAY_VER(display) < 14 ||

sys/dev/pci/drm/i915/display/intel_psr.c

1548

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1554

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1572

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

1576

if (!CAN_PSR(intel_dp) || !display->params.enable_psr)

sys/dev/pci/drm/i915/display/intel_psr.c

1590

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1603

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

1612

drm_dbg_kms(display->drm, "Panel Replay disabled by flag\n");

sys/dev/pci/drm/i915/display/intel_psr.c

1617

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1633

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1644

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1658

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

1660

return (DISPLAY_VER(display) == 20 && crtc_state->entry_setup_frames > 0 &&

sys/dev/pci/drm/i915/display/intel_psr.c

1668

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

1675

drm_dbg_kms(display->drm, "PSR disabled by flag\n");

sys/dev/pci/drm/i915/display/intel_psr.c

1680

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1686

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1697

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1717

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1722

if (DISPLAY_VER(display) != 20 &&

sys/dev/pci/drm/i915/display/intel_psr.c

1723

!IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))

sys/dev/pci/drm/i915/display/intel_psr.c

1731

for_each_intel_crtc(display->drm, crtc)

sys/dev/pci/drm/i915/display/intel_psr.c

1743

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_psr.c

1776

if (HAS_PSR2_SEL_FETCH(display)) {

sys/dev/pci/drm/i915/display/intel_psr.c

1777

val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_psr.c

1778

PSR2_MAN_TRK_CTL(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_psr.c

1785

if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/intel_psr.c

1786

val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_psr.c

1787

TRANS_EXITLINE(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_psr.c

1796

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

1799

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1800

transcoder_has_psr2(display, cpu_transcoder) &&

sys/dev/pci/drm/i915/display/intel_psr.c

1801

intel_de_read(display, EDP_PSR2_CTL(display, cpu_transcoder)) & EDP_PSR2_ENABLE);

sys/dev/pci/drm/i915/display/intel_psr.c

1803

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

1804

intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)) & EDP_PSR_ENABLE);

sys/dev/pci/drm/i915/display/intel_psr.c

1806

drm_WARN_ON(display->drm, intel_dp->psr.active);

sys/dev/pci/drm/i915/display/intel_psr.c

1808

drm_WARN_ON(display->drm, !intel_dp->psr.enabled);

sys/dev/pci/drm/i915/display/intel_psr.c

1830

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

1835

if (IS_DISPLAY_VER(display, 11, 14) && crtc_state->wm_level_disabled)

sys/dev/pci/drm/i915/display/intel_psr.c

1839

if (DISPLAY_VER(display) == 12 &&

sys/dev/pci/drm/i915/display/intel_psr.c

1845

intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,

sys/dev/pci/drm/i915/display/intel_psr.c

1848

intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,

sys/dev/pci/drm/i915/display/intel_psr.c

1855

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

1863

if (DISPLAY_VER(display) < 9)

sys/dev/pci/drm/i915/display/intel_psr.c

1880

if (DISPLAY_VER(display) < 20 || intel_dp_is_edp(intel_dp))

sys/dev/pci/drm/i915/display/intel_psr.c

1894

if (DISPLAY_VER(display) >= 8 || display->platform.haswell_ult)

sys/dev/pci/drm/i915/display/intel_psr.c

1897

if (DISPLAY_VER(display) < 20)

sys/dev/pci/drm/i915/display/intel_psr.c

1904

if (IS_DISPLAY_VER(display, 9, 10))

sys/dev/pci/drm/i915/display/intel_psr.c

1908

if (display->platform.haswell)

sys/dev/pci/drm/i915/display/intel_psr.c

1912

intel_de_write(display, psr_debug_reg(display, cpu_transcoder), mask);

sys/dev/pci/drm/i915/display/intel_psr.c

1921

intel_de_rmw(display,

sys/dev/pci/drm/i915/display/intel_psr.c

1922

TRANS_EXITLINE(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_psr.c

1926

if (HAS_PSR_HW_TRACKING(display) && HAS_PSR2_SEL_FETCH(display))

sys/dev/pci/drm/i915/display/intel_psr.c

1927

intel_de_rmw(display, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,

sys/dev/pci/drm/i915/display/intel_psr.c

1938

if (DISPLAY_VER(display) == 9)

sys/dev/pci/drm/i915/display/intel_psr.c

1939

intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 0,

sys/dev/pci/drm/i915/display/intel_psr.c

1949

(IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) ||

sys/dev/pci/drm/i915/display/intel_psr.c

1950

display->platform.alderlake_p))

sys/dev/pci/drm/i915/display/intel_psr.c

1951

intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_psr.c

1956

IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0))

sys/dev/pci/drm/i915/display/intel_psr.c

1957

intel_de_rmw(display,

sys/dev/pci/drm/i915/display/intel_psr.c

1958

MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_psr.c

1961

else if (display->platform.alderlake_p)

sys/dev/pci/drm/i915/display/intel_psr.c

1962

intel_de_rmw(display, CLKGATE_DIS_MISC, 0,

sys/dev/pci/drm/i915/display/intel_psr.c

1967

if ((DISPLAY_VER(display) == 20 ||

sys/dev/pci/drm/i915/display/intel_psr.c

1968

IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&

sys/dev/pci/drm/i915/display/intel_psr.c

1970

intel_dmc_block_pkgc(display, intel_dp->psr.pipe, true);

sys/dev/pci/drm/i915/display/intel_psr.c

1977

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

1992

val = intel_de_read(display, psr_iir_reg(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_psr.c

1996

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

2008

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

2012

drm_WARN_ON(display->drm, intel_dp->psr.enabled);

sys/dev/pci/drm/i915/display/intel_psr.c

2036

drm_dbg_kms(display->drm, "Enabling Panel Replay\n");

sys/dev/pci/drm/i915/display/intel_psr.c

2038

drm_dbg_kms(display->drm, "Enabling PSR%s\n",

sys/dev/pci/drm/i915/display/intel_psr.c

2077

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

2082

if (transcoder_has_psr2(display, cpu_transcoder)) {

sys/dev/pci/drm/i915/display/intel_psr.c

2083

val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_psr.c

2084

EDP_PSR2_CTL(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_psr.c

2085

drm_WARN_ON(display->drm, val & EDP_PSR2_ENABLE);

sys/dev/pci/drm/i915/display/intel_psr.c

2088

val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_psr.c

2089

psr_ctl_reg(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_psr.c

2090

drm_WARN_ON(display->drm, val & EDP_PSR_ENABLE);

sys/dev/pci/drm/i915/display/intel_psr.c

2096

intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder),

sys/dev/pci/drm/i915/display/intel_psr.c

2101

val = intel_de_rmw(display,

sys/dev/pci/drm/i915/display/intel_psr.c

2102

EDP_PSR2_CTL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_psr.c

2105

drm_WARN_ON(display->drm, !(val & EDP_PSR2_ENABLE));

sys/dev/pci/drm/i915/display/intel_psr.c

2107

if ((DISPLAY_VER(display) == 20 ||

sys/dev/pci/drm/i915/display/intel_psr.c

2108

IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&

sys/dev/pci/drm/i915/display/intel_psr.c

2110

intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display,

sys/dev/pci/drm/i915/display/intel_psr.c

2114

val = intel_de_rmw(display,

sys/dev/pci/drm/i915/display/intel_psr.c

2115

psr_ctl_reg(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_psr.c

2118

drm_WARN_ON(display->drm, !(val & EDP_PSR_ENABLE));

sys/dev/pci/drm/i915/display/intel_psr.c

2125

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

2132

psr_status = EDP_PSR2_STATUS(display, cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_psr.c

2135

psr_status = psr_status_reg(display, cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_psr.c

2140

if (intel_de_wait_for_clear(display, psr_status,

sys/dev/pci/drm/i915/display/intel_psr.c

2142

drm_err(display->drm, "Timed out waiting PSR idle state\n");

sys/dev/pci/drm/i915/display/intel_psr.c

2147

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

2156

drm_dbg_kms(display->drm, "Disabling Panel Replay\n");

sys/dev/pci/drm/i915/display/intel_psr.c

2158

drm_dbg_kms(display->drm, "Disabling PSR%s\n",

sys/dev/pci/drm/i915/display/intel_psr.c

2168

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_psr.c

2169

intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,

sys/dev/pci/drm/i915/display/intel_psr.c

2175

IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0))

sys/dev/pci/drm/i915/display/intel_psr.c

2176

intel_de_rmw(display,

sys/dev/pci/drm/i915/display/intel_psr.c

2177

MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_psr.c

2179

else if (display->platform.alderlake_p)

sys/dev/pci/drm/i915/display/intel_psr.c

2180

intel_de_rmw(display, CLKGATE_DIS_MISC,

sys/dev/pci/drm/i915/display/intel_psr.c

2200

if ((DISPLAY_VER(display) == 20 ||

sys/dev/pci/drm/i915/display/intel_psr.c

2201

IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&

sys/dev/pci/drm/i915/display/intel_psr.c

2203

intel_dmc_block_pkgc(display, intel_dp->psr.pipe, false);

sys/dev/pci/drm/i915/display/intel_psr.c

2225

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

2230

if (drm_WARN_ON(display->drm, !CAN_PSR(intel_dp) &&

sys/dev/pci/drm/i915/display/intel_psr.c

2284

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

2296

drm_warn(display->drm, "Unbalanced PSR pause/resume!\n");

sys/dev/pci/drm/i915/display/intel_psr.c

2321

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_psr.c

2338

if ((DISPLAY_VER(display) == 20 ||

sys/dev/pci/drm/i915/display/intel_psr.c

2339

IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&

sys/dev/pci/drm/i915/display/intel_psr.c

2361

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_psr.c

2364

intel_de_write_dsb(display, dsb,

sys/dev/pci/drm/i915/display/intel_psr.c

2365

CURSURFLIVE(display, crtc->pipe), 0);

sys/dev/pci/drm/i915/display/intel_psr.c

2376

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_psr.c

2382

if (intel_vrr_possible(crtc_state) && IS_DISPLAY_VER(display, 13, 14))

sys/dev/pci/drm/i915/display/intel_psr.c

2386

if (DISPLAY_VER(display) < 20)

sys/dev/pci/drm/i915/display/intel_psr.c

2404

if (DISPLAY_VER(display) >= 30 && (crtc_state->has_panel_replay ||

sys/dev/pci/drm/i915/display/intel_psr.c

2407

else if (DISPLAY_VER(display) < 30 && (crtc_state->has_sel_update ||

sys/dev/pci/drm/i915/display/intel_psr.c

2415

static u32 man_trk_ctl_enable_bit_get(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_psr.c

2417

return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 0 :

sys/dev/pci/drm/i915/display/intel_psr.c

2421

static u32 man_trk_ctl_single_full_frame_bit_get(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_psr.c

2423

return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ?

sys/dev/pci/drm/i915/display/intel_psr.c

2428

static u32 man_trk_ctl_partial_frame_bit_get(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_psr.c

2430

return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ?

sys/dev/pci/drm/i915/display/intel_psr.c

2435

static u32 man_trk_ctl_continuos_full_frame(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_psr.c

2437

return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ?

sys/dev/pci/drm/i915/display/intel_psr.c

2444

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

2459

intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0);

sys/dev/pci/drm/i915/display/intel_psr.c

2465

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_psr.c

2473

for_each_intel_encoder_mask_with_psr(display->drm, encoder,

sys/dev/pci/drm/i915/display/intel_psr.c

2480

if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled)

sys/dev/pci/drm/i915/display/intel_psr.c

2485

intel_de_write_dsb(display, dsb,

sys/dev/pci/drm/i915/display/intel_psr.c

2486

PSR2_MAN_TRK_CTL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_psr.c

2492

intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_psr.c

2505

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_psr.c

2506

u32 val = man_trk_ctl_enable_bit_get(display);

sys/dev/pci/drm/i915/display/intel_psr.c

2509

val |= man_trk_ctl_partial_frame_bit_get(display);

sys/dev/pci/drm/i915/display/intel_psr.c

2512

val |= man_trk_ctl_continuos_full_frame(display);

sys/dev/pci/drm/i915/display/intel_psr.c

2519

if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) {

sys/dev/pci/drm/i915/display/intel_psr.c

2572

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_psr.c

2579

(display->platform.alderlake_p || DISPLAY_VER(display) >= 14))

sys/dev/pci/drm/i915/display/intel_psr.c

264

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

267

display->params.enable_panel_replay;

sys/dev/pci/drm/i915/display/intel_psr.c

2675

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_psr.c

2691

for_each_intel_encoder_mask_with_psr(display->drm, encoder,

sys/dev/pci/drm/i915/display/intel_psr.c

2707

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_psr.c

2711

((IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) ||

sys/dev/pci/drm/i915/display/intel_psr.c

2712

display->platform.alderlake_p || display->platform.tigerlake)) &&

sys/dev/pci/drm/i915/display/intel_psr.c

2717

if (DISPLAY_VER(display) == 30)

sys/dev/pci/drm/i915/display/intel_psr.c

272

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

2724

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_psr.c

274

return DISPLAY_VER(display) >= 12 ? TGL_PSR_ERROR :

sys/dev/pci/drm/i915/display/intel_psr.c

280

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

282

return DISPLAY_VER(display) >= 12 ? TGL_PSR_POST_EXIT :

sys/dev/pci/drm/i915/display/intel_psr.c

2820

drm_info_once(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

288

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

290

return DISPLAY_VER(display) >= 12 ? TGL_PSR_PRE_ENTRY :

sys/dev/pci/drm/i915/display/intel_psr.c

2930

void intel_psr2_panic_force_full_update(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_psr.c

2935

u32 val = man_trk_ctl_enable_bit_get(display);

sys/dev/pci/drm/i915/display/intel_psr.c

2938

val |= man_trk_ctl_partial_frame_bit_get(display);

sys/dev/pci/drm/i915/display/intel_psr.c

2939

val |= man_trk_ctl_continuos_full_frame(display);

sys/dev/pci/drm/i915/display/intel_psr.c

2942

intel_de_write_fw(display, PSR2_MAN_TRK_CTL(display, cpu_transcoder), val);

sys/dev/pci/drm/i915/display/intel_psr.c

2947

intel_de_write_fw(display, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 0);

sys/dev/pci/drm/i915/display/intel_psr.c

2953

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_psr.c

296

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

2960

if (!HAS_PSR(display))

sys/dev/pci/drm/i915/display/intel_psr.c

298

return DISPLAY_VER(display) >= 12 ? TGL_PSR_MASK :

sys/dev/pci/drm/i915/display/intel_psr.c

2985

(DISPLAY_VER(display) < 11 && new_crtc_state->wm_level_disabled))

sys/dev/pci/drm/i915/display/intel_psr.c

2999

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_psr.c

3015

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

302

static i915_reg_t psr_ctl_reg(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_psr.c

3022

keep_disabled |= DISPLAY_VER(display) < 11 &&

sys/dev/pci/drm/i915/display/intel_psr.c

305

if (DISPLAY_VER(display) >= 8)

sys/dev/pci/drm/i915/display/intel_psr.c

3057

struct intel_display *display = to_intel_display(new_crtc_state);

sys/dev/pci/drm/i915/display/intel_psr.c

306

return EDP_PSR_CTL(display, cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_psr.c

3066

intel_dsb_poll(dsb, EDP_PSR2_STATUS(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_psr.c

3072

return intel_de_wait_for_clear(display,

sys/dev/pci/drm/i915/display/intel_psr.c

3073

EDP_PSR2_STATUS(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_psr.c

3082

struct intel_display *display = to_intel_display(new_crtc_state);

sys/dev/pci/drm/i915/display/intel_psr.c

3086

intel_dsb_poll(dsb, psr_status_reg(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_psr.c

3092

return intel_de_wait_for_clear(display,

sys/dev/pci/drm/i915/display/intel_psr.c

3093

psr_status_reg(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_psr.c

3107

struct intel_display *display = to_intel_display(new_crtc_state);

sys/dev/pci/drm/i915/display/intel_psr.c

311

static i915_reg_t psr_debug_reg(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_psr.c

3113

for_each_intel_encoder_mask_with_psr(display->drm, encoder,

sys/dev/pci/drm/i915/display/intel_psr.c

3131

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

314

if (DISPLAY_VER(display) >= 8)

sys/dev/pci/drm/i915/display/intel_psr.c

315

return EDP_PSR_DEBUG(display, cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_psr.c

3150

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

3161

reg = EDP_PSR2_STATUS(display, cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_psr.c

3164

reg = psr_status_reg(display, cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_psr.c

3170

err = intel_de_wait_for_clear(display, reg, mask, 50);

sys/dev/pci/drm/i915/display/intel_psr.c

3172

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

3180

static int intel_psr_fastset_force(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_psr.c

3188

state = drm_atomic_state_alloc(display->drm);

sys/dev/pci/drm/i915/display/intel_psr.c

3198

drm_connector_list_iter_begin(display->drm, &conn_iter);

sys/dev/pci/drm/i915/display/intel_psr.c

320

static i915_reg_t psr_perf_cnt_reg(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_psr.c

323

if (DISPLAY_VER(display) >= 8)

sys/dev/pci/drm/i915/display/intel_psr.c

324

return EDP_PSR_PERF_CNT(display, cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_psr.c

3245

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

3256

drm_dbg_kms(display->drm, "Invalid debug mask %llx\n", val);

sys/dev/pci/drm/i915/display/intel_psr.c

3281

ret = intel_psr_fastset_force(display);

sys/dev/pci/drm/i915/display/intel_psr.c

329

static i915_reg_t psr_status_reg(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_psr.c

332

if (DISPLAY_VER(display) >= 8)

sys/dev/pci/drm/i915/display/intel_psr.c

333

return EDP_PSR_STATUS(display, cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_psr.c

3338

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

3344

if (DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/intel_psr.c

3345

intel_de_write(display, LNL_SFF_CTL(cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_psr.c

3348

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_psr.c

3349

PSR2_MAN_TRK_CTL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_psr.c

3350

man_trk_ctl_enable_bit_get(display) |

sys/dev/pci/drm/i915/display/intel_psr.c

3351

man_trk_ctl_partial_frame_bit_get(display) |

sys/dev/pci/drm/i915/display/intel_psr.c

3352

man_trk_ctl_single_full_frame_bit_get(display) |

sys/dev/pci/drm/i915/display/intel_psr.c

3353

man_trk_ctl_continuos_full_frame(display));

sys/dev/pci/drm/i915/display/intel_psr.c

3358

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

3360

if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) {

sys/dev/pci/drm/i915/display/intel_psr.c

338

static i915_reg_t psr_imr_reg(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_psr.c

3385

void intel_psr_invalidate(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_psr.c

3393

for_each_intel_encoder_with_psr(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_psr.c

341

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_psr.c

342

return TRANS_PSR_IMR(display, cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_psr.c

3423

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

3438

mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work,

sys/dev/pci/drm/i915/display/intel_psr.c

3444

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

3446

if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) {

sys/dev/pci/drm/i915/display/intel_psr.c

347

static i915_reg_t psr_iir_reg(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_psr.c

3479

queue_work(display->wq.unordered, &intel_dp->psr.work);

sys/dev/pci/drm/i915/display/intel_psr.c

3495

void intel_psr_flush(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_psr.c

350

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_psr.c

3500

for_each_intel_encoder_with_psr(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_psr.c

351

return TRANS_PSR_IIR(display, cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_psr.c

3549

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

3553

if (!(HAS_PSR(display) || HAS_DP20(display)))

sys/dev/pci/drm/i915/display/intel_psr.c

356

static i915_reg_t psr_aux_ctl_reg(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_psr.c

3565

if (DISPLAY_VER(display) < 12 && dig_port->base.port != PORT_A) {

sys/dev/pci/drm/i915/display/intel_psr.c

3566

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

3571

if ((HAS_DP20(display) && !intel_dp_is_edp(intel_dp)) ||

sys/dev/pci/drm/i915/display/intel_psr.c

3572

DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/intel_psr.c

3575

if (HAS_PSR(display) && intel_dp_is_edp(intel_dp))

sys/dev/pci/drm/i915/display/intel_psr.c

3579

if (DISPLAY_VER(display) < 12)

sys/dev/pci/drm/i915/display/intel_psr.c

359

if (DISPLAY_VER(display) >= 8)

sys/dev/pci/drm/i915/display/intel_psr.c

360

return EDP_PSR_AUX_CTL(display, cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_psr.c

3629

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

3636

drm_err(display->drm, "Error reading DP_PSR_ESI\n");

sys/dev/pci/drm/i915/display/intel_psr.c

3643

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

365

static i915_reg_t psr_aux_data_reg(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_psr.c

3660

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

3678

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

368

if (DISPLAY_VER(display) >= 8)

sys/dev/pci/drm/i915/display/intel_psr.c

369

return EDP_PSR_AUX_DATA(display, cpu_transcoder, i);

sys/dev/pci/drm/i915/display/intel_psr.c

3691

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

3694

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

3697

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

3700

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

3704

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

376

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

3770

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_psr.c

3776

for_each_intel_encoder_mask_with_psr(display->drm, encoder,

sys/dev/pci/drm/i915/display/intel_psr.c

3793

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_psr.c

3799

for_each_intel_encoder_mask_with_psr(display->drm, encoder,

sys/dev/pci/drm/i915/display/intel_psr.c

3811

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

3823

intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display,

sys/dev/pci/drm/i915/display/intel_psr.c

3830

struct intel_display *display = container_of(work, typeof(*display),

sys/dev/pci/drm/i915/display/intel_psr.c

3834

for_each_intel_encoder_with_psr(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_psr.c

3854

void intel_psr_notify_dc5_dc6(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_psr.c

3856

if (DISPLAY_VER(display) != 20 &&

sys/dev/pci/drm/i915/display/intel_psr.c

3857

!IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))

sys/dev/pci/drm/i915/display/intel_psr.c

3860

schedule_work(&display->psr_dc5_dc6_wa_work);

sys/dev/pci/drm/i915/display/intel_psr.c

3870

void intel_psr_dc5_dc6_wa_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_psr.c

3872

if (DISPLAY_VER(display) != 20 &&

sys/dev/pci/drm/i915/display/intel_psr.c

3873

!IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))

sys/dev/pci/drm/i915/display/intel_psr.c

3876

INIT_WORK(&display->psr_dc5_dc6_wa_work, psr_dc5_dc6_wa_work);

sys/dev/pci/drm/i915/display/intel_psr.c

388

intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_psr.c

3891

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_psr.c

3894

if (DISPLAY_VER(display) != 20 &&

sys/dev/pci/drm/i915/display/intel_psr.c

3895

!IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))

sys/dev/pci/drm/i915/display/intel_psr.c

3898

for_each_intel_encoder_with_psr(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_psr.c

392

static void psr_event_print(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_psr.c

3940

void intel_psr_notify_vblank_enable_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_psr.c

3945

for_each_intel_encoder_with_psr(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_psr.c

395

drm_dbg_kms(display->drm, "PSR exit events: 0x%x\n", val);

sys/dev/pci/drm/i915/display/intel_psr.c

3968

intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE :

sys/dev/pci/drm/i915/display/intel_psr.c

397

drm_dbg_kms(display->drm, "\tPSR2 watchdog timer expired\n");

sys/dev/pci/drm/i915/display/intel_psr.c

3975

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

3980

if ((intel_dp_is_edp(intel_dp) || DISPLAY_VER(display) >= 30) &&

sys/dev/pci/drm/i915/display/intel_psr.c

399

drm_dbg_kms(display->drm, "\tPSR2 disabled\n");

sys/dev/pci/drm/i915/display/intel_psr.c

3995

val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_psr.c

3996

EDP_PSR2_STATUS(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_psr.c

401

drm_dbg_kms(display->drm, "\tSU dirty FIFO underrun\n");

sys/dev/pci/drm/i915/display/intel_psr.c

4011

val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_psr.c

4012

psr_status_reg(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_psr.c

403

drm_dbg_kms(display->drm, "\tSU CRC FIFO underrun\n");

sys/dev/pci/drm/i915/display/intel_psr.c

405

drm_dbg_kms(display->drm, "\tGraphics reset\n");

sys/dev/pci/drm/i915/display/intel_psr.c

407

drm_dbg_kms(display->drm, "\tPCH interrupt\n");

sys/dev/pci/drm/i915/display/intel_psr.c

4074

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

4086

wakeref = intel_display_rpm_get(display);

sys/dev/pci/drm/i915/display/intel_psr.c

409

drm_dbg_kms(display->drm, "\tMemory up\n");

sys/dev/pci/drm/i915/display/intel_psr.c

4099

val = intel_de_read(display, TRANS_DP2_CTL(cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_psr.c

4102

psr2_ctl = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_psr.c

4103

EDP_PSR2_CTL(display,

sys/dev/pci/drm/i915/display/intel_psr.c

4108

val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_psr.c

4109

EDP_PSR2_CTL(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_psr.c

411

drm_dbg_kms(display->drm, "\tFront buffer modification\n");

sys/dev/pci/drm/i915/display/intel_psr.c

4112

val = intel_de_read(display, psr_ctl_reg(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_psr.c

4127

val = intel_de_read(display, psr_perf_cnt_reg(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_psr.c

413

drm_dbg_kms(display->drm, "\tPSR watchdog timer expired\n");

sys/dev/pci/drm/i915/display/intel_psr.c

4145

if (DISPLAY_VER(display) < 13) {

sys/dev/pci/drm/i915/display/intel_psr.c

415

drm_dbg_kms(display->drm, "\tPIPE registers updated\n");

sys/dev/pci/drm/i915/display/intel_psr.c

4151

val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_psr.c

4152

PSR2_SU_STATUS(display, cpu_transcoder, frame));

sys/dev/pci/drm/i915/display/intel_psr.c

417

drm_dbg_kms(display->drm, "\tRegister updated\n");

sys/dev/pci/drm/i915/display/intel_psr.c

4174

intel_display_rpm_put(display, wakeref);

sys/dev/pci/drm/i915/display/intel_psr.c

4181

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/intel_psr.c

4185

if (!HAS_PSR(display))

sys/dev/pci/drm/i915/display/intel_psr.c

4189

for_each_intel_encoder_with_psr(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_psr.c

419

drm_dbg_kms(display->drm, "\tHDCP enabled\n");

sys/dev/pci/drm/i915/display/intel_psr.c

4204

struct intel_display *display = data;

sys/dev/pci/drm/i915/display/intel_psr.c

4208

if (!HAS_PSR(display))

sys/dev/pci/drm/i915/display/intel_psr.c

421

drm_dbg_kms(display->drm, "\tKVMR session enabled\n");

sys/dev/pci/drm/i915/display/intel_psr.c

4211

for_each_intel_encoder_with_psr(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_psr.c

4214

drm_dbg_kms(display->drm, "Setting PSR debug to %llx\n", val);

sys/dev/pci/drm/i915/display/intel_psr.c

4217

with_intel_display_rpm(display)

sys/dev/pci/drm/i915/display/intel_psr.c

4227

struct intel_display *display = data;

sys/dev/pci/drm/i915/display/intel_psr.c

423

drm_dbg_kms(display->drm, "\tVBI enabled\n");

sys/dev/pci/drm/i915/display/intel_psr.c

4230

if (!HAS_PSR(display))

sys/dev/pci/drm/i915/display/intel_psr.c

4233

for_each_intel_encoder_with_psr(display->drm, encoder) {

sys/dev/pci/drm/i915/display/intel_psr.c

4248

void intel_psr_debugfs_register(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_psr.c

425

drm_dbg_kms(display->drm, "\tLPSP mode exited\n");

sys/dev/pci/drm/i915/display/intel_psr.c

4250

struct dentry *debugfs_root = display->drm->debugfs_root;

sys/dev/pci/drm/i915/display/intel_psr.c

4253

display, &i915_edp_psr_debug_fops);

sys/dev/pci/drm/i915/display/intel_psr.c

4256

display, &i915_edp_psr_status_fops);

sys/dev/pci/drm/i915/display/intel_psr.c

427

drm_dbg_kms(display->drm, "\tPSR disabled\n");

sys/dev/pci/drm/i915/display/intel_psr.c

432

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

4337

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_psr.c

4347

if (HAS_PSR(display) || HAS_DP20(display))

sys/dev/pci/drm/i915/display/intel_psr.c

438

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

445

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

449

if (DISPLAY_VER(display) >= 9) {

sys/dev/pci/drm/i915/display/intel_psr.c

452

val = intel_de_rmw(display,

sys/dev/pci/drm/i915/display/intel_psr.c

453

PSR_EVENT(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_psr.c

456

psr_event_print(display, val, intel_dp->psr.sel_update_enabled);

sys/dev/pci/drm/i915/display/intel_psr.c

461

drm_warn(display->drm, "[transcoder %s] PSR aux error\n",

sys/dev/pci/drm/i915/display/intel_psr.c

474

intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_psr.c

477

queue_work(display->wq.unordered, &intel_dp->psr.work);

sys/dev/pci/drm/i915/display/intel_psr.c

483

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

490

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

533

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

559

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

572

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

586

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

604

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

611

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

623

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

631

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

642

drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n",

sys/dev/pci/drm/i915/display/intel_psr.c

646

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

652

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_psr.c

661

if (DISPLAY_VER(display) >= 9 &&

sys/dev/pci/drm/i915/display/intel_psr.c

679

drm_dbg_kms(display->drm, "PSR2 %ssupported\n",

sys/dev/pci/drm/i915/display/intel_psr.c

697

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

712

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_psr.c

713

psr_aux_data_reg(display, cpu_transcoder, i >> 2),

sys/dev/pci/drm/i915/display/intel_psr.c

728

intel_de_write(display, psr_aux_ctl_reg(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_psr.c

734

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

736

if (DISPLAY_VER(display) < 20 || !intel_dp_is_edp(intel_dp) ||

sys/dev/pci/drm/i915/display/intel_psr.c

775

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

784

if (DISPLAY_VER(display) >= 8)

sys/dev/pci/drm/i915/display/intel_psr.c

829

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

833

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/intel_psr.c

836

if (display->params.psr_safest_params) {

sys/dev/pci/drm/i915/display/intel_psr.c

864

if (DISPLAY_VER(display) < 9 &&

sys/dev/pci/drm/i915/display/intel_psr.c

870

if (intel_dp_source_supports_tps3(display) &&

sys/dev/pci/drm/i915/display/intel_psr.c

881

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

891

if (drm_WARN_ON(display->drm, idle_frames > 0xf))

sys/dev/pci/drm/i915/display/intel_psr.c

899

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

900

u32 current_dc_state = intel_display_power_get_current_dc_state(display);

sys/dev/pci/drm/i915/display/intel_psr.c

901

struct intel_crtc *crtc = intel_crtc_for_pipe(display, intel_dp->psr.pipe);

sys/dev/pci/drm/i915/display/intel_psr.c

912

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

919

if (DISPLAY_VER(display) < 20)

sys/dev/pci/drm/i915/display/intel_psr.c

922

if (display->platform.haswell)

sys/dev/pci/drm/i915/display/intel_psr.c

930

if (DISPLAY_VER(display) >= 8)

sys/dev/pci/drm/i915/display/intel_psr.c

933

if (DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/intel_psr.c

936

intel_de_rmw(display, psr_ctl_reg(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_psr.c

940

if ((DISPLAY_VER(display) == 20 ||

sys/dev/pci/drm/i915/display/intel_psr.c

941

IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&

sys/dev/pci/drm/i915/display/intel_psr.c

943

intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display,

sys/dev/pci/drm/i915/display/intel_psr.c

950

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

954

if (display->params.psr_safest_params)

sys/dev/pci/drm/i915/display/intel_psr.c

998

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.h

40

void intel_psr_invalidate(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_psr.h

43

void intel_psr_flush(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_psr.h

62

void intel_psr2_panic_force_full_update(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_psr.h

69

void intel_psr_notify_dc5_dc6(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_psr.h

70

void intel_psr_dc5_dc6_wa_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_psr.h

71

void intel_psr_notify_vblank_enable_disable(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_psr.h

82

void intel_psr_debugfs_register(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_quirks.c

113

void (*hook)(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_quirks.c

14

static void intel_set_quirk(struct intel_display *display, enum intel_quirk_id quirk)

sys/dev/pci/drm/i915/display/intel_quirks.c

16

display->quirks.mask |= BIT(quirk);

sys/dev/pci/drm/i915/display/intel_quirks.c

257

void intel_init_quirks(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_quirks.c

259

struct pci_dev *d = display->drm->pdev;

sys/dev/pci/drm/i915/display/intel_quirks.c

27

static void quirk_ssc_force_disable(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_quirks.c

270

q->hook(display);

sys/dev/pci/drm/i915/display/intel_quirks.c

274

intel_dmi_quirks[i].hook(display);

sys/dev/pci/drm/i915/display/intel_quirks.c

281

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_quirks.c

282

struct pci_dev *d = display->drm->pdev;

sys/dev/pci/drm/i915/display/intel_quirks.c

29

intel_set_quirk(display, QUIRK_LVDS_SSC_DISABLE);

sys/dev/pci/drm/i915/display/intel_quirks.c

30

drm_info(display->drm, "applying lvds SSC disable quirk\n");

sys/dev/pci/drm/i915/display/intel_quirks.c

301

bool intel_has_quirk(struct intel_display *display, enum intel_quirk_id quirk)

sys/dev/pci/drm/i915/display/intel_quirks.c

303

return display->quirks.mask & BIT(quirk);

sys/dev/pci/drm/i915/display/intel_quirks.c

37

static void quirk_invert_brightness(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_quirks.c

39

intel_set_quirk(display, QUIRK_INVERT_BRIGHTNESS);

sys/dev/pci/drm/i915/display/intel_quirks.c

40

drm_info(display->drm, "applying inverted panel brightness quirk\n");

sys/dev/pci/drm/i915/display/intel_quirks.c

44

static void quirk_backlight_present(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_quirks.c

46

intel_set_quirk(display, QUIRK_BACKLIGHT_PRESENT);

sys/dev/pci/drm/i915/display/intel_quirks.c

47

drm_info(display->drm, "applying backlight present quirk\n");

sys/dev/pci/drm/i915/display/intel_quirks.c

53

static void quirk_increase_t12_delay(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_quirks.c

55

intel_set_quirk(display, QUIRK_INCREASE_T12_DELAY);

sys/dev/pci/drm/i915/display/intel_quirks.c

56

drm_info(display->drm, "Applying T12 delay quirk\n");

sys/dev/pci/drm/i915/display/intel_quirks.c

63

static void quirk_increase_ddi_disabled_time(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_quirks.c

65

intel_set_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME);

sys/dev/pci/drm/i915/display/intel_quirks.c

66

drm_info(display->drm, "Applying Increase DDI Disabled quirk\n");

sys/dev/pci/drm/i915/display/intel_quirks.c

69

static void quirk_no_pps_backlight_power_hook(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_quirks.c

71

intel_set_quirk(display, QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK);

sys/dev/pci/drm/i915/display/intel_quirks.c

72

drm_info(display->drm, "Applying no pps backlight power quirk\n");

sys/dev/pci/drm/i915/display/intel_quirks.c

77

struct intel_display *display = to_intel_display(intel_dp);

sys/dev/pci/drm/i915/display/intel_quirks.c

80

drm_info(display->drm, "Applying Fast Wake sync pulse count quirk\n");

sys/dev/pci/drm/i915/display/intel_quirks.c

83

static void quirk_edp_limit_rate_hbr2(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_quirks.c

85

intel_set_quirk(display, QUIRK_EDP_LIMIT_RATE_HBR2);

sys/dev/pci/drm/i915/display/intel_quirks.c

86

drm_info(display->drm, "Applying eDP Limit rate to HBR2 quirk\n");

sys/dev/pci/drm/i915/display/intel_quirks.c

93

void (*hook)(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_quirks.h

26

void intel_init_quirks(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_quirks.h

29

bool intel_has_quirk(struct intel_display *display, enum intel_quirk_id quirk);

sys/dev/pci/drm/i915/display/intel_sbi.c

16

static int intel_sbi_rw(struct intel_display *display, u16 reg,

sys/dev/pci/drm/i915/display/intel_sbi.c

22

lockdep_assert_held(&display->sbi.lock);

sys/dev/pci/drm/i915/display/intel_sbi.c

24

if (intel_de_wait_fw(display, SBI_CTL_STAT, SBI_STATUS_MASK, SBI_STATUS_READY, 100, NULL)) {

sys/dev/pci/drm/i915/display/intel_sbi.c

25

drm_err(display->drm, "timeout waiting for SBI to become ready\n");

sys/dev/pci/drm/i915/display/intel_sbi.c

29

intel_de_write_fw(display, SBI_ADDR, SBI_ADDR_VALUE(reg));

sys/dev/pci/drm/i915/display/intel_sbi.c

30

intel_de_write_fw(display, SBI_DATA, is_read ? 0 : *val);

sys/dev/pci/drm/i915/display/intel_sbi.c

38

intel_de_write_fw(display, SBI_CTL_STAT, cmd | SBI_STATUS_BUSY);

sys/dev/pci/drm/i915/display/intel_sbi.c

40

if (intel_de_wait_fw(display, SBI_CTL_STAT, SBI_STATUS_MASK, SBI_STATUS_READY, 100, &cmd)) {

sys/dev/pci/drm/i915/display/intel_sbi.c

41

drm_err(display->drm, "timeout waiting for SBI to complete read\n");

sys/dev/pci/drm/i915/display/intel_sbi.c

46

drm_err(display->drm, "error during SBI read of reg %x\n", reg);

sys/dev/pci/drm/i915/display/intel_sbi.c

51

*val = intel_de_read_fw(display, SBI_DATA);

sys/dev/pci/drm/i915/display/intel_sbi.c

56

void intel_sbi_lock(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_sbi.c

58

mutex_lock(&display->sbi.lock);

sys/dev/pci/drm/i915/display/intel_sbi.c

61

void intel_sbi_unlock(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_sbi.c

63

mutex_unlock(&display->sbi.lock);

sys/dev/pci/drm/i915/display/intel_sbi.c

66

u32 intel_sbi_read(struct intel_display *display, u16 reg,

sys/dev/pci/drm/i915/display/intel_sbi.c

71

intel_sbi_rw(display, reg, destination, &result, true);

sys/dev/pci/drm/i915/display/intel_sbi.c

76

void intel_sbi_write(struct intel_display *display, u16 reg, u32 value,

sys/dev/pci/drm/i915/display/intel_sbi.c

79

intel_sbi_rw(display, reg, destination, &value, false);

sys/dev/pci/drm/i915/display/intel_sbi.c

82

void intel_sbi_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_sbi.c

84

rw_init(&display->sbi.lock, "dsbi");

sys/dev/pci/drm/i915/display/intel_sbi.c

87

void intel_sbi_fini(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_sbi.c

89

mutex_destroy(&display->sbi.lock);

sys/dev/pci/drm/i915/display/intel_sbi.h

18

void intel_sbi_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_sbi.h

19

void intel_sbi_fini(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_sbi.h

20

void intel_sbi_lock(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_sbi.h

21

void intel_sbi_unlock(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_sbi.h

22

u32 intel_sbi_read(struct intel_display *display, u16 reg,

sys/dev/pci/drm/i915/display/intel_sbi.h

24

void intel_sbi_write(struct intel_display *display, u16 reg, u32 value,

sys/dev/pci/drm/i915/display/intel_sdvo.c

1011

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1024

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_sdvo.c

1051

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1081

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_sdvo.c

1102

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1128

if (drm_WARN_ON(display->drm, ret))

sys/dev/pci/drm/i915/display/intel_sdvo.c

1137

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1146

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_sdvo.c

1151

if (drm_WARN_ON(display->drm, len < 0))

sys/dev/pci/drm/i915/display/intel_sdvo.c

1162

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1174

drm_dbg_kms(display->drm, "failed to read AVI infoframe\n");

sys/dev/pci/drm/i915/display/intel_sdvo.c

1185

drm_dbg_kms(display->drm, "Failed to unpack AVI infoframe\n");

sys/dev/pci/drm/i915/display/intel_sdvo.c

1190

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_sdvo.c

1198

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1214

drm_dbg_kms(display->drm, "failed to read ELD\n");

sys/dev/pci/drm/i915/display/intel_sdvo.c

1284

struct intel_display *display = to_intel_display(pipe_config);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1305

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_sdvo.c

1361

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1368

if (HAS_PCH_SPLIT(display)) {

sys/dev/pci/drm/i915/display/intel_sdvo.c

1374

drm_dbg_kms(display->drm, "forcing bpc to 8 for SDVO\n");

sys/dev/pci/drm/i915/display/intel_sdvo.c

1453

drm_dbg_kms(display->drm, "bad AVI infoframe\n");

sys/dev/pci/drm/i915/display/intel_sdvo.c

1527

struct intel_display *display = to_intel_display(intel_encoder);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1572

drm_info(display->drm,

sys/dev/pci/drm/i915/display/intel_sdvo.c

1602

drm_info(display->drm,

sys/dev/pci/drm/i915/display/intel_sdvo.c

1608

drm_WARN(display->drm, 1,

sys/dev/pci/drm/i915/display/intel_sdvo.c

1619

if (DISPLAY_VER(display) >= 4) {

sys/dev/pci/drm/i915/display/intel_sdvo.c

1623

if (DISPLAY_VER(display) < 5)

sys/dev/pci/drm/i915/display/intel_sdvo.c

1626

sdvox = intel_de_read(display, intel_sdvo->sdvo_reg);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1634

if (HAS_PCH_CPT(display))

sys/dev/pci/drm/i915/display/intel_sdvo.c

1639

if (DISPLAY_VER(display) >= 4) {

sys/dev/pci/drm/i915/display/intel_sdvo.c

1641

} else if (display->platform.i945g || display->platform.i945gm ||

sys/dev/pci/drm/i915/display/intel_sdvo.c

1642

display->platform.g33 || display->platform.pineview) {

sys/dev/pci/drm/i915/display/intel_sdvo.c

1650

DISPLAY_VER(display) < 5)

sys/dev/pci/drm/i915/display/intel_sdvo.c

1667

bool intel_sdvo_port_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_sdvo.c

1672

val = intel_de_read(display, sdvo_reg);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1675

if (HAS_PCH_CPT(display))

sys/dev/pci/drm/i915/display/intel_sdvo.c

1677

else if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_sdvo.c

1688

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1695

ret = intel_sdvo_port_enabled(display, intel_sdvo->sdvo_reg, pipe);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1703

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1714

sdvox = intel_de_read(display, intel_sdvo->sdvo_reg);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1722

drm_dbg_kms(display->drm, "failed to retrieve SDVO DTD\n");

sys/dev/pci/drm/i915/display/intel_sdvo.c

1745

if (display->platform.i915g || display->platform.i915gm) {

sys/dev/pci/drm/i915/display/intel_sdvo.c

1774

drm_WARN(display->drm,

sys/dev/pci/drm/i915/display/intel_sdvo.c

1839

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1849

temp = intel_de_read(display, intel_sdvo->sdvo_reg);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1859

if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B) {

sys/dev/pci/drm/i915/display/intel_sdvo.c

1864

intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1865

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1874

intel_wait_for_vblank_if_active(display, PIPE_A);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1875

intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1876

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1900

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1910

temp = intel_de_read(display, intel_sdvo->sdvo_reg);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1925

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_sdvo.c

1940

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1945

int max_dotclk = display->cdclk.max_dotclk_freq;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1949

status = intel_cpu_transcoder_mode_valid(display, mode);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1981

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1989

drm_dbg_kms(display->drm, "SDVO capabilities:\n"

sys/dev/pci/drm/i915/display/intel_sdvo.c

2031

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2034

if (!HAS_HOTPLUG(display))

sys/dev/pci/drm/i915/display/intel_sdvo.c

2041

if (display->platform.i945g || display->platform.i945gm)

sys/dev/pci/drm/i915/display/intel_sdvo.c

2085

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2088

ddc = intel_gmbus_get_adapter(display, display->vbt.crt_ddc_pin);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2139

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2145

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",

sys/dev/pci/drm/i915/display/intel_sdvo.c

2148

if (!intel_display_device_enabled(display))

sys/dev/pci/drm/i915/display/intel_sdvo.c

2151

if (!intel_display_driver_check_access(display))

sys/dev/pci/drm/i915/display/intel_sdvo.c

216

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2163

drm_dbg_kms(display->drm, "SDVO response %d %d [%x]\n",

sys/dev/pci/drm/i915/display/intel_sdvo.c

2199

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_sdvo.c

220

if (HAS_PCH_SPLIT(display)) {

sys/dev/pci/drm/i915/display/intel_sdvo.c

2206

if (!intel_display_driver_check_access(display))

sys/dev/pci/drm/i915/display/intel_sdvo.c

221

intel_de_write(display, intel_sdvo->sdvo_reg, val);

sys/dev/pci/drm/i915/display/intel_sdvo.c

222

intel_de_posting_read(display, intel_sdvo->sdvo_reg);

sys/dev/pci/drm/i915/display/intel_sdvo.c

227

if (HAS_PCH_IBX(display)) {

sys/dev/pci/drm/i915/display/intel_sdvo.c

228

intel_de_write(display, intel_sdvo->sdvo_reg, val);

sys/dev/pci/drm/i915/display/intel_sdvo.c

229

intel_de_posting_read(display, intel_sdvo->sdvo_reg);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2300

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2310

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",

sys/dev/pci/drm/i915/display/intel_sdvo.c

2313

if (!intel_display_driver_check_access(display))

sys/dev/pci/drm/i915/display/intel_sdvo.c

235

cval = intel_de_read(display, GEN3_SDVOC);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2352

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2354

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",

sys/dev/pci/drm/i915/display/intel_sdvo.c

237

bval = intel_de_read(display, GEN3_SDVOB);

sys/dev/pci/drm/i915/display/intel_sdvo.c

245

intel_de_write(display, GEN3_SDVOB, bval);

sys/dev/pci/drm/i915/display/intel_sdvo.c

246

intel_de_posting_read(display, GEN3_SDVOB);

sys/dev/pci/drm/i915/display/intel_sdvo.c

248

intel_de_write(display, GEN3_SDVOC, cval);

sys/dev/pci/drm/i915/display/intel_sdvo.c

249

intel_de_posting_read(display, GEN3_SDVOC);

sys/dev/pci/drm/i915/display/intel_sdvo.c

255

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2618

struct intel_display *display = to_intel_display(&sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2623

mapping = &display->vbt.sdvo_mappings[0];

sys/dev/pci/drm/i915/display/intel_sdvo.c

2625

mapping = &display->vbt.sdvo_mappings[1];

sys/dev/pci/drm/i915/display/intel_sdvo.c

2641

struct intel_display *display = to_intel_display(&sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2646

mapping = &display->vbt.sdvo_mappings[0];

sys/dev/pci/drm/i915/display/intel_sdvo.c

2648

mapping = &display->vbt.sdvo_mappings[1];

sys/dev/pci/drm/i915/display/intel_sdvo.c

2651

intel_gmbus_is_valid_pin(display, mapping->i2c_pin))

sys/dev/pci/drm/i915/display/intel_sdvo.c

2656

drm_dbg_kms(display->drm, "[ENCODER:%d:%s] I2C pin %d, target addr 0x%x\n",

sys/dev/pci/drm/i915/display/intel_sdvo.c

2660

sdvo->i2c = intel_gmbus_get_adapter(display, pin);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2686

struct intel_display *display = to_intel_display(&sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2690

my_mapping = &display->vbt.sdvo_mappings[0];

sys/dev/pci/drm/i915/display/intel_sdvo.c

2691

other_mapping = &display->vbt.sdvo_mappings[1];

sys/dev/pci/drm/i915/display/intel_sdvo.c

2693

my_mapping = &display->vbt.sdvo_mappings[1];

sys/dev/pci/drm/i915/display/intel_sdvo.c

2694

other_mapping = &display->vbt.sdvo_mappings[0];

sys/dev/pci/drm/i915/display/intel_sdvo.c

2730

struct intel_display *display = to_intel_display(&encoder->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

275

drm_dbg_kms(display->drm, "i2c transfer returned %d\n", ret);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2755

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] using %s\n",

sys/dev/pci/drm/i915/display/intel_sdvo.c

2798

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2805

drm_dbg_kms(display->drm, "initialising DVI type 0x%x\n", type);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2851

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2857

drm_dbg_kms(display->drm, "initialising TV type 0x%x\n", type);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2891

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2897

drm_dbg_kms(display->drm, "initialising analog type 0x%x\n", type);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2923

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2929

drm_dbg_kms(display->drm, "initialising LVDS type 0x%x\n", type);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2950

intel_bios_init_panel_late(display, &intel_connector->panel, NULL, NULL);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2959

mutex_lock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2964

mutex_unlock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/intel_sdvo.c

3013

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

3032

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_sdvo.c

3055

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

3059

&display->drm->mode_config.connector_list, head) {

sys/dev/pci/drm/i915/display/intel_sdvo.c

3071

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

3096

drm_property_create(display->drm, DRM_MODE_PROP_ENUM,

sys/dev/pci/drm/i915/display/intel_sdvo.c

3118

drm_property_create_range(display->drm, 0, #name, 0, data_value[0]); \

sys/dev/pci/drm/i915/display/intel_sdvo.c

3123

drm_dbg_kms(display->drm, #name ": max %d, default %d, current %d\n", \

sys/dev/pci/drm/i915/display/intel_sdvo.c

3135

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

3158

drm_property_create_range(display->drm, 0, "left_margin", 0, data_value[0]);

sys/dev/pci/drm/i915/display/intel_sdvo.c

3166

drm_property_create_range(display->drm, 0, "right_margin", 0, data_value[0]);

sys/dev/pci/drm/i915/display/intel_sdvo.c

3172

drm_dbg_kms(display->drm, "h_overscan: max %d, default %d, current %d\n",

sys/dev/pci/drm/i915/display/intel_sdvo.c

3191

drm_property_create_range(display->drm, 0,

sys/dev/pci/drm/i915/display/intel_sdvo.c

3200

drm_property_create_range(display->drm, 0,

sys/dev/pci/drm/i915/display/intel_sdvo.c

3207

drm_dbg_kms(display->drm, "v_overscan: max %d, default %d, current %d\n",

sys/dev/pci/drm/i915/display/intel_sdvo.c

3230

drm_property_create_range(display->drm, 0, "dot_crawl", 0, 1);

sys/dev/pci/drm/i915/display/intel_sdvo.c

3236

drm_dbg_kms(display->drm, "dot crawl: current %d\n", response);

sys/dev/pci/drm/i915/display/intel_sdvo.c

3247

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

3261

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

3273

drm_dbg_kms(display->drm, "No enhancement is supported\n");

sys/dev/pci/drm/i915/display/intel_sdvo.c

3348

struct intel_display *display = to_intel_display(&sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

3349

struct pci_dev *pdev = display->drm->pdev;

sys/dev/pci/drm/i915/display/intel_sdvo.c

3369

static bool is_sdvo_port_valid(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_sdvo.c

3371

if (HAS_PCH_SPLIT(display))

sys/dev/pci/drm/i915/display/intel_sdvo.c

3377

static bool assert_sdvo_port_valid(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/intel_sdvo.c

3379

return !drm_WARN(display->drm, !is_sdvo_port_valid(display, port),

sys/dev/pci/drm/i915/display/intel_sdvo.c

3383

bool intel_sdvo_init(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_sdvo.c

3390

if (!assert_port_valid(display, port))

sys/dev/pci/drm/i915/display/intel_sdvo.c

3393

if (!assert_sdvo_port_valid(display, port))

sys/dev/pci/drm/i915/display/intel_sdvo.c

3406

drm_encoder_init(display->drm, &intel_encoder->base,

sys/dev/pci/drm/i915/display/intel_sdvo.c

3420

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_sdvo.c

3428

if (HAS_PCH_SPLIT(display)) {

sys/dev/pci/drm/i915/display/intel_sdvo.c

3458

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_sdvo.c

3495

drm_dbg_kms(display->drm, "%s device VID/DID: %02X:%02X.%02X, "

sys/dev/pci/drm/i915/display/intel_sdvo.c

417

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

438

drm_WARN_ON(display->drm, pos >= sizeof(buffer) - 1);

sys/dev/pci/drm/i915/display/intel_sdvo.c

441

drm_dbg_kms(display->drm, "%s: W: %02X %s\n", SDVO_NAME(intel_sdvo),

sys/dev/pci/drm/i915/display/intel_sdvo.c

467

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

517

drm_dbg_kms(display->drm, "I2c transfer returned %d\n", ret);

sys/dev/pci/drm/i915/display/intel_sdvo.c

523

drm_dbg_kms(display->drm, "I2c transfer returned %d/%d\n", ret, i + 3);

sys/dev/pci/drm/i915/display/intel_sdvo.c

542

struct intel_display *display = to_intel_display(&intel_sdvo->base);

sys/dev/pci/drm/i915/display/intel_sdvo.c

607

drm_WARN_ON(display->drm, pos >= sizeof(buffer) - 1);

sys/dev/pci/drm/i915/display/intel_sdvo.c

610

drm_dbg_kms(display->drm, "%s: R: %s\n",

sys/dev/pci/drm/i915/display/intel_sdvo.c

615

drm_dbg_kms(display->drm, "%s: R: ... failed %s\n",

sys/dev/pci/drm/i915/display/intel_sdvo.h

18

bool intel_sdvo_port_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_sdvo.h

20

bool intel_sdvo_init(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_sdvo.h

23

static inline bool intel_sdvo_port_enabled(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_sdvo.h

28

static inline bool intel_sdvo_init(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1822

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1832

intel_de_write(display, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1833

intel_de_write(display, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1834

intel_de_write(display, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1835

intel_de_write(display, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1836

intel_de_write(display, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1837

intel_de_write(display, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1838

intel_de_write(display, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1849

intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1858

intel_de_write(display, SNPS_PHY_MPLLB_DIV(phy),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1866

if (intel_de_wait_for_set(display, enable_reg, PLL_LOCK, 5))

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1867

drm_dbg_kms(display->drm, "Port %c PLL not locked\n", phy_name(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1880

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1894

intel_de_rmw(display, enable_reg, PLL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1900

intel_de_rmw(display, SNPS_PHY_MPLLB_DIV(phy), SNPS_PHY_MPLLB_FORCE_EN, 0);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1906

if (intel_de_wait_for_clear(display, enable_reg, PLL_LOCK, 5))

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1907

drm_err(display->drm, "Port %c PLL not locked\n", phy_name(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1952

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1955

pll_state->mpllb_cp = intel_de_read(display, SNPS_PHY_MPLLB_CP(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1956

pll_state->mpllb_div = intel_de_read(display, SNPS_PHY_MPLLB_DIV(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1957

pll_state->mpllb_div2 = intel_de_read(display, SNPS_PHY_MPLLB_DIV2(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1958

pll_state->mpllb_sscen = intel_de_read(display, SNPS_PHY_MPLLB_SSCEN(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1959

pll_state->mpllb_sscstep = intel_de_read(display, SNPS_PHY_MPLLB_SSCSTEP(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1960

pll_state->mpllb_fracn1 = intel_de_read(display, SNPS_PHY_MPLLB_FRACN1(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1961

pll_state->mpllb_fracn2 = intel_de_read(display, SNPS_PHY_MPLLB_FRACN2(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1969

pll_state->ref_control = intel_de_read(display, SNPS_PHY_REF_CONTROL(phy)) &

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1984

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1991

if (!display->platform.dg2)

sys/dev/pci/drm/i915/display/intel_snps_phy.c

2006

INTEL_DISPLAY_STATE_WARN(display, mpllb_sw_state->__name != mpllb_hw_state.__name, \

sys/dev/pci/drm/i915/display/intel_snps_phy.c

32

void intel_snps_phy_wait_for_calibration(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_snps_phy.c

37

if (!intel_phy_is_snps(display, phy))

sys/dev/pci/drm/i915/display/intel_snps_phy.c

45

if (intel_de_wait_for_clear(display, DG2_PHY_MISC(phy),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

47

display->snps.phy_failed_calibration |= BIT(phy);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

54

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

63

intel_de_rmw(display, SNPS_PHY_TX_REQ(phy),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

70

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

76

if (drm_WARN_ON_ONCE(display->drm, !trans))

sys/dev/pci/drm/i915/display/intel_snps_phy.c

87

intel_de_write(display, SNPS_PHY_TX_EQ(ln, phy), val);

sys/dev/pci/drm/i915/display/intel_snps_phy.h

19

void intel_snps_phy_wait_for_calibration(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_sprite.c

1013

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_sprite.c

1021

if (display->platform.sandybridge)

sys/dev/pci/drm/i915/display/intel_sprite.c

104

intel_de_write_fw(display, SPCSCYGOFF(plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

106

intel_de_write_fw(display, SPCSCCBOFF(plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

108

intel_de_write_fw(display, SPCSCCROFF(plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

1082

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_sprite.c

1098

intel_de_write_fw(display, DVSGAMC_G4X(pipe, i - 1),

sys/dev/pci/drm/i915/display/intel_sprite.c

111

intel_de_write_fw(display, SPCSCC01(plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

1112

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_sprite.c

1127

intel_de_write_fw(display, DVSGAMC_ILK(pipe, i),

sys/dev/pci/drm/i915/display/intel_sprite.c

113

intel_de_write_fw(display, SPCSCC23(plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

1130

intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 0), gamma[i]);

sys/dev/pci/drm/i915/display/intel_sprite.c

1131

intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 1), gamma[i]);

sys/dev/pci/drm/i915/display/intel_sprite.c

1132

intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 2), gamma[i]);

sys/dev/pci/drm/i915/display/intel_sprite.c

1142

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

115

intel_de_write_fw(display, SPCSCC45(plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

1157

intel_de_write_fw(display, DVSSTRIDE(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

1159

intel_de_write_fw(display, DVSPOS(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

1161

intel_de_write_fw(display, DVSSIZE(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

1163

intel_de_write_fw(display, DVSSCALE(pipe), dvsscale);

sys/dev/pci/drm/i915/display/intel_sprite.c

117

intel_de_write_fw(display, SPCSCC67(plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

1172

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

1182

intel_de_write_fw(display, DVSKEYVAL(pipe), key->min_value);

sys/dev/pci/drm/i915/display/intel_sprite.c

1183

intel_de_write_fw(display, DVSKEYMSK(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

1185

intel_de_write_fw(display, DVSKEYMAX(pipe), key->max_value);

sys/dev/pci/drm/i915/display/intel_sprite.c

1188

intel_de_write_fw(display, DVSLINOFF(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

119

intel_de_write_fw(display, SPCSCC8(plane_id), SPCSC_C0(csc[8]));

sys/dev/pci/drm/i915/display/intel_sprite.c

1190

intel_de_write_fw(display, DVSTILEOFF(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

1198

intel_de_write_fw(display, DVSCNTR(pipe), dvscntr);

sys/dev/pci/drm/i915/display/intel_sprite.c

1199

intel_de_write_fw(display, DVSSURF(pipe), plane_state->surf);

sys/dev/pci/drm/i915/display/intel_sprite.c

1201

if (display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_sprite.c

121

intel_de_write_fw(display, SPCSCYGICLAMP(plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

1212

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

1215

intel_de_write_fw(display, DVSCNTR(pipe), 0);

sys/dev/pci/drm/i915/display/intel_sprite.c

1217

intel_de_write_fw(display, DVSSCALE(pipe), 0);

sys/dev/pci/drm/i915/display/intel_sprite.c

1218

intel_de_write_fw(display, DVSSURF(pipe), 0);

sys/dev/pci/drm/i915/display/intel_sprite.c

1225

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

1227

error->ctl = intel_de_read(display, DVSCNTR(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_sprite.c

1228

error->surf = intel_de_read(display, DVSSURF(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_sprite.c

1229

error->surflive = intel_de_read(display, DVSSURFLIVE(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_sprite.c

123

intel_de_write_fw(display, SPCSCCBICLAMP(plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

1236

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

1242

wakeref = intel_display_power_get_if_enabled(display, power_domain);

sys/dev/pci/drm/i915/display/intel_sprite.c

1246

ret = intel_de_read(display, DVSCNTR(plane->pipe)) & DVS_ENABLE;

sys/dev/pci/drm/i915/display/intel_sprite.c

125

intel_de_write_fw(display, SPCSCCRICLAMP(plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

1250

intel_display_power_put(display, power_domain, wakeref);

sys/dev/pci/drm/i915/display/intel_sprite.c

1276

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_sprite.c

128

intel_de_write_fw(display, SPCSCYGOCLAMP(plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

130

intel_de_write_fw(display, SPCSCCBOCLAMP(plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

1302

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_sprite.c

1315

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_sprite.c

132

intel_de_write_fw(display, SPCSCCROCLAMP(plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

1322

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_sprite.c

1329

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_sprite.c

1342

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_sprite.c

1348

if (DISPLAY_VER(display) < 7) {

sys/dev/pci/drm/i915/display/intel_sprite.c

1351

} else if (display->platform.ivybridge) {

sys/dev/pci/drm/i915/display/intel_sprite.c

1377

if (DISPLAY_VER(display) >= 7)

sys/dev/pci/drm/i915/display/intel_sprite.c

1387

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_sprite.c

1391

if (display->platform.cherryview &&

sys/dev/pci/drm/i915/display/intel_sprite.c

1394

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_sprite.c

142

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_sprite.c

1593

intel_sprite_plane_create(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_sprite.c

1608

if (display->platform.valleyview || display->platform.cherryview) {

sys/dev/pci/drm/i915/display/intel_sprite.c

1621

if (intel_scanout_needs_vtd_wa(display))

sys/dev/pci/drm/i915/display/intel_sprite.c

1624

if (display->platform.cherryview && pipe == PIPE_B) {

sys/dev/pci/drm/i915/display/intel_sprite.c

1633

} else if (DISPLAY_VER(display) >= 7) {

sys/dev/pci/drm/i915/display/intel_sprite.c

1642

if (display->platform.broadwell || display->platform.haswell) {

sys/dev/pci/drm/i915/display/intel_sprite.c

1652

if (intel_scanout_needs_vtd_wa(display))

sys/dev/pci/drm/i915/display/intel_sprite.c

1671

if (intel_scanout_needs_vtd_wa(display))

sys/dev/pci/drm/i915/display/intel_sprite.c

1674

if (display->platform.sandybridge) {

sys/dev/pci/drm/i915/display/intel_sprite.c

1687

if (display->platform.cherryview && pipe == PIPE_B) {

sys/dev/pci/drm/i915/display/intel_sprite.c

1700

modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_TILING_X);

sys/dev/pci/drm/i915/display/intel_sprite.c

1702

ret = drm_universal_plane_init(display->drm, &plane->base,

sys/dev/pci/drm/i915/display/intel_sprite.c

1706

"sprite %c", sprite_name(display, pipe, sprite));

sys/dev/pci/drm/i915/display/intel_sprite.c

172

intel_de_write_fw(display, SPCLRC0(pipe, plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

174

intel_de_write_fw(display, SPCLRC1(pipe, plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

344

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_sprite.c

361

intel_de_write_fw(display, SPGAMC(pipe, plane_id, i - 1),

sys/dev/pci/drm/i915/display/intel_sprite.c

371

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

379

intel_de_write_fw(display, SPSTRIDE(pipe, plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

381

intel_de_write_fw(display, SPPOS(pipe, plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

383

intel_de_write_fw(display, SPSIZE(pipe, plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

393

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

403

if (display->platform.cherryview && pipe == PIPE_B)

sys/dev/pci/drm/i915/display/intel_sprite.c

407

intel_de_write_fw(display, SPKEYMINVAL(pipe, plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

409

intel_de_write_fw(display, SPKEYMSK(pipe, plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

411

intel_de_write_fw(display, SPKEYMAXVAL(pipe, plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

415

intel_de_write_fw(display, SPCONSTALPHA(pipe, plane_id), 0);

sys/dev/pci/drm/i915/display/intel_sprite.c

417

intel_de_write_fw(display, SPLINOFF(pipe, plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

419

intel_de_write_fw(display, SPTILEOFF(pipe, plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

427

intel_de_write_fw(display, SPCNTR(pipe, plane_id), sprctl);

sys/dev/pci/drm/i915/display/intel_sprite.c

428

intel_de_write_fw(display, SPSURF(pipe, plane_id), plane_state->surf);

sys/dev/pci/drm/i915/display/intel_sprite.c

439

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

443

intel_de_write_fw(display, SPCNTR(pipe, plane_id), 0);

sys/dev/pci/drm/i915/display/intel_sprite.c

444

intel_de_write_fw(display, SPSURF(pipe, plane_id), 0);

sys/dev/pci/drm/i915/display/intel_sprite.c

451

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

453

error->ctl = intel_de_read(display, SPCNTR(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/intel_sprite.c

454

error->surf = intel_de_read(display, SPSURF(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/intel_sprite.c

455

error->surflive = intel_de_read(display, SPSURFLIVE(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/intel_sprite.c

462

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

469

wakeref = intel_display_power_get_if_enabled(display, power_domain);

sys/dev/pci/drm/i915/display/intel_sprite.c

473

ret = intel_de_read(display, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;

sys/dev/pci/drm/i915/display/intel_sprite.c

477

intel_display_power_put(display, power_domain, wakeref);

sys/dev/pci/drm/i915/display/intel_sprite.c

52

static char sprite_name(struct intel_display *display, enum pipe pipe, int sprite)

sys/dev/pci/drm/i915/display/intel_sprite.c

54

return pipe * DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + sprite + 'A';

sys/dev/pci/drm/i915/display/intel_sprite.c

655

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_sprite.c

659

(display->platform.ivybridge || display->platform.haswell);

sys/dev/pci/drm/i915/display/intel_sprite.c

664

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_sprite.c

672

if (display->platform.ivybridge)

sys/dev/pci/drm/i915/display/intel_sprite.c

70

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_sprite.c

761

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_sprite.c

774

intel_de_write_fw(display, SPRGAMC(pipe, i),

sys/dev/pci/drm/i915/display/intel_sprite.c

777

intel_de_write_fw(display, SPRGAMC16(pipe, 0), gamma[i]);

sys/dev/pci/drm/i915/display/intel_sprite.c

778

intel_de_write_fw(display, SPRGAMC16(pipe, 1), gamma[i]);

sys/dev/pci/drm/i915/display/intel_sprite.c

779

intel_de_write_fw(display, SPRGAMC16(pipe, 2), gamma[i]);

sys/dev/pci/drm/i915/display/intel_sprite.c

782

intel_de_write_fw(display, SPRGAMC17(pipe, 0), gamma[i]);

sys/dev/pci/drm/i915/display/intel_sprite.c

783

intel_de_write_fw(display, SPRGAMC17(pipe, 1), gamma[i]);

sys/dev/pci/drm/i915/display/intel_sprite.c

784

intel_de_write_fw(display, SPRGAMC17(pipe, 2), gamma[i]);

sys/dev/pci/drm/i915/display/intel_sprite.c

794

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

809

intel_de_write_fw(display, SPRSTRIDE(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

811

intel_de_write_fw(display, SPRPOS(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

813

intel_de_write_fw(display, SPRSIZE(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

815

if (display->platform.ivybridge)

sys/dev/pci/drm/i915/display/intel_sprite.c

816

intel_de_write_fw(display, SPRSCALE(pipe), sprscale);

sys/dev/pci/drm/i915/display/intel_sprite.c

825

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

835

intel_de_write_fw(display, SPRKEYVAL(pipe), key->min_value);

sys/dev/pci/drm/i915/display/intel_sprite.c

836

intel_de_write_fw(display, SPRKEYMSK(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

838

intel_de_write_fw(display, SPRKEYMAX(pipe), key->max_value);

sys/dev/pci/drm/i915/display/intel_sprite.c

843

if (display->platform.haswell || display->platform.broadwell) {

sys/dev/pci/drm/i915/display/intel_sprite.c

844

intel_de_write_fw(display, SPROFFSET(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

847

intel_de_write_fw(display, SPRLINOFF(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

849

intel_de_write_fw(display, SPRTILEOFF(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

858

intel_de_write_fw(display, SPRCTL(pipe), sprctl);

sys/dev/pci/drm/i915/display/intel_sprite.c

859

intel_de_write_fw(display, SPRSURF(pipe), plane_state->surf);

sys/dev/pci/drm/i915/display/intel_sprite.c

869

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

872

intel_de_write_fw(display, SPRCTL(pipe), 0);

sys/dev/pci/drm/i915/display/intel_sprite.c

874

if (display->platform.ivybridge)

sys/dev/pci/drm/i915/display/intel_sprite.c

875

intel_de_write_fw(display, SPRSCALE(pipe), 0);

sys/dev/pci/drm/i915/display/intel_sprite.c

876

intel_de_write_fw(display, SPRSURF(pipe), 0);

sys/dev/pci/drm/i915/display/intel_sprite.c

883

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

885

error->ctl = intel_de_read(display, SPRCTL(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_sprite.c

886

error->surf = intel_de_read(display, SPRSURF(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_sprite.c

887

error->surflive = intel_de_read(display, SPRSURFLIVE(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_sprite.c

894

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

900

wakeref = intel_display_power_get_if_enabled(display, power_domain);

sys/dev/pci/drm/i915/display/intel_sprite.c

904

ret = intel_de_read(display, SPRCTL(plane->pipe)) & SPRITE_ENABLE;

sys/dev/pci/drm/i915/display/intel_sprite.c

908

intel_display_power_put(display, power_domain, wakeref);

sys/dev/pci/drm/i915/display/intel_sprite.c

990

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

992

if (intel_scanout_needs_vtd_wa(display))

sys/dev/pci/drm/i915/display/intel_sprite.h

17

struct intel_plane *intel_sprite_plane_create(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_sprite.h

29

static inline struct intel_plane *intel_sprite_plane_create(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_sprite_uapi.c

101

if (!ret && has_dst_key_in_primary_plane(display)) {

sys/dev/pci/drm/i915/display/intel_sprite_uapi.c

103

intel_crtc_for_pipe(display,

sys/dev/pci/drm/i915/display/intel_sprite_uapi.c

11

static bool has_dst_key_in_primary_plane(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_sprite_uapi.c

13

return DISPLAY_VER(display) >= 9;

sys/dev/pci/drm/i915/display/intel_sprite_uapi.c

19

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/intel_sprite_uapi.c

37

if (DISPLAY_VER(display) >= 9 && plane->id != PLANE_PRIMARY &&

sys/dev/pci/drm/i915/display/intel_sprite_uapi.c

45

struct intel_display *display = to_intel_display(dev);

sys/dev/pci/drm/i915/display/intel_sprite_uapi.c

63

if ((display->platform.valleyview || display->platform.cherryview) &&

sys/dev/pci/drm/i915/display/intel_sprite_uapi.c

76

if (DISPLAY_VER(display) >= 9 &&

sys/dev/pci/drm/i915/display/intel_tc.c

1013

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1016

u32 pica_isr_bits = display->hotplug.hpd[hpd_pin];

sys/dev/pci/drm/i915/display/intel_tc.c

1017

u32 pch_isr_bit = display->hotplug.pch_hpd[hpd_pin];

sys/dev/pci/drm/i915/display/intel_tc.c

1023

with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) {

sys/dev/pci/drm/i915/display/intel_tc.c

1024

pica_isr = intel_de_read(display, PICAINTERRUPT_ISR);

sys/dev/pci/drm/i915/display/intel_tc.c

1025

pch_isr = intel_de_read(display, SDEISR);

sys/dev/pci/drm/i915/display/intel_tc.c

1042

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1044

i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);

sys/dev/pci/drm/i915/display/intel_tc.c

1048

return intel_de_read(display, reg) & XELPDP_TCSS_POWER_STATE;

sys/dev/pci/drm/i915/display/intel_tc.c

1054

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1062

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_tc.c

1076

static void xelpdp_tc_power_request_wa(struct intel_display *display, bool enable)

sys/dev/pci/drm/i915/display/intel_tc.c

1079

if (intel_de_wait_for_clear(display, TCSS_DISP_MAILBOX_IN_CMD,

sys/dev/pci/drm/i915/display/intel_tc.c

1081

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_tc.c

1086

intel_de_write(display, TCSS_DISP_MAILBOX_IN_DATA, enable ? 1 : 0);

sys/dev/pci/drm/i915/display/intel_tc.c

1087

intel_de_write(display, TCSS_DISP_MAILBOX_IN_CMD,

sys/dev/pci/drm/i915/display/intel_tc.c

1092

if (intel_de_wait_for_clear(display, TCSS_DISP_MAILBOX_IN_CMD,

sys/dev/pci/drm/i915/display/intel_tc.c

1094

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_tc.c

1102

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1104

i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);

sys/dev/pci/drm/i915/display/intel_tc.c

1109

if (DISPLAY_VER(display) == 30)

sys/dev/pci/drm/i915/display/intel_tc.c

1110

xelpdp_tc_power_request_wa(display, enable);

sys/dev/pci/drm/i915/display/intel_tc.c

1112

val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_tc.c

1117

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_tc.c

1122

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1135

if (drm_WARN_ON(display->drm, tc->mode == TC_PORT_LEGACY))

sys/dev/pci/drm/i915/display/intel_tc.c

1149

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1151

i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);

sys/dev/pci/drm/i915/display/intel_tc.c

1156

val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_tc.c

1161

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/intel_tc.c

1166

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1168

i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);

sys/dev/pci/drm/i915/display/intel_tc.c

1172

return intel_de_read(display, reg) & XELPDP_TC_PHY_OWNERSHIP;

sys/dev/pci/drm/i915/display/intel_tc.c

1177

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1196

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_tc.c

1274

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1280

drm_WARN_ON_ONCE(display->drm, hweight32(mask) > 1);

sys/dev/pci/drm/i915/display/intel_tc.c

1304

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1306

if (DISPLAY_VER(display) < 20) {

sys/dev/pci/drm/i915/display/intel_tc.c

1307

drm_WARN_ON(display->drm, phy_is_owned && !phy_is_ready);

sys/dev/pci/drm/i915/display/intel_tc.c

1318

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1328

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_tc.c

1341

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1349

drm_err(display->drm, "Port %s: timeout waiting for PHY ready\n",

sys/dev/pci/drm/i915/display/intel_tc.c

1419

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1439

drm_WARN_ON(display->drm, live_mode == TC_PORT_TBT_ALT);

sys/dev/pci/drm/i915/display/intel_tc.c

1443

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_tc.c

1483

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1497

drm_WARN_ON(display->drm, !connected);

sys/dev/pci/drm/i915/display/intel_tc.c

1518

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1522

intel_display_power_flush_work(display);

sys/dev/pci/drm/i915/display/intel_tc.c

1527

if (intel_display_power_is_enabled(display, aux_domain))

sys/dev/pci/drm/i915/display/intel_tc.c

1528

drm_dbg_kms(display->drm, "Port %s: AUX unexpectedly powered\n",

sys/dev/pci/drm/i915/display/intel_tc.c

1536

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_tc.c

1570

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1575

return intel_de_read(display, DDI_BUF_CTL(dig_port->base.port)) &

sys/dev/pci/drm/i915/display/intel_tc.c

1588

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1594

drm_WARN_ON(display->drm, tc->mode != TC_PORT_DISCONNECTED);

sys/dev/pci/drm/i915/display/intel_tc.c

1595

drm_WARN_ON(display->drm, tc->lock_wakeref);

sys/dev/pci/drm/i915/display/intel_tc.c

1596

drm_WARN_ON(display->drm, tc->link_refcount);

sys/dev/pci/drm/i915/display/intel_tc.c

1619

drm_WARN_ON(display->drm, !tc->legacy_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1620

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_tc.c

1638

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1652

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_tc.c

1674

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1679

drm_WARN_ON(display->drm, tc->link_refcount != 1);

sys/dev/pci/drm/i915/display/intel_tc.c

1689

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_tc.c

1697

drm_dbg_kms(display->drm, "Port %s: sanitize mode (%s) pin assignment: %c max lanes: %d\n",

sys/dev/pci/drm/i915/display/intel_tc.c

1718

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_tc.c

1723

drm_WARN_ON(display->drm, !intel_tc_port_ref_held(dig_port));

sys/dev/pci/drm/i915/display/intel_tc.c

1758

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1765

ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, ctx);

sys/dev/pci/drm/i915/display/intel_tc.c

1776

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {

sys/dev/pci/drm/i915/display/intel_tc.c

178

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1794

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1800

_state = drm_atomic_state_alloc(display->drm);

sys/dev/pci/drm/i915/display/intel_tc.c

1819

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

182

intel_display_power_legacy_aux_domain(display, dig_port->aux_ch);

sys/dev/pci/drm/i915/display/intel_tc.c

1825

mutex_lock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/intel_tc.c

1827

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_tc.c

1831

drm_WARN_ON(display->drm, ret);

sys/dev/pci/drm/i915/display/intel_tc.c

1833

mutex_unlock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/intel_tc.c

1861

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1871

drm_WARN_ON(display->drm, tc->mode == TC_PORT_DISCONNECTED);

sys/dev/pci/drm/i915/display/intel_tc.c

1872

drm_WARN_ON(display->drm, tc->mode != TC_PORT_TBT_ALT && !tc_phy_is_owned(tc));

sys/dev/pci/drm/i915/display/intel_tc.c

188

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

192

return intel_display_power_get(display, *domain);

sys/dev/pci/drm/i915/display/intel_tc.c

1965

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

1970

if (drm_WARN_ON(display->drm, tc_port == TC_PORT_NONE))

sys/dev/pci/drm/i915/display/intel_tc.c

1980

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_tc.c

1982

else if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/intel_tc.c

1984

else if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_tc.c

212

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

214

intel_display_power_put(display, domain, wakeref);

sys/dev/pci/drm/i915/display/intel_tc.c

220

struct intel_display __maybe_unused *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

224

drm_WARN_ON(display->drm, tc->lock_power_domain != domain);

sys/dev/pci/drm/i915/display/intel_tc.c

232

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

234

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_tc.c

235

!intel_display_power_is_enabled(display, POWER_DOMAIN_DISPLAY_CORE));

sys/dev/pci/drm/i915/display/intel_tc.c

241

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

244

enabled = intel_display_power_is_enabled(display,

sys/dev/pci/drm/i915/display/intel_tc.c

246

drm_WARN_ON(display->drm, !enabled);

sys/dev/pci/drm/i915/display/intel_tc.c

263

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

265

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_tc.c

266

!intel_display_power_is_enabled(display, tc_port_power_domain(tc)));

sys/dev/pci/drm/i915/display/intel_tc.c

271

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

275

with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref)

sys/dev/pci/drm/i915/display/intel_tc.c

276

lane_mask = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia));

sys/dev/pci/drm/i915/display/intel_tc.c

278

drm_WARN_ON(display->drm, lane_mask == 0xffffffff);

sys/dev/pci/drm/i915/display/intel_tc.c

296

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

307

if (DISPLAY_VER(display) >= 20) {

sys/dev/pci/drm/i915/display/intel_tc.c

315

with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref)

sys/dev/pci/drm/i915/display/intel_tc.c

316

val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_tc.c

318

drm_WARN_ON(display->drm, val == 0xffffffff);

sys/dev/pci/drm/i915/display/intel_tc.c

327

drm_WARN_ON(display->drm, DISPLAY_VER(display) > 11);

sys/dev/pci/drm/i915/display/intel_tc.c

386

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

391

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_tc.c

427

struct intel_display *display = to_intel_display(dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

432

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_tc.c

435

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_tc.c

440

val = intel_de_read(display, PORT_TX_DFLEXDPMLE1(tc->phy_fia));

sys/dev/pci/drm/i915/display/intel_tc.c

461

intel_de_write(display, PORT_TX_DFLEXDPMLE1(tc->phy_fia), val);

sys/dev/pci/drm/i915/display/intel_tc.c

467

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

470

drm_WARN_ON(display->drm, tc->mode != TC_PORT_DISCONNECTED);

sys/dev/pci/drm/i915/display/intel_tc.c

485

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_tc.c

516

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

520

return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch);

sys/dev/pci/drm/i915/display/intel_tc.c

527

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

529

u32 isr_bit = display->hotplug.pch_hpd[dig_port->base.hpd_pin];

sys/dev/pci/drm/i915/display/intel_tc.c

535

with_intel_display_power(display, tc_phy_cold_off_domain(tc), wakeref) {

sys/dev/pci/drm/i915/display/intel_tc.c

536

fia_isr = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia));

sys/dev/pci/drm/i915/display/intel_tc.c

537

pch_isr = intel_de_read(display, SDEISR);

sys/dev/pci/drm/i915/display/intel_tc.c

541

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_tc.c

568

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

573

val = intel_de_read(display, PORT_TX_DFLEXDPPMS(tc->phy_fia));

sys/dev/pci/drm/i915/display/intel_tc.c

575

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_tc.c

587

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

592

val = intel_de_read(display, PORT_TX_DFLEXDPCSSS(tc->phy_fia));

sys/dev/pci/drm/i915/display/intel_tc.c

594

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_tc.c

605

intel_de_write(display, PORT_TX_DFLEXDPCSSS(tc->phy_fia), val);

sys/dev/pci/drm/i915/display/intel_tc.c

612

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

617

val = intel_de_read(display, PORT_TX_DFLEXDPCSSS(tc->phy_fia));

sys/dev/pci/drm/i915/display/intel_tc.c

619

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_tc.c

659

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

665

drm_WARN_ON(display->drm, max_lanes != 4);

sys/dev/pci/drm/i915/display/intel_tc.c

669

drm_WARN_ON(display->drm, tc->mode != TC_PORT_DP_ALT);

sys/dev/pci/drm/i915/display/intel_tc.c

676

drm_dbg_kms(display->drm, "Port %s: PHY sudden disconnect\n",

sys/dev/pci/drm/i915/display/intel_tc.c

682

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_tc.c

695

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

707

!drm_WARN_ON(display->drm, tc->mode == TC_PORT_LEGACY)) {

sys/dev/pci/drm/i915/display/intel_tc.c

708

drm_dbg_kms(display->drm, "Port %s: can't take PHY ownership (ready %s)\n",

sys/dev/pci/drm/i915/display/intel_tc.c

776

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

780

with_intel_display_power(display, tc_phy_cold_off_domain(tc), wakeref)

sys/dev/pci/drm/i915/display/intel_tc.c

781

val = intel_de_read(display, PORT_TX_DFLEXDPSP(FIA1));

sys/dev/pci/drm/i915/display/intel_tc.c

783

drm_WARN_ON(display->drm, val == 0xffffffff);

sys/dev/pci/drm/i915/display/intel_tc.c

806

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

810

return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch);

sys/dev/pci/drm/i915/display/intel_tc.c

817

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

820

u32 cpu_isr_bits = display->hotplug.hpd[hpd_pin];

sys/dev/pci/drm/i915/display/intel_tc.c

821

u32 pch_isr_bit = display->hotplug.pch_hpd[hpd_pin];

sys/dev/pci/drm/i915/display/intel_tc.c

827

with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) {

sys/dev/pci/drm/i915/display/intel_tc.c

828

cpu_isr = intel_de_read(display, GEN11_DE_HPD_ISR);

sys/dev/pci/drm/i915/display/intel_tc.c

829

pch_isr = intel_de_read(display, SDEISR);

sys/dev/pci/drm/i915/display/intel_tc.c

852

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

858

val = intel_de_read(display, TCSS_DDI_STATUS(tc_port));

sys/dev/pci/drm/i915/display/intel_tc.c

860

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_tc.c

872

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

877

intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_TC_PHY_OWNERSHIP,

sys/dev/pci/drm/i915/display/intel_tc.c

885

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

891

val = intel_de_read(display, DDI_BUF_CTL(port));

sys/dev/pci/drm/i915/display/intel_tc.c

897

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

902

port_wakeref = intel_display_power_get(display, port_power_domain);

sys/dev/pci/drm/i915/display/intel_tc.c

911

intel_display_power_put(display, port_power_domain, port_wakeref);

sys/dev/pci/drm/i915/display/intel_tc.c

916

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

929

port_wakeref = intel_display_power_get(display, port_power_domain);

sys/dev/pci/drm/i915/display/intel_tc.c

932

!drm_WARN_ON(display->drm, tc->mode == TC_PORT_LEGACY)) {

sys/dev/pci/drm/i915/display/intel_tc.c

933

drm_dbg_kms(display->drm, "Port %s: can't take PHY ownership\n",

sys/dev/pci/drm/i915/display/intel_tc.c

939

!drm_WARN_ON(display->drm, tc->mode == TC_PORT_LEGACY)) {

sys/dev/pci/drm/i915/display/intel_tc.c

940

drm_dbg_kms(display->drm, "Port %s: PHY not ready\n",

sys/dev/pci/drm/i915/display/intel_tc.c

952

intel_display_power_put(display, port_power_domain, port_wakeref);

sys/dev/pci/drm/i915/display/intel_tc.c

961

intel_display_power_put(display, port_power_domain, port_wakeref);

sys/dev/pci/drm/i915/display/intel_tc.c

968

struct intel_display *display = to_intel_display(tc->dig_port);

sys/dev/pci/drm/i915/display/intel_tc.c

973

port_wakeref = intel_display_power_get(display, port_power_domain);

sys/dev/pci/drm/i915/display/intel_tc.c

988

intel_display_power_put(display, port_power_domain, port_wakeref);

sys/dev/pci/drm/i915/display/intel_tdf.h

20

static inline void intel_td_flush(struct intel_display *display) {}

sys/dev/pci/drm/i915/display/intel_tdf.h

22

void intel_td_flush(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_tv.c

1094

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_tv.c

1106

tv_ctl = intel_de_read(display, TV_CTL);

sys/dev/pci/drm/i915/display/intel_tv.c

1107

hctl1 = intel_de_read(display, TV_H_CTL_1);

sys/dev/pci/drm/i915/display/intel_tv.c

1108

hctl3 = intel_de_read(display, TV_H_CTL_3);

sys/dev/pci/drm/i915/display/intel_tv.c

1109

vctl1 = intel_de_read(display, TV_V_CTL_1);

sys/dev/pci/drm/i915/display/intel_tv.c

1110

vctl2 = intel_de_read(display, TV_V_CTL_2);

sys/dev/pci/drm/i915/display/intel_tv.c

1145

tmp = intel_de_read(display, TV_WIN_POS);

sys/dev/pci/drm/i915/display/intel_tv.c

1149

tmp = intel_de_read(display, TV_WIN_SIZE);

sys/dev/pci/drm/i915/display/intel_tv.c

1155

drm_dbg_kms(display->drm, "TV mode: " DRM_MODE_FMT "\n",

sys/dev/pci/drm/i915/display/intel_tv.c

1168

if (display->platform.i965gm)

sys/dev/pci/drm/i915/display/intel_tv.c

1173

static bool intel_tv_source_too_wide(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_tv.c

1176

return DISPLAY_VER(display) == 3 && hdisplay > 1024;

sys/dev/pci/drm/i915/display/intel_tv.c

1194

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_tv.c

1216

drm_dbg_kms(display->drm, "forcing bpc to 8 for TV\n");

sys/dev/pci/drm/i915/display/intel_tv.c

1230

if (intel_tv_source_too_wide(display, hdisplay) ||

sys/dev/pci/drm/i915/display/intel_tv.c

1237

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_tv.c

1271

drm_dbg_kms(display->drm, "TV mode: " DRM_MODE_FMT "\n",

sys/dev/pci/drm/i915/display/intel_tv.c

1349

if (display->platform.i965gm)

sys/dev/pci/drm/i915/display/intel_tv.c

1357

set_tv_mode_timings(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_tv.c

1403

intel_de_write(display, TV_H_CTL_1, hctl1);

sys/dev/pci/drm/i915/display/intel_tv.c

1404

intel_de_write(display, TV_H_CTL_2, hctl2);

sys/dev/pci/drm/i915/display/intel_tv.c

1405

intel_de_write(display, TV_H_CTL_3, hctl3);

sys/dev/pci/drm/i915/display/intel_tv.c

1406

intel_de_write(display, TV_V_CTL_1, vctl1);

sys/dev/pci/drm/i915/display/intel_tv.c

1407

intel_de_write(display, TV_V_CTL_2, vctl2);

sys/dev/pci/drm/i915/display/intel_tv.c

1408

intel_de_write(display, TV_V_CTL_3, vctl3);

sys/dev/pci/drm/i915/display/intel_tv.c

1409

intel_de_write(display, TV_V_CTL_4, vctl4);

sys/dev/pci/drm/i915/display/intel_tv.c

1410

intel_de_write(display, TV_V_CTL_5, vctl5);

sys/dev/pci/drm/i915/display/intel_tv.c

1411

intel_de_write(display, TV_V_CTL_6, vctl6);

sys/dev/pci/drm/i915/display/intel_tv.c

1412

intel_de_write(display, TV_V_CTL_7, vctl7);

sys/dev/pci/drm/i915/display/intel_tv.c

1415

static void set_color_conversion(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_tv.c

1418

intel_de_write(display, TV_CSC_Y,

sys/dev/pci/drm/i915/display/intel_tv.c

1420

intel_de_write(display, TV_CSC_Y2,

sys/dev/pci/drm/i915/display/intel_tv.c

1422

intel_de_write(display, TV_CSC_U,

sys/dev/pci/drm/i915/display/intel_tv.c

1424

intel_de_write(display, TV_CSC_U2,

sys/dev/pci/drm/i915/display/intel_tv.c

1426

intel_de_write(display, TV_CSC_V,

sys/dev/pci/drm/i915/display/intel_tv.c

1428

intel_de_write(display, TV_CSC_V2,

sys/dev/pci/drm/i915/display/intel_tv.c

1437

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_tv.c

1452

tv_ctl = intel_de_read(display, TV_CTL);

sys/dev/pci/drm/i915/display/intel_tv.c

1524

if (display->platform.i915gm)

sys/dev/pci/drm/i915/display/intel_tv.c

1527

set_tv_mode_timings(display, tv_mode, burst_ena);

sys/dev/pci/drm/i915/display/intel_tv.c

1529

intel_de_write(display, TV_SC_CTL_1, scctl1);

sys/dev/pci/drm/i915/display/intel_tv.c

1530

intel_de_write(display, TV_SC_CTL_2, scctl2);

sys/dev/pci/drm/i915/display/intel_tv.c

1531

intel_de_write(display, TV_SC_CTL_3, scctl3);

sys/dev/pci/drm/i915/display/intel_tv.c

1533

set_color_conversion(display, color_conversion);

sys/dev/pci/drm/i915/display/intel_tv.c

1535

if (DISPLAY_VER(display) >= 4)

sys/dev/pci/drm/i915/display/intel_tv.c

1536

intel_de_write(display, TV_CLR_KNOBS, 0x00404000);

sys/dev/pci/drm/i915/display/intel_tv.c

1538

intel_de_write(display, TV_CLR_KNOBS, 0x00606000);

sys/dev/pci/drm/i915/display/intel_tv.c

1541

intel_de_write(display, TV_CLR_LEVEL,

sys/dev/pci/drm/i915/display/intel_tv.c

1544

assert_transcoder_disabled(display, pipe_config->cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_tv.c

1550

intel_de_write(display, TV_FILTER_CTL_1, tv_filter_ctl);

sys/dev/pci/drm/i915/display/intel_tv.c

1561

intel_de_write(display, TV_WIN_POS, (xpos << 16) | ypos);

sys/dev/pci/drm/i915/display/intel_tv.c

1562

intel_de_write(display, TV_WIN_SIZE, (xsize << 16) | ysize);

sys/dev/pci/drm/i915/display/intel_tv.c

1566

intel_de_write(display, TV_H_LUMA(i),

sys/dev/pci/drm/i915/display/intel_tv.c

1569

intel_de_write(display, TV_H_CHROMA(i),

sys/dev/pci/drm/i915/display/intel_tv.c

1572

intel_de_write(display, TV_V_LUMA(i),

sys/dev/pci/drm/i915/display/intel_tv.c

1575

intel_de_write(display, TV_V_CHROMA(i),

sys/dev/pci/drm/i915/display/intel_tv.c

1577

intel_de_write(display, TV_DAC,

sys/dev/pci/drm/i915/display/intel_tv.c

1578

intel_de_read(display, TV_DAC) & TV_DAC_SAVE);

sys/dev/pci/drm/i915/display/intel_tv.c

1579

intel_de_write(display, TV_CTL, tv_ctl);

sys/dev/pci/drm/i915/display/intel_tv.c

1586

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_tv.c

1594

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_tv.c

1595

i915_disable_pipestat(display, 0,

sys/dev/pci/drm/i915/display/intel_tv.c

1598

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_tv.c

1601

save_tv_dac = tv_dac = intel_de_read(display, TV_DAC);

sys/dev/pci/drm/i915/display/intel_tv.c

1602

save_tv_ctl = tv_ctl = intel_de_read(display, TV_CTL);

sys/dev/pci/drm/i915/display/intel_tv.c

1624

if (display->platform.gm45)

sys/dev/pci/drm/i915/display/intel_tv.c

1628

intel_de_write(display, TV_CTL, tv_ctl);

sys/dev/pci/drm/i915/display/intel_tv.c

1629

intel_de_write(display, TV_DAC, tv_dac);

sys/dev/pci/drm/i915/display/intel_tv.c

1630

intel_de_posting_read(display, TV_DAC);

sys/dev/pci/drm/i915/display/intel_tv.c

1635

tv_dac = intel_de_read(display, TV_DAC);

sys/dev/pci/drm/i915/display/intel_tv.c

1636

drm_dbg_kms(display->drm, "TV detected: %x, %x\n", tv_ctl, tv_dac);

sys/dev/pci/drm/i915/display/intel_tv.c

1644

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_tv.c

1648

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_tv.c

1652

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_tv.c

1656

drm_dbg_kms(display->drm, "Unrecognised TV connection\n");

sys/dev/pci/drm/i915/display/intel_tv.c

1660

intel_de_write(display, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);

sys/dev/pci/drm/i915/display/intel_tv.c

1661

intel_de_write(display, TV_CTL, save_tv_ctl);

sys/dev/pci/drm/i915/display/intel_tv.c

1662

intel_de_posting_read(display, TV_CTL);

sys/dev/pci/drm/i915/display/intel_tv.c

1669

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_tv.c

1670

i915_enable_pipestat(display, 0,

sys/dev/pci/drm/i915/display/intel_tv.c

1673

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/intel_tv.c

1712

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_tv.c

1717

drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n",

sys/dev/pci/drm/i915/display/intel_tv.c

1720

if (!intel_display_device_enabled(display))

sys/dev/pci/drm/i915/display/intel_tv.c

1723

if (!intel_display_driver_check_access(display))

sys/dev/pci/drm/i915/display/intel_tv.c

1792

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_tv.c

1806

if (DISPLAY_VER(display) == 3 && input->w > 1024 &&

sys/dev/pci/drm/i915/display/intel_tv.c

1823

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_tv.c

1889

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_tv.c

1905

if (DISPLAY_VER(display) == 3 && tv_modes[i].oversample == 1)

sys/dev/pci/drm/i915/display/intel_tv.c

1910

drm_mode_create_tv_properties_legacy(display->drm, i, tv_format_names);

sys/dev/pci/drm/i915/display/intel_tv.c

1913

display->drm->mode_config.legacy_tv_mode_property,

sys/dev/pci/drm/i915/display/intel_tv.c

1916

display->drm->mode_config.tv_left_margin_property,

sys/dev/pci/drm/i915/display/intel_tv.c

1919

display->drm->mode_config.tv_top_margin_property,

sys/dev/pci/drm/i915/display/intel_tv.c

1922

display->drm->mode_config.tv_right_margin_property,

sys/dev/pci/drm/i915/display/intel_tv.c

1925

display->drm->mode_config.tv_bottom_margin_property,

sys/dev/pci/drm/i915/display/intel_tv.c

1930

intel_tv_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_tv.c

1938

if ((intel_de_read(display, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)

sys/dev/pci/drm/i915/display/intel_tv.c

1941

if (!intel_bios_is_tv_present(display)) {

sys/dev/pci/drm/i915/display/intel_tv.c

1942

drm_dbg_kms(display->drm, "Integrated TV is not present.\n");

sys/dev/pci/drm/i915/display/intel_tv.c

1950

save_tv_dac = intel_de_read(display, TV_DAC);

sys/dev/pci/drm/i915/display/intel_tv.c

1952

intel_de_write(display, TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);

sys/dev/pci/drm/i915/display/intel_tv.c

1953

tv_dac_on = intel_de_read(display, TV_DAC);

sys/dev/pci/drm/i915/display/intel_tv.c

1955

intel_de_write(display, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);

sys/dev/pci/drm/i915/display/intel_tv.c

1956

tv_dac_off = intel_de_read(display, TV_DAC);

sys/dev/pci/drm/i915/display/intel_tv.c

1958

intel_de_write(display, TV_DAC, save_tv_dac);

sys/dev/pci/drm/i915/display/intel_tv.c

1996

drm_connector_init(display->drm, connector, &intel_tv_connector_funcs,

sys/dev/pci/drm/i915/display/intel_tv.c

1999

drm_encoder_init(display->drm, &intel_encoder->base,

sys/dev/pci/drm/i915/display/intel_tv.c

918

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_tv.c

919

u32 tmp = intel_de_read(display, TV_CTL);

sys/dev/pci/drm/i915/display/intel_tv.c

932

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_tv.c

937

intel_de_rmw(display, TV_CTL, 0, TV_ENC_ENABLE);

sys/dev/pci/drm/i915/display/intel_tv.c

946

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/intel_tv.c

948

intel_de_rmw(display, TV_CTL, TV_ENC_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_tv.c

962

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/intel_tv.c

964

int max_dotclk = display->cdclk.max_dotclk_freq;

sys/dev/pci/drm/i915/display/intel_tv.c

967

status = intel_cpu_transcoder_mode_valid(display, mode);

sys/dev/pci/drm/i915/display/intel_tv.h

12

void intel_tv_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_tv.h

14

static inline void intel_tv_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_vblank.c

111

frame = intel_de_read64_2x32(display, PIPEFRAMEPIXEL(display, pipe),

sys/dev/pci/drm/i915/display/intel_vblank.c

112

PIPEFRAME(display, pipe));

sys/dev/pci/drm/i915/display/intel_vblank.c

127

struct intel_display *display = to_intel_display(crtc->dev);

sys/dev/pci/drm/i915/display/intel_vblank.c

134

return intel_de_read(display, PIPE_FRMCOUNT_G4X(display, pipe));

sys/dev/pci/drm/i915/display/intel_vblank.c

139

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_vblank.c

158

scan_prev_time = intel_de_read_fw(display,

sys/dev/pci/drm/i915/display/intel_vblank.c

165

scan_curr_time = intel_de_read_fw(display, IVB_TIMESTAMP_CTR);

sys/dev/pci/drm/i915/display/intel_vblank.c

167

scan_post_time = intel_de_read_fw(display,

sys/dev/pci/drm/i915/display/intel_vblank.c

200

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vblank.c

228

if (DISPLAY_VER(display) >= 20 || display->platform.battlemage)

sys/dev/pci/drm/i915/display/intel_vblank.c

230

else if (DISPLAY_VER(display) >= 9 ||

sys/dev/pci/drm/i915/display/intel_vblank.c

231

display->platform.broadwell || display->platform.haswell)

sys/dev/pci/drm/i915/display/intel_vblank.c

233

else if (DISPLAY_VER(display) >= 3)

sys/dev/pci/drm/i915/display/intel_vblank.c

245

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_vblank.c

259

position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;

sys/dev/pci/drm/i915/display/intel_vblank.c

273

if (HAS_DDI(display) && !position) {

sys/dev/pci/drm/i915/display/intel_vblank.c

278

temp = intel_de_read_fw(display,

sys/dev/pci/drm/i915/display/intel_vblank.c

279

PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;

sys/dev/pci/drm/i915/display/intel_vblank.c

305

static void intel_vblank_section_enter(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_vblank.c

308

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_vblank.c

312

static void intel_vblank_section_exit(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_vblank.c

315

struct drm_i915_private *i915 = to_i915(display->drm);

sys/dev/pci/drm/i915/display/intel_vblank.c

319

static void intel_vblank_section_enter(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_vblank.c

323

static void intel_vblank_section_exit(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_vblank.c

334

struct intel_display *display = to_intel_display(_crtc->dev);

sys/dev/pci/drm/i915/display/intel_vblank.c

340

bool use_scanline_counter = DISPLAY_VER(display) >= 5 ||

sys/dev/pci/drm/i915/display/intel_vblank.c

341

display->platform.g4x || DISPLAY_VER(display) == 2 ||

sys/dev/pci/drm/i915/display/intel_vblank.c

344

if (drm_WARN_ON(display->drm, !mode->crtc_clock)) {

sys/dev/pci/drm/i915/display/intel_vblank.c

345

drm_dbg(display->drm,

sys/dev/pci/drm/i915/display/intel_vblank.c

363

intel_vblank_section_enter(display);

sys/dev/pci/drm/i915/display/intel_vblank.c

395

position = (intel_de_read_fw(display, PIPEFRAMEPIXEL(display, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;

sys/dev/pci/drm/i915/display/intel_vblank.c

431

intel_vblank_section_exit(display);

sys/dev/pci/drm/i915/display/intel_vblank.c

466

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_vblank.c

471

intel_vblank_section_enter(display);

sys/dev/pci/drm/i915/display/intel_vblank.c

475

intel_vblank_section_exit(display);

sys/dev/pci/drm/i915/display/intel_vblank.c

481

static bool pipe_scanline_is_moving(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_vblank.c

484

i915_reg_t reg = PIPEDSL(display, pipe);

sys/dev/pci/drm/i915/display/intel_vblank.c

487

line1 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;

sys/dev/pci/drm/i915/display/intel_vblank.c

489

line2 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;

sys/dev/pci/drm/i915/display/intel_vblank.c

496

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_vblank.c

502

ret = poll_timeout_us(is_moving = pipe_scanline_is_moving(display, pipe),

sys/dev/pci/drm/i915/display/intel_vblank.c

506

drm_err(display->drm,

sys/dev/pci/drm/i915/display/intel_vblank.c

541

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vblank.c

552

drm_WARN_ON(display->drm, (mode_flags & I915_MODE_FLAG_VRR) == 0);

sys/dev/pci/drm/i915/display/intel_vblank.c

568

spin_lock_irqsave(&display->drm->vblank_time_lock, irqflags);

sys/dev/pci/drm/i915/display/intel_vblank.c

569

intel_vblank_section_enter(display);

sys/dev/pci/drm/i915/display/intel_vblank.c

578

intel_vblank_section_exit(display);

sys/dev/pci/drm/i915/display/intel_vblank.c

579

spin_unlock_irqrestore(&display->drm->vblank_time_lock, irqflags);

sys/dev/pci/drm/i915/display/intel_vblank.c

657

struct intel_display *display = to_intel_display(new_crtc_state);

sys/dev/pci/drm/i915/display/intel_vblank.c

665

evade->need_vlv_dsi_wa = (display->platform.valleyview ||

sys/dev/pci/drm/i915/display/intel_vblank.c

666

display->platform.cherryview) &&

sys/dev/pci/drm/i915/display/intel_vblank.c

713

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_vblank.c

735

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_vblank.c

75

struct intel_display *display = to_intel_display(crtc->dev);

sys/dev/pci/drm/i915/display/intel_vdsc.c

1005

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vdsc.c

1017

wakeref = intel_display_power_get_if_enabled(display, power_domain);

sys/dev/pci/drm/i915/display/intel_vdsc.c

1021

dss_ctl1 = intel_de_read(display, dss_ctl1_reg(crtc, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_vdsc.c

1022

dss_ctl2 = intel_de_read(display, dss_ctl2_reg(crtc, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_vdsc.c

1037

intel_display_power_put(display, power_domain, wakeref);

sys/dev/pci/drm/i915/display/intel_vdsc.c

1062

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vdsc.c

1093

int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24;

sys/dev/pci/drm/i915/display/intel_vdsc.c

26

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vdsc.c

274

struct intel_display *display = to_intel_display(pipe_config);

sys/dev/pci/drm/i915/display/intel_vdsc.c

287

drm_dbg_kms(display->drm, "Slice dimension requirements not met\n");

sys/dev/pci/drm/i915/display/intel_vdsc.c

29

if (!HAS_DSC(display))

sys/dev/pci/drm/i915/display/intel_vdsc.c

298

if (DISPLAY_VER(display) >= 14 &&

sys/dev/pci/drm/i915/display/intel_vdsc.c

319

drm_dbg_kms(display->drm, "DSC bpc requirements not met bpc: %d\n",

sys/dev/pci/drm/i915/display/intel_vdsc.c

32

if (DISPLAY_VER(display) == 11 && cpu_transcoder == TRANSCODER_A)

sys/dev/pci/drm/i915/display/intel_vdsc.c

342

if (DISPLAY_VER(display) >= 13 && !is_dsi_dsc_1_1(pipe_config)) {

sys/dev/pci/drm/i915/display/intel_vdsc.c

378

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_vdsc.c

392

if (DISPLAY_VER(display) == 12 && !display->platform.rocketlake &&

sys/dev/pci/drm/i915/display/intel_vdsc.c

40

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/intel_vdsc.c

42

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/intel_vdsc.c

439

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vdsc.c

446

drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe);

sys/dev/pci/drm/i915/display/intel_vdsc.c

451

intel_de_write(display, dsc_reg[i], pps_val);

sys/dev/pci/drm/i915/display/intel_vdsc.c

456

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vdsc.c

51

drm_WARN_ON(display->drm, crtc->pipe == PIPE_A);

sys/dev/pci/drm/i915/display/intel_vdsc.c

551

if (DISPLAY_VER(display) >= 14) {

sys/dev/pci/drm/i915/display/intel_vdsc.c

569

intel_de_write(display, DSCA_RC_BUF_THRESH_0,

sys/dev/pci/drm/i915/display/intel_vdsc.c

571

intel_de_write(display, DSCA_RC_BUF_THRESH_0_UDW,

sys/dev/pci/drm/i915/display/intel_vdsc.c

573

intel_de_write(display, DSCA_RC_BUF_THRESH_1,

sys/dev/pci/drm/i915/display/intel_vdsc.c

575

intel_de_write(display, DSCA_RC_BUF_THRESH_1_UDW,

sys/dev/pci/drm/i915/display/intel_vdsc.c

578

intel_de_write(display, DSCC_RC_BUF_THRESH_0,

sys/dev/pci/drm/i915/display/intel_vdsc.c

580

intel_de_write(display, DSCC_RC_BUF_THRESH_0_UDW,

sys/dev/pci/drm/i915/display/intel_vdsc.c

582

intel_de_write(display, DSCC_RC_BUF_THRESH_1,

sys/dev/pci/drm/i915/display/intel_vdsc.c

584

intel_de_write(display, DSCC_RC_BUF_THRESH_1_UDW,

sys/dev/pci/drm/i915/display/intel_vdsc.c

588

intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

590

intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

592

intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

594

intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

597

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vdsc.c

600

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vdsc.c

603

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vdsc.c

606

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vdsc.c

623

intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0,

sys/dev/pci/drm/i915/display/intel_vdsc.c

625

intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0_UDW,

sys/dev/pci/drm/i915/display/intel_vdsc.c

627

intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1,

sys/dev/pci/drm/i915/display/intel_vdsc.c

629

intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1_UDW,

sys/dev/pci/drm/i915/display/intel_vdsc.c

631

intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2,

sys/dev/pci/drm/i915/display/intel_vdsc.c

633

intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2_UDW,

sys/dev/pci/drm/i915/display/intel_vdsc.c

635

intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3,

sys/dev/pci/drm/i915/display/intel_vdsc.c

637

intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3_UDW,

sys/dev/pci/drm/i915/display/intel_vdsc.c

640

intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_0,

sys/dev/pci/drm/i915/display/intel_vdsc.c

642

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vdsc.c

645

intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_1,

sys/dev/pci/drm/i915/display/intel_vdsc.c

647

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vdsc.c

650

intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_2,

sys/dev/pci/drm/i915/display/intel_vdsc.c

652

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vdsc.c

655

intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_3,

sys/dev/pci/drm/i915/display/intel_vdsc.c

657

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vdsc.c

662

intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

664

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vdsc.c

667

intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

669

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vdsc.c

672

intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

674

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vdsc.c

677

intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

679

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vdsc.c

683

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vdsc.c

686

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vdsc.c

689

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vdsc.c

692

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vdsc.c

695

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vdsc.c

698

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vdsc.c

701

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vdsc.c

704

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vdsc.c

757

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vdsc.c

765

drm_WARN_ON_ONCE(display->drm, su_lines % vdsc_cfg->slice_height);

sys/dev/pci/drm/i915/display/intel_vdsc.c

766

drm_WARN_ON_ONCE(display->drm, vdsc_instances_per_pipe > 2);

sys/dev/pci/drm/i915/display/intel_vdsc.c

771

intel_de_write_dsb(display, dsb, LNL_DSC0_SU_PARAMETER_SET_0(pipe), val);

sys/dev/pci/drm/i915/display/intel_vdsc.c

774

intel_de_write_dsb(display, dsb, LNL_DSC1_SU_PARAMETER_SET_0(pipe), val);

sys/dev/pci/drm/i915/display/intel_vdsc.c

791

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vdsc.c

801

intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vdsc.c

808

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vdsc.c

842

intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);

sys/dev/pci/drm/i915/display/intel_vdsc.c

843

intel_de_write(display, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);

sys/dev/pci/drm/i915/display/intel_vdsc.c

848

struct intel_display *display = to_intel_display(old_crtc_state);

sys/dev/pci/drm/i915/display/intel_vdsc.c

854

intel_de_write(display, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);

sys/dev/pci/drm/i915/display/intel_vdsc.c

855

intel_de_write(display, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);

sys/dev/pci/drm/i915/display/intel_vdsc.c

862

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vdsc.c

870

drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe);

sys/dev/pci/drm/i915/display/intel_vdsc.c

876

val = intel_de_read(display, dsc_reg[0]);

sys/dev/pci/drm/i915/display/intel_vdsc.c

879

if (intel_de_read(display, dsc_reg[i]) != val) {

sys/dev/pci/drm/i915/display/intel_vdsc.c

890

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vdsc.c

895

drm_WARN_ON(display->drm, !all_equal);

sys/dev/pci/drm/i915/display/intel_vdsc.c

902

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vdsc.c

989

if (DISPLAY_VER(display) >= 14) {

sys/dev/pci/drm/i915/display/intel_vga.c

108

int intel_vga_register(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_vga.c

111

struct pci_dev *pdev = display->drm->pdev;

sys/dev/pci/drm/i915/display/intel_vga.c

129

void intel_vga_unregister(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_vga.c

131

struct pci_dev *pdev = display->drm->pdev;

sys/dev/pci/drm/i915/display/intel_vga.c

21

static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_vga.c

23

if (display->platform.valleyview || display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_vga.c

25

else if (DISPLAY_VER(display) >= 5)

sys/dev/pci/drm/i915/display/intel_vga.c

31

static bool has_vga_pipe_sel(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_vga.c

33

if (display->platform.i845g ||

sys/dev/pci/drm/i915/display/intel_vga.c

34

display->platform.i865g)

sys/dev/pci/drm/i915/display/intel_vga.c

37

if (display->platform.valleyview ||

sys/dev/pci/drm/i915/display/intel_vga.c

38

display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_vga.c

41

return DISPLAY_VER(display) < 7;

sys/dev/pci/drm/i915/display/intel_vga.c

45

void intel_vga_disable(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_vga.c

47

struct pci_dev *pdev = display->drm->pdev;

sys/dev/pci/drm/i915/display/intel_vga.c

48

i915_reg_t vga_reg = intel_vga_cntrl_reg(display);

sys/dev/pci/drm/i915/display/intel_vga.c

53

tmp = intel_de_read(display, vga_reg);

sys/dev/pci/drm/i915/display/intel_vga.c

57

if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/intel_vga.c

59

else if (has_vga_pipe_sel(display))

sys/dev/pci/drm/i915/display/intel_vga.c

64

drm_dbg_kms(display->drm, "Disabling VGA plane on pipe %c\n",

sys/dev/pci/drm/i915/display/intel_vga.c

81

intel_de_write(display, vga_reg, VGA_DISP_DISABLE);

sys/dev/pci/drm/i915/display/intel_vga.c

82

intel_de_posting_read(display, vga_reg);

sys/dev/pci/drm/i915/display/intel_vga.c

85

void intel_vga_reset_io_mem(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_vga.c

87

struct pci_dev *pdev = display->drm->pdev;

sys/dev/pci/drm/i915/display/intel_vga.h

11

void intel_vga_reset_io_mem(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_vga.h

12

void intel_vga_disable(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_vga.h

13

int intel_vga_register(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_vga.h

14

void intel_vga_unregister(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_vrr.c

103

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

106

intel_vrr_extra_vblank_delay(display);

sys/dev/pci/drm/i915/display/intel_vrr.c

109

static int intel_vrr_flipline_offset(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_vrr.c

112

return DISPLAY_VER(display) < 13 ? 1 : 0;

sys/dev/pci/drm/i915/display/intel_vrr.c

117

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

119

return crtc_state->vrr.vmin + intel_vrr_flipline_offset(display);

sys/dev/pci/drm/i915/display/intel_vrr.c

140

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

142

if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/intel_vrr.c

151

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

154

if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/intel_vrr.c

163

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

165

if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/intel_vrr.c

185

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

190

if (!HAS_CMRR(display) || true)

sys/dev/pci/drm/i915/display/intel_vrr.c

21

struct intel_display *display = to_intel_display(connector);

sys/dev/pci/drm/i915/display/intel_vrr.c

260

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

263

if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/intel_vrr.c

279

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

282

intel_vrr_flipline_offset(display);

sys/dev/pci/drm/i915/display/intel_vrr.c

293

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

299

intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

301

intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

303

intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

349

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

357

if (!HAS_VRR(display))

sys/dev/pci/drm/i915/display/intel_vrr.c

380

if (HAS_LRR(display))

sys/dev/pci/drm/i915/display/intel_vrr.c

404

crtc_state->vrr.vmin -= intel_vrr_flipline_offset(display);

sys/dev/pci/drm/i915/display/intel_vrr.c

406

if (HAS_AS_SDP(display)) {

sys/dev/pci/drm/i915/display/intel_vrr.c

418

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

424

if (DISPLAY_VER(display) >= 13) {

sys/dev/pci/drm/i915/display/intel_vrr.c

445

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

447

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/intel_vrr.c

450

else if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/intel_vrr.c

461

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

464

if (!HAS_VRR(display))

sys/dev/pci/drm/i915/display/intel_vrr.c

476

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/intel_vrr.c

477

!(intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE));

sys/dev/pci/drm/i915/display/intel_vrr.c

484

if (IS_DISPLAY_VER(display, 12, 13))

sys/dev/pci/drm/i915/display/intel_vrr.c

485

intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

489

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vrr.c

49

return HAS_VRR(display) &&

sys/dev/pci/drm/i915/display/intel_vrr.c

490

TRANS_VRR_CTL(display, cpu_transcoder), 0);

sys/dev/pci/drm/i915/display/intel_vrr.c

495

intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

497

intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

499

intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

501

intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

507

if (!intel_vrr_always_use_vrr_tg(display) && !crtc_state->vrr.enable)

sys/dev/pci/drm/i915/display/intel_vrr.c

508

intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

511

if (HAS_AS_SDP(display))

sys/dev/pci/drm/i915/display/intel_vrr.c

512

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vrr.c

513

TRANS_VRR_VSYNC(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

521

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

530

intel_de_write_dsb(display, dsb,

sys/dev/pci/drm/i915/display/intel_vrr.c

531

TRANS_PUSH(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

541

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

563

intel_dsb_poll(dsb, TRANS_PUSH(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

567

drm_err(display->drm, "[CRTC:%d:%s] VRR push send still pending\n",

sys/dev/pci/drm/i915/display/intel_vrr.c

574

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

580

return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND;

sys/dev/pci/drm/i915/display/intel_vrr.c

583

bool intel_vrr_always_use_vrr_tg(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_vrr.c

585

if (!HAS_VRR(display))

sys/dev/pci/drm/i915/display/intel_vrr.c

588

if (DISPLAY_VER(display) >= 30)

sys/dev/pci/drm/i915/display/intel_vrr.c

597

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

607

if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/intel_vrr.c

608

intel_de_write(display,

sys/dev/pci/drm/i915/display/intel_vrr.c

609

EMP_AS_SDP_TL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

615

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

621

intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

623

intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

625

intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

628

intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

631

if (!intel_vrr_always_use_vrr_tg(display)) {

sys/dev/pci/drm/i915/display/intel_vrr.c

635

intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

639

intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

647

struct intel_display *display = to_intel_display(old_crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

653

if (!intel_vrr_always_use_vrr_tg(display)) {

sys/dev/pci/drm/i915/display/intel_vrr.c

654

intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

656

intel_de_wait_for_clear(display,

sys/dev/pci/drm/i915/display/intel_vrr.c

657

TRANS_VRR_STATUS(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

659

intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);

sys/dev/pci/drm/i915/display/intel_vrr.c

667

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

670

if (!HAS_VRR(display))

sys/dev/pci/drm/i915/display/intel_vrr.c

678

if (!intel_vrr_always_use_vrr_tg(display)) {

sys/dev/pci/drm/i915/display/intel_vrr.c

679

intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

684

intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

689

intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

695

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

698

if (!HAS_VRR(display))

sys/dev/pci/drm/i915/display/intel_vrr.c

704

intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), 0);

sys/dev/pci/drm/i915/display/intel_vrr.c

706

intel_de_wait_for_clear(display, TRANS_VRR_STATUS(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

708

intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);

sys/dev/pci/drm/i915/display/intel_vrr.c

720

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

725

trans_vrr_ctl = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_vrr.c

726

TRANS_VRR_CTL(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_vrr.c

728

if (HAS_CMRR(display))

sys/dev/pci/drm/i915/display/intel_vrr.c

733

intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

734

TRANS_CMRR_N_HI(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_vrr.c

736

intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder),

sys/dev/pci/drm/i915/display/intel_vrr.c

737

TRANS_CMRR_M_HI(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_vrr.c

740

if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/intel_vrr.c

749

crtc_state->vrr.flipline = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_vrr.c

750

TRANS_VRR_FLIPLINE(display, cpu_transcoder)) + 1;

sys/dev/pci/drm/i915/display/intel_vrr.c

751

crtc_state->vrr.vmax = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_vrr.c

752

TRANS_VRR_VMAX(display, cpu_transcoder)) + 1;

sys/dev/pci/drm/i915/display/intel_vrr.c

753

crtc_state->vrr.vmin = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_vrr.c

754

TRANS_VRR_VMIN(display, cpu_transcoder)) + 1;

sys/dev/pci/drm/i915/display/intel_vrr.c

762

if (intel_vrr_always_use_vrr_tg(display))

sys/dev/pci/drm/i915/display/intel_vrr.c

766

if (HAS_AS_SDP(display)) {

sys/dev/pci/drm/i915/display/intel_vrr.c

768

intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_vrr.c

769

TRANS_VRR_VSYNC(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_vrr.c

779

if (intel_vrr_always_use_vrr_tg(display))

sys/dev/pci/drm/i915/display/intel_vrr.c

88

static int intel_vrr_extra_vblank_delay(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_vrr.c

98

return DISPLAY_VER(display) < 13 ? 1 : 0;

sys/dev/pci/drm/i915/display/intel_vrr.h

43

bool intel_vrr_always_use_vrr_tg(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

102

#define TRANS_VRR_VSYNC(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VSYNC_A)

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

110

#define EMP_AS_SDP_TL(display, trans) _MMIO_TRANS2((display), (trans), _EMP_AS_SDP_TL_A)

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

115

#define TRANS_CMRR_M_LO(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_M_LO_A)

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

118

#define TRANS_CMRR_M_HI(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_M_HI_A)

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

121

#define TRANS_CMRR_N_LO(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_N_LO_A)

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

124

#define TRANS_CMRR_N_HI(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_N_HI_A)

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

15

#define TRANS_VRR_CTL(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_CTL_A)

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

30

#define TRANS_VRR_VMAX(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VMAX_A)

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

37

#define TRANS_VRR_VMIN(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VMIN_A)

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

44

#define TRANS_VRR_VMAXSHIFT(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VMAXSHIFT_A)

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

53

#define TRANS_VRR_STATUS(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_STATUS_A)

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

73

#define TRANS_VRR_VTOTAL_PREV(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VTOTAL_PREV_A)

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

83

#define TRANS_VRR_FLIPLINE(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_FLIPLINE_A)

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

90

#define TRANS_VRR_STATUS2(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_STATUS2_A)

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

97

#define TRANS_PUSH(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_PUSH_A)

sys/dev/pci/drm/i915/display/intel_wm.c

101

if (display->funcs.wm->compute_global_watermarks)

sys/dev/pci/drm/i915/display/intel_wm.c

102

return display->funcs.wm->compute_global_watermarks(state);

sys/dev/pci/drm/i915/display/intel_wm.c

107

void intel_wm_get_hw_state(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_wm.c

109

if (display->funcs.wm->get_hw_state)

sys/dev/pci/drm/i915/display/intel_wm.c

110

return display->funcs.wm->get_hw_state(display);

sys/dev/pci/drm/i915/display/intel_wm.c

113

void intel_wm_sanitize(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_wm.c

115

if (display->funcs.wm->sanitize)

sys/dev/pci/drm/i915/display/intel_wm.c

116

return display->funcs.wm->sanitize(display);

sys/dev/pci/drm/i915/display/intel_wm.c

142

void intel_print_wm_latency(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_wm.c

147

for (level = 0; level < display->wm.num_levels; level++) {

sys/dev/pci/drm/i915/display/intel_wm.c

151

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_wm.c

161

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_wm.c

166

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/intel_wm.c

172

void intel_wm_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_wm.c

174

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_wm.c

175

skl_wm_init(display);

sys/dev/pci/drm/i915/display/intel_wm.c

177

i9xx_wm_init(display);

sys/dev/pci/drm/i915/display/intel_wm.c

182

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/intel_wm.c

185

drm_modeset_lock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_wm.c

187

for (level = 0; level < display->wm.num_levels; level++) {

sys/dev/pci/drm/i915/display/intel_wm.c

194

if (DISPLAY_VER(display) >= 9 ||

sys/dev/pci/drm/i915/display/intel_wm.c

195

display->platform.valleyview ||

sys/dev/pci/drm/i915/display/intel_wm.c

196

display->platform.cherryview ||

sys/dev/pci/drm/i915/display/intel_wm.c

197

display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_wm.c

206

drm_modeset_unlock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_wm.c

211

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/intel_wm.c

214

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_wm.c

215

latencies = display->wm.skl_latency;

sys/dev/pci/drm/i915/display/intel_wm.c

217

latencies = display->wm.pri_latency;

sys/dev/pci/drm/i915/display/intel_wm.c

226

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/intel_wm.c

229

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_wm.c

230

latencies = display->wm.skl_latency;

sys/dev/pci/drm/i915/display/intel_wm.c

232

latencies = display->wm.spr_latency;

sys/dev/pci/drm/i915/display/intel_wm.c

241

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/intel_wm.c

244

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_wm.c

245

latencies = display->wm.skl_latency;

sys/dev/pci/drm/i915/display/intel_wm.c

247

latencies = display->wm.cur_latency;

sys/dev/pci/drm/i915/display/intel_wm.c

258

struct intel_display *display = inode->i_private;

sys/dev/pci/drm/i915/display/intel_wm.c

260

if (DISPLAY_VER(display) < 5 && !display->platform.g4x)

sys/dev/pci/drm/i915/display/intel_wm.c

263

return single_open(file, pri_wm_latency_show, display);

sys/dev/pci/drm/i915/display/intel_wm.c

268

struct intel_display *display = inode->i_private;

sys/dev/pci/drm/i915/display/intel_wm.c

270

if (HAS_GMCH(display))

sys/dev/pci/drm/i915/display/intel_wm.c

273

return single_open(file, spr_wm_latency_show, display);

sys/dev/pci/drm/i915/display/intel_wm.c

278

struct intel_display *display = inode->i_private;

sys/dev/pci/drm/i915/display/intel_wm.c

280

if (HAS_GMCH(display))

sys/dev/pci/drm/i915/display/intel_wm.c

283

return single_open(file, cur_wm_latency_show, display);

sys/dev/pci/drm/i915/display/intel_wm.c

290

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/intel_wm.c

307

if (ret != display->wm.num_levels)

sys/dev/pci/drm/i915/display/intel_wm.c

310

drm_modeset_lock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_wm.c

312

for (level = 0; level < display->wm.num_levels; level++)

sys/dev/pci/drm/i915/display/intel_wm.c

315

drm_modeset_unlock_all(display->drm);

sys/dev/pci/drm/i915/display/intel_wm.c

324

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/intel_wm.c

327

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_wm.c

328

latencies = display->wm.skl_latency;

sys/dev/pci/drm/i915/display/intel_wm.c

330

latencies = display->wm.pri_latency;

sys/dev/pci/drm/i915/display/intel_wm.c

339

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/intel_wm.c

342

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_wm.c

343

latencies = display->wm.skl_latency;

sys/dev/pci/drm/i915/display/intel_wm.c

345

latencies = display->wm.spr_latency;

sys/dev/pci/drm/i915/display/intel_wm.c

354

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/intel_wm.c

357

if (DISPLAY_VER(display) >= 9)

sys/dev/pci/drm/i915/display/intel_wm.c

358

latencies = display->wm.skl_latency;

sys/dev/pci/drm/i915/display/intel_wm.c

360

latencies = display->wm.cur_latency;

sys/dev/pci/drm/i915/display/intel_wm.c

394

void intel_wm_debugfs_register(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_wm.c

396

struct dentry *debugfs_root = display->drm->debugfs_root;

sys/dev/pci/drm/i915/display/intel_wm.c

399

display, &i915_pri_wm_latency_fops);

sys/dev/pci/drm/i915/display/intel_wm.c

402

display, &i915_spr_wm_latency_fops);

sys/dev/pci/drm/i915/display/intel_wm.c

405

display, &i915_cur_wm_latency_fops);

sys/dev/pci/drm/i915/display/intel_wm.c

407

skl_watermark_debugfs_register(display);

sys/dev/pci/drm/i915/display/intel_wm.c

49

void intel_update_watermarks(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_wm.c

51

if (display->funcs.wm->update_wm)

sys/dev/pci/drm/i915/display/intel_wm.c

52

display->funcs.wm->update_wm(display);

sys/dev/pci/drm/i915/display/intel_wm.c

58

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_wm.c

60

if (!display->funcs.wm->compute_watermarks)

sys/dev/pci/drm/i915/display/intel_wm.c

63

return display->funcs.wm->compute_watermarks(state, crtc);

sys/dev/pci/drm/i915/display/intel_wm.c

69

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_wm.c

71

if (display->funcs.wm->initial_watermarks) {

sys/dev/pci/drm/i915/display/intel_wm.c

72

display->funcs.wm->initial_watermarks(state, crtc);

sys/dev/pci/drm/i915/display/intel_wm.c

82

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_wm.c

84

if (display->funcs.wm->atomic_update_watermarks)

sys/dev/pci/drm/i915/display/intel_wm.c

85

display->funcs.wm->atomic_update_watermarks(state, crtc);

sys/dev/pci/drm/i915/display/intel_wm.c

91

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_wm.c

93

if (display->funcs.wm->optimize_watermarks)

sys/dev/pci/drm/i915/display/intel_wm.c

94

display->funcs.wm->optimize_watermarks(state, crtc);

sys/dev/pci/drm/i915/display/intel_wm.c

99

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/intel_wm.h

17

void intel_update_watermarks(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_wm.h

27

void intel_wm_get_hw_state(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_wm.h

28

void intel_wm_sanitize(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_wm.h

31

void intel_print_wm_latency(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_wm.h

33

void intel_wm_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/intel_wm.h

34

void intel_wm_debugfs_register(struct intel_display *display);

sys/dev/pci/drm/i915/display/skl_scaler.c

101

} else if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/skl_scaler.c

104

} else if (DISPLAY_VER(display) == 11) {

sys/dev/pci/drm/i915/display/skl_scaler.c

122

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/skl_scaler.c

124

if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/skl_scaler.c

127

} else if (DISPLAY_VER(display) == 11) {

sys/dev/pci/drm/i915/display/skl_scaler.c

137

skl_scaler_mode_valid(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_scaler.c

145

skl_scaler_max_src_size(display, &max_w, &max_h);

sys/dev/pci/drm/i915/display/skl_scaler.c

160

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/skl_scaler.c

185

if (DISPLAY_VER(display) >= 9 && crtc_state->hw.enable &&

sys/dev/pci/drm/i915/display/skl_scaler.c

187

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_scaler.c

208

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_scaler.c

220

skl_scaler_max_src_size(display, &max_src_w, &max_src_h);

sys/dev/pci/drm/i915/display/skl_scaler.c

230

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_scaler.c

248

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_scaler.c

258

drm_dbg_kms(display->drm, "[CRTC:%d:%s] scaler_user index %u.%u: "

sys/dev/pci/drm/i915/display/skl_scaler.c

300

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/skl_scaler.c

307

if (!icl_is_hdr_plane(display, plane->id) &&

sys/dev/pci/drm/i915/display/skl_scaler.c

346

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/skl_scaler.c

356

if (DISPLAY_VER(display) >= 14) {

sys/dev/pci/drm/i915/display/skl_scaler.c

369

} else if (DISPLAY_VER(display) >= 10 || !is_yuv_semiplanar) {

sys/dev/pci/drm/i915/display/skl_scaler.c

384

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/skl_scaler.c

393

if (drm_WARN(display->drm, *scaler_id < 0,

sys/dev/pci/drm/i915/display/skl_scaler.c

403

if (DISPLAY_VER(display) == 9) {

sys/dev/pci/drm/i915/display/skl_scaler.c

405

} else if (icl_is_hdr_plane(display, plane->id)) {

sys/dev/pci/drm/i915/display/skl_scaler.c

421

} else if (DISPLAY_VER(display) >= 10) {

sys/dev/pci/drm/i915/display/skl_scaler.c

457

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_scaler.c

494

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_scaler.c

507

drm_dbg_kms(display->drm, "[CRTC:%d:%s] attached scaler id %u.%u to %s:%d\n",

sys/dev/pci/drm/i915/display/skl_scaler.c

533

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_scaler.c

541

if (drm_WARN_ON(display->drm, plane->pipe != crtc->pipe))

sys/dev/pci/drm/i915/display/skl_scaler.c

551

if (!plane_state && DISPLAY_VER(display) >= 10)

sys/dev/pci/drm/i915/display/skl_scaler.c

583

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/skl_scaler.c

607

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_scaler.c

628

to_intel_plane(drm_plane_from_index(display->drm, i));

sys/dev/pci/drm/i915/display/skl_scaler.c

686

static void glk_program_nearest_filter_coefs(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_scaler.c

692

intel_de_write_dsb(display, dsb,

sys/dev/pci/drm/i915/display/skl_scaler.c

706

intel_de_write_dsb(display, dsb,

sys/dev/pci/drm/i915/display/skl_scaler.c

710

intel_de_write_dsb(display, dsb,

sys/dev/pci/drm/i915/display/skl_scaler.c

726

static void skl_scaler_setup_filter(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_scaler.c

734

glk_program_nearest_filter_coefs(display, dsb, pipe, id, set);

sys/dev/pci/drm/i915/display/skl_scaler.c

743

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/skl_scaler.c

762

if (drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/skl_scaler.c

766

if (intel_display_wa(display, 14011503117))

sys/dev/pci/drm/i915/display/skl_scaler.c

786

skl_scaler_setup_filter(display, NULL, pipe, id, 0,

sys/dev/pci/drm/i915/display/skl_scaler.c

789

intel_de_write_fw(display, SKL_PS_CTRL(pipe, id), ps_ctrl);

sys/dev/pci/drm/i915/display/skl_scaler.c

791

intel_de_write_fw(display, SKL_PS_VPHASE(pipe, id),

sys/dev/pci/drm/i915/display/skl_scaler.c

793

intel_de_write_fw(display, SKL_PS_HPHASE(pipe, id),

sys/dev/pci/drm/i915/display/skl_scaler.c

795

intel_de_write_fw(display, SKL_PS_WIN_POS(pipe, id),

sys/dev/pci/drm/i915/display/skl_scaler.c

797

intel_de_write_fw(display, SKL_PS_WIN_SZ(pipe, id),

sys/dev/pci/drm/i915/display/skl_scaler.c

807

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_scaler.c

831

!icl_is_hdr_plane(display, plane->id)) {

sys/dev/pci/drm/i915/display/skl_scaler.c

853

skl_scaler_setup_filter(display, dsb, pipe, scaler_id, 0,

sys/dev/pci/drm/i915/display/skl_scaler.c

856

intel_de_write_dsb(display, dsb, SKL_PS_CTRL(pipe, scaler_id),

sys/dev/pci/drm/i915/display/skl_scaler.c

858

intel_de_write_dsb(display, dsb, SKL_PS_VPHASE(pipe, scaler_id),

sys/dev/pci/drm/i915/display/skl_scaler.c

860

intel_de_write_dsb(display, dsb, SKL_PS_HPHASE(pipe, scaler_id),

sys/dev/pci/drm/i915/display/skl_scaler.c

862

intel_de_write_dsb(display, dsb, SKL_PS_WIN_POS(pipe, scaler_id),

sys/dev/pci/drm/i915/display/skl_scaler.c

864

intel_de_write_dsb(display, dsb, SKL_PS_WIN_SZ(pipe, scaler_id),

sys/dev/pci/drm/i915/display/skl_scaler.c

871

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/skl_scaler.c

875

intel_de_write_dsb(display, dsb, SKL_PS_CTRL(crtc->pipe, id), 0);

sys/dev/pci/drm/i915/display/skl_scaler.c

876

intel_de_write_dsb(display, dsb, SKL_PS_WIN_POS(crtc->pipe, id), 0);

sys/dev/pci/drm/i915/display/skl_scaler.c

877

intel_de_write_dsb(display, dsb, SKL_PS_WIN_SZ(crtc->pipe, id), 0);

sys/dev/pci/drm/i915/display/skl_scaler.c

909

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/skl_scaler.c

919

ctl = intel_de_read(display, SKL_PS_CTRL(crtc->pipe, i));

sys/dev/pci/drm/i915/display/skl_scaler.c

926

pos = intel_de_read(display, SKL_PS_WIN_POS(crtc->pipe, i));

sys/dev/pci/drm/i915/display/skl_scaler.c

927

size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, i));

sys/dev/pci/drm/i915/display/skl_scaler.c

948

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/skl_scaler.c

95

static void skl_scaler_max_src_size(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_scaler.c

953

intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);

sys/dev/pci/drm/i915/display/skl_scaler.c

958

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/skl_scaler.c

966

intel_de_write_fw(display,

sys/dev/pci/drm/i915/display/skl_scaler.c

969

intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, 0);

sys/dev/pci/drm/i915/display/skl_scaler.c

98

if (DISPLAY_VER(display) >= 14) {

sys/dev/pci/drm/i915/display/skl_scaler.h

40

skl_scaler_mode_valid(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1156

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1159

if (DISPLAY_VER(display) >= 10)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1173

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1181

if (DISPLAY_VER(display) < 10) {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1196

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1206

if (DISPLAY_VER(display) == 13)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1214

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1217

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1231

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1239

if (fb->format->is_yuv && !icl_is_hdr_plane(display, plane->id)) {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1269

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1274

drm_WARN_ON(display->drm, offset & 0x1fffff);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1277

drm_WARN_ON(display->drm, offset & 0xfff);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1306

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1317

if (DISPLAY_VER(display) < 12)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1355

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1359

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 0), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1360

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 1), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1362

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 2), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1363

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 3), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1365

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 4), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1366

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 5), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1368

intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 0), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1369

intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 1), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1370

intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 2), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1372

intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 0), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1373

intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 1), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1374

intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1383

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1398

intel_de_write_dsb(display, dsb, PLANE_STRIDE(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1400

intel_de_write_dsb(display, dsb, PLANE_POS(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1402

intel_de_write_dsb(display, dsb, PLANE_SIZE(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1414

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1429

if (DISPLAY_VER(display) >= 10)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1433

intel_de_write_dsb(display, dsb, PLANE_KEYVAL(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1435

intel_de_write_dsb(display, dsb, PLANE_KEYMSK(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1437

intel_de_write_dsb(display, dsb, PLANE_KEYMAX(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1440

intel_de_write_dsb(display, dsb, PLANE_OFFSET(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1443

intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1446

intel_de_write_dsb(display, dsb, PLANE_AUX_OFFSET(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1450

if (DISPLAY_VER(display) >= 10)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1451

intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1469

intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1471

intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1481

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1498

intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_POS(pipe, plane->id), val);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1513

intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_OFFSET(pipe, plane->id), val);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1518

intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_SIZE(pipe, plane->id), val);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1527

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1550

intel_de_write_dsb(display, dsb, PLANE_STRIDE(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1552

intel_de_write_dsb(display, dsb, PLANE_POS(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1554

intel_de_write_dsb(display, dsb, PLANE_SIZE(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1557

intel_de_write_dsb(display, dsb, PLANE_KEYVAL(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1559

intel_de_write_dsb(display, dsb, PLANE_KEYMSK(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1561

intel_de_write_dsb(display, dsb, PLANE_KEYMAX(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1564

intel_de_write_dsb(display, dsb, PLANE_OFFSET(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1568

intel_de_write_dsb(display, dsb, PLANE_CC_VAL(pipe, plane_id, 0),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1570

intel_de_write_dsb(display, dsb, PLANE_CC_VAL(pipe, plane_id, 1),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1575

if (!HAS_FLAT_CCS(to_i915(display->drm)) && DISPLAY_VER(display) < 20)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1576

intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1579

if (icl_is_hdr_plane(display, plane_id))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1580

intel_de_write_dsb(display, dsb, PLANE_CUS_CTL(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1583

intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1586

if (fb->format->is_yuv && icl_is_hdr_plane(display, plane_id))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1606

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1613

intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1625

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1650

intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1652

intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1660

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1662

error->ctl = intel_de_read(display, PLANE_CTL(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1663

error->surf = intel_de_read(display, PLANE_SURF(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1664

error->surflive = intel_de_read(display, PLANE_SURFLIVE(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1674

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1683

if (DISPLAY_VER(display) >= 30)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1689

intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1691

intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1710

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1720

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1728

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1739

DISPLAY_VER(display) >= 20) {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1740

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1748

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1760

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1773

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1787

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1794

if ((display->platform.alderlake_s || display->platform.tigerlake) &&

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1797

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1809

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1824

if (DISPLAY_VER(display) == 10 &&

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1826

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1840

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1851

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1860

static int skl_plane_max_scale(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1869

if (DISPLAY_VER(display) >= 10 ||

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1958

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1968

if (drm_WARN_ON(display->drm, alignment && !is_power_of_2(alignment)))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1992

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2009

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2026

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2054

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2061

if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2062

drm_WARN_ON(display->drm, x > 65535 || y > 65535);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2064

drm_WARN_ON(display->drm, x > 8191 || y > 8191);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2082

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2099

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2134

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2141

if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2142

drm_WARN_ON(display->drm, x > 65535 || y > 65535);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2144

drm_WARN_ON(display->drm, x > 8191 || y > 8191);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2230

struct intel_display *display;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2235

display = to_intel_display(fb->dev);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2244

return DISPLAY_VER(display) >= 11;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2252

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2256

if (DISPLAY_VER(display) < 11)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2305

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2319

max_scale = skl_plane_max_scale(display, fb);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2360

if (DISPLAY_VER(display) >= 10)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2364

icl_is_hdr_plane(display, plane->id))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2378

struct intel_display *display = to_intel_display(uv_plane_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

238

static u8 icl_nv12_y_plane_mask(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2382

drm_WARN_ON(display->drm, icl_is_nv12_y_plane(display, uv_plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2383

drm_WARN_ON(display->drm, !icl_is_nv12_y_plane(display, y_plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2387

if (icl_is_hdr_plane(display, uv_plane->id)) {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

240

if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2412

static bool skl_plane_has_fbc(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2415

if ((DISPLAY_RUNTIME_INFO(display)->fbc_mask & BIT(fbc_id)) == 0)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2418

if (DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2419

return icl_is_hdr_plane(display, plane_id);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2424

static struct intel_fbc *skl_plane_fbc(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2429

if (skl_plane_has_fbc(display, fbc_id, plane_id))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2430

return display->fbc[fbc_id];

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2435

static bool skl_plane_has_planar(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2439

if (display->platform.skylake || display->platform.broxton)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2442

if (DISPLAY_VER(display) == 9 && pipe == PIPE_C)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2451

static const u32 *skl_get_plane_formats(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2455

if (skl_plane_has_planar(display, pipe, plane_id)) {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

246

bool icl_is_nv12_y_plane(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2464

static const u32 *glk_get_plane_formats(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2468

if (skl_plane_has_planar(display, pipe, plane_id)) {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2477

static const u32 *icl_get_plane_formats(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2481

if (icl_is_hdr_plane(display, plane_id)) {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2484

} else if (icl_is_nv12_y_plane(display, plane_id)) {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

249

return DISPLAY_VER(display) >= 11 &&

sys/dev/pci/drm/i915/display/skl_universal_plane.c

250

icl_nv12_y_plane_mask(display) & BIT(plane_id);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

258

bool icl_is_hdr_plane(struct intel_display *display, enum plane_id plane_id)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

260

return DISPLAY_VER(display) >= 11 &&

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2686

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2689

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2690

bdw_enable_pipe_irq(display, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2691

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2697

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2700

spin_lock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2701

bdw_disable_pipe_irq(display, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2702

spin_unlock_irq(&display->irq.lock);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2705

static bool skl_plane_has_rc_ccs(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2712

static u8 skl_plane_caps(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2719

if (skl_plane_has_rc_ccs(display, pipe, plane_id))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2725

static bool glk_plane_has_rc_ccs(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2731

static u8 glk_plane_caps(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2738

if (glk_plane_has_rc_ccs(display, pipe))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2744

static u8 icl_plane_caps(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2753

static bool tgl_plane_has_mc_ccs(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2757

if (display->platform.dg1 || display->platform.rocketlake ||

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2758

(display->platform.tigerlake && IS_DISPLAY_STEP(display, STEP_A0, STEP_D0)))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2764

static u8 tgl_plane_caps(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2771

if (HAS_4TILE(display))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2776

if (tgl_plane_has_mc_ccs(display, plane_id))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2779

if (DISPLAY_VER(display) >= 14 && display->platform.dgfx)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2788

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2792

plane_ctl = intel_de_read(display, PLANE_CTL(plane->pipe, plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2802

intel_de_write_fw(display, PLANE_STRIDE(plane->pipe, plane->id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2805

intel_de_write_fw(display, PLANE_CTL(plane->pipe, plane->id), plane_ctl);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2807

intel_de_write_fw(display, PLANE_SURF(plane->pipe, plane->id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2812

skl_universal_plane_create(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2834

intel_fbc_add_plane(skl_plane_fbc(display, pipe, plane_id), plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2836

if (DISPLAY_VER(display) >= 30) {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2840

} else if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2842

if (icl_is_hdr_plane(display, plane_id))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2848

} else if (DISPLAY_VER(display) >= 10) {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2861

if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2866

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2871

if (intel_scanout_needs_vtd_wa(display))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2872

plane->vtd_guard = DISPLAY_VER(display) >= 10 ? 168 : 136;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2874

if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2887

if (HAS_ASYNC_FLIPS(display) && plane_id == PLANE_1) {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2888

plane->need_async_flip_toggle_wa = IS_DISPLAY_VER(display, 9, 10);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2893

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2895

else if (DISPLAY_VER(display) == 11)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2901

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2902

formats = icl_get_plane_formats(display, pipe,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2904

else if (DISPLAY_VER(display) >= 10)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2905

formats = glk_get_plane_formats(display, pipe,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2908

formats = skl_get_plane_formats(display, pipe,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2911

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2913

else if (DISPLAY_VER(display) == 11)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2923

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2924

caps = tgl_plane_caps(display, pipe, plane_id);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2925

else if (DISPLAY_VER(display) == 11)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2926

caps = icl_plane_caps(display, pipe, plane_id);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2927

else if (DISPLAY_VER(display) == 10)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2928

caps = glk_plane_caps(display, pipe, plane_id);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2930

caps = skl_plane_caps(display, pipe, plane_id);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2933

if (!IS_ENABLED(I915) && !HAS_FLAT_CCS(to_i915(display->drm)))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2938

modifiers = intel_fb_plane_get_modifiers(display, caps);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2940

ret = drm_universal_plane_init(display->drm, &plane->base,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2952

if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2959

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2968

if (DISPLAY_VER(display) >= 10)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2986

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2989

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3008

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3023

drm_WARN_ON(display->drm, pipe != crtc->pipe);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3026

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3034

drm_dbg_kms(display->drm, "failed to alloc fb\n");

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3040

fb->dev = display->drm;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3042

val = intel_de_read(display, PLANE_CTL(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3044

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3049

if (DISPLAY_VER(display) >= 10) {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3052

color_ctl = intel_de_read(display, PLANE_COLOR_CTL(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3074

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3076

else if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3081

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3089

if (HAS_4TILE(display)) {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3113

if (!display->params.enable_dpt &&

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3114

intel_fb_modifier_uses_dpt(display, fb->modifier)) {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3115

drm_dbg_kms(display->drm, "DPT disabled, skipping initial FB\n");

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3138

if (DISPLAY_VER(display) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3145

base = intel_de_read(display, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3148

offset = intel_de_read(display, PLANE_OFFSET(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3149

drm_WARN_ON(display->drm, offset != 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3151

val = intel_de_read(display, PLANE_SIZE(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3155

val = intel_de_read(display, PLANE_STRIDE(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3164

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3181

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3198

intel_de_write(display, PLANE_SURF(pipe, plane_id), plane_state->surf);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

592

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

605

if (display->platform.alderlake_p &&

sys/dev/pci/drm/i915/display/skl_universal_plane.c

687

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

731

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

733

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

735

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

737

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

739

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

741

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

744

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

746

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

748

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

750

intel_de_write_dsb(display, dsb,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

752

intel_de_write_dsb(display, dsb,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

754

intel_de_write_dsb(display, dsb,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

832

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

845

for (level = 0; level < display->wm.num_levels; level++)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

846

intel_de_write_dsb(display, dsb, PLANE_WM(pipe, plane_id, level),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

849

intel_de_write_dsb(display, dsb, PLANE_WM_TRANS(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

852

if (HAS_HW_SAGV_WM(display)) {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

855

intel_de_write_dsb(display, dsb, PLANE_WM_SAGV(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

857

intel_de_write_dsb(display, dsb, PLANE_WM_SAGV_TRANS(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

861

intel_de_write_dsb(display, dsb, PLANE_BUF_CFG(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

864

if (DISPLAY_VER(display) < 11)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

865

intel_de_write_dsb(display, dsb, PLANE_NV12_BUF_CFG(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

868

if (DISPLAY_VER(display) >= 30)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

869

intel_de_write_dsb(display, dsb, PLANE_MIN_BUF_CFG(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

878

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

884

intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

885

intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

892

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

898

intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

906

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

910

if (icl_is_hdr_plane(display, plane_id))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

911

intel_de_write_dsb(display, dsb, PLANE_CUS_CTL(pipe, plane_id), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

916

intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

917

intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

924

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

931

wakeref = intel_display_power_get_if_enabled(display, power_domain);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

935

ret = intel_de_read(display, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

939

intel_display_power_put(display, power_domain, wakeref);

sys/dev/pci/drm/i915/display/skl_universal_plane.h

22

skl_universal_plane_create(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.h

38

bool icl_is_nv12_y_plane(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.h

41

bool icl_is_hdr_plane(struct intel_display *display, enum plane_id plane_id);

sys/dev/pci/drm/i915/display/skl_watermark.c

103

intel_sagv_block_time(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

105

if (DISPLAY_VER(display) >= 14) {

sys/dev/pci/drm/i915/display/skl_watermark.c

108

val = intel_de_read(display, MTL_LATENCY_SAGV);

sys/dev/pci/drm/i915/display/skl_watermark.c

111

} else if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/skl_watermark.c

115

ret = intel_pcode_read(display->drm,

sys/dev/pci/drm/i915/display/skl_watermark.c

119

drm_dbg_kms(display->drm, "Couldn't read SAGV block time!\n");

sys/dev/pci/drm/i915/display/skl_watermark.c

1238

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/skl_watermark.c

124

} else if (DISPLAY_VER(display) == 11) {

sys/dev/pci/drm/i915/display/skl_watermark.c

1241

if (display->platform.dg2)

sys/dev/pci/drm/i915/display/skl_watermark.c

1243

else if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/skl_watermark.c

1245

else if (DISPLAY_VER(display) == 12)

sys/dev/pci/drm/i915/display/skl_watermark.c

1247

else if (DISPLAY_VER(display) == 11)

sys/dev/pci/drm/i915/display/skl_watermark.c

126

} else if (HAS_SAGV(display)) {

sys/dev/pci/drm/i915/display/skl_watermark.c

1260

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_watermark.c

1263

return IS_DISPLAY_VER(display, 13, 20) &&

sys/dev/pci/drm/i915/display/skl_watermark.c

1287

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/skl_watermark.c

1298

if (DISPLAY_VER(display) < 11)

sys/dev/pci/drm/i915/display/skl_watermark.c

133

static void intel_sagv_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

135

if (!HAS_SAGV(display))

sys/dev/pci/drm/i915/display/skl_watermark.c

136

display->sagv.status = I915_SAGV_NOT_CONTROLLED;

sys/dev/pci/drm/i915/display/skl_watermark.c

1360

static bool skl_need_wm_copy_wa(struct intel_display *display, int level,

sys/dev/pci/drm/i915/display/skl_watermark.c

1419

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_watermark.c

142

if (DISPLAY_VER(display) < 11)

sys/dev/pci/drm/i915/display/skl_watermark.c

143

skl_sagv_disable(display);

sys/dev/pci/drm/i915/display/skl_watermark.c

145

drm_WARN_ON(display->drm, display->sagv.status == I915_SAGV_UNKNOWN);

sys/dev/pci/drm/i915/display/skl_watermark.c

1455

for (level = display->wm.num_levels - 1; level >= 0; level--) {

sys/dev/pci/drm/i915/display/skl_watermark.c

1466

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/skl_watermark.c

147

display->sagv.block_time_us = intel_sagv_block_time(display);

sys/dev/pci/drm/i915/display/skl_watermark.c

1485

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_watermark.c

1487

drm_dbg_kms(display->drm, "minimum required %d/%d\n",

sys/dev/pci/drm/i915/display/skl_watermark.c

149

drm_dbg_kms(display->drm, "SAGV supported: %s, original SAGV block time: %u us\n",

sys/dev/pci/drm/i915/display/skl_watermark.c

150

str_yes_no(intel_has_sagv(display)), display->sagv.block_time_us);

sys/dev/pci/drm/i915/display/skl_watermark.c

1515

if (DISPLAY_VER(display) < 11 &&

sys/dev/pci/drm/i915/display/skl_watermark.c

1526

if (DISPLAY_VER(display) >= 30) {

sys/dev/pci/drm/i915/display/skl_watermark.c

153

if (drm_WARN(display->drm, display->sagv.block_time_us > U16_MAX,

sys/dev/pci/drm/i915/display/skl_watermark.c

1531

drm_WARN_ON(display->drm, iter.size != 0 || iter.data_rate != 0);

sys/dev/pci/drm/i915/display/skl_watermark.c

1539

for (level++; level < display->wm.num_levels; level++) {

sys/dev/pci/drm/i915/display/skl_watermark.c

1548

if (DISPLAY_VER(display) < 11 &&

sys/dev/pci/drm/i915/display/skl_watermark.c

155

display->sagv.block_time_us))

sys/dev/pci/drm/i915/display/skl_watermark.c

1556

if (skl_need_wm_copy_wa(display, level, wm)) {

sys/dev/pci/drm/i915/display/skl_watermark.c

156

display->sagv.block_time_us = 0;

sys/dev/pci/drm/i915/display/skl_watermark.c

1578

if (DISPLAY_VER(display) < 11 &&

sys/dev/pci/drm/i915/display/skl_watermark.c

158

if (!intel_has_sagv(display))

sys/dev/pci/drm/i915/display/skl_watermark.c

1588

if (DISPLAY_VER(display) >= 30)

sys/dev/pci/drm/i915/display/skl_watermark.c

159

display->sagv.block_time_us = 0;

sys/dev/pci/drm/i915/display/skl_watermark.c

1604

skl_wm_method1(struct intel_display *display, u32 pixel_rate,

sys/dev/pci/drm/i915/display/skl_watermark.c

1616

if (DISPLAY_VER(display) >= 10)

sys/dev/pci/drm/i915/display/skl_watermark.c

1642

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/skl_watermark.c

1652

if (drm_WARN_ON(display->drm, pixel_rate == 0))

sys/dev/pci/drm/i915/display/skl_watermark.c

1668

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/skl_watermark.c

1674

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_watermark.c

1692

if (DISPLAY_VER(display) >= 11 &&

sys/dev/pci/drm/i915/display/skl_watermark.c

1717

if (skl_needs_memory_bw_wa(display))

sys/dev/pci/drm/i915/display/skl_watermark.c

1726

if (DISPLAY_VER(display) >= 30)

sys/dev/pci/drm/i915/display/skl_watermark.c

1728

else if (DISPLAY_VER(display) >= 10)

sys/dev/pci/drm/i915/display/skl_watermark.c

173

static void skl_sagv_enable(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

1737

if (!wp->x_tiled || DISPLAY_VER(display) >= 10)

sys/dev/pci/drm/i915/display/skl_watermark.c

177

if (!intel_has_sagv(display))

sys/dev/pci/drm/i915/display/skl_watermark.c

1774

static bool skl_wm_has_lines(struct intel_display *display, int level)

sys/dev/pci/drm/i915/display/skl_watermark.c

1776

if (DISPLAY_VER(display) >= 10)

sys/dev/pci/drm/i915/display/skl_watermark.c

1783

static int skl_wm_max_lines(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

1785

if (DISPLAY_VER(display) >= 13)

sys/dev/pci/drm/i915/display/skl_watermark.c

1793

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_watermark.c

1795

return DISPLAY_VER(display) >= 30 && level == 0 && plane->id != PLANE_CURSOR;

sys/dev/pci/drm/i915/display/skl_watermark.c

180

if (display->sagv.status == I915_SAGV_ENABLED)

sys/dev/pci/drm/i915/display/skl_watermark.c

1806

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/skl_watermark.c

1818

method1 = skl_wm_method1(display, wp->plane_pixel_rate,

sys/dev/pci/drm/i915/display/skl_watermark.c

183

drm_dbg_kms(display->drm, "Enabling SAGV\n");

sys/dev/pci/drm/i915/display/skl_watermark.c

1833

if (DISPLAY_VER(display) == 9)

sys/dev/pci/drm/i915/display/skl_watermark.c

184

ret = intel_pcode_write(display->drm, GEN9_PCODE_SAGV_CONTROL,

sys/dev/pci/drm/i915/display/skl_watermark.c

1843

if (DISPLAY_VER(display) < 30)

sys/dev/pci/drm/i915/display/skl_watermark.c

1862

if (skl_wm_has_lines(display, level))

sys/dev/pci/drm/i915/display/skl_watermark.c

1868

if (DISPLAY_VER(display) == 9) {

sys/dev/pci/drm/i915/display/skl_watermark.c

1893

if (DISPLAY_VER(display) >= 11) {

sys/dev/pci/drm/i915/display/skl_watermark.c

1910

if (!skl_wm_has_lines(display, level))

sys/dev/pci/drm/i915/display/skl_watermark.c

1913

if (lines > skl_wm_max_lines(display)) {

sys/dev/pci/drm/i915/display/skl_watermark.c

193

if (display->platform.skylake && ret == -ENXIO) {

sys/dev/pci/drm/i915/display/skl_watermark.c

1932

if (DISPLAY_VER(display) < 12 && display->sagv.block_time_us)

sys/dev/pci/drm/i915/display/skl_watermark.c

1933

result->can_sagv = latency >= display->sagv.block_time_us;

sys/dev/pci/drm/i915/display/skl_watermark.c

194

drm_dbg(display->drm, "No SAGV found on system, ignoring\n");

sys/dev/pci/drm/i915/display/skl_watermark.c

1942

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/skl_watermark.c

1946

for (level = 0; level < display->wm.num_levels; level++) {

sys/dev/pci/drm/i915/display/skl_watermark.c

1948

unsigned int latency = skl_wm_latency(display, level, wm_params);

sys/dev/pci/drm/i915/display/skl_watermark.c

195

display->sagv.status = I915_SAGV_NOT_CONTROLLED;

sys/dev/pci/drm/i915/display/skl_watermark.c

1962

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/skl_watermark.c

1967

if (display->sagv.block_time_us)

sys/dev/pci/drm/i915/display/skl_watermark.c

1968

latency = display->sagv.block_time_us +

sys/dev/pci/drm/i915/display/skl_watermark.c

1969

skl_wm_latency(display, 0, wm_params);

sys/dev/pci/drm/i915/display/skl_watermark.c

1976

static void skl_compute_transition_wm(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_watermark.c

198

drm_err(display->drm, "Failed to enable SAGV\n");

sys/dev/pci/drm/i915/display/skl_watermark.c

1985

if (!skl_watermark_ipc_enabled(display))

sys/dev/pci/drm/i915/display/skl_watermark.c

1992

if (DISPLAY_VER(display) == 9)

sys/dev/pci/drm/i915/display/skl_watermark.c

1995

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/skl_watermark.c

2001

if (DISPLAY_VER(display) == 10)

sys/dev/pci/drm/i915/display/skl_watermark.c

202

display->sagv.status = I915_SAGV_ENABLED;

sys/dev/pci/drm/i915/display/skl_watermark.c

2043

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/skl_watermark.c

205

static void skl_sagv_disable(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

2055

skl_compute_transition_wm(display, &wm->trans_wm,

sys/dev/pci/drm/i915/display/skl_watermark.c

2058

if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/skl_watermark.c

2061

skl_compute_transition_wm(display, &wm->sagv.trans_wm,

sys/dev/pci/drm/i915/display/skl_watermark.c

209

if (!intel_has_sagv(display))

sys/dev/pci/drm/i915/display/skl_watermark.c

212

if (display->sagv.status == I915_SAGV_DISABLED)

sys/dev/pci/drm/i915/display/skl_watermark.c

2121

struct intel_display *display = to_intel_display(plane_state);

sys/dev/pci/drm/i915/display/skl_watermark.c

2136

drm_WARN_ON(display->drm,

sys/dev/pci/drm/i915/display/skl_watermark.c

2138

drm_WARN_ON(display->drm, !fb->format->is_yuv ||

sys/dev/pci/drm/i915/display/skl_watermark.c

215

drm_dbg_kms(display->drm, "Disabling SAGV\n");

sys/dev/pci/drm/i915/display/skl_watermark.c

2163

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/skl_watermark.c

217

ret = intel_pcode_request(display->drm, GEN9_PCODE_SAGV_CONTROL,

sys/dev/pci/drm/i915/display/skl_watermark.c

2170

drm_WARN_ON(display->drm, PTR_ERR(cdclk_state));

sys/dev/pci/drm/i915/display/skl_watermark.c

224

if (display->platform.skylake && ret == -ENXIO) {

sys/dev/pci/drm/i915/display/skl_watermark.c

225

drm_dbg(display->drm, "No SAGV found on system, ignoring\n");

sys/dev/pci/drm/i915/display/skl_watermark.c

226

display->sagv.status = I915_SAGV_NOT_CONTROLLED;

sys/dev/pci/drm/i915/display/skl_watermark.c

2283

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/skl_watermark.c

2286

for (level = display->wm.num_levels - 1; level >= 0; level--) {

sys/dev/pci/drm/i915/display/skl_watermark.c

229

drm_err(display->drm, "Failed to disable SAGV (%d)\n", ret);

sys/dev/pci/drm/i915/display/skl_watermark.c

2290

latency = skl_wm_latency(display, level, NULL);

sys/dev/pci/drm/i915/display/skl_watermark.c

2307

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/skl_watermark.c

2324

crtc_state->wm_level_disabled = level < display->wm.num_levels - 1;

sys/dev/pci/drm/i915/display/skl_watermark.c

2326

for (level++; level < display->wm.num_levels; level++) {

sys/dev/pci/drm/i915/display/skl_watermark.c

233

display->sagv.status = I915_SAGV_DISABLED;

sys/dev/pci/drm/i915/display/skl_watermark.c

2342

if (DISPLAY_VER(display) >= 12 &&

sys/dev/pci/drm/i915/display/skl_watermark.c

2343

display->sagv.block_time_us &&

sys/dev/pci/drm/i915/display/skl_watermark.c

2345

display->sagv.block_time_us)) {

sys/dev/pci/drm/i915/display/skl_watermark.c

2363

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/skl_watermark.c

2379

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/skl_watermark.c

238

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_watermark.c

2402

static bool skl_plane_wm_equals(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_watermark.c

2408

for (level = 0; level < display->wm.num_levels; level++) {

sys/dev/pci/drm/i915/display/skl_watermark.c

245

if (!intel_bw_can_enable_sagv(display, new_bw_state))

sys/dev/pci/drm/i915/display/skl_watermark.c

246

skl_sagv_disable(display);

sys/dev/pci/drm/i915/display/skl_watermark.c

2460

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_watermark.c

2467

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/skl_watermark.c

2478

drm_dbg_kms(display->drm, "[PLANE:%d:%s] Can't change DDB during async flip\n",

sys/dev/pci/drm/i915/display/skl_watermark.c

2497

struct intel_display *display = to_intel_display(dbuf_state->base.state->base.dev);

sys/dev/pci/drm/i915/display/skl_watermark.c

2507

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/skl_watermark.c

251

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_watermark.c

2516

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_watermark.c

2544

if (HAS_MBUS_JOINING(display)) {

sys/dev/pci/drm/i915/display/skl_watermark.c

2555

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/skl_watermark.c

2578

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_watermark.c

258

if (intel_bw_can_enable_sagv(display, new_bw_state))

sys/dev/pci/drm/i915/display/skl_watermark.c

2582

DISPLAY_INFO(display)->dbuf.slice_mask,

sys/dev/pci/drm/i915/display/skl_watermark.c

259

skl_sagv_enable(display);

sys/dev/pci/drm/i915/display/skl_watermark.c

2600

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/skl_watermark.c

2625

skl_print_plane_changes(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_watermark.c

2630

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_watermark.c

264

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_watermark.c

2649

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_watermark.c

2676

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_watermark.c

2695

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_watermark.c

2718

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_watermark.c

273

if (!intel_has_sagv(display))

sys/dev/pci/drm/i915/display/skl_watermark.c

2735

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/skl_watermark.c

2744

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_watermark.c

2751

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/skl_watermark.c

2758

if (skl_plane_wm_equals(display, old_wm, new_wm))

sys/dev/pci/drm/i915/display/skl_watermark.c

276

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/skl_watermark.c

2761

skl_print_plane_changes(display, plane, old_wm, new_wm);

sys/dev/pci/drm/i915/display/skl_watermark.c

2770

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_watermark.c

2773

for (level = 0; level < display->wm.num_levels; level++) {

sys/dev/pci/drm/i915/display/skl_watermark.c

2784

if (HAS_HW_SAGV_WM(display)) {

sys/dev/pci/drm/i915/display/skl_watermark.c

2822

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_watermark.c

2829

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/skl_watermark.c

284

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_watermark.c

2848

drm_dbg_kms(display->drm, "[PLANE:%d:%s] Can't change watermarks during async flip\n",

sys/dev/pci/drm/i915/display/skl_watermark.c

2867

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_watermark.c

2877

display->pkgc.disable[crtc->pipe] = crtc_state->vrr.enable;

sys/dev/pci/drm/i915/display/skl_watermark.c

2878

display->pkgc.linetime[crtc->pipe] = DIV_ROUND_UP(crtc_state->linetime, 8);

sys/dev/pci/drm/i915/display/skl_watermark.c

2882

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/skl_watermark.c

2883

if (display->pkgc.disable[crtc->pipe])

sys/dev/pci/drm/i915/display/skl_watermark.c

2886

max_linetime = max(display->pkgc.linetime[crtc->pipe], max_linetime);

sys/dev/pci/drm/i915/display/skl_watermark.c

2895

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_watermark.c

2898

if (DISPLAY_VER(display) < 20)

sys/dev/pci/drm/i915/display/skl_watermark.c

2901

mutex_lock(&display->wm.wm_mutex);

sys/dev/pci/drm/i915/display/skl_watermark.c

2903

latency = skl_watermark_max_latency(display, 1);

sys/dev/pci/drm/i915/display/skl_watermark.c

2906

if (display->params.enable_flipq)

sys/dev/pci/drm/i915/display/skl_watermark.c

2907

added_wake_time = intel_flipq_exec_time_us(display);

sys/dev/pci/drm/i915/display/skl_watermark.c

2913

if (latency && IS_DISPLAY_VER(display, 20, 30)) {

sys/dev/pci/drm/i915/display/skl_watermark.c

293

if (!intel_has_sagv(display))

sys/dev/pci/drm/i915/display/skl_watermark.c

2933

intel_de_write(display, LNL_PKG_C_LATENCY,

sys/dev/pci/drm/i915/display/skl_watermark.c

2937

mutex_unlock(&display->wm.wm_mutex);

sys/dev/pci/drm/i915/display/skl_watermark.c

2943

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_watermark.c

296

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/skl_watermark.c

2983

pipe_wm->use_sagv_wm = !HAS_HW_SAGV_WM(display) &&

sys/dev/pci/drm/i915/display/skl_watermark.c

2984

DISPLAY_VER(display) >= 12 &&

sys/dev/pci/drm/i915/display/skl_watermark.c

2997

static void skl_wm_level_from_reg_val(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_watermark.c

3004

level->auto_min_alloc_wm_enable = DISPLAY_VER(display) >= 30 ?

sys/dev/pci/drm/i915/display/skl_watermark.c

3011

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/skl_watermark.c

3020

for (level = 0; level < display->wm.num_levels; level++) {

sys/dev/pci/drm/i915/display/skl_watermark.c

3022

val = intel_de_read(display, PLANE_WM(pipe, plane_id, level));

sys/dev/pci/drm/i915/display/skl_watermark.c

3024

val = intel_de_read(display, CUR_WM(pipe, level));

sys/dev/pci/drm/i915/display/skl_watermark.c

3026

skl_wm_level_from_reg_val(display, val, &wm->wm[level]);

sys/dev/pci/drm/i915/display/skl_watermark.c

3030

val = intel_de_read(display, PLANE_WM_TRANS(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_watermark.c

3032

val = intel_de_read(display, CUR_WM_TRANS(pipe));

sys/dev/pci/drm/i915/display/skl_watermark.c

3034

skl_wm_level_from_reg_val(display, val, &wm->trans_wm);

sys/dev/pci/drm/i915/display/skl_watermark.c

3036

if (HAS_HW_SAGV_WM(display)) {

sys/dev/pci/drm/i915/display/skl_watermark.c

3038

val = intel_de_read(display, PLANE_WM_SAGV(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_watermark.c

304

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/skl_watermark.c

3040

val = intel_de_read(display, CUR_WM_SAGV(pipe));

sys/dev/pci/drm/i915/display/skl_watermark.c

3042

skl_wm_level_from_reg_val(display, val, &wm->sagv.wm0);

sys/dev/pci/drm/i915/display/skl_watermark.c

3045

val = intel_de_read(display, PLANE_WM_SAGV_TRANS(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_watermark.c

3047

val = intel_de_read(display, CUR_WM_SAGV_TRANS(pipe));

sys/dev/pci/drm/i915/display/skl_watermark.c

3049

skl_wm_level_from_reg_val(display, val, &wm->sagv.trans_wm);

sys/dev/pci/drm/i915/display/skl_watermark.c

3050

} else if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/skl_watermark.c

3057

static void skl_wm_get_hw_state(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

3060

to_intel_dbuf_state(display->dbuf.obj.state);

sys/dev/pci/drm/i915/display/skl_watermark.c

3063

if (HAS_MBUS_JOINING(display))

sys/dev/pci/drm/i915/display/skl_watermark.c

3064

dbuf_state->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN;

sys/dev/pci/drm/i915/display/skl_watermark.c

3066

dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(display, &display->cdclk.hw);

sys/dev/pci/drm/i915/display/skl_watermark.c

3069

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/skl_watermark.c

309

if (!intel_has_sagv(display))

sys/dev/pci/drm/i915/display/skl_watermark.c

3100

skl_ddb_get_hw_plane_state(display, crtc->pipe,

sys/dev/pci/drm/i915/display/skl_watermark.c

3116

mbus_offset = mbus_ddb_offset(display, slices);

sys/dev/pci/drm/i915/display/skl_watermark.c

3122

skl_ddb_dbuf_slice_mask(display, &crtc_state->wm.skl.ddb);

sys/dev/pci/drm/i915/display/skl_watermark.c

3124

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_watermark.c

3132

dbuf_state->enabled_slices = display->dbuf.enabled_slices;

sys/dev/pci/drm/i915/display/skl_watermark.c

3135

bool skl_watermark_ipc_enabled(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

3137

return display->wm.ipc_enabled;

sys/dev/pci/drm/i915/display/skl_watermark.c

3140

void skl_watermark_ipc_update(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

3142

if (!HAS_IPC(display))

sys/dev/pci/drm/i915/display/skl_watermark.c

3145

intel_de_rmw(display, DISP_ARB_CTL2, DISP_IPC_ENABLE,

sys/dev/pci/drm/i915/display/skl_watermark.c

3146

skl_watermark_ipc_enabled(display) ? DISP_IPC_ENABLE : 0);

sys/dev/pci/drm/i915/display/skl_watermark.c

3149

static bool skl_watermark_ipc_can_enable(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

3152

if (display->platform.skylake)

sys/dev/pci/drm/i915/display/skl_watermark.c

3156

if (display->platform.kabylake ||

sys/dev/pci/drm/i915/display/skl_watermark.c

3157

display->platform.coffeelake ||

sys/dev/pci/drm/i915/display/skl_watermark.c

3158

display->platform.cometlake) {

sys/dev/pci/drm/i915/display/skl_watermark.c

3159

const struct dram_info *dram_info = intel_dram_info(display->drm);

sys/dev/pci/drm/i915/display/skl_watermark.c

3167

void skl_watermark_ipc_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

3169

if (!HAS_IPC(display))

sys/dev/pci/drm/i915/display/skl_watermark.c

3172

display->wm.ipc_enabled = skl_watermark_ipc_can_enable(display);

sys/dev/pci/drm/i915/display/skl_watermark.c

3174

skl_watermark_ipc_update(display);

sys/dev/pci/drm/i915/display/skl_watermark.c

3178

adjust_wm_latency(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_watermark.c

3181

const struct dram_info *dram_info = intel_dram_info(display->drm);

sys/dev/pci/drm/i915/display/skl_watermark.c

3217

if (!display->platform.dg2 && dram_info->has_16gb_dimms)

sys/dev/pci/drm/i915/display/skl_watermark.c

3221

static void mtl_read_wm_latency(struct intel_display *display, u16 wm[])

sys/dev/pci/drm/i915/display/skl_watermark.c

3223

int num_levels = display->wm.num_levels;

sys/dev/pci/drm/i915/display/skl_watermark.c

3226

val = intel_de_read(display, MTL_LATENCY_LP0_LP1);

sys/dev/pci/drm/i915/display/skl_watermark.c

3230

val = intel_de_read(display, MTL_LATENCY_LP2_LP3);

sys/dev/pci/drm/i915/display/skl_watermark.c

3234

val = intel_de_read(display, MTL_LATENCY_LP4_LP5);

sys/dev/pci/drm/i915/display/skl_watermark.c

3238

adjust_wm_latency(display, wm, num_levels, 6);

sys/dev/pci/drm/i915/display/skl_watermark.c

3241

static void skl_read_wm_latency(struct intel_display *display, u16 wm[])

sys/dev/pci/drm/i915/display/skl_watermark.c

3243

int num_levels = display->wm.num_levels;

sys/dev/pci/drm/i915/display/skl_watermark.c

3244

int read_latency = DISPLAY_VER(display) >= 12 ? 3 : 2;

sys/dev/pci/drm/i915/display/skl_watermark.c

3245

int mult = display->platform.dg2 ? 2 : 1;

sys/dev/pci/drm/i915/display/skl_watermark.c

3251

ret = intel_pcode_read(display->drm, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);

sys/dev/pci/drm/i915/display/skl_watermark.c

3253

drm_err(display->drm, "SKL Mailbox read error = %d\n", ret);

sys/dev/pci/drm/i915/display/skl_watermark.c

3264

ret = intel_pcode_read(display->drm, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);

sys/dev/pci/drm/i915/display/skl_watermark.c

3266

drm_err(display->drm, "SKL Mailbox read error = %d\n", ret);

sys/dev/pci/drm/i915/display/skl_watermark.c

3275

adjust_wm_latency(display, wm, num_levels, read_latency);

sys/dev/pci/drm/i915/display/skl_watermark.c

3278

static void skl_setup_wm_latency(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

328

for (level = display->wm.num_levels - 1;

sys/dev/pci/drm/i915/display/skl_watermark.c

3280

if (HAS_HW_SAGV_WM(display))

sys/dev/pci/drm/i915/display/skl_watermark.c

3281

display->wm.num_levels = 6;

sys/dev/pci/drm/i915/display/skl_watermark.c

3283

display->wm.num_levels = 8;

sys/dev/pci/drm/i915/display/skl_watermark.c

3285

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/skl_watermark.c

3286

mtl_read_wm_latency(display, display->wm.skl_latency);

sys/dev/pci/drm/i915/display/skl_watermark.c

3288

skl_read_wm_latency(display, display->wm.skl_latency);

sys/dev/pci/drm/i915/display/skl_watermark.c

3290

intel_print_wm_latency(display, "Gen9 Plane", display->wm.skl_latency);

sys/dev/pci/drm/i915/display/skl_watermark.c

3318

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_watermark.c

3321

dbuf_state = intel_atomic_get_global_obj_state(state, &display->dbuf.obj);

sys/dev/pci/drm/i915/display/skl_watermark.c

3328

int intel_dbuf_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

3336

intel_atomic_global_obj_init(display, &display->dbuf.obj,

sys/dev/pci/drm/i915/display/skl_watermark.c

3364

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/skl_watermark.c

3367

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/skl_watermark.c

3370

if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/skl_watermark.c

3376

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/display/skl_watermark.c

3379

else if (display->platform.alderlake_p)

sys/dev/pci/drm/i915/display/skl_watermark.c

3386

if (DISPLAY_VER(display) >= 14) {

sys/dev/pci/drm/i915/display/skl_watermark.c

3388

} else if (display->platform.alderlake_p) {

sys/dev/pci/drm/i915/display/skl_watermark.c

3391

} else if (DISPLAY_VER(display) >= 12) {

sys/dev/pci/drm/i915/display/skl_watermark.c

3399

if (DISPLAY_VERx100(display) == 1400) {

sys/dev/pci/drm/i915/display/skl_watermark.c

3409

static void pipe_mbus_dbox_ctl_update(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_watermark.c

3414

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, dbuf_state->active_pipes)

sys/dev/pci/drm/i915/display/skl_watermark.c

3415

intel_de_write(display, PIPE_MBUS_DBOX_CTL(crtc->pipe),

sys/dev/pci/drm/i915/display/skl_watermark.c

3421

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_watermark.c

3424

if (DISPLAY_VER(display) < 11)

sys/dev/pci/drm/i915/display/skl_watermark.c

3434

pipe_mbus_dbox_ctl_update(display, new_dbuf_state);

sys/dev/pci/drm/i915/display/skl_watermark.c

3451

void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_watermark.c

3456

if (!HAS_MBUS_JOINING(display))

sys/dev/pci/drm/i915/display/skl_watermark.c

3459

if (DISPLAY_VER(display) >= 20)

sys/dev/pci/drm/i915/display/skl_watermark.c

3460

intel_de_rmw(display, MBUS_CTL, MBUS_TRANSLATION_THROTTLE_MIN_MASK,

sys/dev/pci/drm/i915/display/skl_watermark.c

3466

drm_dbg_kms(display->drm, "Updating dbuf ratio to %d (mbus joined: %s)\n",

sys/dev/pci/drm/i915/display/skl_watermark.c

3469

for_each_dbuf_slice(display, slice)

sys/dev/pci/drm/i915/display/skl_watermark.c

3470

intel_de_rmw(display, DBUF_CTL_S(slice),

sys/dev/pci/drm/i915/display/skl_watermark.c

3477

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_watermark.c

3492

intel_dbuf_mdclk_cdclk_ratio_update(display, mdclk_cdclk_ratio,

sys/dev/pci/drm/i915/display/skl_watermark.c

3499

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_watermark.c

3504

drm_WARN_ON(display->drm, !dbuf_state->joined_mbus);

sys/dev/pci/drm/i915/display/skl_watermark.c

3505

drm_WARN_ON(display->drm, !is_power_of_2(dbuf_state->active_pipes));

sys/dev/pci/drm/i915/display/skl_watermark.c

3507

crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/skl_watermark.c

3516

static void mbus_ctl_join_update(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_watermark.c

3532

intel_de_rmw(display, MBUS_CTL,

sys/dev/pci/drm/i915/display/skl_watermark.c

3540

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_watermark.c

3546

drm_dbg_kms(display->drm, "Changing mbus joined: %s -> %s (pipe: %c)\n",

sys/dev/pci/drm/i915/display/skl_watermark.c

3551

mbus_ctl_join_update(display, new_dbuf_state, pipe);

sys/dev/pci/drm/i915/display/skl_watermark.c

3577

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_watermark.c

3596

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/skl_watermark.c

3612

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_watermark.c

3630

gen9_dbuf_slices_update(display, new_slices);

sys/dev/pci/drm/i915/display/skl_watermark.c

3635

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_watermark.c

3653

gen9_dbuf_slices_update(display, new_slices);

sys/dev/pci/drm/i915/display/skl_watermark.c

3668

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_watermark.c

3678

if (DISPLAY_VER(display) < 30) {

sys/dev/pci/drm/i915/display/skl_watermark.c

3688

static void skl_mbus_sanitize(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

3691

to_intel_dbuf_state(display->dbuf.obj.state);

sys/dev/pci/drm/i915/display/skl_watermark.c

3693

if (!HAS_MBUS_JOINING(display))

sys/dev/pci/drm/i915/display/skl_watermark.c

3700

drm_dbg_kms(display->drm, "Disabling redundant MBUS joining (active pipes 0x%x)\n",

sys/dev/pci/drm/i915/display/skl_watermark.c

3704

intel_dbuf_mdclk_cdclk_ratio_update(display,

sys/dev/pci/drm/i915/display/skl_watermark.c

3707

pipe_mbus_dbox_ctl_update(display, dbuf_state);

sys/dev/pci/drm/i915/display/skl_watermark.c

3708

mbus_ctl_join_update(display, dbuf_state, INVALID_PIPE);

sys/dev/pci/drm/i915/display/skl_watermark.c

3711

static bool skl_dbuf_is_misconfigured(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

3714

to_intel_dbuf_state(display->dbuf.obj.state);

sys/dev/pci/drm/i915/display/skl_watermark.c

3718

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/skl_watermark.c

3725

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/skl_watermark.c

3743

static void skl_dbuf_sanitize(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

3758

if (!skl_dbuf_is_misconfigured(display))

sys/dev/pci/drm/i915/display/skl_watermark.c

376

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/skl_watermark.c

3761

drm_dbg_kms(display->drm, "BIOS has misprogrammed the DBUF, disabling all planes\n");

sys/dev/pci/drm/i915/display/skl_watermark.c

3763

for_each_intel_crtc(display->drm, crtc) {

sys/dev/pci/drm/i915/display/skl_watermark.c

3773

drm_WARN_ON(display->drm, crtc_state->active_planes != 0);

sys/dev/pci/drm/i915/display/skl_watermark.c

3779

static void skl_wm_sanitize(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

378

if (!display->params.enable_sagv)

sys/dev/pci/drm/i915/display/skl_watermark.c

3781

skl_mbus_sanitize(display);

sys/dev/pci/drm/i915/display/skl_watermark.c

3782

skl_dbuf_sanitize(display);

sys/dev/pci/drm/i915/display/skl_watermark.c

3787

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/skl_watermark.c

3791

to_intel_dbuf_state(display->dbuf.obj.state);

sys/dev/pci/drm/i915/display/skl_watermark.c

3794

if (DISPLAY_VER(display) < 9)

sys/dev/pci/drm/i915/display/skl_watermark.c

3810

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/skl_watermark.c

3814

if (DISPLAY_VER(display) < 9)

sys/dev/pci/drm/i915/display/skl_watermark.c

3832

struct intel_display *display = to_intel_display(state);

sys/dev/pci/drm/i915/display/skl_watermark.c

3847

if (DISPLAY_VER(display) < 9 || !new_crtc_state->hw.active)

sys/dev/pci/drm/i915/display/skl_watermark.c

3858

hw_enabled_slices = intel_enabled_dbuf_slices_mask(display);

sys/dev/pci/drm/i915/display/skl_watermark.c

3860

if (DISPLAY_VER(display) >= 11 &&

sys/dev/pci/drm/i915/display/skl_watermark.c

3861

hw_enabled_slices != display->dbuf.enabled_slices)

sys/dev/pci/drm/i915/display/skl_watermark.c

3862

drm_err(display->drm,

sys/dev/pci/drm/i915/display/skl_watermark.c

3864

display->dbuf.enabled_slices,

sys/dev/pci/drm/i915/display/skl_watermark.c

3867

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/skl_watermark.c

3872

for (level = 0; level < display->wm.num_levels; level++) {

sys/dev/pci/drm/i915/display/skl_watermark.c

3879

drm_err(display->drm,

sys/dev/pci/drm/i915/display/skl_watermark.c

389

if (DISPLAY_VER(display) >= 12)

sys/dev/pci/drm/i915/display/skl_watermark.c

3894

drm_err(display->drm,

sys/dev/pci/drm/i915/display/skl_watermark.c

3908

if (HAS_HW_SAGV_WM(display) &&

sys/dev/pci/drm/i915/display/skl_watermark.c

3910

drm_err(display->drm,

sys/dev/pci/drm/i915/display/skl_watermark.c

3924

if (HAS_HW_SAGV_WM(display) &&

sys/dev/pci/drm/i915/display/skl_watermark.c

3926

drm_err(display->drm,

sys/dev/pci/drm/i915/display/skl_watermark.c

3942

drm_err(display->drm,

sys/dev/pci/drm/i915/display/skl_watermark.c

3959

void skl_wm_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

3961

intel_sagv_init(display);

sys/dev/pci/drm/i915/display/skl_watermark.c

3963

skl_setup_wm_latency(display);

sys/dev/pci/drm/i915/display/skl_watermark.c

3965

display->funcs.wm = &skl_wm_funcs;

sys/dev/pci/drm/i915/display/skl_watermark.c

3972

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/skl_watermark.c

3975

str_yes_no(skl_watermark_ipc_enabled(display)));

sys/dev/pci/drm/i915/display/skl_watermark.c

3981

struct intel_display *display = inode->i_private;

sys/dev/pci/drm/i915/display/skl_watermark.c

3983

return single_open(file, skl_watermark_ipc_status_show, display);

sys/dev/pci/drm/i915/display/skl_watermark.c

3991

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/skl_watermark.c

3999

with_intel_display_rpm(display) {

sys/dev/pci/drm/i915/display/skl_watermark.c

4000

if (!skl_watermark_ipc_enabled(display) && enable)

sys/dev/pci/drm/i915/display/skl_watermark.c

4001

drm_info(display->drm,

sys/dev/pci/drm/i915/display/skl_watermark.c

4003

display->wm.ipc_enabled = enable;

sys/dev/pci/drm/i915/display/skl_watermark.c

4004

skl_watermark_ipc_update(display);

sys/dev/pci/drm/i915/display/skl_watermark.c

4023

struct intel_display *display = m->private;

sys/dev/pci/drm/i915/display/skl_watermark.c

4031

seq_printf(m, "SAGV available: %s\n", str_yes_no(intel_has_sagv(display)));

sys/dev/pci/drm/i915/display/skl_watermark.c

4033

str_enabled_disabled(display->params.enable_sagv));

sys/dev/pci/drm/i915/display/skl_watermark.c

4034

seq_printf(m, "SAGV status: %s\n", sagv_status[display->sagv.status]);

sys/dev/pci/drm/i915/display/skl_watermark.c

4035

seq_printf(m, "SAGV block time: %d usec\n", display->sagv.block_time_us);

sys/dev/pci/drm/i915/display/skl_watermark.c

404

static int intel_dbuf_slice_size(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

4042

void skl_watermark_debugfs_register(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

4044

struct dentry *debugfs_root = display->drm->debugfs_root;

sys/dev/pci/drm/i915/display/skl_watermark.c

4046

if (HAS_IPC(display))

sys/dev/pci/drm/i915/display/skl_watermark.c

4048

display, &skl_watermark_ipc_status_fops);

sys/dev/pci/drm/i915/display/skl_watermark.c

4050

if (HAS_SAGV(display))

sys/dev/pci/drm/i915/display/skl_watermark.c

4052

display, &intel_sagv_status_fops);

sys/dev/pci/drm/i915/display/skl_watermark.c

4055

unsigned int skl_watermark_max_latency(struct intel_display *display, int initial_wm_level)

sys/dev/pci/drm/i915/display/skl_watermark.c

4059

for (level = display->wm.num_levels - 1; level >= initial_wm_level; level--) {

sys/dev/pci/drm/i915/display/skl_watermark.c

406

return DISPLAY_INFO(display)->dbuf.size /

sys/dev/pci/drm/i915/display/skl_watermark.c

4060

unsigned int latency = skl_wm_latency(display, level, NULL);

sys/dev/pci/drm/i915/display/skl_watermark.c

407

hweight8(DISPLAY_INFO(display)->dbuf.slice_mask);

sys/dev/pci/drm/i915/display/skl_watermark.c

411

skl_ddb_entry_for_slices(struct intel_display *display, u8 slice_mask,

sys/dev/pci/drm/i915/display/skl_watermark.c

414

int slice_size = intel_dbuf_slice_size(display);

sys/dev/pci/drm/i915/display/skl_watermark.c

426

WARN_ON(ddb->end > DISPLAY_INFO(display)->dbuf.size);

sys/dev/pci/drm/i915/display/skl_watermark.c

429

static unsigned int mbus_ddb_offset(struct intel_display *display, u8 slice_mask)

sys/dev/pci/drm/i915/display/skl_watermark.c

438

skl_ddb_entry_for_slices(display, slice_mask, &ddb);

sys/dev/pci/drm/i915/display/skl_watermark.c

443

u32 skl_ddb_dbuf_slice_mask(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_watermark.c

446

int slice_size = intel_dbuf_slice_size(display);

sys/dev/pci/drm/i915/display/skl_watermark.c

492

struct intel_display *display = to_intel_display(dbuf_state->base.state->base.dev);

sys/dev/pci/drm/i915/display/skl_watermark.c

499

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/skl_watermark.c

525

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/skl_watermark.c

547

skl_ddb_entry_for_slices(display, dbuf_slice_mask, &ddb_slices);

sys/dev/pci/drm/i915/display/skl_watermark.c

548

mbus_offset = mbus_ddb_offset(display, dbuf_slice_mask);

sys/dev/pci/drm/i915/display/skl_watermark.c

56

static void skl_sagv_disable(struct intel_display *display);

sys/dev/pci/drm/i915/display/skl_watermark.c

582

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/skl_watermark.c

607

static unsigned int skl_wm_latency(struct intel_display *display, int level,

sys/dev/pci/drm/i915/display/skl_watermark.c

610

unsigned int latency = display->wm.skl_latency[level];

sys/dev/pci/drm/i915/display/skl_watermark.c

619

if ((display->platform.kabylake || display->platform.coffeelake ||

sys/dev/pci/drm/i915/display/skl_watermark.c

620

display->platform.cometlake) && skl_watermark_ipc_enabled(display))

sys/dev/pci/drm/i915/display/skl_watermark.c

623

if (skl_needs_memory_bw_wa(display) && wp && wp->x_tiled)

sys/dev/pci/drm/i915/display/skl_watermark.c

633

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/skl_watermark.c

645

drm_WARN_ON(display->drm, ret);

sys/dev/pci/drm/i915/display/skl_watermark.c

647

for (level = 0; level < display->wm.num_levels; level++) {

sys/dev/pci/drm/i915/display/skl_watermark.c

648

unsigned int latency = skl_wm_latency(display, level, &wp);

sys/dev/pci/drm/i915/display/skl_watermark.c

670

skl_ddb_get_hw_plane_state(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_watermark.c

681

val = intel_de_read(display, CUR_BUF_CFG(pipe));

sys/dev/pci/drm/i915/display/skl_watermark.c

686

val = intel_de_read(display, PLANE_BUF_CFG(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_watermark.c

689

if (DISPLAY_VER(display) >= 30) {

sys/dev/pci/drm/i915/display/skl_watermark.c

690

val = intel_de_read(display, PLANE_MIN_BUF_CFG(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_watermark.c

696

if (DISPLAY_VER(display) >= 11)

sys/dev/pci/drm/i915/display/skl_watermark.c

699

val = intel_de_read(display, PLANE_NV12_BUF_CFG(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_watermark.c

708

struct intel_display *display = to_intel_display(crtc);

sys/dev/pci/drm/i915/display/skl_watermark.c

715

wakeref = intel_display_power_get_if_enabled(display, power_domain);

sys/dev/pci/drm/i915/display/skl_watermark.c

720

skl_ddb_get_hw_plane_state(display, pipe,

sys/dev/pci/drm/i915/display/skl_watermark.c

727

intel_display_power_put(display, power_domain, wakeref);

sys/dev/pci/drm/i915/display/skl_watermark.c

74

u8 intel_enabled_dbuf_slices_mask(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

79

for_each_dbuf_slice(display, slice) {

sys/dev/pci/drm/i915/display/skl_watermark.c

80

if (intel_de_read(display, DBUF_CTL_S(slice)) & DBUF_POWER_STATE)

sys/dev/pci/drm/i915/display/skl_watermark.c

91

static bool skl_needs_memory_bw_wa(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

93

return DISPLAY_VER(display) == 9;

sys/dev/pci/drm/i915/display/skl_watermark.c

97

intel_has_sagv(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

99

return HAS_SAGV(display) && display->sagv.status != I915_SAGV_NOT_CONTROLLED;

sys/dev/pci/drm/i915/display/skl_watermark.h

23

u8 intel_enabled_dbuf_slices_mask(struct intel_display *display);

sys/dev/pci/drm/i915/display/skl_watermark.h

28

bool intel_has_sagv(struct intel_display *display);

sys/dev/pci/drm/i915/display/skl_watermark.h

30

u32 skl_ddb_dbuf_slice_mask(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_watermark.h

44

void skl_watermark_ipc_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/skl_watermark.h

45

void skl_watermark_ipc_update(struct intel_display *display);

sys/dev/pci/drm/i915/display/skl_watermark.h

46

bool skl_watermark_ipc_enabled(struct intel_display *display);

sys/dev/pci/drm/i915/display/skl_watermark.h

47

void skl_watermark_debugfs_register(struct intel_display *display);

sys/dev/pci/drm/i915/display/skl_watermark.h

49

unsigned int skl_watermark_max_latency(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_watermark.h

51

void skl_wm_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/skl_watermark.h

68

int intel_dbuf_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/skl_watermark.h

74

void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,

sys/dev/pci/drm/i915/display/vlv_dsi.c

1005

intel_display_power_put(display, encoder->power_domain, wakeref);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1013

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi.c

102

static void write_data(struct intel_display *display,

sys/dev/pci/drm/i915/display/vlv_dsi.c

1035

if (intel_de_read(display, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)

sys/dev/pci/drm/i915/display/vlv_dsi.c

1039

fmt = intel_de_read(display, MIPI_DSI_FUNC_PRG(display, port)) & VID_MODE_FORMAT_MASK;

sys/dev/pci/drm/i915/display/vlv_dsi.c

1051

intel_de_read(display,

sys/dev/pci/drm/i915/display/vlv_dsi.c

1054

intel_de_read(display,

sys/dev/pci/drm/i915/display/vlv_dsi.c

1057

intel_de_read(display,

sys/dev/pci/drm/i915/display/vlv_dsi.c

1061

hfp = intel_de_read(display, MIPI_HFP_COUNT(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi.c

1067

hsync = intel_de_read(display, MIPI_HSYNC_PADDING_COUNT(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi.c

1068

hbp = intel_de_read(display, MIPI_HBP_COUNT(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi.c

1085

vfp = intel_de_read(display, MIPI_VFP_COUNT(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi.c

1086

vbp = intel_de_read(display, MIPI_VBP_COUNT(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi.c

1087

vsync = intel_de_read(display, MIPI_VSYNC_PADDING_COUNT(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi.c

1095

drm_WARN_ON(display->drm, adjusted_mode->crtc_vdisplay +

sys/dev/pci/drm/i915/display/vlv_dsi.c

114

intel_de_write(display, reg, val);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1178

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi.c

118

static void read_data(struct intel_display *display,

sys/dev/pci/drm/i915/display/vlv_dsi.c

1182

drm_dbg_kms(display->drm, "\n");

sys/dev/pci/drm/i915/display/vlv_dsi.c

1186

if (display->platform.geminilake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/vlv_dsi.c

1218

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi.c

125

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1253

if (display->platform.geminilake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/vlv_dsi.c

1260

intel_de_write(display, BXT_MIPI_TRANS_HACTIVE(port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1262

intel_de_write(display, BXT_MIPI_TRANS_VACTIVE(port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1264

intel_de_write(display, BXT_MIPI_TRANS_VTOTAL(port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1268

intel_de_write(display, MIPI_HACTIVE_AREA_COUNT(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1270

intel_de_write(display, MIPI_HFP_COUNT(display, port), hfp);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1274

intel_de_write(display, MIPI_HSYNC_PADDING_COUNT(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1276

intel_de_write(display, MIPI_HBP_COUNT(display, port), hbp);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1279

intel_de_write(display, MIPI_VFP_COUNT(display, port), vfp);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1280

intel_de_write(display, MIPI_VSYNC_PADDING_COUNT(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1282

intel_de_write(display, MIPI_VBP_COUNT(display, port), vbp);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1306

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1315

drm_dbg_kms(display->drm, "pipe %c\n", pipe_name(crtc->pipe));

sys/dev/pci/drm/i915/display/vlv_dsi.c

1326

if (display->platform.valleyview || display->platform.cherryview) {

sys/dev/pci/drm/i915/display/vlv_dsi.c

1331

tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A));

sys/dev/pci/drm/i915/display/vlv_dsi.c

1333

intel_de_write(display, MIPI_CTRL(display, PORT_A),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1337

tmp = intel_de_read(display, MIPI_CTRL(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi.c

1339

intel_de_write(display, MIPI_CTRL(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1341

} else if (display->platform.geminilake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/vlv_dsi.c

1344

intel_de_rmw(display, MIPI_CTRL(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1349

intel_de_write(display, MIPI_INTR_STAT(display, port), 0xffffffff);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1350

intel_de_write(display, MIPI_INTR_EN(display, port), 0xffffffff);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1352

intel_de_write(display, MIPI_DPHY_PARAM(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1355

intel_de_write(display, MIPI_DPI_RESOLUTION(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

137

struct intel_display *display = to_intel_display(&intel_dsi->base);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1376

if (display->platform.geminilake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/vlv_dsi.c

1383

intel_de_write(display, MIPI_DSI_FUNC_PRG(display, port), val);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1404

intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1407

intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1410

intel_de_write(display, MIPI_LP_RX_TIMEOUT(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1412

intel_de_write(display, MIPI_TURN_AROUND_TIMEOUT(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1414

intel_de_write(display, MIPI_DEVICE_RESET_TIMER(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1420

intel_de_write(display, MIPI_INIT_COUNT(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1423

if ((display->platform.geminilake || display->platform.broxton) &&

sys/dev/pci/drm/i915/display/vlv_dsi.c

1431

intel_de_write(display,

sys/dev/pci/drm/i915/display/vlv_dsi.c

1432

MIPI_INIT_COUNT(display, port == PORT_A ? PORT_C : PORT_A),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1437

intel_de_write(display, MIPI_EOT_DISABLE(display, port), tmp);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1440

intel_de_write(display, MIPI_INIT_COUNT(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1448

intel_de_write(display, MIPI_HIGH_LOW_SWITCH_COUNT(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1457

intel_de_write(display, MIPI_LP_BYTECLK(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1460

if (display->platform.geminilake) {

sys/dev/pci/drm/i915/display/vlv_dsi.c

1461

intel_de_write(display, MIPI_TLPX_TIME_COUNT(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1464

intel_de_write(display, MIPI_CLK_LANE_TIMING(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1473

intel_de_write(display, MIPI_DBI_BW_CTRL(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1476

intel_de_write(display, MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1504

intel_de_write(display, MIPI_VIDEO_MODE_FORMAT(display, port), fmt);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1511

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1515

if (display->platform.geminilake)

sys/dev/pci/drm/i915/display/vlv_dsi.c

152

data_reg = MIPI_LP_GEN_DATA(display, port);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1520

intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x0);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1522

if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/vlv_dsi.c

1526

intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1528

intel_de_rmw(display, MIPI_DSI_FUNC_PRG(display, port), VID_MODE_FORMAT_MASK, 0);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1530

intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x1);

sys/dev/pci/drm/i915/display/vlv_dsi.c

154

ctrl_reg = MIPI_LP_GEN_CTRL(display, port);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1541

struct intel_display *display = to_intel_display(connector->dev);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1543

if (display->platform.valleyview || display->platform.cherryview) {

sys/dev/pci/drm/i915/display/vlv_dsi.c

1546

status = intel_cpu_transcoder_mode_valid(display, mode);

sys/dev/pci/drm/i915/display/vlv_dsi.c

157

data_reg = MIPI_HS_GEN_DATA(display, port);

sys/dev/pci/drm/i915/display/vlv_dsi.c

159

ctrl_reg = MIPI_HS_GEN_CTRL(display, port);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1594

struct intel_display *display = to_intel_display(&intel_dsi->base);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1643

mul = display->platform.geminilake ? 8 : 2;

sys/dev/pci/drm/i915/display/vlv_dsi.c

165

if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1651

drm_dbg_kms(display->drm, "prepare count too high %u\n",

sys/dev/pci/drm/i915/display/vlv_dsi.c

167

drm_err(display->drm,

sys/dev/pci/drm/i915/display/vlv_dsi.c

1672

drm_dbg_kms(display->drm, "exit zero count too high %u\n",

sys/dev/pci/drm/i915/display/vlv_dsi.c

1683

drm_dbg_kms(display->drm, "clock zero count too high %u\n",

sys/dev/pci/drm/i915/display/vlv_dsi.c

1693

drm_dbg_kms(display->drm, "trail count too high %u\n",

sys/dev/pci/drm/i915/display/vlv_dsi.c

170

write_data(display, data_reg, packet.payload,

sys/dev/pci/drm/i915/display/vlv_dsi.c

175

intel_de_write(display, MIPI_INTR_STAT(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1759

struct intel_display *display = to_intel_display(crtc_state);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1768

if (display->platform.valleyview)

sys/dev/pci/drm/i915/display/vlv_dsi.c

1776

if (display->platform.geminilake)

sys/dev/pci/drm/i915/display/vlv_dsi.c

179

if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

181

drm_err(display->drm,

sys/dev/pci/drm/i915/display/vlv_dsi.c

185

intel_de_write(display, ctrl_reg,

sys/dev/pci/drm/i915/display/vlv_dsi.c

1901

void vlv_dsi_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/vlv_dsi.c

191

if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

1911

drm_dbg_kms(display->drm, "\n");

sys/dev/pci/drm/i915/display/vlv_dsi.c

1914

if (!intel_bios_is_dsi_present(display, &port))

sys/dev/pci/drm/i915/display/vlv_dsi.c

1917

if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/vlv_dsi.c

1918

display->dsi.mmio_base = BXT_MIPI_BASE;

sys/dev/pci/drm/i915/display/vlv_dsi.c

1920

display->dsi.mmio_base = VLV_MIPI_BASE;

sys/dev/pci/drm/i915/display/vlv_dsi.c

193

drm_err(display->drm,

sys/dev/pci/drm/i915/display/vlv_dsi.c

1935

drm_encoder_init(display->drm, &encoder->base, &intel_dsi_funcs,

sys/dev/pci/drm/i915/display/vlv_dsi.c

1940

if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/vlv_dsi.c

196

read_data(display, data_reg, msg->rx_buf, msg->rx_len);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1960

if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/vlv_dsi.c

1969

intel_bios_init_panel_late(display, &connector->panel, NULL, NULL);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1976

if (drm_WARN_ON(display->drm, connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))

sys/dev/pci/drm/i915/display/vlv_dsi.c

1979

if (drm_WARN_ON(display->drm, connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))

sys/dev/pci/drm/i915/display/vlv_dsi.c

1995

drm_dbg_kms(display->drm, "no device found\n");

sys/dev/pci/drm/i915/display/vlv_dsi.c

2002

drm_dbg_kms(display->drm, "Calculated pclk %d GOP %d\n",

sys/dev/pci/drm/i915/display/vlv_dsi.c

2006

drm_dbg_kms(display->drm, "Using GOP pclk\n");

sys/dev/pci/drm/i915/display/vlv_dsi.c

2018

drm_connector_init(display->drm, &connector->base, &intel_dsi_connector_funcs,

sys/dev/pci/drm/i915/display/vlv_dsi.c

2027

mutex_lock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/vlv_dsi.c

2029

mutex_unlock(&display->drm->mode_config.mutex);

sys/dev/pci/drm/i915/display/vlv_dsi.c

2032

drm_dbg_kms(display->drm, "no fixed mode\n");

sys/dev/pci/drm/i915/display/vlv_dsi.c

229

struct intel_display *display = to_intel_display(&intel_dsi->base);

sys/dev/pci/drm/i915/display/vlv_dsi.c

239

intel_de_write(display, MIPI_INTR_STAT(display, port), SPL_PKT_SENT_INTERRUPT);

sys/dev/pci/drm/i915/display/vlv_dsi.c

242

if (cmd == intel_de_read(display, MIPI_DPI_CONTROL(display, port)))

sys/dev/pci/drm/i915/display/vlv_dsi.c

243

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/vlv_dsi.c

246

intel_de_write(display, MIPI_DPI_CONTROL(display, port), cmd);

sys/dev/pci/drm/i915/display/vlv_dsi.c

249

if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port), mask, 100))

sys/dev/pci/drm/i915/display/vlv_dsi.c

250

drm_err(display->drm,

sys/dev/pci/drm/i915/display/vlv_dsi.c

256

static void band_gap_reset(struct intel_display *display)

sys/dev/pci/drm/i915/display/vlv_dsi.c

258

vlv_flisdsi_get(display->drm);

sys/dev/pci/drm/i915/display/vlv_dsi.c

260

vlv_flisdsi_write(display->drm, 0x08, 0x0001);

sys/dev/pci/drm/i915/display/vlv_dsi.c

261

vlv_flisdsi_write(display->drm, 0x0F, 0x0005);

sys/dev/pci/drm/i915/display/vlv_dsi.c

262

vlv_flisdsi_write(display->drm, 0x0F, 0x0025);

sys/dev/pci/drm/i915/display/vlv_dsi.c

264

vlv_flisdsi_write(display->drm, 0x0F, 0x0000);

sys/dev/pci/drm/i915/display/vlv_dsi.c

265

vlv_flisdsi_write(display->drm, 0x08, 0x0000);

sys/dev/pci/drm/i915/display/vlv_dsi.c

267

vlv_flisdsi_put(display->drm);

sys/dev/pci/drm/i915/display/vlv_dsi.c

274

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi.c

280

drm_dbg_kms(display->drm, "\n");

sys/dev/pci/drm/i915/display/vlv_dsi.c

303

if (display->platform.geminilake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/vlv_dsi.c

330

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi.c

340

intel_de_rmw(display, MIPI_CTRL(display, port), 0, GLK_MIPIIO_ENABLE);

sys/dev/pci/drm/i915/display/vlv_dsi.c

343

intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);

sys/dev/pci/drm/i915/display/vlv_dsi.c

347

u32 tmp = intel_de_read(display, MIPI_DEVICE_READY(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi.c

349

intel_de_rmw(display, MIPI_CTRL(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

355

if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

357

drm_err(display->drm, "MIPIO port is powergated\n");

sys/dev/pci/drm/i915/display/vlv_dsi.c

363

!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY);

sys/dev/pci/drm/i915/display/vlv_dsi.c

371

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi.c

377

if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

379

drm_err(display->drm, "PHY is not ON\n");

sys/dev/pci/drm/i915/display/vlv_dsi.c

383

intel_de_rmw(display, MIPI_CTRL(display, PORT_A), 0, GLK_MIPIIO_RESET_RELEASED);

sys/dev/pci/drm/i915/display/vlv_dsi.c

387

if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) {

sys/dev/pci/drm/i915/display/vlv_dsi.c

388

intel_de_rmw(display, MIPI_DEVICE_READY(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

393

intel_de_rmw(display, MIPI_DEVICE_READY(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

397

if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

399

drm_err(display->drm, "ULPS not active\n");

sys/dev/pci/drm/i915/display/vlv_dsi.c

402

intel_de_rmw(display, MIPI_DEVICE_READY(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

406

intel_de_rmw(display, MIPI_DEVICE_READY(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

410

intel_de_rmw(display, MIPI_CTRL(display, port), GLK_LP_WAKE, 0);

sys/dev/pci/drm/i915/display/vlv_dsi.c

416

if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

418

drm_err(display->drm,

sys/dev/pci/drm/i915/display/vlv_dsi.c

424

if (intel_de_wait_for_set(display, BXT_MIPI_PORT_CTRL(port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

426

drm_err(display->drm,

sys/dev/pci/drm/i915/display/vlv_dsi.c

433

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi.c

438

drm_dbg_kms(display->drm, "\n");

sys/dev/pci/drm/i915/display/vlv_dsi.c

442

intel_de_rmw(display, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD);

sys/dev/pci/drm/i915/display/vlv_dsi.c

448

val = intel_de_read(display, MIPI_DEVICE_READY(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi.c

450

intel_de_write(display, MIPI_DEVICE_READY(display, port), val);

sys/dev/pci/drm/i915/display/vlv_dsi.c

453

intel_de_write(display, MIPI_DEVICE_READY(display, port), val);

sys/dev/pci/drm/i915/display/vlv_dsi.c

459

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi.c

463

drm_dbg_kms(display->drm, "\n");

sys/dev/pci/drm/i915/display/vlv_dsi.c

465

vlv_flisdsi_get(display->drm);

sys/dev/pci/drm/i915/display/vlv_dsi.c

468

vlv_flisdsi_write(display->drm, 0x04, 0x0004);

sys/dev/pci/drm/i915/display/vlv_dsi.c

469

vlv_flisdsi_put(display->drm);

sys/dev/pci/drm/i915/display/vlv_dsi.c

472

band_gap_reset(display);

sys/dev/pci/drm/i915/display/vlv_dsi.c

476

intel_de_write(display, MIPI_DEVICE_READY(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

484

intel_de_rmw(display, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD);

sys/dev/pci/drm/i915/display/vlv_dsi.c

487

intel_de_write(display, MIPI_DEVICE_READY(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

491

intel_de_write(display, MIPI_DEVICE_READY(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

499

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi.c

501

if (display->platform.geminilake)

sys/dev/pci/drm/i915/display/vlv_dsi.c

503

else if (display->platform.geminilake || display->platform.broxton)

sys/dev/pci/drm/i915/display/vlv_dsi.c

511

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi.c

517

intel_de_rmw(display, MIPI_DEVICE_READY(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

522

if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

524

drm_err(display->drm, "PHY is not turning OFF\n");

sys/dev/pci/drm/i915/display/vlv_dsi.c

529

if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

531

drm_err(display->drm,

sys/dev/pci/drm/i915/display/vlv_dsi.c

538

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi.c

543

intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);

sys/dev/pci/drm/i915/display/vlv_dsi.c

547

if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

549

drm_err(display->drm, "PHY is not turning OFF\n");

sys/dev/pci/drm/i915/display/vlv_dsi.c

554

intel_de_rmw(display, MIPI_CTRL(display, port), GLK_MIPIIO_ENABLE, 0);

sys/dev/pci/drm/i915/display/vlv_dsi.c

563

static i915_reg_t port_ctrl_reg(struct intel_display *display, enum port port)

sys/dev/pci/drm/i915/display/vlv_dsi.c

565

return display->platform.geminilake || display->platform.broxton ?

sys/dev/pci/drm/i915/display/vlv_dsi.c

571

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi.c

575

drm_dbg_kms(display->drm, "\n");

sys/dev/pci/drm/i915/display/vlv_dsi.c

578

i915_reg_t port_ctrl = display->platform.broxton ?

sys/dev/pci/drm/i915/display/vlv_dsi.c

581

intel_de_write(display, MIPI_DEVICE_READY(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

585

intel_de_write(display, MIPI_DEVICE_READY(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

589

intel_de_write(display, MIPI_DEVICE_READY(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

597

if ((display->platform.broxton || port == PORT_A) &&

sys/dev/pci/drm/i915/display/vlv_dsi.c

598

intel_de_wait_for_clear(display, port_ctrl,

sys/dev/pci/drm/i915/display/vlv_dsi.c

600

drm_err(display->drm, "DSI LP not going Low\n");

sys/dev/pci/drm/i915/display/vlv_dsi.c

603

intel_de_rmw(display, port_ctrl, LP_OUTPUT_HOLD, 0);

sys/dev/pci/drm/i915/display/vlv_dsi.c

606

intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x00);

sys/dev/pci/drm/i915/display/vlv_dsi.c

614

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi.c

622

if (display->platform.geminilake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/vlv_dsi.c

624

intel_de_rmw(display, MIPI_CTRL(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

628

intel_de_rmw(display, VLV_CHICKEN_3,

sys/dev/pci/drm/i915/display/vlv_dsi.c

635

i915_reg_t port_ctrl = port_ctrl_reg(display, port);

sys/dev/pci/drm/i915/display/vlv_dsi.c

638

temp = intel_de_read(display, port_ctrl);

sys/dev/pci/drm/i915/display/vlv_dsi.c

646

if (display->platform.broxton)

sys/dev/pci/drm/i915/display/vlv_dsi.c

658

intel_de_write(display, port_ctrl, temp | DPI_ENABLE);

sys/dev/pci/drm/i915/display/vlv_dsi.c

659

intel_de_posting_read(display, port_ctrl);

sys/dev/pci/drm/i915/display/vlv_dsi.c

665

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi.c

670

i915_reg_t port_ctrl = port_ctrl_reg(display, port);

sys/dev/pci/drm/i915/display/vlv_dsi.c

673

intel_de_rmw(display, port_ctrl, DPI_ENABLE, 0);

sys/dev/pci/drm/i915/display/vlv_dsi.c

674

intel_de_posting_read(display, port_ctrl);

sys/dev/pci/drm/i915/display/vlv_dsi.c

728

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi.c

735

drm_dbg_kms(display->drm, "\n");

sys/dev/pci/drm/i915/display/vlv_dsi.c

739

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/vlv_dsi.c

745

if (display->platform.geminilake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/vlv_dsi.c

753

if (display->platform.broxton) {

sys/dev/pci/drm/i915/display/vlv_dsi.c

755

intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL);

sys/dev/pci/drm/i915/display/vlv_dsi.c

758

intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);

sys/dev/pci/drm/i915/display/vlv_dsi.c

759

intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, 0);

sys/dev/pci/drm/i915/display/vlv_dsi.c

762

if (display->platform.valleyview || display->platform.cherryview) {

sys/dev/pci/drm/i915/display/vlv_dsi.c

764

intel_de_rmw(display, VLV_DSPCLK_GATE_D,

sys/dev/pci/drm/i915/display/vlv_dsi.c

768

if (!display->platform.geminilake)

sys/dev/pci/drm/i915/display/vlv_dsi.c

776

if (display->platform.geminilake) {

sys/dev/pci/drm/i915/display/vlv_dsi.c

788

if (display->platform.geminilake && !glk_cold_boot)

sys/dev/pci/drm/i915/display/vlv_dsi.c

800

intel_de_write(display,

sys/dev/pci/drm/i915/display/vlv_dsi.c

801

MIPI_MAX_RETURN_PKT_SIZE(display, port), 8 * 4);

sys/dev/pci/drm/i915/display/vlv_dsi.c

836

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi.c

840

drm_dbg_kms(display->drm, "\n");

sys/dev/pci/drm/i915/display/vlv_dsi.c

860

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi.c

862

if (display->platform.geminilake)

sys/dev/pci/drm/i915/display/vlv_dsi.c

873

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi.c

877

drm_dbg_kms(display->drm, "\n");

sys/dev/pci/drm/i915/display/vlv_dsi.c

879

if (display->platform.geminilake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/vlv_dsi.c

906

if (display->platform.broxton) {

sys/dev/pci/drm/i915/display/vlv_dsi.c

908

intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);

sys/dev/pci/drm/i915/display/vlv_dsi.c

909

intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL,

sys/dev/pci/drm/i915/display/vlv_dsi.c

91

struct intel_display *display = to_intel_display(&intel_dsi->base);

sys/dev/pci/drm/i915/display/vlv_dsi.c

913

intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0);

sys/dev/pci/drm/i915/display/vlv_dsi.c

916

if (display->platform.geminilake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/vlv_dsi.c

921

intel_de_rmw(display, VLV_DSPCLK_GATE_D,

sys/dev/pci/drm/i915/display/vlv_dsi.c

937

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi.c

943

drm_dbg_kms(display->drm, "\n");

sys/dev/pci/drm/i915/display/vlv_dsi.c

945

wakeref = intel_display_power_get_if_enabled(display,

sys/dev/pci/drm/i915/display/vlv_dsi.c

955

if ((display->platform.geminilake || display->platform.broxton) &&

sys/dev/pci/drm/i915/display/vlv_dsi.c

956

!bxt_dsi_pll_is_enabled(display))

sys/dev/pci/drm/i915/display/vlv_dsi.c

961

i915_reg_t port_ctrl = port_ctrl_reg(display, port);

sys/dev/pci/drm/i915/display/vlv_dsi.c

962

bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE;

sys/dev/pci/drm/i915/display/vlv_dsi.c

969

if ((display->platform.valleyview || display->platform.cherryview) &&

sys/dev/pci/drm/i915/display/vlv_dsi.c

97

if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi.c

971

enabled = intel_de_read(display,

sys/dev/pci/drm/i915/display/vlv_dsi.c

972

TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE;

sys/dev/pci/drm/i915/display/vlv_dsi.c

976

u32 tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/vlv_dsi.c

977

MIPI_DSI_FUNC_PRG(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi.c

984

if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY))

sys/dev/pci/drm/i915/display/vlv_dsi.c

987

if (display->platform.geminilake || display->platform.broxton) {

sys/dev/pci/drm/i915/display/vlv_dsi.c

988

u32 tmp = intel_de_read(display, MIPI_CTRL(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi.c

99

drm_err(display->drm, "DPI FIFOs are not empty\n");

sys/dev/pci/drm/i915/display/vlv_dsi.c

992

if (drm_WARN_ON(display->drm, tmp > PIPE_C))

sys/dev/pci/drm/i915/display/vlv_dsi.h

17

void vlv_dsi_init(struct intel_display *display);

sys/dev/pci/drm/i915/display/vlv_dsi.h

26

static inline void vlv_dsi_init(struct intel_display *display)

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

121

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

127

int refclk = display->platform.cherryview ? 100000 : 25000;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

150

drm_err(display->drm, "wrong P1 divisor\n");

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

160

drm_err(display->drm, "wrong m_seed programmed\n");

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

178

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

185

ret = dsi_calc_mnp(display, config, dsi_clk);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

187

drm_dbg_kms(display->drm, "dsi_calc_mnp failed\n");

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

199

drm_dbg_kms(display->drm, "dsi pll div %08x, ctrl %08x\n",

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

216

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

220

drm_dbg_kms(display->drm, "\n");

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

222

vlv_cck_get(display->drm);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

224

vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL, 0);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

225

vlv_cck_write(display->drm, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

226

vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL,

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

234

vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

236

ret = poll_timeout_us(val = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL),

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

240

vlv_cck_put(display->drm);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

241

drm_err(display->drm, "DSI PLL lock failed\n");

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

244

vlv_cck_put(display->drm);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

246

drm_dbg_kms(display->drm, "DSI PLL locked\n");

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

251

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

254

drm_dbg_kms(display->drm, "\n");

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

256

vlv_cck_get(display->drm);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

258

tmp = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

261

vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL, tmp);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

263

vlv_cck_put(display->drm);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

266

static bool has_dsic_clock(struct intel_display *display)

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

268

return display->platform.broxton;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

271

bool bxt_dsi_pll_is_enabled(struct intel_display *display)

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

278

val = intel_de_read(display, BXT_DSI_PLL_ENABLE);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

292

val = intel_de_read(display, BXT_DSI_PLL_CTL);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

293

if (!has_dsic_clock(display)) {

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

295

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

301

drm_dbg_kms(display->drm,

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

312

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

314

drm_dbg_kms(display->drm, "\n");

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

316

intel_de_rmw(display, BXT_DSI_PLL_ENABLE, BXT_DSI_PLL_DO_ENABLE, 0);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

322

if (intel_de_wait_for_clear(display, BXT_DSI_PLL_ENABLE,

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

324

drm_err(display->drm,

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

331

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

334

drm_dbg_kms(display->drm, "\n");

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

336

vlv_cck_get(display->drm);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

337

pll_ctl = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

338

pll_div = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_DIVIDER);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

339

vlv_cck_put(display->drm);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

363

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

366

config->dsi_pll.ctrl = intel_de_read(display, BXT_DSI_PLL_CTL);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

367

if (!has_dsic_clock(display))

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

372

drm_dbg_kms(display->drm, "Calculated pclk=%u\n", pclk);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

378

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

382

temp = intel_de_read(display, MIPI_CTRL(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

384

intel_de_write(display, MIPI_CTRL(display, port),

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

388

static void glk_dsi_program_esc_clock(struct intel_display *display,

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

427

intel_de_write(display, MIPIO_TXESC_CLK_DIV1,

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

429

intel_de_write(display, MIPIO_TXESC_CLK_DIV2,

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

434

static void bxt_dsi_program_clocks(struct intel_display *display, enum port port,

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

447

tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

483

intel_de_write(display, BXT_MIPI_CLOCK_CTL, tmp);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

489

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

505

if (display->platform.broxton) {

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

514

drm_err(display->drm,

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

518

drm_dbg_kms(display->drm, "DSI PLL calculation is Done!!\n");

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

526

if (has_dsic_clock(display))

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

532

if (display->platform.broxton && dsi_ratio <= 50)

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

549

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

553

drm_dbg_kms(display->drm, "\n");

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

556

intel_de_write(display, BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

557

intel_de_posting_read(display, BXT_DSI_PLL_CTL);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

560

if (display->platform.broxton) {

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

562

bxt_dsi_program_clocks(display, port, config);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

564

glk_dsi_program_esc_clock(display, config);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

568

intel_de_rmw(display, BXT_DSI_PLL_ENABLE, 0, BXT_DSI_PLL_DO_ENABLE);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

571

if (intel_de_wait_for_set(display, BXT_DSI_PLL_ENABLE,

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

573

drm_err(display->drm,

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

578

drm_dbg_kms(display->drm, "DSI PLL locked\n");

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

583

struct intel_display *display = to_intel_display(encoder);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

587

if (display->platform.broxton) {

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

588

tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

593

intel_de_write(display, BXT_MIPI_CLOCK_CTL, tmp);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

595

intel_de_rmw(display, MIPIO_TXESC_CLK_DIV1, GLK_TX_ESC_CLK_DIV1_MASK, 0);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

597

intel_de_rmw(display, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, 0);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

599

intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

602

static void assert_dsi_pll(struct intel_display *display, bool state)

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

606

vlv_cck_get(display->drm);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

607

cur_state = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL) & DSI_PLL_VCO_EN;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

608

vlv_cck_put(display->drm);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

610

INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

615

void assert_dsi_pll_enabled(struct intel_display *display)

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

617

assert_dsi_pll(display, true);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

62

static int dsi_calc_mnp(struct intel_display *display,

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

620

void assert_dsi_pll_disabled(struct intel_display *display)

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

622

assert_dsi_pll(display, false);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

73

drm_err(display->drm, "DSI CLK Out of Range\n");

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

77

if (display->platform.cherryview) {

sys/dev/pci/drm/i915/display/vlv_dsi_pll.h

35

bool bxt_dsi_pll_is_enabled(struct intel_display *display);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.h

36

void assert_dsi_pll_enabled(struct intel_display *display);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.h

37

void assert_dsi_pll_disabled(struct intel_display *display);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.h

39

static inline bool bxt_dsi_pll_is_enabled(struct intel_display *display)

sys/dev/pci/drm/i915/display/vlv_dsi_pll.h

43

static inline void assert_dsi_pll_enabled(struct intel_display *display)

sys/dev/pci/drm/i915/display/vlv_dsi_pll.h

47

static inline void assert_dsi_pll_disabled(struct intel_display *display)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

107

#define MIPI_INTR_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

110

#define MIPI_INTR_EN(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

14

#define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

146

#define MIPI_DSI_FUNC_PRG(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

169

#define MIPI_HS_TX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

174

#define MIPI_LP_RX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

179

#define MIPI_TURN_AROUND_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

184

#define MIPI_DEVICE_RESET_TIMER(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

189

#define MIPI_DPI_RESOLUTION(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

197

#define MIPI_DBI_FIFO_THROTTLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

205

#define MIPI_HSYNC_PADDING_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

209

#define MIPI_HBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

213

#define MIPI_HFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

217

#define MIPI_HACTIVE_AREA_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

221

#define MIPI_VSYNC_PADDING_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

225

#define MIPI_VBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

229

#define MIPI_VFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

233

#define MIPI_HIGH_LOW_SWITCH_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

237

#define MIPI_DPI_CONTROL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

248

#define MIPI_DPI_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

254

#define MIPI_INIT_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

260

#define MIPI_MAX_RETURN_PKT_SIZE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

266

#define MIPI_VIDEO_MODE_FORMAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

276

#define MIPI_EOT_DISABLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

290

#define MIPI_LP_BYTECLK(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

296

#define MIPI_TLPX_TIME_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

300

#define MIPI_CLK_LANE_TIMING(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

305

#define MIPI_LP_GEN_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

310

#define MIPI_HS_GEN_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

314

#define MIPI_LP_GEN_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

317

#define MIPI_HS_GEN_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

330

#define MIPI_GEN_FIFO_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

348

#define MIPI_HS_LP_DBI_ENABLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

355

#define MIPI_DPHY_PARAM(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

367

#define MIPI_DBI_BW_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

371

#define MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

379

#define MIPI_STOP_STATE_STALL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

385

#define MIPI_INTR_STAT_REG_1(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

388

#define MIPI_INTR_EN_REG_1(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

392

#define MIPIA_DBI_TYPEC_CTRL(display) (_MIPI_MMIO_BASE(display) + 0xb100)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

407

#define MIPI_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CTRL, _MIPIC_CTRL)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

440

#define MIPI_DATA_ADDRESS(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

447

#define MIPI_DATA_LENGTH(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

453

#define MIPI_COMMAND_ADDRESS(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

462

#define MIPI_COMMAND_LENGTH(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

468

#define MIPI_READ_DATA_RETURN(display, port, n) _MMIO_MIPI(_MIPI_MMIO_BASE(display) + 4 * (n), port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) /* n: 0...7 */

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

472

#define MIPI_READ_DATA_VALID(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

97

#define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)

sys/dev/pci/drm/i915/display/vlv_sideband.c

11

static enum vlv_iosf_sb_unit vlv_dpio_phy_to_unit(struct intel_display *display,

sys/dev/pci/drm/i915/display/vlv_sideband.c

18

if (display->platform.cherryview)

sys/dev/pci/drm/i915/display/vlv_sideband.c

26

struct intel_display *display = to_intel_display(drm);

sys/dev/pci/drm/i915/display/vlv_sideband.c

27

enum vlv_iosf_sb_unit unit = vlv_dpio_phy_to_unit(display, phy);

sys/dev/pci/drm/i915/display/vlv_sideband.c

36

drm_WARN(display->drm, val == 0xffffffff,

sys/dev/pci/drm/i915/display/vlv_sideband.c

46

struct intel_display *display = to_intel_display(drm);

sys/dev/pci/drm/i915/display/vlv_sideband.c

47

enum vlv_iosf_sb_unit unit = vlv_dpio_phy_to_unit(display, phy);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

113

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

125

return intel_display_device_present(display);

sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c

331

struct intel_display *display = ggtt->vm.i915->display;

sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c

357

if (intel_has_pending_fb_unpin(display))

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

106

gt->awake = intel_display_power_get(display, POWER_DOMAIN_GT_IRQ);

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

125

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

143

intel_display_power_put_async(display, POWER_DOMAIN_GT_IRQ, wakeref);

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

91

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/gt/intel_reset.c

1217

struct intel_display *display = gt->i915->display;

sys/dev/pci/drm/i915/gt/intel_reset.c

1263

intel_overlay_reset(display);

sys/dev/pci/drm/i915/gt/intel_reset.c

1437

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/gt/intel_reset.c

1444

reset_display = intel_display_reset_test(display) ||

sys/dev/pci/drm/i915/gt/intel_reset.c

1448

reset_display = intel_display_reset_prepare(display,

sys/dev/pci/drm/i915/gt/intel_reset.c

1455

intel_display_reset_finish(display, !need_display_reset);

sys/dev/pci/drm/i915/gt/intel_rps.c

562

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/gt/intel_rps.c

620

ilk_display_rps_enable(display);

sys/dev/pci/drm/i915/gt/intel_rps.c

632

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/gt/intel_rps.c

638

ilk_display_rps_disable(display);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1291

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1320

info->ctrl_reg = DSPCNTR(display, info->pipe);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1321

info->stride_reg = DSPSTRIDE(display, info->pipe);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1322

info->surf_reg = DSPSURF(display, info->pipe);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1338

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1387

info->ctrl_reg = DSPCNTR(display, info->pipe);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1388

info->stride_reg = DSPSTRIDE(display, info->pipe);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1389

info->surf_reg = DSPSURF(display, info->pipe);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1426

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1444

vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, info->pipe))++;

sys/dev/pci/drm/i915/gvt/display.c

188

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/gvt/display.c

201

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/gvt/display.c

202

vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) &=

sys/dev/pci/drm/i915/gvt/display.c

204

vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE;

sys/dev/pci/drm/i915/gvt/display.c

206

vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK;

sys/dev/pci/drm/i915/gvt/display.c

207

vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE;

sys/dev/pci/drm/i915/gvt/display.c

211

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, trans)) &=

sys/dev/pci/drm/i915/gvt/display.c

215

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=

sys/dev/pci/drm/i915/gvt/display.c

263

vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE;

sys/dev/pci/drm/i915/gvt/display.c

264

vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE;

sys/dev/pci/drm/i915/gvt/display.c

272

vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64);

sys/dev/pci/drm/i915/gvt/display.c

273

vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e;

sys/dev/pci/drm/i915/gvt/display.c

274

vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000;

sys/dev/pci/drm/i915/gvt/display.c

275

vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e;

sys/dev/pci/drm/i915/gvt/display.c

276

vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000;

sys/dev/pci/drm/i915/gvt/display.c

299

TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)) |=

sys/dev/pci/drm/i915/gvt/display.c

329

TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=

sys/dev/pci/drm/i915/gvt/display.c

360

TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=

sys/dev/pci/drm/i915/gvt/display.c

409

vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64);

sys/dev/pci/drm/i915/gvt/display.c

410

vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e;

sys/dev/pci/drm/i915/gvt/display.c

411

vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000;

sys/dev/pci/drm/i915/gvt/display.c

412

vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e;

sys/dev/pci/drm/i915/gvt/display.c

413

vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000;

sys/dev/pci/drm/i915/gvt/display.c

424

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=

sys/dev/pci/drm/i915/gvt/display.c

427

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=

sys/dev/pci/drm/i915/gvt/display.c

450

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=

sys/dev/pci/drm/i915/gvt/display.c

453

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=

sys/dev/pci/drm/i915/gvt/display.c

476

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=

sys/dev/pci/drm/i915/gvt/display.c

479

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=

sys/dev/pci/drm/i915/gvt/display.c

517

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/gvt/display.c

518

vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE;

sys/dev/pci/drm/i915/gvt/display.c

520

vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK;

sys/dev/pci/drm/i915/gvt/display.c

521

vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE;

sys/dev/pci/drm/i915/gvt/display.c

524

vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE;

sys/dev/pci/drm/i915/gvt/display.c

583

vgpu->display.port_num = port_num;

sys/dev/pci/drm/i915/gvt/display.c

609

intel_vgpu_port(vgpu, vgpu->display.port_num);

sys/dev/pci/drm/i915/gvt/display.c

639

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/gvt/display.c

661

vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(display, pipe))++;

sys/dev/pci/drm/i915/gvt/display.c

669

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/gvt/display.c

673

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/gvt/display.c

74

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/gvt/display.c

76

if (!(vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_EDP)) & TRANSCONF_ENABLE))

sys/dev/pci/drm/i915/gvt/display.c

87

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/gvt/display.c

93

if (vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) & TRANSCONF_ENABLE)

sys/dev/pci/drm/i915/gvt/display.h

48

(&(vgpu->display.ports[port]))

sys/dev/pci/drm/i915/gvt/edid.c

135

if (!vgpu->display.i2c_edid.edid_available)

sys/dev/pci/drm/i915/gvt/edid.c

137

vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;

sys/dev/pci/drm/i915/gvt/edid.c

165

vgpu->display.i2c_edid.state = I2C_GMBUS;

sys/dev/pci/drm/i915/gvt/edid.c

166

vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;

sys/dev/pci/drm/i915/gvt/edid.c

173

vgpu->display.i2c_edid.port = port;

sys/dev/pci/drm/i915/gvt/edid.c

174

vgpu->display.i2c_edid.edid_available = true;

sys/dev/pci/drm/i915/gvt/edid.c

184

struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;

sys/dev/pci/drm/i915/gvt/edid.c

296

struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;

sys/dev/pci/drm/i915/gvt/edid.c

485

struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;

sys/dev/pci/drm/i915/gvt/edid.c

57

struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;

sys/dev/pci/drm/i915/gvt/edid.c

572

struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

159

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

161

u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(display, pipe)) & stride_mask;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

216

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

224

val = vgpu_vreg_t(vgpu, DSPCNTR(display, pipe));

sys/dev/pci/drm/i915/gvt/fb_decoder.c

258

plane->base = vgpu_vreg_t(vgpu, DSPSURF(display, pipe)) & I915_GTT_PAGE_MASK;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

274

plane->width = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) & _PIPE_H_SRCSZ_MASK) >>

sys/dev/pci/drm/i915/gvt/fb_decoder.c

277

plane->height = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) &

sys/dev/pci/drm/i915/gvt/fb_decoder.c

281

val = vgpu_vreg_t(vgpu, DSPTILEOFF(display, pipe));

sys/dev/pci/drm/i915/gvt/fb_decoder.c

347

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

356

val = vgpu_vreg_t(vgpu, CURCNTR(display, pipe));

sys/dev/pci/drm/i915/gvt/fb_decoder.c

382

plane->base = vgpu_vreg_t(vgpu, CURBASE(display, pipe)) & I915_GTT_PAGE_MASK;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

393

val = vgpu_vreg_t(vgpu, CURPOS(display, pipe));

sys/dev/pci/drm/i915/gvt/gvt.h

206

struct intel_vgpu_display display;

sys/dev/pci/drm/i915/gvt/handlers.c

1021

#define DSPSURF_TO_PIPE(display, offset) \

sys/dev/pci/drm/i915/gvt/handlers.c

1022

calc_index(offset, DSPSURF(display, PIPE_A), DSPSURF(display, PIPE_B), DSPSURF(display, PIPE_C))

sys/dev/pci/drm/i915/gvt/handlers.c

1028

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/gvt/handlers.c

1029

u32 pipe = DSPSURF_TO_PIPE(display, offset);

sys/dev/pci/drm/i915/gvt/handlers.c

1033

vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);

sys/dev/pci/drm/i915/gvt/handlers.c

1035

vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++;

sys/dev/pci/drm/i915/gvt/handlers.c

1037

if (vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) & PLANE_CTL_ASYNC_FLIP)

sys/dev/pci/drm/i915/gvt/handlers.c

1070

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/gvt/handlers.c

1077

vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);

sys/dev/pci/drm/i915/gvt/handlers.c

1078

vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++;

sys/dev/pci/drm/i915/gvt/handlers.c

1184

struct intel_vgpu_display *display = &vgpu->display;

sys/dev/pci/drm/i915/gvt/handlers.c

1217

port = &display->ports[port_index];

sys/dev/pci/drm/i915/gvt/handlers.c

1377

struct intel_vgpu_display *display = &vgpu->display;

sys/dev/pci/drm/i915/gvt/handlers.c

1378

int num = display->sbi.number;

sys/dev/pci/drm/i915/gvt/handlers.c

1382

if (display->sbi.registers[i].offset == sbi_offset)

sys/dev/pci/drm/i915/gvt/handlers.c

1388

return display->sbi.registers[i].value;

sys/dev/pci/drm/i915/gvt/handlers.c

1394

struct intel_vgpu_display *display = &vgpu->display;

sys/dev/pci/drm/i915/gvt/handlers.c

1395

int num = display->sbi.number;

sys/dev/pci/drm/i915/gvt/handlers.c

1399

if (display->sbi.registers[i].offset == offset)

sys/dev/pci/drm/i915/gvt/handlers.c

1408

display->sbi.number++;

sys/dev/pci/drm/i915/gvt/handlers.c

1411

display->sbi.registers[i].offset = offset;

sys/dev/pci/drm/i915/gvt/handlers.c

1412

display->sbi.registers[i].value = value;

sys/dev/pci/drm/i915/gvt/handlers.c

2205

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/gvt/handlers.c

2294

MMIO_DH(TRANSCONF(display, TRANSCODER_A), D_ALL, NULL,

sys/dev/pci/drm/i915/gvt/handlers.c

2296

MMIO_DH(TRANSCONF(display, TRANSCODER_B), D_ALL, NULL,

sys/dev/pci/drm/i915/gvt/handlers.c

2298

MMIO_DH(TRANSCONF(display, TRANSCODER_C), D_ALL, NULL,

sys/dev/pci/drm/i915/gvt/handlers.c

2300

MMIO_DH(TRANSCONF(display, TRANSCODER_EDP), D_ALL, NULL,

sys/dev/pci/drm/i915/gvt/handlers.c

2302

MMIO_DH(DSPSURF(display, PIPE_A), D_ALL, NULL, pri_surf_mmio_write);

sys/dev/pci/drm/i915/gvt/handlers.c

2305

MMIO_DH(DSPSURF(display, PIPE_B), D_ALL, NULL, pri_surf_mmio_write);

sys/dev/pci/drm/i915/gvt/handlers.c

2308

MMIO_DH(DSPSURF(display, PIPE_C), D_ALL, NULL, pri_surf_mmio_write);

sys/dev/pci/drm/i915/gvt/handlers.c

664

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/gvt/handlers.c

669

port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &

sys/dev/pci/drm/i915/gvt/handlers.c

685

link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A));

sys/dev/pci/drm/i915/gvt/handlers.c

686

link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A));

sys/dev/pci/drm/i915/gvt/handlers.c

689

htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(display, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);

sys/dev/pci/drm/i915/gvt/handlers.c

690

vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(display, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);

sys/dev/pci/drm/i915/gvt/handlers.c

695

u32 *old_rate = &(intel_vgpu_port(vgpu, vgpu->display.port_num)->vrefresh_k);

sys/dev/pci/drm/i915/i915_driver.c

1001

intel_power_domains_disable(display);

sys/dev/pci/drm/i915/i915_driver.c

1004

if (intel_display_device_present(display)) {

sys/dev/pci/drm/i915/i915_driver.c

1006

intel_display_driver_disable_user_access(display);

sys/dev/pci/drm/i915/i915_driver.c

1011

intel_dp_mst_suspend(display);

sys/dev/pci/drm/i915/i915_driver.c

1014

intel_hpd_cancel_work(display);

sys/dev/pci/drm/i915/i915_driver.c

1016

if (intel_display_device_present(display))

sys/dev/pci/drm/i915/i915_driver.c

1017

intel_display_driver_suspend_access(display);

sys/dev/pci/drm/i915/i915_driver.c

1019

intel_encoder_suspend_all(display);

sys/dev/pci/drm/i915/i915_driver.c

1020

intel_encoder_shutdown_all(display);

sys/dev/pci/drm/i915/i915_driver.c

1022

intel_dmc_suspend(display);

sys/dev/pci/drm/i915/i915_driver.c

1037

intel_power_domains_driver_remove(display);

sys/dev/pci/drm/i915/i915_driver.c

1077

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_driver.c

1085

intel_power_domains_disable(display);

sys/dev/pci/drm/i915/i915_driver.c

1087

if (intel_display_device_present(display)) {

sys/dev/pci/drm/i915/i915_driver.c

1089

intel_display_driver_disable_user_access(display);

sys/dev/pci/drm/i915/i915_driver.c

1094

intel_display_driver_suspend(display);

sys/dev/pci/drm/i915/i915_driver.c

1097

intel_hpd_cancel_work(display);

sys/dev/pci/drm/i915/i915_driver.c

1099

if (intel_display_device_present(display))

sys/dev/pci/drm/i915/i915_driver.c

1100

intel_display_driver_suspend_access(display);

sys/dev/pci/drm/i915/i915_driver.c

1102

intel_encoder_suspend_all(display);

sys/dev/pci/drm/i915/i915_driver.c

1105

intel_dpt_suspend(display);

sys/dev/pci/drm/i915/i915_driver.c

1108

i9xx_display_sr_save(display);

sys/dev/pci/drm/i915/i915_driver.c

1111

intel_opregion_suspend(display, opregion_target_state);

sys/dev/pci/drm/i915/i915_driver.c

1115

intel_dmc_suspend(display);

sys/dev/pci/drm/i915/i915_driver.c

1127

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_driver.c

1143

intel_display_power_suspend_late(display, s2idle);

sys/dev/pci/drm/i915/i915_driver.c

1148

intel_display_power_resume_early(display);

sys/dev/pci/drm/i915/i915_driver.c

1201

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_driver.c

1224

intel_dpt_resume(display);

sys/dev/pci/drm/i915/i915_driver.c

1226

intel_dmc_resume(display);

sys/dev/pci/drm/i915/i915_driver.c

1228

i9xx_display_sr_restore(display);

sys/dev/pci/drm/i915/i915_driver.c

1230

intel_gmbus_reset(display);

sys/dev/pci/drm/i915/i915_driver.c

1232

intel_pps_unlock_regs_wa(display);

sys/dev/pci/drm/i915/i915_driver.c

1234

intel_init_pch_refclk(display);

sys/dev/pci/drm/i915/i915_driver.c

1248

if (intel_display_device_present(display))

sys/dev/pci/drm/i915/i915_driver.c

1253

intel_display_driver_init_hw(display);

sys/dev/pci/drm/i915/i915_driver.c

1257

if (intel_display_device_present(display))

sys/dev/pci/drm/i915/i915_driver.c

1258

intel_display_driver_resume_access(display);

sys/dev/pci/drm/i915/i915_driver.c

1260

intel_hpd_init(display);

sys/dev/pci/drm/i915/i915_driver.c

1262

intel_display_driver_resume(display);

sys/dev/pci/drm/i915/i915_driver.c

1264

if (intel_display_device_present(display)) {

sys/dev/pci/drm/i915/i915_driver.c

1265

intel_display_driver_enable_user_access(display);

sys/dev/pci/drm/i915/i915_driver.c

1268

intel_hpd_poll_disable(display);

sys/dev/pci/drm/i915/i915_driver.c

1270

intel_opregion_resume(display);

sys/dev/pci/drm/i915/i915_driver.c

1274

intel_power_domains_enable(display);

sys/dev/pci/drm/i915/i915_driver.c

1286

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_driver.c

1346

intel_display_power_resume_early(display);

sys/dev/pci/drm/i915/i915_driver.c

1520

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_driver.c

1550

intel_display_power_suspend(display);

sys/dev/pci/drm/i915/i915_driver.c

1595

intel_opregion_notify_adapter(display, PCI_D3hot);

sys/dev/pci/drm/i915/i915_driver.c

1604

intel_opregion_notify_adapter(display, PCI_D1);

sys/dev/pci/drm/i915/i915_driver.c

1610

intel_hpd_poll_enable(display);

sys/dev/pci/drm/i915/i915_driver.c

1619

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_driver.c

1634

intel_opregion_notify_adapter(display, PCI_D0);

sys/dev/pci/drm/i915/i915_driver.c

1644

intel_display_power_resume(display);

sys/dev/pci/drm/i915/i915_driver.c

1668

intel_hpd_init(display);

sys/dev/pci/drm/i915/i915_driver.c

1669

intel_hpd_poll_disable(display);

sys/dev/pci/drm/i915/i915_driver.c

1672

skl_watermark_ipc_update(display);

sys/dev/pci/drm/i915/i915_driver.c

222

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_driver.c

2248

struct intel_display *display;

sys/dev/pci/drm/i915/i915_driver.c

2317

display = intel_display_device_probe(dev->pdev);

sys/dev/pci/drm/i915/i915_driver.c

2318

if (IS_ERR(display)) {

sys/dev/pci/drm/i915/i915_driver.c

2323

dev_priv->display = display;

sys/dev/pci/drm/i915/i915_driver.c

236

intel_sbi_init(display);

sys/dev/pci/drm/i915/i915_driver.c

2531

if (dev_priv->display == NULL ||

sys/dev/pci/drm/i915/i915_driver.c

2532

dev_priv->display->wq.modeset == NULL)

sys/dev/pci/drm/i915/i915_driver.c

268

intel_display_driver_early_probe(display);

sys/dev/pci/drm/i915/i915_driver.c

291

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_driver.c

294

intel_power_domains_cleanup(display);

sys/dev/pci/drm/i915/i915_driver.c

303

intel_sbi_fini(display);

sys/dev/pci/drm/i915/i915_driver.c

307

intel_display_device_remove(display);

sys/dev/pci/drm/i915/i915_driver.c

321

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_driver.c

347

intel_display_device_info_runtime_init(display);

sys/dev/pci/drm/i915/i915_driver.c

468

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_driver.c

569

intel_opregion_setup(display);

sys/dev/pci/drm/i915/i915_driver.c

583

intel_bw_init_hw(display);

sys/dev/pci/drm/i915/i915_driver.c

588

intel_opregion_cleanup(display);

sys/dev/pci/drm/i915/i915_driver.c

609

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_driver.c

614

intel_opregion_cleanup(display);

sys/dev/pci/drm/i915/i915_driver.c

629

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_driver.c

663

intel_display_driver_register(display);

sys/dev/pci/drm/i915/i915_driver.c

665

intel_power_domains_enable(display);

sys/dev/pci/drm/i915/i915_driver.c

680

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_driver.c

687

intel_power_domains_disable(display);

sys/dev/pci/drm/i915/i915_driver.c

689

intel_display_driver_unregister(display);

sys/dev/pci/drm/i915/i915_driver.c

754

struct intel_display *display;

sys/dev/pci/drm/i915/i915_driver.c

769

display = intel_display_device_probe(pdev);

sys/dev/pci/drm/i915/i915_driver.c

770

if (IS_ERR(display))

sys/dev/pci/drm/i915/i915_driver.c

771

return ERR_CAST(display);

sys/dev/pci/drm/i915/i915_driver.c

773

i915->display = display;

sys/dev/pci/drm/i915/i915_driver.c

797

struct intel_display *display;

sys/dev/pci/drm/i915/i915_driver.c

812

struct intel_display *display;

sys/dev/pci/drm/i915/i915_driver.c

817

display = i915->display;

sys/dev/pci/drm/i915/i915_driver.c

839

ret = intel_display_driver_probe_noirq(display);

sys/dev/pci/drm/i915/i915_driver.c

847

ret = intel_display_driver_probe_nogem(display);

sys/dev/pci/drm/i915/i915_driver.c

859

ret = intel_display_driver_probe(display);

sys/dev/pci/drm/i915/i915_driver.c

886

intel_display_driver_remove(display);

sys/dev/pci/drm/i915/i915_driver.c

888

intel_display_driver_remove_noirq(display);

sys/dev/pci/drm/i915/i915_driver.c

893

intel_display_driver_remove_nogem(display);

sys/dev/pci/drm/i915/i915_driver.c

913

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/i915_driver.c

927

intel_display_driver_remove(display);

sys/dev/pci/drm/i915/i915_driver.c

931

intel_display_driver_remove_noirq(display);

sys/dev/pci/drm/i915/i915_driver.c

936

intel_display_driver_remove_nogem(display);

sys/dev/pci/drm/i915/i915_driver.c

997

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/i915_drv.h

203

struct intel_display *display;

sys/dev/pci/drm/i915/i915_getparam.c

19

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/i915_getparam.c

42

value = intel_overlay_available(display);

sys/dev/pci/drm/i915/i915_gpu_error.c

2231

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/i915_gpu_error.c

2273

error->display_snapshot = intel_display_snapshot_capture(display);

sys/dev/pci/drm/i915/i915_irq.c

1026

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_irq.c

1052

i965_display_irq_postinstall(display);

sys/dev/pci/drm/i915/i915_irq.c

1058

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_irq.c

1080

hotplug_status = i9xx_hpd_irq_ack(display);

sys/dev/pci/drm/i915/i915_irq.c

1084

i9xx_pipestat_irq_ack(display, iir, pipe_stats);

sys/dev/pci/drm/i915/i915_irq.c

1103

i9xx_hpd_irq_handler(display, hotplug_status);

sys/dev/pci/drm/i915/i915_irq.c

1105

i965_pipestat_irq_handler(display, iir, pipe_stats);

sys/dev/pci/drm/i915/i915_irq.c

1258

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_irq.c

1271

intel_hpd_cancel_work(display);

sys/dev/pci/drm/i915/i915_irq.c

228

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_irq.c

275

hotplug_status = i9xx_hpd_irq_ack(display);

sys/dev/pci/drm/i915/i915_irq.c

278

vlv_display_error_irq_ack(display, &eir, &dpinvgtt);

sys/dev/pci/drm/i915/i915_irq.c

282

i9xx_pipestat_irq_ack(display, iir, pipe_stats);

sys/dev/pci/drm/i915/i915_irq.c

286

intel_lpe_audio_irq_handler(display);

sys/dev/pci/drm/i915/i915_irq.c

304

i9xx_hpd_irq_handler(display, hotplug_status);

sys/dev/pci/drm/i915/i915_irq.c

307

vlv_display_error_irq_handler(display, eir, dpinvgtt);

sys/dev/pci/drm/i915/i915_irq.c

309

valleyview_pipestat_irq_handler(display, pipe_stats);

sys/dev/pci/drm/i915/i915_irq.c

322

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_irq.c

365

hotplug_status = i9xx_hpd_irq_ack(display);

sys/dev/pci/drm/i915/i915_irq.c

368

vlv_display_error_irq_ack(display, &eir, &dpinvgtt);

sys/dev/pci/drm/i915/i915_irq.c

372

i9xx_pipestat_irq_ack(display, iir, pipe_stats);

sys/dev/pci/drm/i915/i915_irq.c

377

intel_lpe_audio_irq_handler(display);

sys/dev/pci/drm/i915/i915_irq.c

390

i9xx_hpd_irq_handler(display, hotplug_status);

sys/dev/pci/drm/i915/i915_irq.c

393

vlv_display_error_irq_handler(display, eir, dpinvgtt);

sys/dev/pci/drm/i915/i915_irq.c

395

valleyview_pipestat_irq_handler(display, pipe_stats);

sys/dev/pci/drm/i915/i915_irq.c

416

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/i915_irq.c

436

if (!HAS_PCH_NOP(display)) {

sys/dev/pci/drm/i915/i915_irq.c

456

if (DISPLAY_VER(display) >= 7)

sys/dev/pci/drm/i915/i915_irq.c

457

ivb_display_irq_handler(display, de_iir);

sys/dev/pci/drm/i915/i915_irq.c

459

ilk_display_irq_handler(display, de_iir);

sys/dev/pci/drm/i915/i915_irq.c

505

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_irq.c

524

gen8_de_irq_handler(display, master_ctl);

sys/dev/pci/drm/i915/i915_irq.c

556

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/i915_irq.c

576

gen11_display_irq_handler(display);

sys/dev/pci/drm/i915/i915_irq.c

578

gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);

sys/dev/pci/drm/i915/i915_irq.c

582

gen11_gu_misc_irq_handler(display, gu_misc_iir);

sys/dev/pci/drm/i915/i915_irq.c

614

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/i915_irq.c

643

gen11_display_irq_handler(display);

sys/dev/pci/drm/i915/i915_irq.c

645

gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);

sys/dev/pci/drm/i915/i915_irq.c

649

gen11_gu_misc_irq_handler(display, gu_misc_iir);

sys/dev/pci/drm/i915/i915_irq.c

658

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_irq.c

674

ibx_display_irq_reset(display);

sys/dev/pci/drm/i915/i915_irq.c

679

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_irq.c

686

vlv_display_irq_reset(display);

sys/dev/pci/drm/i915/i915_irq.c

691

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_irq.c

697

gen8_display_irq_reset(display);

sys/dev/pci/drm/i915/i915_irq.c

703

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_irq.c

710

gen11_display_irq_reset(display);

sys/dev/pci/drm/i915/i915_irq.c

718

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_irq.c

728

gen11_display_irq_reset(display);

sys/dev/pci/drm/i915/i915_irq.c

738

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_irq.c

748

vlv_display_irq_reset(display);

sys/dev/pci/drm/i915/i915_irq.c

753

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_irq.c

757

ilk_de_irq_postinstall(display);

sys/dev/pci/drm/i915/i915_irq.c

762

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_irq.c

766

vlv_display_irq_postinstall(display);

sys/dev/pci/drm/i915/i915_irq.c

774

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_irq.c

777

gen8_de_irq_postinstall(display);

sys/dev/pci/drm/i915/i915_irq.c

784

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_irq.c

790

gen11_de_irq_postinstall(display);

sys/dev/pci/drm/i915/i915_irq.c

800

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_irq.c

811

dg1_de_irq_postinstall(display);

sys/dev/pci/drm/i915/i915_irq.c

819

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_irq.c

823

vlv_display_irq_postinstall(display);

sys/dev/pci/drm/i915/i915_irq.c

831

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/i915_irq.c

844

if (HAS_FBC(display))

sys/dev/pci/drm/i915/i915_irq.c

893

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_irq.c

896

i9xx_display_irq_reset(display);

sys/dev/pci/drm/i915/i915_irq.c

905

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_irq.c

922

if (DISPLAY_VER(display) >= 3) {

sys/dev/pci/drm/i915/i915_irq.c

927

if (HAS_HOTPLUG(display)) {

sys/dev/pci/drm/i915/i915_irq.c

934

i915_display_irq_postinstall(display);

sys/dev/pci/drm/i915/i915_irq.c

940

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_irq.c

961

if (HAS_HOTPLUG(display) &&

sys/dev/pci/drm/i915/i915_irq.c

963

hotplug_status = i9xx_hpd_irq_ack(display);

sys/dev/pci/drm/i915/i915_irq.c

967

i9xx_pipestat_irq_ack(display, iir, pipe_stats);

sys/dev/pci/drm/i915/i915_irq.c

981

i9xx_hpd_irq_handler(display, hotplug_status);

sys/dev/pci/drm/i915/i915_irq.c

983

i915_pipestat_irq_handler(display, iir, pipe_stats);

sys/dev/pci/drm/i915/i915_irq.c

995

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/i915_irq.c

998

i9xx_display_irq_reset(display);

sys/dev/pci/drm/i915/i915_switcheroo.c

20

struct intel_display *display = i915 ? i915->display : NULL;

sys/dev/pci/drm/i915/i915_switcheroo.c

27

if (!intel_display_device_present(display)) {

sys/dev/pci/drm/i915/i915_switcheroo.c

50

struct intel_display *display = i915 ? i915->display : NULL;

sys/dev/pci/drm/i915/i915_switcheroo.c

57

return i915 && intel_display_device_present(display) &&

sys/dev/pci/drm/i915/intel_clock_gating.c

135

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/intel_clock_gating.c

138

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/intel_clock_gating.c

139

intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(display, pipe),

sys/dev/pci/drm/i915/intel_clock_gating.c

142

intel_uncore_rmw(&dev_priv->uncore, DSPSURF(display, pipe),

sys/dev/pci/drm/i915/intel_clock_gating.c

145

DSPSURF(display, pipe));

sys/dev/pci/drm/i915/intel_clock_gating.c

206

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/intel_clock_gating.c

222

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/intel_clock_gating.c

226

if (display->vbt.fdi_rx_polarity_inverted)

sys/dev/pci/drm/i915/intel_clock_gating.c

233

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/intel_clock_gating.c

311

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/intel_clock_gating.c

317

if (HAS_PCH_LPT_LP(display))

sys/dev/pci/drm/i915/intel_clock_gating.c

361

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/intel_clock_gating.c

363

if (!HAS_PCH_CNP(display))

sys/dev/pci/drm/i915/intel_clock_gating.c

429

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/intel_clock_gating.c

441

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/intel_clock_gating.c

477

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/intel_clock_gating.c

486

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/intel_clock_gating.c

504

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/intel_clock_gating.c

543

if (!HAS_PCH_NOP(display))

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1115

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1247

MMIO_D(HSW_TVIDEO_DIP_GCP(display, TRANSCODER_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1248

MMIO_D(HSW_TVIDEO_DIP_GCP(display, TRANSCODER_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1249

MMIO_D(HSW_TVIDEO_DIP_GCP(display, TRANSCODER_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

137

MMIO_D(PIPEDSL(display, PIPE_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

138

MMIO_D(PIPEDSL(display, PIPE_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

139

MMIO_D(PIPEDSL(display, PIPE_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

140

MMIO_D(PIPEDSL(display, _PIPE_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

141

MMIO_D(TRANSCONF(display, TRANSCODER_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

142

MMIO_D(TRANSCONF(display, TRANSCODER_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

143

MMIO_D(TRANSCONF(display, TRANSCODER_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

144

MMIO_D(TRANSCONF(display, TRANSCODER_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

145

MMIO_D(PIPESTAT(display, PIPE_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

146

MMIO_D(PIPESTAT(display, PIPE_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

147

MMIO_D(PIPESTAT(display, PIPE_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

148

MMIO_D(PIPESTAT(display, _PIPE_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

149

MMIO_D(PIPE_FLIPCOUNT_G4X(display, PIPE_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

150

MMIO_D(PIPE_FLIPCOUNT_G4X(display, PIPE_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

151

MMIO_D(PIPE_FLIPCOUNT_G4X(display, PIPE_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

152

MMIO_D(PIPE_FLIPCOUNT_G4X(display, _PIPE_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

153

MMIO_D(PIPE_FRMCOUNT_G4X(display, PIPE_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

154

MMIO_D(PIPE_FRMCOUNT_G4X(display, PIPE_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

155

MMIO_D(PIPE_FRMCOUNT_G4X(display, PIPE_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

156

MMIO_D(PIPE_FRMCOUNT_G4X(display, _PIPE_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

157

MMIO_D(CURCNTR(display, PIPE_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

158

MMIO_D(CURCNTR(display, PIPE_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

159

MMIO_D(CURCNTR(display, PIPE_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

160

MMIO_D(CURPOS(display, PIPE_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

161

MMIO_D(CURPOS(display, PIPE_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

162

MMIO_D(CURPOS(display, PIPE_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

163

MMIO_D(CURBASE(display, PIPE_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

164

MMIO_D(CURBASE(display, PIPE_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

165

MMIO_D(CURBASE(display, PIPE_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

166

MMIO_D(CUR_FBC_CTL(display, PIPE_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

167

MMIO_D(CUR_FBC_CTL(display, PIPE_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

168

MMIO_D(CUR_FBC_CTL(display, PIPE_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

176

MMIO_D(DSPCNTR(display, PIPE_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

177

MMIO_D(DSPADDR(display, PIPE_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

178

MMIO_D(DSPSTRIDE(display, PIPE_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

179

MMIO_D(DSPPOS(display, PIPE_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

180

MMIO_D(DSPSIZE(display, PIPE_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

181

MMIO_D(DSPSURF(display, PIPE_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

182

MMIO_D(DSPOFFSET(display, PIPE_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

183

MMIO_D(DSPSURFLIVE(display, PIPE_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

185

MMIO_D(DSPCNTR(display, PIPE_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

186

MMIO_D(DSPADDR(display, PIPE_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

187

MMIO_D(DSPSTRIDE(display, PIPE_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

188

MMIO_D(DSPPOS(display, PIPE_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

189

MMIO_D(DSPSIZE(display, PIPE_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

190

MMIO_D(DSPSURF(display, PIPE_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

191

MMIO_D(DSPOFFSET(display, PIPE_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

192

MMIO_D(DSPSURFLIVE(display, PIPE_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

194

MMIO_D(DSPCNTR(display, PIPE_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

195

MMIO_D(DSPADDR(display, PIPE_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

196

MMIO_D(DSPSTRIDE(display, PIPE_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

197

MMIO_D(DSPPOS(display, PIPE_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

198

MMIO_D(DSPSIZE(display, PIPE_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

199

MMIO_D(DSPSURF(display, PIPE_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

200

MMIO_D(DSPOFFSET(display, PIPE_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

201

MMIO_D(DSPSURFLIVE(display, PIPE_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

242

MMIO_D(TRANS_HTOTAL(display, TRANSCODER_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

243

MMIO_D(TRANS_HBLANK(display, TRANSCODER_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

244

MMIO_D(TRANS_HSYNC(display, TRANSCODER_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

245

MMIO_D(TRANS_VTOTAL(display, TRANSCODER_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

246

MMIO_D(TRANS_VBLANK(display, TRANSCODER_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

247

MMIO_D(TRANS_VSYNC(display, TRANSCODER_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

248

MMIO_D(BCLRPAT(display, TRANSCODER_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

249

MMIO_D(TRANS_VSYNCSHIFT(display, TRANSCODER_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

250

MMIO_D(PIPESRC(display, TRANSCODER_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

251

MMIO_D(TRANS_HTOTAL(display, TRANSCODER_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

252

MMIO_D(TRANS_HBLANK(display, TRANSCODER_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

253

MMIO_D(TRANS_HSYNC(display, TRANSCODER_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

254

MMIO_D(TRANS_VTOTAL(display, TRANSCODER_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

255

MMIO_D(TRANS_VBLANK(display, TRANSCODER_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

256

MMIO_D(TRANS_VSYNC(display, TRANSCODER_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

257

MMIO_D(BCLRPAT(display, TRANSCODER_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

258

MMIO_D(TRANS_VSYNCSHIFT(display, TRANSCODER_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

259

MMIO_D(PIPESRC(display, TRANSCODER_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

260

MMIO_D(TRANS_HTOTAL(display, TRANSCODER_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

261

MMIO_D(TRANS_HBLANK(display, TRANSCODER_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

262

MMIO_D(TRANS_HSYNC(display, TRANSCODER_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

263

MMIO_D(TRANS_VTOTAL(display, TRANSCODER_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

264

MMIO_D(TRANS_VBLANK(display, TRANSCODER_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

265

MMIO_D(TRANS_VSYNC(display, TRANSCODER_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

266

MMIO_D(BCLRPAT(display, TRANSCODER_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

267

MMIO_D(TRANS_VSYNCSHIFT(display, TRANSCODER_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

268

MMIO_D(PIPESRC(display, TRANSCODER_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

269

MMIO_D(TRANS_HTOTAL(display, TRANSCODER_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

270

MMIO_D(TRANS_HBLANK(display, TRANSCODER_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

271

MMIO_D(TRANS_HSYNC(display, TRANSCODER_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

272

MMIO_D(TRANS_VTOTAL(display, TRANSCODER_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

273

MMIO_D(TRANS_VBLANK(display, TRANSCODER_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

274

MMIO_D(TRANS_VSYNC(display, TRANSCODER_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

275

MMIO_D(BCLRPAT(display, TRANSCODER_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

276

MMIO_D(TRANS_VSYNCSHIFT(display, TRANSCODER_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

277

MMIO_D(PIPE_DATA_M1(display, TRANSCODER_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

278

MMIO_D(PIPE_DATA_N1(display, TRANSCODER_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

279

MMIO_D(PIPE_DATA_M2(display, TRANSCODER_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

280

MMIO_D(PIPE_DATA_N2(display, TRANSCODER_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

281

MMIO_D(PIPE_LINK_M1(display, TRANSCODER_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

282

MMIO_D(PIPE_LINK_N1(display, TRANSCODER_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

283

MMIO_D(PIPE_LINK_M2(display, TRANSCODER_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

284

MMIO_D(PIPE_LINK_N2(display, TRANSCODER_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

285

MMIO_D(PIPE_DATA_M1(display, TRANSCODER_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

286

MMIO_D(PIPE_DATA_N1(display, TRANSCODER_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

287

MMIO_D(PIPE_DATA_M2(display, TRANSCODER_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

288

MMIO_D(PIPE_DATA_N2(display, TRANSCODER_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

289

MMIO_D(PIPE_LINK_M1(display, TRANSCODER_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

290

MMIO_D(PIPE_LINK_N1(display, TRANSCODER_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

291

MMIO_D(PIPE_LINK_M2(display, TRANSCODER_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

292

MMIO_D(PIPE_LINK_N2(display, TRANSCODER_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

293

MMIO_D(PIPE_DATA_M1(display, TRANSCODER_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

294

MMIO_D(PIPE_DATA_N1(display, TRANSCODER_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

295

MMIO_D(PIPE_DATA_M2(display, TRANSCODER_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

296

MMIO_D(PIPE_DATA_N2(display, TRANSCODER_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

297

MMIO_D(PIPE_LINK_M1(display, TRANSCODER_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

298

MMIO_D(PIPE_LINK_N1(display, TRANSCODER_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

299

MMIO_D(PIPE_LINK_M2(display, TRANSCODER_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

300

MMIO_D(PIPE_LINK_N2(display, TRANSCODER_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

301

MMIO_D(PIPE_DATA_M1(display, TRANSCODER_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

302

MMIO_D(PIPE_DATA_N1(display, TRANSCODER_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

303

MMIO_D(PIPE_DATA_M2(display, TRANSCODER_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

304

MMIO_D(PIPE_DATA_N2(display, TRANSCODER_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

305

MMIO_D(PIPE_LINK_M1(display, TRANSCODER_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

306

MMIO_D(PIPE_LINK_N1(display, TRANSCODER_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

307

MMIO_D(PIPE_LINK_M2(display, TRANSCODER_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

308

MMIO_D(PIPE_LINK_N2(display, TRANSCODER_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

517

MMIO_D(TRANS_MULT(display, TRANSCODER_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

518

MMIO_D(TRANS_MULT(display, TRANSCODER_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

519

MMIO_D(TRANS_MULT(display, TRANSCODER_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

520

MMIO_D(HSW_TVIDEO_DIP_CTL(display, TRANSCODER_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

521

MMIO_D(HSW_TVIDEO_DIP_CTL(display, TRANSCODER_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

522

MMIO_D(HSW_TVIDEO_DIP_CTL(display, TRANSCODER_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

65

struct intel_display *display = dev_priv->display;

sys/dev/pci/drm/i915/intel_uncore.c

2546

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/intel_uncore.c

2581

if (HAS_FPGA_DBG_UNCLAIMED(display))

sys/dev/pci/drm/i915/selftests/intel_uncore.c

281

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/selftests/intel_uncore.c

286

if (!HAS_FPGA_DBG_UNCLAIMED(display) &&

sys/dev/pci/drm/i915/selftests/mock_gem_device.c

146

struct intel_display *display;

sys/dev/pci/drm/i915/selftests/mock_gem_device.c

186

display = intel_display_device_probe(pdev);

sys/dev/pci/drm/i915/selftests/mock_gem_device.c

187

if (IS_ERR(display))

sys/dev/pci/drm/i915/selftests/mock_gem_device.c

190

i915->display = display;

sys/dev/pci/drm/i915/selftests/mock_gem_device.c

277

intel_display_device_remove(i915->display);

sys/dev/pci/drm/i915/soc/intel_dram.c

731

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/soc/intel_dram.c

735

if (IS_DG2(i915) || !intel_display_device_present(display))

sys/dev/pci/drm/i915/soc/intel_dram.c

744

if (DISPLAY_VER(display) >= 14)

sys/dev/pci/drm/i915/soc/intel_gmch.c

184

struct intel_display *display = i915->display;

sys/dev/pci/drm/i915/soc/intel_gmch.c

185

unsigned int reg = DISPLAY_VER(display) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;

sys/dev/pci/drm/include/drm/drm_modes.h

464

bool drm_mode_is_420_only(const struct drm_display_info *display,

sys/dev/pci/drm/include/drm/drm_modes.h

466

bool drm_mode_is_420_also(const struct drm_display_info *display,

sys/dev/pci/drm/include/drm/drm_modes.h

468

bool drm_mode_is_420(const struct drm_display_info *display,

sys/dev/pci/drm/radeon/atombios_encoders.c

2537

if (rdev->asic->display.hdmi_enable)

sys/dev/pci/drm/radeon/radeon.h

1913

} display;

sys/dev/pci/drm/radeon/radeon.h

2765

#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))

sys/dev/pci/drm/radeon/radeon.h

2766

#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))

sys/dev/pci/drm/radeon/radeon.h

2767

#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))

sys/dev/pci/drm/radeon/radeon.h

2768

#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))

sys/dev/pci/drm/radeon/radeon.h

2769

#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))

sys/dev/pci/drm/radeon/radeon.h

2790

#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))

sys/dev/pci/drm/radeon/radeon.h

2803

#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))

sys/dev/pci/drm/radeon/radeon_asic.c

1043

.display = {

sys/dev/pci/drm/radeon/radeon_asic.c

1136

.display = {

sys/dev/pci/drm/radeon/radeon_asic.c

1242

.display = {

sys/dev/pci/drm/radeon/radeon_asic.c

1362

.display = {

sys/dev/pci/drm/radeon/radeon_asic.c

1456

.display = {

sys/dev/pci/drm/radeon/radeon_asic.c

1550

.display = {

sys/dev/pci/drm/radeon/radeon_asic.c

1698

.display = {

sys/dev/pci/drm/radeon/radeon_asic.c

1818

.display = {

sys/dev/pci/drm/radeon/radeon_asic.c

1956

.display = {

sys/dev/pci/drm/radeon/radeon_asic.c

2126

.display = {

sys/dev/pci/drm/radeon/radeon_asic.c

220

.display = {

sys/dev/pci/drm/radeon/radeon_asic.c

2239

.display = {

sys/dev/pci/drm/radeon/radeon_asic.c

2364

rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;

sys/dev/pci/drm/radeon/radeon_asic.c

288

.display = {

sys/dev/pci/drm/radeon/radeon_asic.c

384

.display = {

sys/dev/pci/drm/radeon/radeon_asic.c

452

.display = {

sys/dev/pci/drm/radeon/radeon_asic.c

520

.display = {

sys/dev/pci/drm/radeon/radeon_asic.c

588

.display = {

sys/dev/pci/drm/radeon/radeon_asic.c

656

.display = {

sys/dev/pci/drm/radeon/radeon_asic.c

724

.display = {

sys/dev/pci/drm/radeon/radeon_asic.c

792

.display = {

sys/dev/pci/drm/radeon/radeon_asic.c

860

.display = {

sys/dev/pci/drm/radeon/radeon_asic.c

957

.display = {

sys/dev/sbus/vigra.c

124

u_int32_t display;

sys/dev/sbus/vigra.c

95

u_int32_t display;

usr.bin/cal/cal.c

479

int display, val;

usr.bin/cal/cal.c

498

display = 1;

usr.bin/cal/cal.c

501

display = 0;

usr.bin/cal/cal.c

504

if (val || display)

usr.bin/chpass/chpass.c

136

display(tempname, dfd, pw);

usr.bin/chpass/chpass.h

60

void display(char *, int, struct passwd *);

usr.bin/hexdump/hexdump.c

79

display();

usr.bin/hexdump/hexdump.h

89

void display(void);

usr.bin/ipcs/ipcs.c

149

int display = SHMINFO | MSGINFO | SEMINFO;

usr.bin/ipcs/ipcs.c

160

display = SHMTOTAL;

usr.bin/ipcs/ipcs.c

163

display = SHMINFO;

usr.bin/ipcs/ipcs.c

166

display = MSGTOTAL;

usr.bin/ipcs/ipcs.c

169

display = MSGINFO;

usr.bin/ipcs/ipcs.c

172

display = SEMTOTAL;

usr.bin/ipcs/ipcs.c

175

display = SEMINFO;

usr.bin/ipcs/ipcs.c

178

display = SHMTOTAL | MSGTOTAL | SEMTOTAL;

usr.bin/ipcs/ipcs.c

212

if (display & (MSGINFO | MSGTOTAL))

usr.bin/ipcs/ipcs.c

214

if (display & (SHMINFO | SHMTOTAL))

usr.bin/ipcs/ipcs.c

216

if (display & (SEMINFO | SEMTOTAL))

usr.bin/ipcs/ipcs.c

464

if (!(display & MSGINFO)) {

usr.bin/ipcs/ipcs.c

482

if (display & MSGTOTAL)

usr.bin/ipcs/ipcs.c

485

if (display & MSGINFO) {

usr.bin/ipcs/ipcs.c

536

if (!(display & SHMINFO)) {

usr.bin/ipcs/ipcs.c

554

if (display & SHMTOTAL)

usr.bin/ipcs/ipcs.c

557

if (display & SHMINFO) {

usr.bin/ipcs/ipcs.c

607

if (!(display & SEMINFO)) {

usr.bin/ipcs/ipcs.c

625

if (display & SEMTOTAL)

usr.bin/ipcs/ipcs.c

628

if (display & SEMINFO) {

usr.bin/ipcs/ipcs.c

702

if ((display & (MSGINFO | MSGTOTAL)) &&

usr.bin/ipcs/ipcs.c

706

if (display & MSGTOTAL)

usr.bin/ipcs/ipcs.c

709

if (display & MSGINFO) {

usr.bin/ipcs/ipcs.c

754

if (display & (MSGINFO | MSGTOTAL)) {

usr.bin/ipcs/ipcs.c

759

if ((display & (SHMINFO | SHMTOTAL)) &&

usr.bin/ipcs/ipcs.c

763

if (display & SHMTOTAL)

usr.bin/ipcs/ipcs.c

766

if (display & SHMINFO) {

usr.bin/ipcs/ipcs.c

810

if (display & (SHMINFO | SHMTOTAL)) {

usr.bin/ipcs/ipcs.c

814

if ((display & (SEMINFO | SEMTOTAL)) &&

usr.bin/ipcs/ipcs.c

817

if (display & SEMTOTAL)

usr.bin/ipcs/ipcs.c

820

if (display & SEMINFO) {

usr.bin/ipcs/ipcs.c

860

if (display & (SEMINFO | SEMTOTAL)) {

usr.bin/nfsstat/nfsstat.c

104

display = SHOW_SERVER;

usr.bin/nfsstat/nfsstat.c

107

display = SHOW_CLIENT;

usr.bin/nfsstat/nfsstat.c

160

sidewaysintpr(interval, display);

usr.bin/nfsstat/nfsstat.c

162

intpr(display);

usr.bin/nfsstat/nfsstat.c

190

intpr(u_int display)

usr.bin/nfsstat/nfsstat.c

196

if (display & SHOW_CLIENT) {

usr.bin/nfsstat/nfsstat.c

266

if (display == SHOW_ALL)

usr.bin/nfsstat/nfsstat.c

269

if (display & SHOW_SERVER) {

usr.bin/nfsstat/nfsstat.c

332

sidewaysintpr(u_int interval, u_int display)

usr.bin/nfsstat/nfsstat.c

351

if (display & SHOW_CLIENT)

usr.bin/nfsstat/nfsstat.c

372

if (display & SHOW_SERVER)

usr.bin/nfsstat/nfsstat.c

80

u_int interval, display = SHOW_ALL;

usr.bin/sndioctl/sndioctl.c

314

if (strcmp(e1->desc.display,

usr.bin/sndioctl/sndioctl.c

315

e2->desc.display) != 0)

usr.bin/sndioctl/sndioctl.c

346

s = p->desc.display;

usr.bin/sndioctl/sndioctl.c

389

if (e->desc.display[0] != 0)

usr.bin/sndiod/dev.c

1921

if (c->display[0] != 0)

usr.bin/sndiod/dev.c

1922

p += snprintf(p, size, " (%s)", c->display);

usr.bin/sndiod/dev.c

1976

int type, char *display, char *gstr,

usr.bin/sndiod/dev.c

2003

strlcpy(c->display, display, CTL_DISPLAYMAX);

usr.bin/sndiod/dev.c

2155

char *display;

usr.bin/sndiod/dev.c

2157

display = "";

usr.bin/sndiod/dev.c

2166

display = c->display;

usr.bin/sndiod/dev.c

2168

return display;

usr.bin/sndiod/dev.c

2176

const char *display;

usr.bin/sndiod/dev.c

2205

display = dev_getdisplay(d);

usr.bin/sndiod/dev.c

2209

strcmp(c->display, display) == 0)

usr.bin/sndiod/dev.c

2211

strlcpy(c->display, display, CTL_DISPLAYMAX);

usr.bin/sndiod/dev.h

155

char display[CTL_DISPLAYMAX]; /* free-format hint */

usr.bin/sndiod/dev_sioctl.c

73

desc->type, desc->display, group,

usr.bin/sndiod/sock.c

1332

display) + AMSG_CTL_DISPLAYMAX) {

usr.bin/sndiod/sock.c

1333

strlcpy(desc->display, c->display, AMSG_CTL_DISPLAYMAX);

usr.bin/ssh/channels.c

5147

const char *display;

usr.bin/ssh/channels.c

5154

display = getenv("DISPLAY");

usr.bin/ssh/channels.c

5155

if (!display) {

usr.bin/ssh/channels.c

5168

if (strncmp(display, "unix:", 5) == 0 ||

usr.bin/ssh/channels.c

5169

display[0] == ':') {

usr.bin/ssh/channels.c

5171

if (sscanf(strrchr(display, ':') + 1, "%u",

usr.bin/ssh/channels.c

5174

"%.100s", display);

usr.bin/ssh/channels.c

5189

strlcpy(buf, display, sizeof(buf));

usr.bin/ssh/channels.c

5192

error("Could not find ':' in DISPLAY: %.100s", display);

usr.bin/ssh/channels.c

5203

display);

usr.bin/ssh/clientloop.c

261

client_x11_display_valid(const char *display)

usr.bin/ssh/clientloop.c

265

if (display == NULL)

usr.bin/ssh/clientloop.c

268

dlen = strlen(display);

usr.bin/ssh/clientloop.c

270

if (!isalnum((u_char)display[i]) &&

usr.bin/ssh/clientloop.c

271

strchr(SSH_X11_VALID_DISPLAY_CHARS, display[i]) == NULL) {

usr.bin/ssh/clientloop.c

272

debug("Invalid character '%c' in DISPLAY", display[i]);

usr.bin/ssh/clientloop.c

282

client_x11_get_proto(struct ssh *ssh, const char *display,

usr.bin/ssh/clientloop.c

298

if (!client_x11_display_valid(display)) {

usr.bin/ssh/clientloop.c

299

if (display != NULL)

usr.bin/ssh/clientloop.c

301

display);

usr.bin/ssh/clientloop.c

317

if (strncmp(display, "localhost:", 10) == 0) {

usr.bin/ssh/clientloop.c

319

display + 10)) < 0 ||

usr.bin/ssh/clientloop.c

324

display = xdisplay;

usr.bin/ssh/clientloop.c

352

xauth_path, xauthfile, display,

usr.bin/ssh/clientloop.c

365

xauth_path, xauthfile, display,

usr.bin/ssh/clientloop.c

396

display);

usr.bin/ssh/mux.c

1405

const char *display;

usr.bin/ssh/mux.c

1427

display = getenv("DISPLAY");

usr.bin/ssh/mux.c

1428

if (cctx->want_x_fwd && options.forward_x11 && display != NULL) {

usr.bin/ssh/mux.c

1432

if (client_x11_get_proto(ssh, display, options.xauth_location,

usr.bin/ssh/mux.c

1439

display, proto, data, 1);

usr.bin/ssh/session.c

2003

free(s->display);

usr.bin/ssh/session.c

2004

s->display = NULL;

usr.bin/ssh/session.c

2083

free(s->display);

usr.bin/ssh/session.c

2204

char display[512], auth_display[512];

usr.bin/ssh/session.c

2221

if (s->display != NULL) {

usr.bin/ssh/session.c

2245

snprintf(display, sizeof display, "localhost:%u.%u",

usr.bin/ssh/session.c

2249

s->display = xstrdup(display);

usr.bin/ssh/session.c

2252

snprintf(display, sizeof display, "%.400s:%u.%u", hostname,

usr.bin/ssh/session.c

2254

s->display = xstrdup(display);

usr.bin/ssh/session.c

2255

s->auth_display = xstrdup(display);

usr.bin/ssh/session.c

837

if (s->display)

usr.bin/ssh/session.c

838

child_set_env(&env, &envsize, "DISPLAY", s->display);

usr.bin/ssh/session.c

932

s->display != NULL && s->auth_proto != NULL && s->auth_data != NULL;

usr.bin/ssh/session.h

48

char *display;

usr.bin/ssh/ssh.c

2145

const char *display, *term;

usr.bin/ssh/ssh.c

2151

display = getenv("DISPLAY");

usr.bin/ssh/ssh.c

2152

if (display == NULL && options.forward_x11)

usr.bin/ssh/ssh.c

2154

if (options.forward_x11 && client_x11_get_proto(ssh, display,

usr.bin/ssh/ssh.c

2160

x11_request_forwarding_with_spoofing(ssh, id, display, proto,

usr.bin/talk/io.c

106

display(&my_win, buf, nb);

usr.bin/talk/io.c

97

display(&his_win, buf, nb);

usr.bin/talk/talk.h

70

void display(xwin_t *, char *, int);

usr.bin/telnet/commands.c

1946

{ "display", displayhelp, display, 0 },

usr.bin/vi/vi/vs_line.c

215

goto display;

usr.bin/vi/vi/vs_line.c

227

goto display;

usr.bin/vi/vi/vs_line.c

249

goto display;

usr.bin/vi/vi/vs_line.c

311

display:

usr.bin/watch/watch.c

113

int display(BUFFER *, BUFFER *, highlight_mode_t);

usr.bin/watch/watch.c

255

display(cur_buf, prev_buf, highlight_mode);

usr.bin/watch/watch.c

511

display(cur_buf, prev_buf, highlight_mode);

usr.bin/watch/watch.c

590

display(buf, prev_buf, highlight_mode);

usr.bin/watch/watch.c

872

display(cur_buf, prev_buf, highlight_mode);

usr.bin/watch/watch.c

898

display(cur_buf, prev_buf, highlight_mode);

usr.sbin/iostat/iostat.c

110

static void display(void);

usr.sbin/iostat/iostat.c

200

display();

usr.sbin/smtpd/smtpctl.c

54

static void display(const char *);

usr.sbin/smtpd/smtpctl.c

706

display(buf);

usr.sbin/smtpd/smtpctl.c

737

display(buf);