sys/dev/pci/drm/i915/display/intel_cdclk.c

1028

switch (cdctl & CDCLK_FREQ_SEL_MASK) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

1042

MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1046

switch (cdctl & CDCLK_FREQ_SEL_MASK) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

1060

MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1205

cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1219

cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1264

expected = (cdctl & CDCLK_FREQ_SEL_MASK) |

sys/dev/pci/drm/i915/display/intel_display_regs.h

2499

#define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2500

#define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2501

#define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2502

#define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)