Symbol: dcn_bw_yes
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1003
v->immediate_flip_supported = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1029
if ((v->dispclk_dppclk_support_per_ratio[0] == dcn_bw_yes && v->dispclk_dppclk_support_per_ratio[1] == dcn_bw_no) || (v->dispclk_dppclk_support_per_ratio[0] == v->dispclk_dppclk_support_per_ratio[1] && (v->total_number_of_active_dpp_per_ratio[0] < v->total_number_of_active_dpp_per_ratio[1] || (((v->total_number_of_active_dpp_per_ratio[0] == v->total_number_of_active_dpp_per_ratio[1]) && v->required_dispclk_per_ratio[0] <= 0.5 * v->required_dispclk_per_ratio[1]))))) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1115
if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1124
if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1205
if (v->odm_capable == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1229
if (v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1230
v->dcc_enabled_any_plane = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1234
if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1238
if (v->dcc_enabled_any_plane == dcn_bw_yes && v->critical_compression > 1.0 && v->critical_compression < 4.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1242
if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1246
if (v->dcc_enabled_any_plane == dcn_bw_yes && v->critical_compression > 1.0 && v->critical_compression < 4.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1289
if (v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
130
v->scale_ratio_support = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1319
if (v->pte_enable == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1369
if (v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1375
if (v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1378
if (v->pte_enable == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
138
v->source_format_pixel_and_scan_support = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1392
if (v->synchronized_vblank == dcn_bw_yes || v->number_of_active_planes == 1) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1470
if (v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1474
if (v->pte_enable == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1491
if (v->pte_enable == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1529
if (v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1533
if (v->pte_enable == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1550
if (v->pte_enable == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1625
if (v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1636
v->planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1682
if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1688
if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1689
if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1700
if ((v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1701
if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1750
if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1754
v->v_ratio_prefetch_more_than4 = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1757
v->destination_line_times_for_prefetch_less_than2 = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1764
v->planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4 = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1767
v->planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2 = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
177
if (v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1772
v->prefetch_mode_supported = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1778
} while (!(v->prefetch_mode_supported == dcn_bw_yes || (v->planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw == dcn_bw_yes && v->planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4 == dcn_bw_no && v->planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2 == dcn_bw_no)));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1780
} while (!(v->prefetch_mode_supported == dcn_bw_yes || v->prefetch_mode == 2.0));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
180
if (v->pte_enable == dcn_bw_yes && v->source_scan[k] != dcn_bw_hor && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1804
v->allow_dram_clock_change_during_vblank[k] = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1805
v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1810
v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
183
else if (v->pte_enable == dcn_bw_yes && v->source_scan[k] == dcn_bw_hor && (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32) && (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
186
else if (v->pte_enable == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1877
if (v->allow_dram_clock_change_during_vblank[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1903
if (v->synchronized_vblank == dcn_bw_yes || v->number_of_active_planes == 1) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
207
if (v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
208
v->dcc_enabled_in_any_plane = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
214
if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->return_bw_todcn_per_state > v->dcfclk_per_state[i] * v->return_bus_width / 4.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
218
if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->critical_point > 1.0 && v->critical_point < 4.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
222
if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->return_bw_todcn_per_state > v->dcfclk_per_state[i] * v->return_bus_width / 4.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
226
if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->critical_point > 1.0 && v->critical_point < 4.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
232
v->bandwidth_support[i] = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
240
v->writeback_latency_support = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
254
v->rob_support[i] = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
263
if (v->output[k] == dcn_bw_dp && v->dsc_capability == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
299
v->dio_support[i] = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
315
v->total_available_writeback_support = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
398
if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
407
if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
438
v->dispclk_dppclk_support[i][j] = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
44
if (v->allow_different_hratio_vratio == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
441
if (v->odm_capability == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
469
v->dispclk_dppclk_support[i][j] = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
498
v->viewport_size_support = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
509
v->total_available_pipes_support[i][j] = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
569
v->urgent_latency_support[i][j] = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
583
if (v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
618
if (v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
623
if (v->pte_enable == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
640
if (v->pte_enable == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
678
if (v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
683
if (v->pte_enable == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
700
if (v->pte_enable == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
791
if (v->pte_enable == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
794
if (v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
806
if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
815
if (v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
846
if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
852
if (v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
928
v->prefetch_supported_with_immediate_flip[i][j] = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
937
v->prefetch_supported_without_immediate_flip[i][j] = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
950
v->v_ratio_in_prefetch_supported_with_immediate_flip[i][j] = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
956
v->v_ratio_in_prefetch_supported_without_immediate_flip[i][j] = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
968
if (v->scale_ratio_support == dcn_bw_yes && v->source_format_pixel_and_scan_support == dcn_bw_yes && v->viewport_size_support == dcn_bw_yes && v->bandwidth_support[i] == dcn_bw_yes && v->dio_support[i] == dcn_bw_yes && v->urgent_latency_support[i][j] == dcn_bw_yes && v->rob_support[i] == dcn_bw_yes && v->dispclk_dppclk_support[i][j] == dcn_bw_yes && v->total_available_pipes_support[i][j] == dcn_bw_yes && v->total_available_writeback_support == dcn_bw_yes && v->writeback_latency_support == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
969
if (v->prefetch_supported_with_immediate_flip[i][j] == dcn_bw_yes && v->v_ratio_in_prefetch_supported_with_immediate_flip[i][j] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
970
v->mode_support_with_immediate_flip[i][j] = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
975
if (v->prefetch_supported_without_immediate_flip[i][j] == dcn_bw_yes && v->v_ratio_in_prefetch_supported_without_immediate_flip[i][j] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
976
v->mode_support_without_immediate_flip[i][j] = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
989
if ((i == number_of_states_plus_one || v->mode_support_with_immediate_flip[i][1] == dcn_bw_yes || v->mode_support_with_immediate_flip[i][0] == dcn_bw_yes) && i >= v->voltage_override_level) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
994
if ((i == number_of_states_plus_one || v->mode_support_without_immediate_flip[i][1] == dcn_bw_yes || v->mode_support_without_immediate_flip[i][0] == dcn_bw_yes) && i >= v->voltage_override_level) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1004
pipe->plane_state->format, &bpe) ? dcn_bw_yes : dcn_bw_no;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1027
if (v->is_line_buffer_bpp_fixed == dcn_bw_yes)
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
131
.pte_enable = dcn_bw_yes,
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1590
dc->dml.ip.pte_enable = dc->dcn_ip->pte_enable == dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1596
dc->dml.ip.IsLineBufferBppFixed = dc->dcn_ip->is_line_buffer_bpp_fixed == dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1615
dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1617
dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
518
v->pte_enable == dcn_bw_yes,
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
891
v->allow_different_hratio_vratio = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
916
v->dcc_enable[input_idx] = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
993
v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;