sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

147

struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

232

rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

237

rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

259

dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

263

dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

267

dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

271

dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

274

dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

285

vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

298

dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

310

dcn315_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

322

dcn316_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

333

dcn32_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

345

dcn314_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

358

dcn351_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

360

dcn35_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

367

struct clk_mgr_internal *clk_mgr = dcn401_clk_mgr_construct(ctx, dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h

48

int dce12_get_dp_ref_freq_khz(struct clk_mgr *dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

109

clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

119

prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

122

clk_mgr->dccg->funcs->update_dpp_dto(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

123

clk_mgr->dccg, dpp_inst, dppclk_khz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

155

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

168

dccg->funcs->set_fifo_errdet_ovr_en(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

169

dccg,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

172

dccg->funcs->otg_drop_pixel(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

173

dccg,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

175

dccg->funcs->set_fifo_errdet_ovr_en(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

176

dccg,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

185

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

199

dccg->funcs->set_fifo_errdet_ovr_en(dccg, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

201

dccg->funcs->otg_add_pixel(dccg,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

203

dccg->funcs->set_fifo_errdet_ovr_en(dccg, false);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

396

clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

532

struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

546

clk_mgr->dccg = dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

29

void dcn2_update_clocks(struct clk_mgr *dccg,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

44

struct dccg *dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

182

struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

192

clk_mgr->dccg = dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.h

32

struct dccg *dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

111

clk_mgr->dccg->ref_dppclk = ref_dpp_clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

122

prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[dpp_inst];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

125

clk_mgr->dccg->funcs->update_dpp_dto(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

126

clk_mgr->dccg, dpp_inst, dppclk_khz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

704

struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

719

clk_mgr->dccg = dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h

47

struct dccg *dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

524

struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

534

clk_mgr->dccg = dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h

94

struct dccg *dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

681

struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

691

clk_mgr->base.dccg = dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.h

48

struct dccg *dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

677

struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

687

clk_mgr->base.dccg = dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h

52

struct dccg *dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

919

struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

929

clk_mgr->base.dccg = dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h

64

struct dccg *dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

607

struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

617

clk_mgr->base.dccg = dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h

45

struct dccg *dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

582

struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

592

clk_mgr->base.dccg = dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.h

45

struct dccg *dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1148

struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1164

clk_mgr->dccg = dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

270

struct dccg *dccg = clk_mgr->dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

286

dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

319

clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

340

prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

343

clk_mgr->dccg->funcs->update_dpp_dto(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

344

clk_mgr->dccg, dpp_inst, dppclk_khz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

374

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

387

dccg->funcs->set_fifo_errdet_ovr_en(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

388

dccg,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

391

dccg->funcs->otg_drop_pixel(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

392

dccg,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

394

dccg->funcs->set_fifo_errdet_ovr_en(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

395

dccg,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

427

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

441

dccg->funcs->set_fifo_errdet_ovr_en(dccg, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

443

dccg->funcs->otg_add_pixel(dccg,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

445

dccg->funcs->set_fifo_errdet_ovr_en(dccg, false);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h

33

struct dccg *dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

130

struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

137

dcn35_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1288

clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1373

struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1382

clk_mgr->base.dccg = dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

202

struct dccg *dccg = clk_mgr_internal->dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

233

has_active_hpo = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(old_pipe) &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

234

dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(new_pipe);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

240

!dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

258

struct dccg *dccg = clk_mgr->dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

274

dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

287

clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

308

prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

311

clk_mgr->dccg->funcs->update_dpp_dto(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

312

clk_mgr->dccg, dpp_inst, dppclk_khz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

320

clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, old_dpp->inst, 0);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h

59

struct dccg *dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h

66

struct dccg *dccg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1549

struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1565

clk_mgr->dccg = dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

529

struct dccg *dccg = clk_mgr->dccg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

542

use_hpo_encoder = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(otg_master);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

550

dccg->ctx->dc->link_srv->dp_get_encoding_format(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

561

clk_mgr->dccg->ref_dppclk = ref_dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

582

prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

585

clk_mgr->dccg->funcs->update_dpp_dto(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

586

clk_mgr->dccg, dpp_inst, dppclk_khz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

111

struct dccg *dccg);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1148

dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

102

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

108

void dccg2_otg_add_pixel(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

111

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

120

void dccg2_otg_drop_pixel(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

123

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

132

void dccg2_init(struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

145

struct dccg *dccg2_create(

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

152

struct dccg *base;

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

170

void dcn_dccg_destroy(struct dccg **dccg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

172

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(*dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

175

*dccg = NULL;

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

32

#define TO_DCN_DCCG(dccg)\

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

33

container_of(dccg, struct dcn_dccg, base)

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

45

dccg->ctx->logger

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

47

void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

49

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

51

if (dccg->ref_dppclk && req_dppclk) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

52

int ref_dppclk = dccg->ref_dppclk;

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

74

dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

77

void dccg2_get_dccg_ref_freq(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

81

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

99

void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

434

struct dccg base;

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

440

void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

442

void dccg2_get_dccg_ref_freq(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

446

void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

448

void dccg2_otg_add_pixel(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

450

void dccg2_otg_drop_pixel(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

454

void dccg2_init(struct dccg *dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

456

struct dccg *dccg2_create(

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

462

void dcn_dccg_destroy(struct dccg **dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

31

#define TO_DCN_DCCG(dccg)\

sys/dev/pci/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

32

container_of(dccg, struct dcn_dccg, base)

sys/dev/pci/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

45

dccg->ctx->logger

sys/dev/pci/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

47

static void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

62

struct dccg *dccg201_create(

sys/dev/pci/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

69

struct dccg *base;

sys/dev/pci/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.h

31

struct dccg *dccg201_create(

sys/dev/pci/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

109

struct dccg *dccg21_create(

sys/dev/pci/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

116

struct dccg *base;

sys/dev/pci/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

31

#define TO_DCN_DCCG(dccg)\

sys/dev/pci/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

32

container_of(dccg, struct dcn_dccg, base)

sys/dev/pci/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

44

dccg->ctx->logger

sys/dev/pci/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

46

static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

48

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

50

if (dccg->ref_dppclk) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

51

int ref_dppclk = dccg->ref_dppclk;

sys/dev/pci/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

96

dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;

sys/dev/pci/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.h

29

struct dccg *dccg21_create(

sys/dev/pci/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

30

#define TO_DCN_DCCG(dccg)\

sys/dev/pci/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

31

container_of(dccg, struct dcn_dccg, base)

sys/dev/pci/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

43

dccg->ctx->logger

sys/dev/pci/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

55

struct dccg *dccg3_create(

sys/dev/pci/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

62

struct dccg *base;

sys/dev/pci/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

80

struct dccg *dccg30_create(

sys/dev/pci/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

87

struct dccg *base;

sys/dev/pci/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h

54

struct dccg *dccg3_create(

sys/dev/pci/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h

60

struct dccg *dccg30_create(

sys/dev/pci/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c

30

#define TO_DCN_DCCG(dccg)\

sys/dev/pci/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c

31

container_of(dccg, struct dcn_dccg, base)

sys/dev/pci/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c

43

dccg->ctx->logger

sys/dev/pci/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c

54

struct dccg *dccg301_create(

sys/dev/pci/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c

61

struct dccg *base;

sys/dev/pci/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h

53

struct dccg *dccg301_create(

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

123

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

129

static void dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

131

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

133

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

162

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

168

dccg31_disable_dpstreamclk(dccg, otg_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

170

dccg31_enable_dpstreamclk(dccg, otg_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

174

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

178

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

185

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

194

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

203

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

212

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

227

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

230

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

238

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

247

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

256

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

265

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

277

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

281

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

304

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

307

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

31

#define TO_DCN_DCCG(dccg)\

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

32

container_of(dccg, struct dcn_dccg, base)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

328

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

332

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

334

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

354

void dccg31_disable_dscclk(struct dccg *dccg, int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

356

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

358

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

398

void dccg31_enable_dscclk(struct dccg *dccg, int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

400

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

402

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

44

dccg->ctx->logger

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

443

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

448

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

457

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

46

void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

464

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

474

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

48

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

481

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

491

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

498

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

50

if (dccg->dpp_clock_gated[dpp_inst]) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

508

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

515

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

525

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

532

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

545

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

548

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

58

if (dccg->ref_dppclk && req_dppclk) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

59

int ref_dppclk = dccg->ref_dppclk;

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

611

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

614

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

642

void dccg31_get_dccg_ref_freq(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

655

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

658

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

664

void dccg31_init(struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

670

dccg31_disable_symclk32_se(dccg, 0);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

671

dccg31_disable_symclk32_se(dccg, 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

672

dccg31_disable_symclk32_se(dccg, 2);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

673

dccg31_disable_symclk32_se(dccg, 3);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

675

dccg31_set_symclk32_le_root_clock_gating(dccg, 0, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

676

dccg31_set_symclk32_le_root_clock_gating(dccg, 1, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

678

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

679

dccg31_disable_dpstreamclk(dccg, 0);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

680

dccg31_disable_dpstreamclk(dccg, 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

681

dccg31_disable_dpstreamclk(dccg, 2);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

682

dccg31_disable_dpstreamclk(dccg, 3);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

685

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

686

dccg31_set_physymclk(dccg, 0, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

687

dccg31_set_physymclk(dccg, 1, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

688

dccg31_set_physymclk(dccg, 2, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

689

dccg31_set_physymclk(dccg, 3, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

690

dccg31_set_physymclk(dccg, 4, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

694

void dccg31_otg_add_pixel(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

697

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

703

void dccg31_otg_drop_pixel(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

706

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

732

struct dccg *dccg31_create(

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

739

struct dccg *base;

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

80

dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

97

static void dccg31_enable_dpstreamclk(struct dccg *dccg, int otg_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

99

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

162

struct dccg *dccg31_create(

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

168

void dccg31_init(struct dccg *dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

171

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

176

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

180

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

185

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

189

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

194

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

200

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

204

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

209

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

214

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

220

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

224

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

228

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

232

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

235

void dccg31_disable_dscclk(struct dccg *dccg, int inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

237

void dccg31_enable_dscclk(struct dccg *dccg, int inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

101

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

106

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

117

dccg314_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2);

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

149

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

153

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

206

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

209

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

231

dccg314_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

250

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

255

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

258

dccg314_set_dtbclk_p_src(dccg, src, otg_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

288

static void dccg314_init(struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

297

dccg31_disable_symclk32_se(dccg, otg_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

299

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

301

dccg31_disable_symclk32_le(dccg, otg_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

303

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

305

dccg314_set_dpstreamclk(dccg, REFCLK, otg_inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

308

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

310

dccg31_set_physymclk(dccg, otg_inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

315

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

326

dccg314_set_dtbclk_dto(dccg, &dto_params);

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

33

#define TO_DCN_DCCG(dccg)\

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

330

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

334

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

336

if (dccg->dpp_clock_gated[dpp_inst] != clock_on)

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

34

container_of(dccg, struct dcn_dccg, base)

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

353

dccg->dpp_clock_gated[dpp_inst] = !clock_on;

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

383

struct dccg *dccg314_create(

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

390

struct dccg *base;

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

46

dccg->ctx->logger

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

49

struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

51

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

59

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

64

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h

200

struct dccg *dccg314_create(

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h

207

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

101

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

106

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

117

dccg32_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2);

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

149

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

153

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

205

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

208

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

230

dccg32_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

248

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

260

dccg32_set_dtbclk_dto(dccg, &dto_params);

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

263

static void dccg32_get_dccg_ref_freq(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

276

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

281

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

285

dccg32_set_dtbclk_p_src(dccg, DTBCLK0, otg_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

30

#define TO_DCN_DCCG(dccg)\

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

31

container_of(dccg, struct dcn_dccg, base)

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

312

static void dccg32_otg_add_pixel(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

315

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

321

static void dccg32_otg_drop_pixel(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

324

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

352

struct dccg *dccg32_create(

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

359

struct dccg *base;

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

43

dccg->ctx->logger

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

46

struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

48

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

59

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

64

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h

119

struct dccg *dccg32_create(

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1001

if (dccg35_is_symclk32_se_rcg(dccg, i) == 0) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1003

if (dccg35_is_symclk32_se_src_functional_le_new(dccg, i, inst))

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1004

dccg35_disable_symclk32_se_new(dccg, i);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1008

dccg35_set_symclk32_le_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1011

static void dccg35_enable_physymclk_new(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1015

dccg35_set_physymclk_rcg(dccg, inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1016

dccg35_set_physymclk_src_new(dccg, src, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1019

static void dccg35_disable_physymclk_new(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1022

dccg35_set_physymclk_src_new(dccg, PHYSYMCLK_REFCLK, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1023

dccg35_set_physymclk_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1027

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1031

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1037

dccg35_set_dppclk_rcg(dccg, inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1038

dcn35_set_dppclk_src_new(dccg, inst, src);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1047

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1050

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1056

dcn35_set_dppclk_src_new(dccg, inst, DPP_REFCLK);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1060

dccg35_set_dppclk_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1063

static void dccg35_disable_dscclk_new(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1066

dccg35_set_dsc_clk_src_new(dccg, inst, DSC_CLK_REF_CLK);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1067

dccg35_set_dsc_clk_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1070

static void dccg35_enable_dscclk_new(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1074

dccg35_set_dsc_clk_rcg(dccg, inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1075

dccg35_set_dsc_clk_src_new(dccg, inst, src);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1078

static void dccg35_enable_dtbclk_p_new(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1082

dccg35_set_dtbclk_p_rcg(dccg, inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1083

dccg35_set_dtbclk_p_src_new(dccg, src, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1086

static void dccg35_disable_dtbclk_p_new(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1089

dccg35_set_dtbclk_p_src_new(dccg, DTBCLK_REFCLK, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1090

dccg35_set_dtbclk_p_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1093

static void dccg35_disable_dpstreamclk_new(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1096

dccg35_set_dpstreamclk_src_new(dccg, DP_STREAM_REFCLK, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1097

dccg35_set_dpstreamclk_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1100

static void dccg35_enable_dpstreamclk_new(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1104

dccg35_set_dpstreamclk_rcg(dccg, inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1105

dccg35_set_dpstreamclk_src_new(dccg, src, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1108

static void dccg35_trigger_dio_fifo_resync(struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1110

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1118

static void dcn35_set_dppclk_enable(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1121

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1144

static void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1147

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1149

if (dccg->dpp_clock_gated[dpp_inst]) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1156

if (dccg->ref_dppclk && req_dppclk) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1157

int ref_dppclk = dccg->ref_dppclk;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1168

dccg35_set_dppclk_rcg(dccg, dpp_inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1174

dcn35_set_dppclk_enable(dccg, dpp_inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1176

dcn35_set_dppclk_enable(dccg, dpp_inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1180

dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1183

static void dccg35_set_dppclk_root_clock_gating(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1186

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1188

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && !disallow_rcg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1215

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1220

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1257

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1262

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1274

dccg35_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1306

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1310

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1362

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1365

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

137

static void dccg35_set_dsc_clk_rcg(struct dccg *dccg, int inst, bool allow_rcg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

139

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1402

dccg35_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

141

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc && allow_rcg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1445

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1450

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1453

dccg35_set_dtbclk_p_src(dccg, src, otg_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1460

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1466

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1472

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1478

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1491

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1495

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1499

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1505

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1511

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1517

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1533

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1537

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1539

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1572

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1577

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1645

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1657

dccg35_set_dtbclk_dto(dccg, &dto_params);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1661

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1665

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1667

if (dccg->dpp_clock_gated[dpp_inst] == clock_on)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1671

dccg35_set_dppclk_rcg(dccg, dpp_inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1674

dcn35_set_dppclk_enable(dccg, dpp_inst, 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1679

dcn35_set_dppclk_enable(dccg, dpp_inst, 0);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

168

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1688

dccg->dpp_clock_gated[dpp_inst] = !clock_on;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1693

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1696

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1704

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1715

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

172

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1726

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1737

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

174

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1751

static void dccg35_init_cb(struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1753

(void)dccg;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1756

void dccg35_init(struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1764

dccg35_disable_symclk32_se(dccg, otg_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1766

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1768

dccg31_disable_symclk32_le(dccg, otg_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1769

dccg31_set_symclk32_le_root_clock_gating(dccg, otg_inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1779

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1781

dccg35_set_dpstreamclk(dccg, REFCLK, otg_inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1783

dccg35_set_dpstreamclk_root_clock_gating(dccg, otg_inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1794

void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1796

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1801

static void dccg35_enable_dscclk(struct dccg *dccg, int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1803

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1848

static void dccg35_disable_dscclk(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1851

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1859

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1867

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1875

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1883

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1894

static void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1896

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1902

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1908

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1914

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1920

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1926

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1936

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1943

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1950

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1957

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1964

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1971

static uint8_t dccg35_get_number_enabled_symclk_fe_connected_to_be(struct dccg *dccg, uint32_t link_enc_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1975

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2001

static void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2004

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2045

num_enabled_symclk_fe = dccg35_get_number_enabled_symclk_fe_connected_to_be(dccg, link_enc_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

207

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2085

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

211

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2114

dccg35_disable_dtbclk_p_new(dccg, otg_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2115

dccg35_disable_dpstreamclk_new(dccg, dp_hpo_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2117

dccg35_enable_dtbclk_p_new(dccg, dtb_clk_src, otg_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2118

dccg35_enable_dpstreamclk_new(dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2125

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

213

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2136

dccg35_enable_dpstreamclk_new(dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2140

dccg35_disable_dpstreamclk_new(dccg, dp_hpo_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2143

static void dccg35_update_dpp_dto_cb(struct dccg *dccg, int dpp_inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2146

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2148

if (dccg->dpp_clock_gated[dpp_inst]) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2155

if (dccg->ref_dppclk && req_dppclk) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2156

int ref_dppclk = dccg->ref_dppclk;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2169

dccg35_enable_dpp_clk_new(dccg, dpp_inst, DPP_DCCG_DTO);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2176

dccg35_disable_dpp_clk_new(dccg, dpp_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2178

dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2182

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2186

if (dccg->dpp_clock_gated[dpp_inst] == power_on)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2193

dccg35_set_dppclk_rcg(dccg, dpp_inst, !power_on);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2195

dccg->dpp_clock_gated[dpp_inst] = !power_on;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2199

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2203

dccg35_enable_symclk32_se_new(dccg, inst, (enum symclk32_se_clk_source)phyd32clk);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2206

static void dccg35_disable_symclk32_se_cb(struct dccg *dccg, int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2208

dccg35_disable_symclk32_se_new(dccg, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2212

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2216

dccg35_enable_symclk32_le_new(dccg, inst, (enum symclk32_le_clk_source) src);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2219

static void dccg35_disable_symclk32_le_cb(struct dccg *dccg, int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2221

dccg35_disable_symclk32_le_new(dccg, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2225

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2235

dccg35_enable_symclk32_le_new(dccg, inst, SYMCLK32_LE_REFCLK);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2237

dccg35_disable_symclk32_le_new(dccg, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2241

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2248

dccg35_enable_physymclk_new(dccg, inst, (enum physymclk_source)clk_src);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2250

dccg35_disable_physymclk_new(dccg, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2254

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2262

dccg35_enable_physymclk_new(dccg, inst, PHYSYMCLK_REFCLK);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2264

dccg35_disable_physymclk_new(dccg, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2268

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2278

dccg35_enable_symclk32_le_new(dccg, inst, SYMCLK32_LE_REFCLK);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2280

dccg35_disable_symclk32_le_new(dccg, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2284

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2289

dccg35_enable_dtbclk_p_new(dccg, DTBCLK_DTBCLK0, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2291

dccg35_disable_dtbclk_p_new(dccg, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2295

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2301

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2308

dccg35_enable_dtbclk_p_new(dccg, DTBCLK_DTBCLK0, params->otg_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2325

dccg35_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2334

dccg35_disable_dtbclk_p_new(dccg, params->otg_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

234

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2345

static void dccg35_disable_dscclk_cb(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2348

dccg35_disable_dscclk_new(dccg, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2351

static void dccg35_enable_dscclk_cb(struct dccg *dccg, int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2353

dccg35_enable_dscclk_new(dccg, inst, DSC_DTO_TUNED_CK_GPU_DISCLK_3);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2356

static void dccg35_enable_symclk_se_cb(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2359

dccg35_enable_symclk_be_new(dccg, SYMCLK_BE_PHYCLK, link_enc_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2361

dccg35_enable_symclk_fe_new(dccg, stream_enc_inst, (enum symclk_fe_source) link_enc_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2366

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2370

dccg35_disable_symclk_fe_new(dccg, stream_enc_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2375

void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2377

dccg35_set_dppclk_root_clock_gating(dccg, pipe_idx, disable_clock_gating);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

238

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

240

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2443

struct dccg *dccg35_create(

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2450

struct dccg *base;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

271

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

275

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

277

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

30

#define TO_DCN_DCCG(dccg)\

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

31

container_of(dccg, struct dcn_dccg, base)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

318

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

323

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

326

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

366

static void dccg35_set_dtbclk_p_rcg(struct dccg *dccg, int inst, bool enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

369

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

371

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

393

static void dccg35_set_dppclk_rcg(struct dccg *dccg, int inst, bool allow_rcg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

395

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

397

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && allow_rcg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

424

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

428

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

430

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

44

dccg->ctx->logger

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

461

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

465

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

467

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

497

static void dccg35_set_dsc_clk_src_new(struct dccg *dccg, int inst, enum dsc_clk_source src)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

499

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

523

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

528

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

558

dccg35_is_symclk32_se_src_functional_le_new(struct dccg *dccg, int symclk_32_se_inst, int symclk_32_le_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

563

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

575

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

579

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

598

static void dcn35_set_dppclk_src_new(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

601

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

623

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

627

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

661

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

665

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

701

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

705

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

745

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

749

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

780

static int dccg35_is_symclk_fe_src_functional_be(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

788

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

814

static void dccg35_set_symclk_fe_src_new(struct dccg *dccg, enum symclk_fe_source src, int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

816

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

847

static uint32_t dccg35_is_fe_rcg(struct dccg *dccg, int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

850

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

880

static uint32_t dccg35_is_symclk32_se_rcg(struct dccg *dccg, int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

884

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

917

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

921

dccg35_set_symclk_fe_rcg(dccg, inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

922

dccg35_set_symclk_fe_src_new(dccg, src, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

926

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

929

dccg35_set_symclk_fe_src_new(dccg, SYMCLK_FE_REFCLK, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

930

dccg35_set_symclk_fe_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

934

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

938

dccg35_set_symclk_be_rcg(dccg, inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

939

dccg35_set_symclk_be_src_new(dccg, inst, src);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

943

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

949

dccg35_set_symclk_be_src_new(dccg, inst, SYMCLK_BE_REFCLK);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

954

if (dccg35_is_fe_rcg(dccg, i) == 0) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

955

if (dccg35_is_symclk_fe_src_functional_be(dccg, i, inst))

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

956

dccg35_disable_symclk_fe_new(dccg, i);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

960

dccg35_set_symclk_be_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

964

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

968

dccg35_set_symclk32_se_rcg(dccg, inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

969

dccg35_set_symclk32_se_src_new(dccg, inst, src);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

973

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

976

dccg35_set_symclk32_se_src_new(dccg, SYMCLK32_SE_REFCLK, inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

977

dccg35_set_symclk32_se_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

981

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

985

dccg35_set_symclk32_le_rcg(dccg, inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

986

dccg35_set_symclk32_le_src_new(dccg, inst, src);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

990

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

996

dccg35_set_symclk32_le_src_new(dccg, inst, SYMCLK32_LE_REFCLK);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

235

struct dccg *dccg35_create(

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

241

void dccg35_init(struct dccg *dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

243

void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

244

void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

102

dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

109

struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

111

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

120

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

125

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

158

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

163

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

173

dccg401_get_pixel_rate_div(dccg, otg_inst, &cur_tmds_div, &dp_dto_int);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

185

dccg401_wait_for_dentist_change_done(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

191

dccg401_wait_for_dentist_change_done(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

197

dccg401_wait_for_dentist_change_done(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

203

dccg401_wait_for_dentist_change_done(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

213

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

217

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

268

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

273

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

282

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

289

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

299

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

306

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

316

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

323

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

333

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

340

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

351

void dccg401_get_dccg_ref_freq(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

363

static void dccg401_otg_add_pixel(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

366

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

372

static void dccg401_otg_drop_pixel(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

375

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

382

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

386

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

391

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

40

#define TO_DCN_DCCG(dccg)\

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

400

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

409

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

41

container_of(dccg, struct dcn_dccg, base)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

418

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

433

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

436

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

444

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

453

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

462

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

471

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

482

static void dccg401_enable_dpstreamclk(struct dccg *dccg, int otg_inst, int dp_hpo_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

484

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

489

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

498

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

507

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

516

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

528

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

53

dccg->ctx->logger

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

534

void dccg401_disable_dpstreamclk(struct dccg *dccg, int dp_hpo_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

536

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

542

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

55

static void dcn401_set_dppclk_enable(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

550

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

558

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

566

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

578

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

58

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

585

dccg401_disable_dpstreamclk(dccg, dp_hpo_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

587

dccg401_enable_dpstreamclk(dccg, otg_inst, dp_hpo_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

591

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

594

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

663

dccg401_set_dtbclk_p_src(dccg, params->clk_src, params->otg_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

697

void dccg401_init(struct dccg *dccg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

703

dccg31_disable_symclk32_se(dccg, 0);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

704

dccg31_disable_symclk32_se(dccg, 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

705

dccg31_disable_symclk32_se(dccg, 2);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

706

dccg31_disable_symclk32_se(dccg, 3);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

708

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

709

dccg401_disable_symclk32_le(dccg, 0);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

710

dccg401_disable_symclk32_le(dccg, 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

711

dccg401_disable_symclk32_le(dccg, 2);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

712

dccg401_disable_symclk32_le(dccg, 3);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

715

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

716

dccg401_disable_dpstreamclk(dccg, 0);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

717

dccg401_disable_dpstreamclk(dccg, 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

718

dccg401_disable_dpstreamclk(dccg, 2);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

719

dccg401_disable_dpstreamclk(dccg, 3);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

722

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

723

dccg401_set_physymclk(dccg, 0, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

724

dccg401_set_physymclk(dccg, 1, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

725

dccg401_set_physymclk(dccg, 2, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

726

dccg401_set_physymclk(dccg, 3, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

730

void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst, uint32_t num_slices_h)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

732

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

766

void dccg401_set_ref_dscclk(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

769

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

77

void dccg401_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

79

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

801

void dccg401_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

803

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

81

if (dccg->ref_dppclk && req_dppclk) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

810

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

817

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

82

int ref_dppclk = dccg->ref_dppclk;

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

824

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

831

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

837

void dccg401_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

839

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

891

struct dccg *dccg401_create(

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

898

struct dccg *base;

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

97

dcn401_set_dppclk_enable(dccg, dpp_inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

99

dcn401_set_dppclk_enable(dccg, dpp_inst, false);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

193

void dccg401_init(struct dccg *dccg);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

195

void dccg401_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

196

void dccg401_get_dccg_ref_freq(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

200

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

205

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

209

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

211

void dccg401_disable_dpstreamclk(struct dccg *dccg, int dp_hpo_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

212

void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst, uint32_t num_slices_h);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

213

void dccg401_set_ref_dscclk(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

216

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

219

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

224

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

229

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

231

void dccg401_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

232

void dccg401_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

234

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

237

struct dccg *dccg401_create(

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

244

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1104

clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto(

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1105

clock_source->ctx->dc->res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1113

clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto(

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1114

clock_source->ctx->dc->res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1155

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1183

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1187

if (dccg) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1188

dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1189

dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1191

if (dccg && dccg->funcs->set_dtbclk_dto)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1192

dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1195

} else if (dccg && dccg->funcs->disable_symclk_se) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1196

dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1861

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1890

if (dccg->funcs->set_ref_dscclk)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1891

dccg->funcs->set_ref_dscclk(dccg, dsc->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1967

dc->res_pool->dccg->funcs->get_pixel_rate_div(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1968

dc->res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2400

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2403

dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2404

dc->res_pool->dccg, &dto_params);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2891

struct clk_mgr *dccg = dc->clk_mgr;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2894

if (dccg)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2895

dccg->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2896

dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2905

struct clk_mgr *dccg = dc->clk_mgr;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2909

if (dccg)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2910

dccg->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2911

dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1781

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1782

dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1795

if (res_pool->dccg && res_pool->hubbub) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1797

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3034

if (dc->res_pool->dccg)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3035

dc->res_pool->dccg->funcs->update_dpp_dto(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3036

dc->res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1688

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1696

dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2215

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2238

if (dccg->funcs->set_ref_dscclk)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2239

dccg->funcs->set_ref_dscclk(dccg, dsc->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2816

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2878

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2882

if (dccg && dccg->funcs->set_dtbclk_dto)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2883

dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3031

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3047

dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3049

dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3053

dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3055

dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3058

if (dccg->funcs->enable_symclk_se && link_enc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3062

if (dccg->funcs->disable_symclk_se)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3063

dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3066

dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3071

if (dc->res_pool->dccg->funcs->set_pixel_rate_div)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3072

dc->res_pool->dccg->funcs->set_pixel_rate_div(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3073

dc->res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3142

if (res_pool->dccg->funcs->dccg_init)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3143

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

853

if (dc->res_pool->dccg->funcs->set_pixel_rate_div)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

854

dc->res_pool->dccg->funcs->set_pixel_rate_div(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

855

dc->res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

896

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

900

if (dccg->funcs->set_dtbclk_p_src)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

901

dccg->funcs->set_dtbclk_p_src(dccg, DTBCLK0, tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

908

dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

231

if (res_pool->dccg->funcs->dccg_init)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

232

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

244

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

653

if (res_pool->dccg->funcs->dccg_init)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

654

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

685

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

128

if (res_pool->dccg->funcs->dccg_init)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

129

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

139

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

294

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

296

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

297

hws->ctx->dc->res_pool->dccg, dsc_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

337

if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

338

hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

339

hws->ctx->dc->res_pool->dccg, dsc_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

237

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

239

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

240

hws->ctx->dc->res_pool->dccg, dsc_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

288

if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

289

hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

290

hws->ctx->dc->res_pool->dccg, dsc_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

425

hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

460

if (hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

461

hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

462

hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1020

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1030

bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1068

dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1078

dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1270

hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

793

if (res_pool->dccg->funcs->dccg_init)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

794

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

817

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1329

if (dc->res_pool->dccg->funcs->enable_dsc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1330

dc->res_pool->dccg->funcs->enable_dsc(dc->res_pool->dccg, i);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1332

if (dc->res_pool->dccg->funcs->disable_dsc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1333

dc->res_pool->dccg->funcs->disable_dsc(dc->res_pool->dccg, i);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

161

if (res_pool->dccg->funcs->dccg_init)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

162

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

172

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

485

if (hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

486

hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

487

hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

496

if (hws->ctx->dc->res_pool->dccg->funcs->set_dpstreamclk_root_clock_gating) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

497

hws->ctx->dc->res_pool->dccg->funcs->set_dpstreamclk_root_clock_gating(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

498

hws->ctx->dc->res_pool->dccg, dp_hpo_inst, clock_on);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

507

if (hws->ctx->dc->res_pool->dccg->funcs->set_physymclk_root_clock_gating) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

508

hws->ctx->dc->res_pool->dccg->funcs->set_physymclk_root_clock_gating(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

509

hws->ctx->dc->res_pool->dccg, phy_inst, clock_on);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

819

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

828

dccg->funcs->dccg_root_gate_disable_control(dccg, dpp->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

862

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

881

dccg->funcs->dccg_root_gate_disable_control(dccg, dpp->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

158

if (res_pool->dccg->funcs->dccg_init)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

159

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

182

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1886

if (dc->res_pool->dccg->funcs->set_dtbclk_p_src)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1887

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, REFCLK, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

788

if (dc->res_pool->dccg->funcs->set_pixel_rate_div) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

789

dc->res_pool->dccg->funcs->set_pixel_rate_div(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

790

dc->res_pool->dccg, pipe_ctx->stream_res.tg->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

806

if (dc->res_pool->dccg->funcs->set_dtbclk_p_src) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

808

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DPREFCLK, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

959

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

975

dccg->funcs->set_dpstreamclk(dccg, DPREFCLK, tg->inst, dp_hpo_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

977

dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

979

dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

982

dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

987

if (dc->res_pool->dccg->funcs->set_pixel_rate_div) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

988

dc->res_pool->dccg->funcs->set_pixel_rate_div(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

989

dc->res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

314

struct dccg *dccg;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

361

struct dccg;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

363

struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg);

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

350

struct dccg *dccg;

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

102

void (*set_fifo_errdet_ovr_en)(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

104

void (*otg_add_pixel)(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

106

void (*otg_drop_pixel)(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

108

void (*dccg_init)(struct dccg *dccg);

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

110

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

115

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

121

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

126

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

130

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

135

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

139

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

144

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

150

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

155

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

159

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

163

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

167

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

171

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

174

void (*set_pixel_rate_div)(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

179

void (*get_pixel_rate_div)(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

185

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

191

struct dccg *dccg);

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

194

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

199

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

204

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

208

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

211

struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

214

void (*set_dto_dscclk)(struct dccg *dccg, uint32_t dsc_inst, uint32_t num_slices_h);

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

215

void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst);

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

216

void (*dccg_root_gate_disable_control)(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating);

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

96

void (*update_dpp_dto)(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

99

void (*get_dccg_ref_freq)(struct dccg *dccg,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

118

if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

119

link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

120

link->dc->res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

142

if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

143

link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

144

link->dc->res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

812

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

822

bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) &&

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

846

dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

853

dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

931

if (dccg->funcs->set_ref_dscclk)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

932

dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1183

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1184

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2529

pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2530

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1188

pool->base.dccg = dccg201_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1189

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

977

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

978

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1510

pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1511

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

759

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

760

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1186

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1187

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2432

pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2433

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1154

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1155

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1548

pool->base.dccg = dccg301_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1549

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1105

if (pool->dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1106

dcn_dccg_destroy(&pool->dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1344

pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1345

if (pool->dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1049

if (pool->dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1050

dcn_dccg_destroy(&pool->dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1276

pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1277

if (pool->dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1490

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1491

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2045

pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2046

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1548

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1549

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1970

pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1971

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1490

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1491

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1993

pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1994

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1483

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1484

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1869

pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1870

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1493

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1494

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2351

pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2352

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1473

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1474

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1851

pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1852

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1562

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1563

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2003

pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2004

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1542

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1543

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1975

pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1976

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1543

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1544

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1976

pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1977

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1496

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1497

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2049

pool->base.dccg = dccg401_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2050

if (pool->base.dccg == NULL) {