sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2677

struct dc_dmub_srv *dc_dmub_srv;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2687

dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2688

if (dc_dmub_srv && dc_dmub_srv->dmub) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2691

&dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw;

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

1029

struct dc_dmub_srv *dmcub,

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

110

struct dc_dmub_srv *dmcub,

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

247

struct dc_dmub_srv *dmcub,

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

309

struct dc_dmub_srv *dmcub,

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

462

struct dc_dmub_srv *dmcub,

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

825

struct dc_dmub_srv *dmcub,

sys/dev/pci/drm/amd/display/dc/core/dc.c

547

dc_stream_forward_dmub_crc_window(struct dc_dmub_srv *dmub_srv,

sys/dev/pci/drm/amd/display/dc/core/dc.c

585

struct dc_dmub_srv *dmub_srv;

sys/dev/pci/drm/amd/display/dc/core/dc.c

620

dc_stream_forward_dmub_multiple_crc_window(struct dc_dmub_srv *dmub_srv,

sys/dev/pci/drm/amd/display/dc/core/dc.c

651

struct dc_dmub_srv *dmub_srv;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1110

struct dc_dmub_srv *dc_dmub_srv = params->subvp_save_surf_addr.dc_dmub_srv;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1114

dc_dmub_srv_subvp_save_surf_addr(dc_dmub_srv, addr, subvp_index);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

802

block_sequence[*num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

100

struct dmub_srv *dmub = dc_dmub_srv->dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1000

DC_LOG_DEBUG(" is_soft_reset : %d", dc_dmub_srv->dmub->debug.is_dmcub_soft_reset);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1001

DC_LOG_DEBUG(" is_secure_reset : %d", dc_dmub_srv->dmub->debug.is_dmcub_secure_reset);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1002

DC_LOG_DEBUG(" is_traceport_en : %d", dc_dmub_srv->dmub->debug.is_traceport_en);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1003

DC_LOG_DEBUG(" is_cw0_en : %d", dc_dmub_srv->dmub->debug.is_cw0_enabled);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1004

DC_LOG_DEBUG(" is_cw6_en : %d", dc_dmub_srv->dmub->debug.is_cw6_enabled);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

101

struct dc_context *dc_ctx = dc_dmub_srv->ctx;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

107

dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

111

void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dc_dmub_srv)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

113

struct dmub_srv *dmub = dc_dmub_srv->dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

114

struct dc_context *dc_ctx = dc_dmub_srv->ctx;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1150

struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1152

if (!dc_dmub_srv || !dc_dmub_srv->dmub) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1172

void dc_dmub_srv_subvp_save_surf_addr(const struct dc_dmub_srv *dc_dmub_srv, const struct dc_plane_address *addr, uint8_t subvp_index)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1174

dmub_srv_subvp_save_surf_addr(dc_dmub_srv->dmub, addr, subvp_index);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1177

bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1182

if (!dc_dmub_srv || !dc_dmub_srv->dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1185

if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1188

dc_ctx = dc_dmub_srv->ctx;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1191

if (dc_dmub_srv->ctx->dc->debug.disable_timeout) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1193

status = dmub_srv_wait_for_hw_pwr_up(dc_dmub_srv->dmub, 500000);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1196

status = dmub_srv_wait_for_hw_pwr_up(dc_dmub_srv->dmub, 500000);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

120

dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1203

return dmub_srv_is_hw_pwr_up(dc_dmub_srv->dmub);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1225

struct dc_dmub_srv *dc_dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1234

dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1235

ips_fw = &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

124

void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dc_dmub_srv,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1251

&dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER].data.ips_driver;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

127

struct dmub_srv *dmub = dc_dmub_srv->dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

128

struct dc_context *dc_ctx = dc_dmub_srv->ctx;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1325

dc_dmub_srv->driver_signals = ips_driver->signals;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

134

dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1341

dc_dmub_srv->needs_idle_wake = true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1346

struct dc_dmub_srv *dc_dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1355

dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1359

&dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1361

&dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER].data.ips_driver;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1370

dc_dmub_srv->driver_signals = ips_driver->signals;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

138

static bool dc_dmub_srv_reg_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1388

dc_dmub_srv->needs_idle_wake = false;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

147

if (!dc_dmub_srv || !dc_dmub_srv->dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1481

void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_cm_power_state power_state)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1485

if (!dc_dmub_srv)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1488

dmub = dc_dmub_srv->dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1496

void dc_dmub_srv_notify_fw_dc_power_state(struct dc_dmub_srv *dc_dmub_srv,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

150

dc_ctx = dc_dmub_srv->ctx;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1501

if (!dc_dmub_srv)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

151

dmub = dc_dmub_srv->dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1519

dc_wake_and_execute_dmub_cmd(dc_dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1522

bool dc_dmub_srv_should_detect(struct dc_dmub_srv *dc_dmub_srv)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1527

if (!dc_dmub_srv || !dc_dmub_srv->dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1530

if (dc_dmub_srv->dmub->shared_state &&

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1531

dc_dmub_srv->dmub->meta_info.feature_bits.bits.shared_state_link_detection) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1532

ips_fw = &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1537

if (dc_dmub_srv->idle_allowed) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1538

dc_dmub_srv_apply_idle_power_optimizations(dc_dmub_srv->ctx->dc, false);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1542

should_detect = dmub_srv_should_detect(dc_dmub_srv->dmub);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1545

if (!should_detect && reallow_idle && dc_dmub_srv->idle_exit_counter == 0 &&

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1546

!dc_dmub_srv->ctx->dc->debug.disable_dmub_reallow_idle)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1547

dc_dmub_srv_apply_idle_power_optimizations(dc_dmub_srv->ctx->dc, true);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1554

struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1556

if (!dc_dmub_srv || !dc_dmub_srv->dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1561

if (dc_dmub_srv->idle_allowed == allow_idle)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1564

DC_LOG_IPS("%s state change: old=%d new=%d", __func__, dc_dmub_srv->idle_allowed, allow_idle);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

157

} while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1574

dc_dmub_srv->idle_exit_counter += 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1586

dc_dmub_srv->idle_allowed = false;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1588

dc_dmub_srv->idle_exit_counter -= 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1589

if (dc_dmub_srv->idle_exit_counter < 0) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1591

dc_dmub_srv->idle_exit_counter = 0;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1596

dc_dmub_srv->idle_allowed = true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1611

struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1614

if (!dc_dmub_srv || !dc_dmub_srv->dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1620

if (dc_dmub_srv->idle_allowed) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1634

if (result && reallow_idle && dc_dmub_srv->idle_exit_counter == 0 &&

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1644

struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1651

if (!dc_dmub_srv || !dc_dmub_srv->dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1654

status = dmub_srv_send_gpint_command(dc_dmub_srv->dmub, command_code, param, wait_us);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1663

dmub_srv_get_gpint_response(dc_dmub_srv->dmub, response);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1671

struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1674

if (!dc_dmub_srv || !dc_dmub_srv->dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1677

if (dc_dmub_srv->idle_allowed) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1684

if (result && reallow_idle && dc_dmub_srv->idle_exit_counter == 0 &&

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

172

dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

180

static bool dc_dmub_srv_fb_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

189

if (!dc_dmub_srv || !dc_dmub_srv->dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

192

dc_ctx = dc_dmub_srv->ctx;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

193

dmub = dc_dmub_srv->dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1988

bool dmub_lsdma_init(struct dc_dmub_srv *dc_dmub_srv)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1990

struct dc_context *dc_ctx = dc_dmub_srv->ctx;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2014

struct dc_dmub_srv *dc_dmub_srv,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2020

struct dc_context *dc_ctx = dc_dmub_srv->ctx;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2047

struct dc_dmub_srv *dc_dmub_srv,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2051

struct dc_context *dc_ctx = dc_dmub_srv->ctx;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2091

struct dc_dmub_srv *dc_dmub_srv,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2095

struct dc_context *dc_ctx = dc_dmub_srv->ctx;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

212

} while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2142

struct dc_dmub_srv *dc_dmub_srv,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2149

struct dc_context *dc_ctx = dc_dmub_srv->ctx;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2177

struct dc_dmub_srv *dc_dmub_srv,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2183

struct dc_context *dc_ctx = dc_dmub_srv->ctx;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2209

bool dmub_lsdma_send_poll_reg_write_command(struct dc_dmub_srv *dc_dmub_srv, uint32_t reg_addr, uint32_t reg_data)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

221

dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2211

struct dc_context *dc_ctx = dc_dmub_srv->ctx;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2236

struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2239

if (!dc_dmub_srv || !dc_dmub_srv->dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

231

dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

239

bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

245

if (dc_dmub_srv && dc_dmub_srv->dmub) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

246

if (dc_dmub_srv->dmub->inbox_type == DMUB_CMD_INTERFACE_REG) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

247

res = dc_dmub_srv_reg_cmd_list_queue_execute(dc_dmub_srv, count, cmd_list);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

249

res = dc_dmub_srv_fb_cmd_list_queue_execute(dc_dmub_srv, count, cmd_list);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

253

res = dmub_srv_update_inbox_status(dc_dmub_srv->dmub) == DMUB_STATUS_OK;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

259

bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv *dc_dmub_srv,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

266

if (!dc_dmub_srv || !dc_dmub_srv->dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

269

dmub = dc_dmub_srv->dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

275

} while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

283

dmub->debug.timeout_info.timestamp = dm_get_timestamp(dc_dmub_srv->ctx);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

285

dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

291

dmub_srv_cmd_get_response(dc_dmub_srv->dmub, cmd_list);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

298

bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

300

return dc_dmub_srv_cmd_run_list(dc_dmub_srv, 1, cmd, wait_type);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

303

bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

305

if (!dc_dmub_srv_cmd_list_queue_execute(dc_dmub_srv, count, cmd_list))

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

308

return dc_dmub_srv_wait_for_idle(dc_dmub_srv, wait_type, cmd_list);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

311

bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

318

if (!dc_dmub_srv || !dc_dmub_srv->dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

321

dmub = dc_dmub_srv->dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

322

dc_ctx = dc_dmub_srv->ctx;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

333

bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

336

if (!dc_dmub_srv || !dc_dmub_srv->dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

339

return dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

343

bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

350

if (!dc_dmub_srv || !dc_dmub_srv->dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

353

dmub = dc_dmub_srv->dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

354

dc_ctx = dc_dmub_srv->ctx;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

40

#define CTX dc_dmub_srv->ctx

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

44

static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

507

void dc_dmub_srv_query_caps_cmd(struct dc_dmub_srv *dc_dmub_srv)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

51

struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

511

if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

523

if (dc_wake_and_execute_dmub_cmd(dc_dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

525

memcpy(&dc_dmub_srv->dmub->feature_caps,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

53

struct dc_dmub_srv *dc_srv =

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

54

kzalloc(sizeof(struct dc_dmub_srv), GFP_KERNEL);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

66

void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

74

bool dc_dmub_srv_wait_for_pending(struct dc_dmub_srv *dc_dmub_srv)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

80

if (!dc_dmub_srv || !dc_dmub_srv->dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

83

dc_ctx = dc_dmub_srv->ctx;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

84

dmub = dc_dmub_srv->dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

88

} while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

92

dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

944

bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

946

if (!dc_dmub_srv || !dc_dmub_srv->dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

948

return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

951

void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

955

if (!dc_dmub_srv || !dc_dmub_srv->dmub) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

962

if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv)) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

968

DC_LOG_DEBUG(" dmcub_version : %08x", dc_dmub_srv->dmub->debug.dmcub_version);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

969

DC_LOG_DEBUG(" scratch [0] : %08x", dc_dmub_srv->dmub->debug.scratch[0]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

970

DC_LOG_DEBUG(" scratch [1] : %08x", dc_dmub_srv->dmub->debug.scratch[1]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

971

DC_LOG_DEBUG(" scratch [2] : %08x", dc_dmub_srv->dmub->debug.scratch[2]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

972

DC_LOG_DEBUG(" scratch [3] : %08x", dc_dmub_srv->dmub->debug.scratch[3]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

973

DC_LOG_DEBUG(" scratch [4] : %08x", dc_dmub_srv->dmub->debug.scratch[4]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

974

DC_LOG_DEBUG(" scratch [5] : %08x", dc_dmub_srv->dmub->debug.scratch[5]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

975

DC_LOG_DEBUG(" scratch [6] : %08x", dc_dmub_srv->dmub->debug.scratch[6]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

976

DC_LOG_DEBUG(" scratch [7] : %08x", dc_dmub_srv->dmub->debug.scratch[7]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

977

DC_LOG_DEBUG(" scratch [8] : %08x", dc_dmub_srv->dmub->debug.scratch[8]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

978

DC_LOG_DEBUG(" scratch [9] : %08x", dc_dmub_srv->dmub->debug.scratch[9]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

979

DC_LOG_DEBUG(" scratch [10] : %08x", dc_dmub_srv->dmub->debug.scratch[10]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

98

void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dc_dmub_srv)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

980

DC_LOG_DEBUG(" scratch [11] : %08x", dc_dmub_srv->dmub->debug.scratch[11]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

981

DC_LOG_DEBUG(" scratch [12] : %08x", dc_dmub_srv->dmub->debug.scratch[12]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

982

DC_LOG_DEBUG(" scratch [13] : %08x", dc_dmub_srv->dmub->debug.scratch[13]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

983

DC_LOG_DEBUG(" scratch [14] : %08x", dc_dmub_srv->dmub->debug.scratch[14]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

984

DC_LOG_DEBUG(" scratch [15] : %08x", dc_dmub_srv->dmub->debug.scratch[15]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

986

DC_LOG_DEBUG(" pc[%d] : %08x", i, dc_dmub_srv->dmub->debug.pc[i]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

987

DC_LOG_DEBUG(" unk_fault_addr : %08x", dc_dmub_srv->dmub->debug.undefined_address_fault_addr);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

988

DC_LOG_DEBUG(" inst_fault_addr : %08x", dc_dmub_srv->dmub->debug.inst_fetch_fault_addr);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

989

DC_LOG_DEBUG(" data_fault_addr : %08x", dc_dmub_srv->dmub->debug.data_write_fault_addr);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

990

DC_LOG_DEBUG(" inbox1_rptr : %08x", dc_dmub_srv->dmub->debug.inbox1_rptr);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

991

DC_LOG_DEBUG(" inbox1_wptr : %08x", dc_dmub_srv->dmub->debug.inbox1_wptr);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

992

DC_LOG_DEBUG(" inbox1_size : %08x", dc_dmub_srv->dmub->debug.inbox1_size);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

993

DC_LOG_DEBUG(" inbox0_rptr : %08x", dc_dmub_srv->dmub->debug.inbox0_rptr);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

994

DC_LOG_DEBUG(" inbox0_wptr : %08x", dc_dmub_srv->dmub->debug.inbox0_wptr);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

995

DC_LOG_DEBUG(" inbox0_size : %08x", dc_dmub_srv->dmub->debug.inbox0_size);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

996

DC_LOG_DEBUG(" outbox1_rptr : %08x", dc_dmub_srv->dmub->debug.outbox1_rptr);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

997

DC_LOG_DEBUG(" outbox1_wptr : %08x", dc_dmub_srv->dmub->debug.outbox1_wptr);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

998

DC_LOG_DEBUG(" outbox1_size : %08x", dc_dmub_srv->dmub->debug.outbox1_size);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

999

DC_LOG_DEBUG(" is_enabled : %d", dc_dmub_srv->dmub->debug.is_dmcub_enabled);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

100

void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

106

void dc_dmub_srv_subvp_save_surf_addr(const struct dc_dmub_srv *dc_dmub_srv, const struct dc_plane_address *addr, uint8_t subvp_index);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

108

bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

121

void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_cm_power_state power_state);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

133

void dc_dmub_srv_notify_fw_dc_power_state(struct dc_dmub_srv *dc_dmub_srv,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

144

bool dc_dmub_srv_should_detect(struct dc_dmub_srv *dc_dmub_srv);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

213

bool dmub_lsdma_init(struct dc_dmub_srv *dc_dmub_srv);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

215

struct dc_dmub_srv *dc_dmub_srv,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

250

struct dc_dmub_srv *dc_dmub_srv,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

254

struct dc_dmub_srv *dc_dmub_srv,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

260

struct dc_dmub_srv *dc_dmub_srv,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

297

struct dc_dmub_srv *dc_dmub_srv,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

299

bool dmub_lsdma_send_poll_reg_write_command(struct dc_dmub_srv *dc_dmub_srv, uint32_t reg_addr, uint32_t reg_data);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

61

bool dc_dmub_srv_wait_for_pending(struct dc_dmub_srv *dc_dmub_srv);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

63

bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

65

bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

69

bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv *dc_dmub_srv,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

73

bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

75

bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

77

bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

80

bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

91

void dc_dmub_srv_query_caps_cmd(struct dc_dmub_srv *dc_dmub_srv);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

93

void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

94

void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

95

void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_data_register data);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

97

bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv);

sys/dev/pci/drm/amd/display/dc/dc_types.h

51

struct dc_dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_types.h

817

struct dc_dmub_srv *dmub_srv;

sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

31

void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv,

sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

53

void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,

sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h

32

void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv,

sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h

37

void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,

sys/dev/pci/drm/amd/display/dc/dce/dmub_outbox.c

39

void dmub_enable_outbox_notification(struct dc_dmub_srv *dmub_srv)

sys/dev/pci/drm/amd/display/dc/dce/dmub_outbox.h

29

struct dc_dmub_srv;

sys/dev/pci/drm/amd/display/dc/dce/dmub_outbox.h

31

void dmub_enable_outbox_notification(struct dc_dmub_srv *dmub_srv);

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

110

if (!dc_wake_and_execute_dmub_cmd(dc_dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

44

struct dc_dmub_srv *dc_dmub_srv = panel_cntl->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

46

if (!dc_dmub_srv)

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

55

return dc_wake_and_execute_dmub_cmd(dc_dmub_srv->ctx, cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

71

struct dc_dmub_srv *dc_dmub_srv = panel_cntl->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

75

if (!dc_dmub_srv)

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

89

if (!dc_wake_and_execute_dmub_cmd(dc_dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

105

struct dc_dmub_srv *dc_dmub_srv = enc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

111

return dc_dmub_srv &&

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

112

!(dc_dmub_srv->dmub->fw_version >= DMUB_FW_VERSION(4, 0, 0) &&

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

113

dc_dmub_srv->dmub->fw_version <= DMUB_FW_VERSION(4, 0, 10));

sys/dev/pci/drm/amd/display/dc/dm_services.h

127

struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dc/dm_services.h

128

void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv);

sys/dev/pci/drm/amd/display/dc/dm_services.h

42

struct dc_dmub_srv;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1862

params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

141

struct dc_dmub_srv *dc_dmub_srv;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia.c

117

struct dc_dmub_srv *dmub_srv = link->ctx->dmub_srv;