cpu_id
cpu_pause_resume(u_long cpu_id, int pause)
u_long cpu_mask = (1UL << cpu_id);
alpha_send_ipi(cpu_id, ALPHA_IPI_PAUSE);
u_long cpu_id = cpu_number();
struct pcs *pcsp = LOCATE_PCS(hwrpb, cpu_id);
atomic_clearbits_ulong(&cpus_running, (1UL << cpu_id));
atomic_clearbits_ulong(&cpus_booted, (1U << cpu_id));
u_long cpu_id = cpu_number();
u_long cpumask = (1UL << cpu_id);
cpu_iccb_send(cpuid_t cpu_id, const char *msg)
struct pcs *pcsp = LOCATE_PCS(hwrpb, cpu_id);
u_long cpumask = (1UL << cpu_id);
cpuid_t cpu_id;
for (cpu_id = 0; cpu_id < hwrpb->rpb_pcs_cnt; cpu_id++) {
if (txrdy & (1UL << cpu_id)) {
pcsp = LOCATE_PCS(hwrpb, cpu_id);
cpu_id, pcsp->pcs_halt_reason, pcsp->pcs_flags);
printf("Message from CPU %lu: %s\n", cpu_id, buf);
if (cpu_id >= hwrpb->rpb_pcs_cnt ||
cpu_info[cpu_id] == NULL)
if (((1UL << cpu_id) & cpus_running) == 0)
panic("alpha_send_ipi: CPU %ld not running", cpu_id);
atomic_setbits_ulong(&cpu_info[cpu_id]->ci_ipis, ipimask);
alpha_pal_wripir(cpu_id);
u_long cpu_id = cpu_number();
cpumask = cpus_running & ~(1UL << cpu_id);
u_long cpu_id = cpu_number();
cpumask &= ~(1UL << cpu_id);
alpha_send_ipi(u_long cpu_id, u_long ipimask)
cpuid_t cpu_id;
cpu_id = cpu_number();
cpu_info[cpu_id] = &cpu_info_primary;
ci->ci_cpuid = cpu_id;
cpuid_t cpu_id = cpu_number();
l3pte, TRUE, cpu_id);
cpu_id);
saved_l3pte, cpu_id);
cpuid_t cpu_id = cpu_number();
PMAP_ISACTIVE(pv->pv_pmap, cpu_id), cpu_id);
FALSE, cpu_id) == TRUE) {
cpuid_t cpu_id = cpu_number();
isactive = PMAP_ISACTIVE(pmap, cpu_id);
isactive, cpu_id);
cpuid_t cpu_id = cpu_number();
isactive = PMAP_ISACTIVE(pmap, cpu_id);
needisync |= pmap_remove_mapping(pmap, va, pte, TRUE, cpu_id);
pmap_l3pt_delref(pmap, va, pte, cpu_id);
PMAP_INVALIDATE_TLB(pmap, va, hadasm, isactive, cpu_id);
cpuid_t cpu_id = cpu_number();
PMAP_INVALIDATE_TLB(pmap, va, TRUE, TRUE, cpu_id);
cpuid_t cpu_id = cpu_number();
PMAP_INVALIDATE_TLB(pmap, va, TRUE, TRUE, cpu_id);
cpuid_t cpu_id = cpu_number();
atomic_setbits_ulong(&pmap->pm_cpus, (1UL << cpu_id));
pmap_asn_alloc(pmap, cpu_id);
PMAP_ACTIVATE(pmap, p, cpu_id);
cpuid_t cpu_id = cpu_number();
pmap_changebit(pg, PG_FOW, ~0, cpu_id);
cpuid_t cpu_id = cpu_number();
pmap_changebit(pg, PG_FOR | PG_FOW | PG_FOE, ~0, cpu_id);
boolean_t dolock, cpuid_t cpu_id)
pmap, va, pte, dolock, cpu_id);
isactive = PMAP_ISACTIVE(pmap, cpu_id);
PMAP_INVALIDATE_TLB(pmap, va, hadasm, isactive, cpu_id);
pmap_l3pt_delref(pmap, va, pte, cpu_id);
pmap_changebit(struct vm_page *pg, u_long set, u_long mask, cpuid_t cpu_id)
isactive = PMAP_ISACTIVE(pv->pv_pmap, cpu_id);
cpu_id);
cpuid_t cpu_id = cpu_number();
pmap_changebit(pg, 0, ~faultoff, cpu_id);
pmap_lev1map_create(pmap_t pmap, cpuid_t cpu_id)
KASSERT(pmap->pm_asni[cpu_id].pma_asn == PMAP_ASN_RESERVED);
pmap_l3pt_delref(pmap_t pmap, vaddr_t va, pt_entry_t *l3pte, cpuid_t cpu_id)
PMAP_ISACTIVE(pmap, cpu_id), cpu_id);
pmap_asn_alloc(pmap_t pmap, cpuid_t cpu_id)
struct pmap_asn_info *pma = &pmap->pm_asni[cpu_id];
struct pmap_asn_info *cpma = &pmap_asn_info[cpu_id];
atomic_clearbits_ulong(&pmap->pm_needisync, (1UL << cpu_id));
u_long cpu_id = ci->ci_cpuid;
u_long cpu_mask = (1UL << cpu_id);
struct pmap_tlb_shootdown_q *pq = &pmap_tlb_shootdown_q[cpu_id];
pj->pj_pmap->pm_cpus & cpu_mask, cpu_id);
#define PMAP_ISACTIVE_TEST(pm, cpu_id) \
(((pm)->pm_cpus & (1UL << (cpu_id))) != 0)
#define PMAP_ISACTIVE(pm, cpu_id) \
int isactive_ = PMAP_ISACTIVE_TEST(pm, cpu_id); \
#define PMAP_ISACTIVE(pm, cpu_id) PMAP_ISACTIVE_TEST(pm, cpu_id)
#define PMAP_ACTIVATE_ASN_SANITY(pmap, cpu_id) \
struct pmap_asn_info *__pma = &(pmap)->pm_asni[(cpu_id)]; \
struct pmap_asn_info *__cpma = &pmap_asn_info[(cpu_id)]; \
#define PMAP_ACTIVATE_ASN_SANITY(pmap, cpu_id) /* nothing */
#define PMAP_ACTIVATE(pmap, p, cpu_id) \
PMAP_ACTIVATE_ASN_SANITY(pmap, cpu_id); \
(pmap)->pm_asni[(cpu_id)].pma_asn; \
#define PMAP_INVALIDATE_ASN(pmap, cpu_id) \
(pmap)->pm_asni[(cpu_id)].pma_asn = PMAP_ASN_RESERVED; \
#define PMAP_INVALIDATE_TLB(pmap, va, hadasm, isactive, cpu_id) \
} else if ((pmap)->pm_asni[(cpu_id)].pma_asngen == \
pmap_asn_info[(cpu_id)].pma_asngen) { \
PMAP_INVALIDATE_ASN((pmap), (cpu_id)); \
alpha_pal_wripir(unsigned long cpu_id)
register unsigned long a0 __asm("$16") = cpu_id;
int cpu_id = 0; /* cpuid(1).eax */
ci->ci_signature = cpu_id;
if (mpi->ioapic == NULL && (mpi->cpu_id == MPS_ALL_APICS
|| mpi->cpu_id == ci->ci_apicid)) {
{ CPU_CPUID, &cpu_id, SYSCTL_INT_READONLY },
mpi->cpu_id = id;
family = (cpu_id >> 8) & 0xf;
model = (cpu_id >> 4) & 0xf;
step = (cpu_id >> 0) & 0xf;
#define usepctr ((pctr_isamd && ((cpu_id >> 8) & 15) >= 6) || \
*rax = cpu_id;
extern int cpu_id;
int cpu_id;
family = (cpu_id >> 8) & 0xf;
model = (cpu_id >> 4) & 0xf;
switch (cpu_id & 0xf00) {
if (mpi->ioapic == NULL && (mpi->cpu_id == MPS_ALL_APICS
|| mpi->cpu_id == ci->ci_apicid)) {
i386_cpuid_cpus[i].cpu_id, 12)) {
token = cpup->cpu_id;
{ CPU_CPUID, &cpu_id, SYSCTL_INT_READONLY },
caa.cpu_signature = cpu_id;
mpi->cpu_id = id;
caa.cpu_signature = cpu_id;
family = (cpu_id >> 8) & 0xf;
model = (cpu_id >> 4) & 0xf;
step = (cpu_id >> 0) & 0xf;
#define usep5ctr (pctr_isintel && (((cpu_id >> 8) & 15) == 5) && \
(((cpu_id >> 4) & 15) > 0))
#define usepctr ((pctr_isamd && ((cpu_id >> 8) & 15) >= 6) || \
const char *cpu_id;
extern int cpu_id;
int cpu_id;
extern int cpu_id, cpu_feature;
caa.cpu_signature = cpu_id;
extern int cpu_id, cpu_feature;
caa.cpu_signature = cpu_id;
map->cpu_id = lapic_map[entry->madt_lapic_nmi.acpi_proc_id];
self->dv_xname, map->cpu_id);
int mib[2], cpu_id, cpu_feature;
len = sizeof(cpu_id);
if (sysctl(mib, 2, &cpu_id, &len, NULL, 0) == -1)
if (((cpu_id >> 8) & 15) >= 6)
if (((cpu_id >> 8) & 15) == 6 &&
((cpu_id >> 4) & 15) > 14)
else if (((cpu_id >> 8) & 15) >= 6)
else if (((cpu_id >> 4) & 15) > 0)