core
pci_1000_pickintr(void *core, bus_space_tag_t iot, bus_space_tag_t memt,
pc->pc_intr_v = core;
pci_1000a_pickintr(void *core, bus_space_tag_t iot, bus_space_tag_t memt,
pc->pc_intr_v = core;
REGVAL32(LS3_IPI_BASE(node, core) + LS3_IPI_IMR) = 0u;
int core, node;
for (core = 0; core < 4; core++)
#define LS3_IRT_ROUTE(core, intr) ((0x01 << (core)) | (0x10 << (intr)))
#define POW_PP_GRP_MSK_OFFSET(core) (0x0ULL + (core) * 8)
int core = ci->ci_cpuid;
CIU3_WR_8(sc, CIU3_IDT_CTL(CIU3_IDT(core, 0)), 0);
CIU3_WR_8(sc, CIU3_IDT_PP(CIU3_IDT(core, 0)), 1ul << core);
CIU3_WR_8(sc, CIU3_IDT_IO(CIU3_IDT(core, 0)), 0);
CIU3_WR_8(sc, CIU3_IDT_CTL(CIU3_IDT(core , 1)), 1);
CIU3_WR_8(sc, CIU3_IDT_PP(CIU3_IDT(core, 1)), 1ul << core);
CIU3_WR_8(sc, CIU3_IDT_IO(CIU3_IDT(core, 1)), 0);
CIU3_WR_8(sc, CIU3_IDT_CTL(CIU3_IDT(core, 2)), 0);
CIU3_WR_8(sc, CIU3_IDT_PP(CIU3_IDT(core, 2)), 0);
CIU3_WR_8(sc, CIU3_IDT_IO(CIU3_IDT(core, 2)), 0);
CIU3_WR_8(sc, CIU3_IDT_CTL(CIU3_IDT(core, 3)), 0);
CIU3_WR_8(sc, CIU3_IDT_PP(CIU3_IDT(core, 3)), 0);
CIU3_WR_8(sc, CIU3_IDT_IO(CIU3_IDT(core, 3)), 0);
unsigned int core = ci->ci_cpuid;
CIU3_WR_8(sc, CIU3_IDT_PP(CIU3_IDT(core, 0)), 0);
(void)CIU3_RD_8(sc, CIU3_IDT_PP(CIU3_IDT(core, 0)));
destpp = CIU3_RD_8(sc, CIU3_DEST_PP_INT(core));
#define CIU3_IDT(core, ipl) ((core) * 4 + (ipl))
#define CIU3_DEST_PP_INT(core) ((core) * 8 + 0x200000u)
unsigned int core = ci->ci_cpuid;
CIU3_WR_8(sc, CIU3_IDT_PP(CIU3_IDT(core, 0)), 1ul << core);
(void)CIU3_RD_8(sc, CIU3_IDT_PP(CIU3_IDT(core, 0)));
#define MBOX_INTSN(core) ((core) + 0x4000u)
#define SSO_PP_GRPMSK(core, set, i) (0x40001000ULL + (core) * 0x10000 + \
LIST_FOREACH_SAFE(core, &sc->sc_chip.ch_list, co_link, tmp) {
LIST_REMOVE(core, co_link);
free(core, M_DEVBUF, sizeof(*core));
struct bwfm_core *core;
LIST_FOREACH(core, &sc->sc_chip.ch_list, co_link) {
if (core->co_id == id && idx-- == 0)
return core;
bwfm_chip_ai_isup(struct bwfm_softc *sc, struct bwfm_core *core)
core->co_wrapbase + BWFM_AGENT_IOCTL);
core->co_wrapbase + BWFM_AGENT_RESET_CTL);
bwfm_chip_ai_disable(struct bwfm_softc *sc, struct bwfm_core *core,
core->co_wrapbase + BWFM_AGENT_RESET_CTL);
core->co_wrapbase + BWFM_AGENT_IOCTL,
core->co_wrapbase + BWFM_AGENT_IOCTL);
core->co_wrapbase + BWFM_AGENT_RESET_CTL,
core->co_wrapbase + BWFM_AGENT_RESET_CTL) ==
core->co_wrapbase + BWFM_AGENT_IOCTL,
core->co_wrapbase + BWFM_AGENT_IOCTL);
bwfm_chip_ai_reset(struct bwfm_softc *sc, struct bwfm_core *core,
bwfm_chip_ai_disable(sc, core, prereset, reset);
core->co_wrapbase + BWFM_AGENT_RESET_CTL) &
core->co_wrapbase + BWFM_AGENT_RESET_CTL, 0);
core->co_wrapbase + BWFM_AGENT_IOCTL,
core->co_wrapbase + BWFM_AGENT_IOCTL);
struct bwfm_core *core;
core = malloc(sizeof(*core), M_DEVBUF, M_WAITOK);
core->co_id = id;
core->co_base = base;
core->co_wrapbase = wrap;
core->co_rev = rev;
LIST_INSERT_HEAD(&sc->sc_chip.ch_list, core, co_link);
struct bwfm_core *core;
core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_ARM_CR4);
sc->sc_chip.ch_core_reset(sc, core,
struct bwfm_core *core;
core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_ARM_CR4);
core->co_wrapbase + BWFM_AGENT_IOCTL);
sc->sc_chip.ch_core_reset(sc, core,
while ((core = bwfm_chip_get_core_idx(sc, BWFM_AGENT_CORE_80211, i++)))
sc->sc_chip.ch_core_disable(sc, core,
struct bwfm_core *core;
core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_ARM_CA7);
sc->sc_chip.ch_core_reset(sc, core,
struct bwfm_core *core;
core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_ARM_CA7);
core->co_wrapbase + BWFM_AGENT_IOCTL);
sc->sc_chip.ch_core_reset(sc, core,
while ((core = bwfm_chip_get_core_idx(sc, BWFM_AGENT_CORE_80211, i++)))
sc->sc_chip.ch_core_disable(sc, core,
struct bwfm_core *core;
core = bwfm_chip_get_core(sc, BWFM_AGENT_INTERNAL_MEM);
if (!sc->sc_chip.ch_core_isup(sc, core))
core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_ARM_CM3);
sc->sc_chip.ch_core_reset(sc, core, 0, 0, 0);
struct bwfm_core *core;
core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_ARM_CM3);
sc->sc_chip.ch_core_disable(sc, core, 0, 0);
core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_80211);
sc->sc_chip.ch_core_reset(sc, core, BWFM_AGENT_D11_IOCTL_PHYRESET |
core = bwfm_chip_get_core(sc, BWFM_AGENT_INTERNAL_MEM);
sc->sc_chip.ch_core_reset(sc, core, 0, 0, 0);
core->co_base + BWFM_SOCRAM_BANKIDX, 3);
core->co_base + BWFM_SOCRAM_BANKPDA, 0);
struct bwfm_core *core;
core = bwfm_chip_get_pmu(sc);
sc->sc_buscore_ops->bc_write(sc, core->co_base +
reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +
core = bwfm_chip_get_pmu(sc);
sc->sc_buscore_ops->bc_write(sc, core->co_base +
reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +
core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_CHIPCOMMON);
reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +
core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_CHIPCOMMON);
reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +
core = bwfm_chip_get_pmu(sc);
reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +
core = bwfm_chip_get_pmu(sc);
reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +
reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +
bwfm_chip_socram_ramsize(struct bwfm_softc *sc, struct bwfm_core *core)
if (!sc->sc_chip.ch_core_isup(sc, core))
sc->sc_chip.ch_core_reset(sc, core, 0, 0, 0);
core->co_base + BWFM_SOCRAM_COREINFO);
if (core->co_rev <= 7 || core->co_rev == 12) {
core->co_base + BWFM_SOCRAM_BANKIDX,
core->co_base + BWFM_SOCRAM_BANKINFO);
bwfm_chip_sysmem_ramsize(struct bwfm_softc *sc, struct bwfm_core *core)
if (!sc->sc_chip.ch_core_isup(sc, core))
sc->sc_chip.ch_core_reset(sc, core, 0, 0, 0);
core->co_base + BWFM_SOCRAM_COREINFO);
core->co_base + BWFM_SOCRAM_BANKIDX,
core->co_base + BWFM_SOCRAM_BANKINFO);
bwfm_chip_tcm_ramsize(struct bwfm_softc *sc, struct bwfm_core *core)
cap = sc->sc_buscore_ops->bc_read(sc, core->co_base + BWFM_ARMCR4_CAP);
core->co_base + BWFM_ARMCR4_BANKIDX, i);
core->co_base + BWFM_ARMCR4_BANKINFO);
struct bwfm_core *core;
LIST_FOREACH(core, &sc->sc_chip.ch_list, co_link) {
DEVNAME(sc), core->co_id, core->co_rev,
core->co_base, core->co_wrapbase));
switch (core->co_id) {
if ((core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_ARM_CR4)) != NULL) {
bwfm_chip_tcm_ramsize(sc, core);
} else if ((core = bwfm_chip_get_core(sc, BWFM_AGENT_SYS_MEM)) != NULL) {
bwfm_chip_sysmem_ramsize(sc, core);
} else if ((core = bwfm_chip_get_core(sc, BWFM_AGENT_INTERNAL_MEM)) != NULL) {
bwfm_chip_socram_ramsize(sc, core);
core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_CHIPCOMMON);
core->co_base + BWFM_CHIP_REG_CAPABILITIES);
core->co_base + BWFM_CHIP_REG_CAPABILITIES_EXT);
core = bwfm_chip_get_pmu(sc);
core->co_base + BWFM_CHIP_REG_PMUCAPABILITIES);
struct bwfm_core *core, *tmp;
struct dml2_core_instance *core = in_out->instance;
core->minimum_clock_table = in_out->minimum_clock_table;
memcpy(&core->clean_me_up.mode_lib.ip, in_out->explicit_ip_bb, in_out->explicit_ip_bb_size);
core->clean_me_up.mode_lib.ip.subvp_pstate_allow_width_us = core_dcn4_ip_caps_base.subvp_pstate_allow_width_us;
core->clean_me_up.mode_lib.ip.subvp_fw_processing_delay_us = core_dcn4_ip_caps_base.subvp_pstate_allow_width_us;
core->clean_me_up.mode_lib.ip.subvp_swath_height_margin_lines = core_dcn4_ip_caps_base.subvp_swath_height_margin_lines;
memcpy(&core->clean_me_up.mode_lib.ip, &core_dcn4_ip_caps_base, sizeof(struct dml2_core_ip_params));
patch_ip_params_with_ip_caps(&core->clean_me_up.mode_lib.ip, in_out->ip_caps);
core->clean_me_up.mode_lib.ip.imall_supported = false;
memcpy(&core->clean_me_up.mode_lib.soc, in_out->soc_bb, sizeof(struct dml2_soc_bb));
memcpy(&core->clean_me_up.mode_lib.ip_caps, in_out->ip_caps, sizeof(struct dml2_ip_capabilities));
static void pack_mode_programming_params_with_implicit_subvp(struct dml2_core_instance *core, const struct display_configuation_with_meta *display_cfg,
dml2_core_calcs_get_arb_params(&display_cfg->display_config, &core->clean_me_up.mode_lib, &programming->global_regs.arb_regs);
dml2_core_calcs_get_watermarks(&display_cfg->display_config, &core->clean_me_up.mode_lib, &programming->global_regs.wm_regs[0]);
dml2_core_calcs_get_global_fams2_programming(&core->clean_me_up.mode_lib, display_cfg, &programming->fams2_global_config);
programming->plane_programming[plane_index].num_dpps_required = core->clean_me_up.mode_lib.mp.NoOfDPP[plane_index];
dml2_core_calcs_get_mall_allocation(&core->clean_me_up.mode_lib, &programming->plane_programming[plane_index].surface_size_mall_bytes, dml_internal_pipe_index);
dml2_core_calcs_get_pipe_regs(svp_expanded_display_cfg, &core->clean_me_up.mode_lib, programming->plane_programming[plane_index].pipe_regs[pipe_offset], dml_internal_pipe_index);
dml2_core_calcs_get_stream_programming(&core->clean_me_up.mode_lib, &programming->stream_programming[main_plane->stream_index], dml_internal_pipe_index);
dml2_core_calcs_get_stream_fams2_programming(&core->clean_me_up.mode_lib,
dml2_core_calcs_get_mall_allocation(&core->clean_me_up.mode_lib, &programming->plane_programming[main_plane_index].svp_size_mall_bytes, dml_internal_pipe_index);
dml2_core_calcs_get_pipe_regs(svp_expanded_display_cfg, &core->clean_me_up.mode_lib, programming->plane_programming[main_plane_index].phantom_plane.pipe_regs[pipe_offset], dml_internal_pipe_index);
dml2_core_calcs_get_global_sync_programming(&core->clean_me_up.mode_lib, &programming->stream_programming[main_plane->stream_index].phantom_stream.global_sync, dml_internal_pipe_index);
struct dml2_core_instance *core = (struct dml2_core_instance *)in_out->instance;
struct dml2_core_mode_support_locals *l = &core->scratch.mode_support_locals;
expand_implict_subvp(in_out->display_cfg, &l->svp_expanded_display_cfg, &core->scratch);
l->mode_support_ex_params.mode_lib = &core->clean_me_up.mode_lib;
in_out->mode_support_result.global.dispclk_khz = (unsigned int)(core->clean_me_up.mode_lib.ms.RequiredDISPCLK * 1000);
in_out->mode_support_result.global.dcfclk_deepsleep_khz = (unsigned int)(core->clean_me_up.mode_lib.ms.dcfclk_deepsleep * 1000);
in_out->mode_support_result.global.socclk_khz = (unsigned int)(core->clean_me_up.mode_lib.ms.SOCCLK * 1000);
in_out->mode_support_result.global.active.fclk_khz = (unsigned long)(core->clean_me_up.mode_lib.ms.FabricClock * 1000);
in_out->mode_support_result.global.active.dcfclk_khz = (unsigned long)(core->clean_me_up.mode_lib.ms.DCFCLK * 1000);
in_out->mode_support_result.global.svp_prefetch.fclk_khz = (unsigned long)core->clean_me_up.mode_lib.ms.FabricClock * 1000;
in_out->mode_support_result.global.svp_prefetch.dcfclk_khz = (unsigned long)core->clean_me_up.mode_lib.ms.DCFCLK * 1000;
in_out->mode_support_result.per_plane[i].dppclk_khz = (unsigned int)(core->clean_me_up.mode_lib.ms.RequiredDPPCLK[i] * 1000);
dml2_core_calcs_get_plane_support_info(&l->svp_expanded_display_cfg, &core->clean_me_up.mode_lib, &in_out->mode_support_result.cfg_support_info.plane_support_info[i], i);
in_out->mode_support_result.per_stream[stream_index].dscclk_khz = (unsigned int)core->clean_me_up.mode_lib.ms.required_dscclk_freq_mhz[i] * 1000;
dml2_core_calcs_get_stream_support_info(&l->svp_expanded_display_cfg, &core->clean_me_up.mode_lib, &in_out->mode_support_result.cfg_support_info.stream_support_info[stream_index], i);
in_out->mode_support_result.per_stream[stream_index].dtbclk_khz = (unsigned int)(core->clean_me_up.mode_lib.ms.RequiredDTBCLK[i] * 1000);
struct dml2_core_instance *core = (struct dml2_core_instance *)in_out->instance;
struct dml2_core_mode_programming_locals *l = &core->scratch.mode_programming_locals;
expand_implict_subvp(in_out->display_cfg, &l->svp_expanded_display_cfg, &core->scratch);
l->mode_programming_ex_params.mode_lib = &core->clean_me_up.mode_lib;
&core->clean_me_up.mode_lib.soc);
pack_mode_programming_params_with_implicit_subvp(core, in_out->display_cfg, &l->svp_expanded_display_cfg, in_out->programming, &core->scratch);
dml2_core_calcs_get_arb_params(&l->svp_expanded_display_cfg, &core->clean_me_up.mode_lib, &in_out->programming->global_regs.arb_regs);
dml2_core_calcs_get_watermarks(&l->svp_expanded_display_cfg, &core->clean_me_up.mode_lib, &in_out->programming->global_regs.wm_regs[0]);
in_out->programming->plane_programming[plane_index].num_dpps_required = core->clean_me_up.mode_lib.mp.NoOfDPP[plane_index];
if (core->clean_me_up.mode_lib.mp.MaxActiveDRAMClockChangeLatencySupported[plane_index] >= core->clean_me_up.mode_lib.soc.power_management_parameters.dram_clk_change_blackout_us)
else if (core->clean_me_up.mode_lib.mp.TWait[plane_index] >= core->clean_me_up.mode_lib.soc.power_management_parameters.dram_clk_change_blackout_us)
dml2_core_calcs_get_mall_allocation(&core->clean_me_up.mode_lib, &in_out->programming->plane_programming[plane_index].surface_size_mall_bytes, dml_internal_pipe_index);
dml2_core_calcs_get_pipe_regs(&l->svp_expanded_display_cfg, &core->clean_me_up.mode_lib, in_out->programming->plane_programming[plane_index].pipe_regs[pipe_offset], dml_internal_pipe_index);
dml2_core_calcs_get_stream_programming(&core->clean_me_up.mode_lib, &in_out->programming->stream_programming[main_stream_index], dml_internal_pipe_index);
const struct dml2_core_internal_display_mode_lib *mode_lib = &in_out->core->clean_me_up.mode_lib;
l->dppm_map_watermarks_params.core = &dml->core_instance;
const struct dml2_core_instance *core;
#define DDI_POWERGATING_ARG(phyID, lanemask, rx, tx, core) \
((core) ? DISPLAYPHY_CORE_SELECT : 0))
int dptxport_connect(struct apple_epic_service *service, u8 core, u8 atc,
u32 target = FIELD_PREP(DCPDPTX_REMOTE_PORT_CORE, core) |
trace_dptxport_connect(dptx, core, atc, die);
int dptxport_validate_connection(struct apple_epic_service *service, u8 core,
u32 target = FIELD_PREP(DCPDPTX_REMOTE_PORT_CORE, core) |
trace_dptxport_validate_connection(dptx, core, atc, die);
int dptxport_validate_connection(struct apple_epic_service *service, u8 core,
int dptxport_connect(struct apple_epic_service *service, u8 core, u8 atc,
TP_PROTO(struct dptx_port *dptx, u8 core, u8 atc, u8 die),
TP_ARGS(dptx, core, atc, die),
__field(u32, unit) __field(u8, core) __field(u8, atc) __field(u8, die)),
__entry->unit = dptx->unit; __entry->core = core; __entry->atc = atc; __entry->die = die;),
__entry->unit, __entry->core, __entry->atc, __entry->die));
TP_PROTO(struct dptx_port *dptx, u8 core, u8 atc, u8 die),
TP_ARGS(dptx, core, atc, die),
__field(u32, unit) __field(u8, core) __field(u8, atc) __field(u8, die)),
__entry->unit = dptx->unit; __entry->core = core; __entry->atc = atc; __entry->die = die;),
__entry->unit, __entry->core, __entry->atc, __entry->die));
struct bwfm_core *core;
core = bwfm_chip_get_core(bwfm, coreid);
if (core == NULL)
page = (core->co_base + base) & ~(BWFM_PCI_BAR0_REG_SIZE - 1);
offset = (core->co_base + base) & (BWFM_PCI_BAR0_REG_SIZE - 1);
struct bwfm_core *core;
core = bwfm_chip_get_core(bwfm, id);
if (core == NULL) {
BWFM_PCI_BAR0_WINDOW, core->co_base);
BWFM_PCI_BAR0_WINDOW) != core->co_base)
BWFM_PCI_BAR0_WINDOW, core->co_base);
struct bwfm_core *core;
core = bwfm_chip_get_core(bwfm, BWFM_AGENT_CORE_PCIE2);
if (core->co_rev <= 13) {
if (core->co_rev >= 64)
struct bwfm_core *core;
core = bwfm_chip_get_core(bwfm, BWFM_AGENT_CORE_PCIE2);
if (core->co_rev <= 13)
struct bwfm_core *core;
core = bwfm_chip_get_core(bwfm, BWFM_AGENT_INTERNAL_MEM);
bwfm->sc_chip.ch_core_reset(bwfm, core, 0, 0, 0);
struct bwfm_core *core;
core = bwfm_chip_get_core(&sc->sc_sc, BWFM_AGENT_CORE_SDIO_DEV);
if (core->co_rev >= 12) {
core = bwfm_chip_get_pmu(&sc->sc_sc);
bwfm_sdio_write_4(sc, core->co_base + BWFM_CHIP_REG_PMUCONTROL,
bwfm_sdio_read_4(sc, core->co_base + BWFM_CHIP_REG_PMUCONTROL) |
struct bwfm_core *core;
core = bwfm_chip_get_core(&sc->sc_sc, BWFM_AGENT_CORE_SDIO_DEV);
return bwfm_sdio_read_4(sc, core->co_base + reg);
struct bwfm_core *core;
core = bwfm_chip_get_core(&sc->sc_sc, BWFM_AGENT_CORE_SDIO_DEV);
bwfm_sdio_write_4(sc, core->co_base + reg, val);
char *core = NULL, *namelist = NULL;
core = optarg;
if (namelist == NULL && core == NULL) {
if ((kd = kvm_openfiles(namelist, core, NULL, O_RDONLY,
typedef struct core core;
struct core *next;
struct core *link;
extern core *first_state;
extern core **state_table;
core *sp;
state_table = NEW2(nstates, core *);
core *sp;
core **state_table;
state_set = NEW2(nitems, core *);
core *sp;
core *p;
p = malloc(sizeof(core) + i * sizeof(short));
core *
core *p;
p = allocate(sizeof(core) + (n - 1) * sizeof(short));
core *first_state;
core *new_state(int);
static core **state_set;
static core *this_state;
static core *last_state;
core *cp, *next;
core *statep;
pri_link_core(struct md *md, struct md_node *node, struct core *core)
pri_link_core(md, node2, core);
cpu->core = core;
struct core *core;
core = xzalloc(sizeof(*core));
TAILQ_INSERT_TAIL(&cores, core, link);
pri_link_core(md, node, core);
TAILQ_ENTRY(core) link;
TAILQ_HEAD(, core) cores;
if (cpu->core->guests[i] == cpu->guest) {
if (cpu->core->guests[i] == NULL) {
cpu->core->guests[i] = cpu->guest;
struct core;
struct core *core;
char *sys = NULL, *core = NULL, *cp, errbuf[_POSIX2_LINE_MAX];
core = optarg;
if (core != NULL || sys != NULL)
kd = kvm_openfiles(sys, core, NULL, O_RDONLY, errbuf);
if (core == NULL && sys == NULL)