Symbol: clk_src_regs
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
1022
dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
1024
dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
1026
dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
1031
dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
1034
dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
1036
dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
330
static const struct dce110_clk_src_regs clk_src_regs[] = {
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
331
clk_src_regs(0),
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
332
clk_src_regs(1),
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
333
clk_src_regs(2)
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
1393
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
1396
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
365
static const struct dce110_clk_src_regs clk_src_regs[] = {
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
366
clk_src_regs(0),
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
367
clk_src_regs(1),
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
368
clk_src_regs(2)
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
1260
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
1265
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
1270
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
1275
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
1280
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
1285
&clk_src_regs[5], false);
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
1290
CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
370
static const struct dce110_clk_src_regs clk_src_regs[] = {
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
371
clk_src_regs(0, A),
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
372
clk_src_regs(1, B),
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
373
clk_src_regs(2, C),
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
374
clk_src_regs(3, D),
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
375
clk_src_regs(4, E),
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
376
clk_src_regs(5, F)
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
1101
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
1105
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
1109
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
1113
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
1117
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
1121
&clk_src_regs[5], false);
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
1127
&clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
409
static const struct dce110_clk_src_regs clk_src_regs[] = {
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
410
clk_src_regs(0, A),
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
411
clk_src_regs(1, B),
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
412
clk_src_regs(2, C),
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
413
clk_src_regs(3, D),
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
414
clk_src_regs(4, E),
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
415
clk_src_regs(5, F)
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1124
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1126
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1128
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1133
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1136
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1138
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1323
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1325
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1330
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1333
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1335
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
354
static const struct dce110_clk_src_regs clk_src_regs[] = {
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
355
clk_src_regs(0),
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
356
clk_src_regs(1),
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
357
clk_src_regs(2)
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
928
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
930
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
935
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
938
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
940
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1136
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1138
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1140
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1145
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1148
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1150
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1337
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1339
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1344
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1347
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
356
static const struct dce110_clk_src_regs clk_src_regs[] = {
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
357
clk_src_regs(0),
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
358
clk_src_regs(1),
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
359
clk_src_regs(2)
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
936
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
938
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
940
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
945
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
948
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
950
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1409
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1413
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1417
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1423
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1435
&clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
474
static const struct dce110_clk_src_regs clk_src_regs[] = {
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
475
clk_src_regs(0, A),
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
476
clk_src_regs(1, B),
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
477
clk_src_regs(2, C),
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
478
clk_src_regs(3, D)
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
193
static const struct dce110_clk_src_regs clk_src_regs[] = {
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
194
clk_src_regs(0, A),
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
195
clk_src_regs(1, B),
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
196
clk_src_regs(2, C),
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
197
clk_src_regs(3, D),
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
198
clk_src_regs(4, E),
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
199
clk_src_regs(5, F)
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2493
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2497
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2501
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2505
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2509
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2513
&clk_src_regs[5], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2519
&clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
1167
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
1171
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
1179
&clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
310
static const struct dce110_clk_src_regs clk_src_regs[] = {
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
311
clk_src_regs(0, A),
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
312
clk_src_regs(1, B)
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1476
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1480
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1484
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1488
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1492
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1500
&clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
152
static const struct dce110_clk_src_regs clk_src_regs[] = {
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
153
clk_src_regs(0, A),
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
154
clk_src_regs(1, B),
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
155
clk_src_regs(2, C),
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
156
clk_src_regs(3, D),
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
157
clk_src_regs(4, E),
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
200
static const struct dce110_clk_src_regs clk_src_regs[] = {
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
201
clk_src_regs(0, A),
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
202
clk_src_regs(1, B),
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
203
clk_src_regs(2, C),
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
204
clk_src_regs(3, D),
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
205
clk_src_regs(4, E),
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
206
clk_src_regs(5, F)
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2393
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2397
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2401
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2405
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2409
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2413
&clk_src_regs[5], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2421
&clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1517
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1521
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1525
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1529
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1537
&clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
203
static const struct dce110_clk_src_regs clk_src_regs[] = {
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
204
clk_src_regs(0, A),
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
205
clk_src_regs(1, B),
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
206
clk_src_regs(2, C),
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
207
clk_src_regs(3, D)
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1309
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1313
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1317
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1321
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1325
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1333
&clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
426
static const struct dce110_clk_src_regs clk_src_regs[] = {
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
427
clk_src_regs(0, A),
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
428
clk_src_regs(1, B),
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
429
clk_src_regs(2, C),
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
430
clk_src_regs(3, D),
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
431
clk_src_regs(4, E)
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
1253
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
1257
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
1265
&clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
413
static const struct dce110_clk_src_regs clk_src_regs[] = {
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
414
clk_src_regs(0, A),
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
415
clk_src_regs(1, B)
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1997
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
2001
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
2016
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
2020
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
2026
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
2034
&clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
211
static const struct dce110_clk_src_regs clk_src_regs[] = {
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
212
clk_src_regs(0, A),
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
213
clk_src_regs(1, B),
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
214
clk_src_regs(2, C),
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
215
clk_src_regs(3, D),
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
216
clk_src_regs(4, E)
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
220
clk_src_regs(0, A),
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
221
clk_src_regs(1, B),
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
222
clk_src_regs(2, F),
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
223
clk_src_regs(3, G),
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
224
clk_src_regs(4, E)
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1936
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1940
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1944
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1948
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1952
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1960
&clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
228
static const struct dce110_clk_src_regs clk_src_regs[] = {
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
229
clk_src_regs(0, A),
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
230
clk_src_regs(1, B),
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
231
clk_src_regs(2, C),
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
232
clk_src_regs(3, D),
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
233
clk_src_regs(4, E)
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1958
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1962
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1966
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1970
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1974
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1982
&clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
222
static const struct dce110_clk_src_regs clk_src_regs[] = {
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
223
clk_src_regs(0, A),
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
224
clk_src_regs(1, B),
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
225
clk_src_regs(2, C),
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
226
clk_src_regs(3, D),
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
227
clk_src_regs(4, E)
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1834
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1838
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1842
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1846
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1850
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1858
&clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
208
static const struct dce110_clk_src_regs clk_src_regs[] = {
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
209
clk_src_regs(0, A),
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
210
clk_src_regs(1, B),
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
211
clk_src_regs(2, C),
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
212
clk_src_regs(3, D),
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
213
clk_src_regs(4, E)
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
212
static struct dce110_clk_src_regs clk_src_regs[5];
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2148
#define REG_STRUCT clk_src_regs
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2316
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2320
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2324
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2328
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2332
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2340
&clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1651
#define REG_STRUCT clk_src_regs
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1816
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1820
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1824
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1828
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1832
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1840
&clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
211
static struct dce110_clk_src_regs clk_src_regs[5];
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1822
#define REG_STRUCT clk_src_regs
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1966
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1970
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1974
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1978
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1982
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1990
&clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
224
static struct dce110_clk_src_regs clk_src_regs[5];
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1795
#define REG_STRUCT clk_src_regs
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1938
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1942
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1946
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1950
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1954
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1962
&clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
204
static struct dce110_clk_src_regs clk_src_regs[5];
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1795
#define REG_STRUCT clk_src_regs
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1939
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1943
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1947
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1951
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1955
&clk_src_regs[4], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1963
&clk_src_regs[0], true);
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
209
static struct dce110_clk_src_regs clk_src_regs[5];
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1834
#define REG_STRUCT clk_src_regs
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
196
static struct dce110_clk_src_regs clk_src_regs[5];
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2014
&clk_src_regs[0], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2018
&clk_src_regs[1], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2022
&clk_src_regs[2], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2026
&clk_src_regs[3], false);
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2038
&clk_src_regs[0], true);