Symbol: AFMT_INFOFRAME_CONTROL0
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1642
tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1601
tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1369
REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
639
REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
145
SE_SF(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
59
SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
646
uint32_t AFMT_INFOFRAME_CONTROL0;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c
165
REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c
186
REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h
34
SRI(AFMT_INFOFRAME_CONTROL0, AFMT, id), \
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h
45
uint32_t AFMT_INFOFRAME_CONTROL0;
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h
34
SRI(AFMT_INFOFRAME_CONTROL0, AFMT, id), \
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h
45
uint32_t AFMT_INFOFRAME_CONTROL0;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1359
REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
591
REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
120
uint32_t AFMT_INFOFRAME_CONTROL0;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
45
SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
250
SRI_ARR(AFMT_INFOFRAME_CONTROL0, AFMT, id), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
69
SRI_ARR(AFMT_INFOFRAME_CONTROL0, AFMT, id), \
sys/dev/pci/drm/radeon/evergreen_hdmi.c
361
WREG32(AFMT_INFOFRAME_CONTROL0 + offset,