lib/libc/softfloat/timesoftfloat.c

62

static void reportTime( int32 count, long clocks )

lib/libc/softfloat/timesoftfloat.c

67

( count / ( ( (float) clocks ) / CLOCKS_PER_SEC ) ) / 1000,

sys/arch/armv7/exynos/exclock.c

335

exclock_decode_pll_clk(enum clocks pll, unsigned int r, unsigned int k)

sys/arch/armv7/exynos/exclock.c

385

exclock_get_pll_clk(struct exclock_softc *sc, enum clocks pll)

sys/arch/armv7/exynos/exclock.c

92

uint32_t exclock_decode_pll_clk(enum clocks, unsigned int, unsigned int);

sys/arch/armv7/exynos/exclock.c

93

uint32_t exclock_get_pll_clk(struct exclock_softc *, enum clocks);

sys/dev/fdt/imxesdhc.c

492

uint32_t clocks;

sys/dev/fdt/imxesdhc.c

505

clocks = OF_getpropint(node, "clocks", 0);

sys/dev/fdt/imxesdhc.c

506

if (clocks)

sys/dev/fdt/imxesdhc.c

507

imxesdhc_clock_enable(clocks);

sys/dev/ic/i82596.c

1377

int result, clocks;

sys/dev/ic/i82596.c

1394

clocks = result & IE_TDR_TIME;

sys/dev/ic/i82596.c

1403

sc->sc_dev.dv_xname, clocks, clocks == 1? "":"s");

sys/dev/ic/i82596.c

1406

sc->sc_dev.dv_xname, clocks, clocks == 1? "":"s");

sys/dev/ofw/ofw_clock.c

143

uint32_t *clocks;

sys/dev/ofw/ofw_clock.c

152

clocks = malloc(len, M_TEMP, M_WAITOK);

sys/dev/ofw/ofw_clock.c

153

OF_getpropintarray(node, "clocks", clocks, len);

sys/dev/ofw/ofw_clock.c

155

clock = clocks;

sys/dev/ofw/ofw_clock.c

156

while (clock && clock < clocks + (len / sizeof(uint32_t))) {

sys/dev/ofw/ofw_clock.c

165

free(clocks, M_TEMP, len);

sys/dev/ofw/ofw_clock.c

184

uint32_t *clocks;

sys/dev/ofw/ofw_clock.c

193

clocks = malloc(len, M_TEMP, M_WAITOK);

sys/dev/ofw/ofw_clock.c

194

OF_getpropintarray(node, "clocks", clocks, len);

sys/dev/ofw/ofw_clock.c

196

clock = clocks;

sys/dev/ofw/ofw_clock.c

197

while (clock && clock < clocks + (len / sizeof(uint32_t))) {

sys/dev/ofw/ofw_clock.c

206

free(clocks, M_TEMP, len);

sys/dev/ofw/ofw_clock.c

225

uint32_t *clocks;

sys/dev/ofw/ofw_clock.c

233

clocks = malloc(len, M_TEMP, M_WAITOK);

sys/dev/ofw/ofw_clock.c

234

OF_getpropintarray(node, "clocks", clocks, len);

sys/dev/ofw/ofw_clock.c

236

clock = clocks;

sys/dev/ofw/ofw_clock.c

237

while (clock && clock < clocks + (len / sizeof(uint32_t))) {

sys/dev/ofw/ofw_clock.c

246

free(clocks, M_TEMP, len);

sys/dev/ofw/ofw_clock.c

288

uint32_t *clocks, *parents, *rates;

sys/dev/ofw/ofw_clock.c

299

clock = clocks = malloc(clen, M_TEMP, M_WAITOK);

sys/dev/ofw/ofw_clock.c

300

OF_getpropintarray(node, "assigned-clocks", clocks, clen);

sys/dev/ofw/ofw_clock.c

313

while (clock && clock < clocks + (clen / sizeof(uint32_t))) {

sys/dev/ofw/ofw_clock.c

329

free(clocks, M_TEMP, clen);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

530

static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

536

if (clocks[i] > max)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

537

max = clocks[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

251

cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

252

cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

254

cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

255

cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

520

static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

526

if (clocks[i] > max)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

527

max = clocks[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

535

const uint32_t clocks[],

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

544

return clocks[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

548

clock = clocks[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

400

cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

401

cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

403

cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

404

cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

736

static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

742

if (clocks[i] > max)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

743

max = clocks[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

238

cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

239

cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

241

cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

242

cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

246

cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

247

cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

249

cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

250

cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

446

static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

452

if (clocks[i] > max)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

453

max = clocks[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

461

const uint32_t clocks[],

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

470

return clocks[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

474

clock = clocks[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

526

cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

527

cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

529

cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

530

cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

980

static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

986

if (clocks[i] > max)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

987

max = clocks[i];

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

35

#define TO_DCE_CLK_MGR(clocks)\

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

36

container_of(clocks, struct dce_clk_mgr, base)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

751

struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

753

clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

754

clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

755

clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

756

clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

757

clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

758

clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

759

clocks->fclk_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

760

clocks->p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

762

clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

769

clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

56

struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

58

clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

59

clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

60

clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

61

clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

62

clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

64

clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

72

clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

74

clocks->dispclk_khz = dc->clk_mgr->boot_snapshot.dispclk * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

77

clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

78

clocks->fclk_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

79

clocks->p_state_change_support = true;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2516

struct dmub_clocks clocks; /**< clock data */

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

477

struct amd_pp_clock_info *clocks);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

480

struct amd_pp_clocks *clocks);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

483

struct pp_clock_levels_with_latency *clocks);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

486

struct pp_clock_levels_with_voltage *clocks);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

492

struct amd_pp_simple_clock_info *clocks);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1767

struct amd_pp_clocks *clocks)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1778

clocks);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1785

struct amd_pp_simple_clock_info *clocks)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1795

clocks);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1803

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1814

clocks);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1822

struct pp_clock_levels_with_voltage *clocks)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1833

clocks);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1874

struct amd_pp_clock_info *clocks)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1884

clocks);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4921

static const struct cg_flag_name clocks[] = {

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4963

for (i = 0; clocks[i].flag; i++)

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4964

seq_printf(m, "\t%s: %s\n", clocks[i].name,

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4965

(flags & clocks[i].flag) ? "On" : "Off");

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

572

struct amd_pp_clocks *clocks);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

574

struct amd_pp_simple_clock_info *clocks);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

577

struct pp_clock_levels_with_latency *clocks);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

580

struct pp_clock_levels_with_voltage *clocks);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

586

struct amd_pp_clock_info *clocks);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3235

static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3240

if ((clocks == NULL) || (clocks->count == 0))

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3243

for (i = 0; i < clocks->count; i++) {

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3244

if (clocks->values[i] >= requested_clock)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3245

return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3248

return (clocks->values[clocks->count - 1] < max_clock) ?

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3249

clocks->values[clocks->count - 1] : max_clock;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1050

struct amd_pp_clock_info *clocks)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1075

clocks->min_engine_clock = hw_clocks.min_eng_clk;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1076

clocks->max_engine_clock = hw_clocks.max_eng_clk;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1077

clocks->min_memory_clock = hw_clocks.min_mem_clk;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1078

clocks->max_memory_clock = hw_clocks.max_mem_clk;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1079

clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1080

clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1082

clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1083

clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1086

clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1088

clocks->max_clocks_state = simple_clocks.level;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1091

clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1092

clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1097

static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1104

if (clocks == NULL)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1107

return phm_get_clock_by_type(hwmgr, type, clocks);

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1112

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1116

if (!hwmgr || !hwmgr->pm_en || !clocks)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1119

return phm_get_clock_by_type_with_latency(hwmgr, type, clocks);

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1124

struct pp_clock_levels_with_voltage *clocks)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1128

if (!hwmgr || !hwmgr->pm_en || !clocks)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1131

return phm_get_clock_by_type_with_voltage(hwmgr, type, clocks);

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1158

struct amd_pp_simple_clock_info *clocks)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1163

if (!hwmgr || !hwmgr->pm_en || !clocks)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1166

clocks->level = PP_DAL_POWERLEVEL_7;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1169

ret = phm_get_max_high_clocks(hwmgr, clocks);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c

419

int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c

426

return hwmgr->hwmgr_func->get_clock_by_type(hwmgr, type, clocks);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c

432

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c

439

return hwmgr->hwmgr_func->get_clock_by_type_with_latency(hwmgr, type, clocks);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c

445

struct pp_clock_levels_with_voltage *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c

452

return hwmgr->hwmgr_func->get_clock_by_type_with_voltage(hwmgr, type, clocks);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c

479

int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c

486

return hwmgr->hwmgr_func->get_max_high_clocks(hwmgr, clocks);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1168

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1207

clocks->num_levels = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1210

clocks->data[clocks->num_levels].clocks_in_khz =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1212

clocks->data[clocks->num_levels].latency_in_us = latency_required ?

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1216

clocks->num_levels++;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1225

struct pp_clock_levels_with_voltage *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1261

clocks->num_levels = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1264

clocks->data[clocks->num_levels].clocks_in_khz = pclk_vol_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1265

clocks->data[clocks->num_levels].voltage_in_mv = pclk_vol_table->entries[i].vol;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1266

clocks->num_levels++;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1275

static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1277

clocks->engine_max_clock = 80000; /* driver can't get engine clock, temp hard code to 800MHz */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

191

struct PP_Clocks clocks = {0};

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

194

clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

196

clock_req.clock_freq_in_khz = clocks.dcefClock * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5174

static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5187

clocks->clock[i] = dep_sclk_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5188

clocks->count = dep_sclk_table->count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5192

clocks->clock[i] = sclk_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5193

clocks->count = sclk_table->count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5211

static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5224

clocks->clock[i] = dep_mclk_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5225

clocks->latency[i] = smu7_get_mem_latency(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5228

clocks->count = dep_mclk_table->count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5232

clocks->clock[i] = mclk_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5233

clocks->count = mclk_table->count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5239

struct amd_pp_clocks *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5243

smu7_get_sclks(hwmgr, clocks);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5246

smu7_get_mclks(hwmgr, clocks);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5256

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5264

clocks->num_levels = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5267

clocks->data[clocks->num_levels].clocks_in_khz =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5269

clocks->num_levels++;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5277

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5286

clocks->num_levels = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5290

clocks->data[clocks->num_levels].clocks_in_khz =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5294

clocks->data[clocks->num_levels].latency_in_us =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5297

clocks->num_levels++;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5307

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5315

smu7_get_sclks_with_latency(hwmgr, clocks);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5318

smu7_get_mclks_with_latency(hwmgr, clocks);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5416

struct amd_pp_simple_clock_info *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5422

if (clocks == NULL)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5425

clocks->memory_max_clock = mclk_table->count > 1 ?

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5428

clocks->engine_max_clock = sclk_table->count > 1 ?

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1080

struct PP_Clocks clocks = {0, 0, 0, 0};

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1093

clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ?

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1099

clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1101

force_high = (clocks.memoryClock > data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1])

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1658

struct amd_pp_clocks *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1664

clocks->count = smu8_get_max_sclk_level(hwmgr);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1667

for (i = 0; i < clocks->count; i++)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1668

clocks->clock[i] = data->sys_info.display_clock[i] * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1672

for (i = 0; i < clocks->count; i++)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1673

clocks->clock[i] = table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1676

clocks->count = SMU8_NUM_NBPMEMORYCLOCK;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1677

for (i = 0; i < clocks->count; i++)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1678

clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i] * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1687

static int smu8_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1695

if ((NULL == table) || (table->count <= 0) || (clocks == NULL))

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1701

clocks->engine_max_clock = table->entries[level].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1703

clocks->engine_max_clock = table->entries[table->count - 1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1705

clocks->memory_max_clock = limits->mclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4405

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4413

clocks->num_levels = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4416

clocks->data[clocks->num_levels].clocks_in_khz =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4418

clocks->num_levels++;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4425

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4438

clocks->data[j].clocks_in_khz =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4442

clocks->data[j].latency_in_us =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4447

clocks->num_levels = data->mclk_latency_table.count = j;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4451

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4460

clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4461

clocks->data[i].latency_in_us = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4462

clocks->num_levels++;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4467

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4476

clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4477

clocks->data[i].latency_in_us = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4478

clocks->num_levels++;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4484

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4488

vega10_get_sclks(hwmgr, clocks);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4491

vega10_get_memclocks(hwmgr, clocks);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4494

vega10_get_dcefclocks(hwmgr, clocks);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4497

vega10_get_socclocks(hwmgr, clocks);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4508

struct pp_clock_levels_with_voltage *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4536

clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4537

clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table->

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4539

clocks->num_levels++;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1856

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1871

clocks->data[i].clocks_in_khz =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1874

clocks->data[i].latency_in_us = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1877

clocks->num_levels = ucount;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1889

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1903

clocks->data[i].clocks_in_khz = dpm_table->dpm_levels[i].value * 1000;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1905

clocks->data[i].latency_in_us =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1910

clocks->num_levels = data->mclk_latency_table.count = ucount;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1916

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1932

clocks->data[i].clocks_in_khz =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1935

clocks->data[i].latency_in_us = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1938

clocks->num_levels = ucount;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1944

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1960

clocks->data[i].clocks_in_khz =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1963

clocks->data[i].latency_in_us = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1966

clocks->num_levels = ucount;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1974

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1980

ret = vega12_get_sclks(hwmgr, clocks);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1983

ret = vega12_get_memclocks(hwmgr, clocks);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1986

ret = vega12_get_dcefclocks(hwmgr, clocks);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1989

ret = vega12_get_socclocks(hwmgr, clocks);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2000

struct pp_clock_levels_with_voltage *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2002

clocks->num_levels = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2278

struct pp_clock_levels_with_latency clocks;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2288

vega12_get_sclks(hwmgr, &clocks) == 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2291

for (i = 0; i < clocks.num_levels; i++)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2293

i, clocks.data[i].clocks_in_khz / 1000,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2294

(clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2304

vega12_get_memclocks(hwmgr, &clocks) == 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2307

for (i = 0; i < clocks.num_levels; i++)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2309

i, clocks.data[i].clocks_in_khz / 1000,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2310

(clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2322

vega12_get_socclocks(hwmgr, &clocks) == 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2325

for (i = 0; i < clocks.num_levels; i++)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2327

i, clocks.data[i].clocks_in_khz / 1000,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2328

(clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2340

vega12_get_dcefclocks(hwmgr, &clocks) == 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2343

for (i = 0; i < clocks.num_levels; i++)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2345

i, clocks.data[i].clocks_in_khz / 1000,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2346

(clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2816

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2826

clocks->num_levels = count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2829

clocks->data[i].clocks_in_khz =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2831

clocks->data[i].latency_in_us = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2844

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2854

clocks->num_levels = data->mclk_latency_table.count = count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2857

clocks->data[i].clocks_in_khz =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2860

clocks->data[i].latency_in_us =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2869

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2879

clocks->num_levels = count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2882

clocks->data[i].clocks_in_khz =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2884

clocks->data[i].latency_in_us = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2891

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2901

clocks->num_levels = count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2904

clocks->data[i].clocks_in_khz =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2906

clocks->data[i].latency_in_us = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2915

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2921

ret = vega20_get_sclks(hwmgr, clocks);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2924

ret = vega20_get_memclocks(hwmgr, clocks);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2927

ret = vega20_get_dcefclocks(hwmgr, clocks);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2930

ret = vega20_get_socclocks(hwmgr, clocks);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2941

struct pp_clock_levels_with_voltage *clocks)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2943

clocks->num_levels = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3375

struct pp_clock_levels_with_latency clocks;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3389

if (vega20_get_sclks(hwmgr, &clocks)) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3395

for (i = 0; i < clocks.num_levels; i++)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3397

i, clocks.data[i].clocks_in_khz / 1000,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3398

(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3407

if (vega20_get_memclocks(hwmgr, &clocks)) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3413

for (i = 0; i < clocks.num_levels; i++)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3415

i, clocks.data[i].clocks_in_khz / 1000,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3416

(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3425

if (vega20_get_socclocks(hwmgr, &clocks)) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3431

for (i = 0; i < clocks.num_levels; i++)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3433

i, clocks.data[i].clocks_in_khz / 1000,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3434

(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3455

if (vega20_get_dcefclocks(hwmgr, &clocks)) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3461

for (i = 0; i < clocks.num_levels; i++)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3463

i, clocks.data[i].clocks_in_khz / 1000,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3464

(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

446

extern int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

450

struct pp_clock_levels_with_latency *clocks);

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

453

struct pp_clock_levels_with_voltage *clocks);

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

459

extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

301

int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

304

struct pp_clock_levels_with_latency *clocks);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

307

struct pp_clock_levels_with_voltage *clocks);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

311

int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3428

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3456

ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

770

*clocks);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

779

*clocks);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

615

struct pp_clock_levels_with_latency *clocks,

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

620

clocks->num_levels = min_t(uint32_t,

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

624

for (i = 0; i < clocks->num_levels; i++) {

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

625

clocks->data[i].clocks_in_khz =

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

627

clocks->data[i].latency_in_us = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

804

struct pp_clock_levels_with_latency clocks;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

830

arcturus_get_clk_table(smu, &clocks, single_dpm_table);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

842

arcturus_get_clk_table(smu, &clocks, single_dpm_table);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

854

arcturus_get_clk_table(smu, &clocks, single_dpm_table);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

866

arcturus_get_clk_table(smu, &clocks, single_dpm_table);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

878

arcturus_get_clk_table(smu, &clocks, single_dpm_table);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

890

arcturus_get_clk_table(smu, &clocks, single_dpm_table);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

914

for (i = 0; i < clocks.num_levels; i++) {

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

915

clock_mhz = clocks.data[i].clocks_in_khz / 1000;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

917

freq_match |= (clocks.num_levels == 1);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1802

struct pp_clock_levels_with_latency *clocks)

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1818

clocks->num_levels = level_count;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1825

clocks->data[i].clocks_in_khz = freq * 1000;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1826

clocks->data[i].latency_in_us = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

642

struct pp_clock_levels_with_latency *clocks,

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

647

clocks->num_levels = min_t(uint32_t,

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

651

for (i = 0; i < clocks->num_levels; i++) {

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

652

clocks->data[i].clocks_in_khz =

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

654

clocks->data[i].latency_in_us = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

831

struct pp_clock_levels_with_latency clocks;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

866

aldebaran_get_clk_table(smu, &clocks, single_dpm_table);

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

868

display_levels = (clocks.num_levels == 1) ? 1 : 2;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

898

aldebaran_get_clk_table(smu, &clocks, single_dpm_table);

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

909

aldebaran_get_clk_table(smu, &clocks, single_dpm_table);

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

920

aldebaran_get_clk_table(smu, &clocks, single_dpm_table);

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

931

aldebaran_get_clk_table(smu, &clocks, single_dpm_table);

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

942

aldebaran_get_clk_table(smu, &clocks, single_dpm_table);

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

967

for (i = 0; i < clocks.num_levels; i++) {

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

968

clock_mhz = clocks.data[i].clocks_in_khz / 1000;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

970

freq_match |= (clocks.num_levels == 1);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1225

struct pp_clock_levels_with_latency *clocks,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1232

clocks->num_levels = count;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1235

clocks->data[i].clocks_in_khz =

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1237

clocks->data[i].latency_in_us = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1381

struct pp_clock_levels_with_latency clocks;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1385

ret = smu_v13_0_6_get_clk_table(smu, &clocks, single_dpm_table);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1392

if (!clocks.num_levels)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1397

for (i = 0; i < clocks.num_levels; i++)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1399

clocks.data[i].clocks_in_khz /

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1403

if ((clocks.num_levels == 1) ||

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1404

(curr_clk < (clocks.data[0].clocks_in_khz / 1000)))

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1406

for (i = 0; i < clocks.num_levels; i++) {

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1407

clk1 = clocks.data[i].clocks_in_khz / 1000;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1409

if (i < (clocks.num_levels - 1))

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1410

clk2 = clocks.data[i + 1].clocks_in_khz / 1000;

sys/dev/pci/drm/i915/display/intel_sdvo.c

728

struct intel_sdvo_pixel_clock_range clocks;

sys/dev/pci/drm/i915/display/intel_sdvo.c

730

BUILD_BUG_ON(sizeof(clocks) != 4);

sys/dev/pci/drm/i915/display/intel_sdvo.c

733

&clocks, sizeof(clocks)))

sys/dev/pci/drm/i915/display/intel_sdvo.c

737

*clock_min = clocks.min * 10;

sys/dev/pci/drm/i915/display/intel_sdvo.c

738

*clock_max = clocks.max * 10;

sys/dev/pci/drm/radeon/btc_dpm.c

1181

static u32 btc_find_valid_clock(struct radeon_clock_array *clocks,

sys/dev/pci/drm/radeon/btc_dpm.c

1186

if ((clocks == NULL) || (clocks->count == 0))

sys/dev/pci/drm/radeon/btc_dpm.c

1189

for (i = 0; i < clocks->count; i++) {

sys/dev/pci/drm/radeon/btc_dpm.c

1190

if (clocks->values[i] >= requested_clock)

sys/dev/pci/drm/radeon/btc_dpm.c

1191

return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;

sys/dev/pci/drm/radeon/btc_dpm.c

1194

return (clocks->values[clocks->count - 1] < max_clock) ?

sys/dev/pci/drm/radeon/btc_dpm.c

1195

clocks->values[clocks->count - 1] : max_clock;

usr.bin/telnet/defines.h

42

extern Clocks clocks;

usr.bin/telnet/defines.h

44

#define settimer(x) clocks.x = clocks.system++

usr.bin/telnet/telnet.c

146

Clocks clocks;

usr.bin/telnet/terminal.c

144

if (dontlecho && (clocks.echotoggle > clocks.modenegotiated)) {