Symbol: clk_type
sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c
526
u32 freq, u8 clk_type, u8 clk_src)
sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c
545
args.v2_1.asParam.ucDCEClkType = clk_type;
sys/dev/pci/drm/amd/amdgpu/atombios_crtc.h
41
u32 freq, u8 clk_type, u8 clk_src);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
113
enum dm_pp_clock_type clk_type,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
122
switch (clk_type) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
296
enum dm_pp_clock_type clk_type,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
305
dc_to_pp_clock_type(clk_type), &pp_clks)) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
307
get_default_clock_levels(clk_type, dc_clks);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
311
pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
334
if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
347
} else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
363
enum dm_pp_clock_type clk_type,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
371
dc_to_pp_clock_type(clk_type),
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
376
pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
383
enum dm_pp_clock_type clk_type,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
391
dc_to_pp_clock_type(clk_type),
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
396
pp_to_dc_clock_levels_with_voltage(&pp_clk_info, clk_level_info, clk_type);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
436
pp_clock_request.clock_type = dc_to_pp_clock_type(clock_for_voltage_req->clk_type);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c
113
clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c
98
clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1499
unsigned int dcn401_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1505
switch (clk_type) {
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
115
unsigned int dcn401_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
767
clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK;
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
782
clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK;
sys/dev/pci/drm/amd/display/dc/dm_services.h
192
enum dm_pp_clock_type clk_type,
sys/dev/pci/drm/amd/display/dc/dm_services.h
197
enum dm_pp_clock_type clk_type,
sys/dev/pci/drm/amd/display/dc/dm_services.h
202
enum dm_pp_clock_type clk_type,
sys/dev/pci/drm/amd/display/dc/dm_services_types.h
254
enum dm_pp_clock_type clk_type;
sys/dev/pci/drm/amd/display/dc/dm_services_types.h
82
#define DC_DECODE_PP_CLOCK_TYPE(clk_type) \
sys/dev/pci/drm/amd/display/dc/dm_services_types.h
83
(clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
sys/dev/pci/drm/amd/display/dc/dm_services_types.h
84
(clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
sys/dev/pci/drm/amd/display/dc/dm_services_types.h
85
(clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : \
sys/dev/pci/drm/amd/display/dc/dm_services_types.h
86
(clk_type) == DM_PP_CLOCK_TYPE_DCFCLK ? "DCF" : \
sys/dev/pci/drm/amd/display/dc/dm_services_types.h
87
(clk_type) == DM_PP_CLOCK_TYPE_DCEFCLK ? "DCEF" : \
sys/dev/pci/drm/amd/display/dc/dm_services_types.h
88
(clk_type) == DM_PP_CLOCK_TYPE_SOCCLK ? "SoC" : \
sys/dev/pci/drm/amd/display/dc/dm_services_types.h
89
(clk_type) == DM_PP_CLOCK_TYPE_PIXELCLK ? "Pixel" : \
sys/dev/pci/drm/amd/display/dc/dm_services_types.h
90
(clk_type) == DM_PP_CLOCK_TYPE_DISPLAYPHYCLK ? "Display PHY" : \
sys/dev/pci/drm/amd/display/dc/dm_services_types.h
91
(clk_type) == DM_PP_CLOCK_TYPE_DPPCLK ? "DPP" : \
sys/dev/pci/drm/amd/display/dc/dm_services_types.h
92
(clk_type) == DM_PP_CLOCK_TYPE_FCLK ? "F" : \
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h
342
unsigned int (*get_max_clock_khz)(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
55
enum amd_pp_clock_type clk_type = clock_req->clock_type;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
59
switch (clk_type) {
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
4041
enum amd_pp_clock_type clk_type = clock_req->clock_type;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
4046
switch (clk_type) {
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
1578
enum amd_pp_clock_type clk_type = clock_req->clock_type;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
1584
switch (clk_type) {
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
2303
enum amd_pp_clock_type clk_type = clock_req->clock_type;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
2309
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
145
enum smu_clk_type clk_type;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
148
clk_type = smu_convert_to_smuclk(type);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
149
if (clk_type == SMU_CLK_COUNT)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
154
clk_type,
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
163
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
174
clk_type,
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2622
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2637
ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2639
smu->user_dpm_profile.clk_mask[clk_type] = mask;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2640
smu_set_user_clk_dependencies(smu, clk_type);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2652
enum smu_clk_type clk_type;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2656
clk_type = SMU_SCLK; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2658
clk_type = SMU_MCLK; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2660
clk_type = SMU_PCIE; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2662
clk_type = SMU_SOCCLK; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2664
clk_type = SMU_FCLK; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2666
clk_type = SMU_DCEFCLK; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2668
clk_type = SMU_VCLK; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2670
clk_type = SMU_VCLK1; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2672
clk_type = SMU_DCLK; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2674
clk_type = SMU_DCLK1; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2676
clk_type = SMU_OD_SCLK; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2678
clk_type = SMU_OD_MCLK; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2680
clk_type = SMU_OD_VDDC_CURVE; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2682
clk_type = SMU_OD_RANGE; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2687
return smu_force_smuclk_levels(smu, clk_type, mask);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3021
static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3029
ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3036
enum smu_clk_type clk_type;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3040
clk_type = SMU_SCLK; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3042
clk_type = SMU_MCLK; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3044
clk_type = SMU_PCIE; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3046
clk_type = SMU_SOCCLK; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3048
clk_type = SMU_FCLK; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3050
clk_type = SMU_DCEFCLK; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3052
clk_type = SMU_VCLK; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3054
clk_type = SMU_VCLK1; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3056
clk_type = SMU_DCLK; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3058
clk_type = SMU_DCLK1; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3060
clk_type = SMU_ISPICLK;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3063
clk_type = SMU_ISPXCLK;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3066
clk_type = SMU_OD_SCLK; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3068
clk_type = SMU_OD_MCLK; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3070
clk_type = SMU_OD_VDDC_CURVE; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3072
clk_type = SMU_OD_RANGE; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3074
clk_type = SMU_OD_VDDGFX_OFFSET; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3076
clk_type = SMU_OD_CCLK; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3078
clk_type = SMU_OD_FAN_CURVE; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3080
clk_type = SMU_OD_ACOUSTIC_LIMIT; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3082
clk_type = SMU_OD_ACOUSTIC_TARGET; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3084
clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3086
clk_type = SMU_OD_FAN_MINIMUM_PWM; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3088
clk_type = SMU_OD_FAN_ZERO_RPM_ENABLE; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3090
clk_type = SMU_OD_FAN_ZERO_RPM_STOP_TEMP; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3092
clk_type = SMU_CLK_COUNT; break;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3095
return clk_type;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3103
enum smu_clk_type clk_type;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3105
clk_type = smu_convert_to_smuclk(type);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3106
if (clk_type == SMU_CLK_COUNT)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3109
return smu_print_smuclk_levels(smu, clk_type, buf);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3115
enum smu_clk_type clk_type;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3117
clk_type = smu_convert_to_smuclk(type);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3118
if (clk_type == SMU_CLK_COUNT)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3127
return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3431
enum smu_clk_type clk_type;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3440
clk_type = SMU_GFXCLK;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3443
clk_type = SMU_MCLK;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3446
clk_type = SMU_DCEFCLK;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3449
clk_type = SMU_DISPCLK;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3456
ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
520
enum smu_clk_type clk_type;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
522
for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) {
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
527
if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) &&
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
528
smu->user_dpm_profile.clk_mask[clk_type]) {
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
529
ret = smu_force_smuclk_levels(smu, clk_type,
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
530
smu->user_dpm_profile.clk_mask[clk_type]);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
533
"Failed to set clock type = %d\n", clk_type);
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
63
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1315
int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1321
int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max,
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1748
int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1751
int smu_set_soft_freq_range(struct smu_context *smu, enum pp_clock_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
723
int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
736
int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
744
int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
767
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h
254
int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h
257
int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h
261
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h
272
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h
277
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h
281
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v12_0.h
58
int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h
216
int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h
219
int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h
229
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h
233
enum smu_clk_type clk_type, uint16_t level,
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h
297
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h
186
int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h
189
int smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h
193
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h
204
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
736
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
747
clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
260
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
265
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
291
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
300
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
327
ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value);
sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
334
ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value);
sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
536
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
543
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
550
ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &low);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1184
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1192
clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1224
static int navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1232
clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1258
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1277
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1287
ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1291
ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1295
ret = navi10_is_support_fine_grained_dpm(smu, clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1302
clk_type, i, &value);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1313
clk_type, 0, &freq_values[0]);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1317
clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1469
enum smu_clk_type clk_type, char *buf)
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1488
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1498
ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1502
ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1506
ret = navi10_is_support_fine_grained_dpm(smu, clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1512
ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1520
ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1523
ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1660
enum smu_clk_type clk_type, uint32_t mask)
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1669
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1677
ret = navi10_is_support_fine_grained_dpm(smu, clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1686
ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1690
ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1694
ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1801
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1807
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1813
ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &level_count);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1821
ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &freq);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1196
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1204
clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1246
static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1255
clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1273
enum smu_clk_type clk_type, char *buf)
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1293
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1305
ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1309
ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1313
if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1315
ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1323
ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1326
ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1441
enum smu_clk_type clk_type, uint32_t mask)
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1449
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1457
if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1462
ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1466
ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1470
ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2193
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2196
return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1062
enum amd_pp_clock_type clk_type = clock_req->clock_type;
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1069
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1715
int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1722
if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1723
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1751
clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1775
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1783
if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1788
clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1819
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1829
if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1834
clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1982
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1992
if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1997
clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
2020
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
2024
clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
2030
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
2038
clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
2047
clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1004
ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1009
ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1014
ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1019
ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1084
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1091
if (!vangogh_clk_dpm_is_enabled(smu, clk_type))
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1094
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1167
enum smu_clk_type clk_type, uint32_t mask)
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1176
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1178
ret = vangogh_get_dpm_clk_limited(smu, clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1182
ret = vangogh_get_dpm_clk_limited(smu, clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1199
clk_type, soft_min_level, &min_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1203
clk_type, soft_max_level, &max_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1219
clk_type, soft_min_level, &min_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1224
clk_type, soft_max_level, &max_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1244
clk_type, soft_min_level, &min_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1249
clk_type, soft_max_level, &max_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1277
enum smu_clk_type clk_type;
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1287
clk_type = clks[i];
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1288
ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1293
ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1305
enum smu_clk_type clk_type;
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1308
enum smu_clk_type clk_type;
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1322
clk_type = clk_feature_map[i].clk_type;
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1324
ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1329
ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
527
static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
532
if (!clk_table || clk_type >= SMU_CLK_COUNT)
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
535
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
571
enum smu_clk_type clk_type, char *buf)
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
588
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
643
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
650
idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
651
ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
673
enum smu_clk_type clk_type, char *buf)
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
690
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
746
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
753
idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
754
ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
794
enum smu_clk_type clk_type, char *buf)
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
799
ret = vangogh_print_legacy_clk_levels(smu, clk_type, buf);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
801
ret = vangogh_print_clk_levels(smu, clk_type, buf);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
861
enum smu_clk_type clk_type)
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
865
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
893
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
905
if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
906
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
951
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
954
ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
959
ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
964
ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
969
ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
974
ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
996
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
999
ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
202
static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
207
if (!clk_table || clk_type >= SMU_CLK_COUNT)
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
210
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
281
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
289
if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
290
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
325
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
337
ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
342
ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
353
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
365
ret = renoir_get_dpm_clk_limited(smu, clk_type, NUM_MEMCLK_DPM_LEVELS - 1, min);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
370
ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
495
enum smu_clk_type clk_type, char *buf)
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
510
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
582
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
590
idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
591
ret = renoir_get_dpm_clk_limited(smu, clk_type, idx, &value);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
692
enum smu_clk_type clk_type;
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
701
clk_type = clks[i];
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
702
ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
707
ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
719
enum smu_clk_type clk_type;
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
722
enum smu_clk_type clk_type;
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
734
clk_type = clk_feature_map[i].clk_type;
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
736
ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
740
ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
793
enum smu_clk_type clk_type, uint32_t mask)
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
802
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
827
ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
830
ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
842
ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
845
ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
911
enum smu_clk_type clk_type)
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
916
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c
213
int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c
218
if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c
221
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
1360
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
1373
if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK)
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
346
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
354
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
394
return smu_v13_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
762
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
773
clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1484
int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1491
if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1492
ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1507
clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1540
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1548
if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1553
clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1793
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1798
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1827
enum smu_clk_type clk_type, uint16_t level,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1836
if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1837
return smu_v13_0_get_boot_freq_by_index(smu, clk_type, value);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1841
clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1860
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1865
ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1874
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1884
if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1889
clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1912
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1920
clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1929
clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1939
clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1009
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1017
clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1188
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1209
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1237
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1247
ret = smu_v13_0_0_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1986
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1999
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
2026
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
2051
clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
873
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
881
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
389
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
394
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
425
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
431
if (!clk_table || clk_type >= SMU_CLK_COUNT)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
434
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
469
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
474
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
498
enum smu_clk_type clk_type, char *buf)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
506
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
525
ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type, &cur_value);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
529
ret = smu_v13_0_4_get_dpm_level_count(smu, clk_type, &count);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
534
idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
535
ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, idx, &value);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
545
ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type, &cur_value);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
722
enum smu_clk_type clk_type)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
726
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
751
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
760
if (!smu_v13_0_4_clk_dpm_is_enabled(smu, clk_type)) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
761
ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
775
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
796
if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
797
ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
806
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
827
if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
828
ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
838
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
847
if (!smu_v13_0_4_clk_dpm_is_enabled(smu, clk_type))
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
850
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
873
if (clk_type == SMU_VCLK) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
887
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
897
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
902
ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
906
ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
910
ret = smu_v13_0_4_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
922
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
929
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
595
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
600
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
626
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
631
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
655
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
661
if (!clk_table || clk_type >= SMU_CLK_COUNT)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
664
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
699
enum smu_clk_type clk_type)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
703
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
728
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
737
if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type)) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
738
ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
752
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
774
if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
775
ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
782
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
804
if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
805
ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
816
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
826
if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type))
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
829
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
844
if (clk_type == SMU_VCLK) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
862
enum smu_clk_type clk_type, char *buf)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
870
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
887
ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
891
ret = smu_v13_0_5_get_dpm_level_count(smu, clk_type, &count);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
896
idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
897
ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, idx, &value);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
907
ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
936
enum smu_clk_type clk_type, uint32_t mask)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
945
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
948
ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
952
ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
956
ret = smu_v13_0_5_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
971
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
978
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1005
if (!(clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1007
smu, CMN2ASIC_MAPPING_CLK, clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1016
if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1027
if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1040
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1045
ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, levels);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1130
smu, dpm_map[j].clk_type, &levels);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1343
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1351
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2097
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2109
if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK &&
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2110
clk_type != SMU_UCLK)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2124
if (clk_type == SMU_GFXCLK) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2137
if (clk_type == SMU_UCLK) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
252
enum smu_clk_type clk_type;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
955
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
968
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1006
clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1177
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1198
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1226
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1236
ret = smu_v13_0_7_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1975
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1988
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
2015
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
2040
clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
862
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
870
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
998
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1006
enum smu_clk_type clk_type)
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1011
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1042
enum smu_clk_type clk_type, char *buf)
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1051
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1069
ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value);
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1073
ret = yellow_carp_get_dpm_level_count(smu, clk_type, &count);
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1078
idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1079
ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, idx, &value);
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1089
clk_limit = yellow_carp_get_umd_pstate_clk_default(smu, clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1090
ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value);
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1118
enum smu_clk_type clk_type, uint32_t mask)
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1127
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1132
ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1136
ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1140
ret = yellow_carp_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1155
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1162
clk_limit = yellow_carp_get_umd_pstate_clk_default(smu, clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1164
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
726
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
731
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
760
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
765
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
789
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
795
if (!clk_table || clk_type >= SMU_CLK_COUNT)
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
798
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
833
enum smu_clk_type clk_type)
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
837
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
862
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
871
if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type)) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
872
ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit);
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
886
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
908
if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
909
ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
916
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
938
if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
939
ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
950
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
961
if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type))
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
964
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
987
if (clk_type == SMU_VCLK) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1094
int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1101
if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1102
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1130
clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1163
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1171
if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1176
clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1208
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1218
if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1223
clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1442
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1452
if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1457
clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1476
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1481
ret = smu_v14_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1487
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1497
if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1502
clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1525
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1533
clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1541
clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1550
clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1009
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1014
smu_v14_0_1_get_dpm_ultimate_freq(smu, clk_type, min, max);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1015
else if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1016
smu_v14_0_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1022
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1027
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1061
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1066
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1092
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1097
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1121
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1125
smu_v14_0_1_get_dpm_level_count(smu, clk_type, count);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1126
else if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1127
smu_v14_0_0_get_dpm_level_count(smu, clk_type, count);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1133
enum smu_clk_type clk_type, char *buf)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1141
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1162
ret = smu_v14_0_0_get_current_clk_freq(smu, clk_type, &cur_value);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1166
ret = smu_v14_0_common_get_dpm_level_count(smu, clk_type, &count);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1171
idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i;
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1172
ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, idx, &value);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1182
ret = smu_v14_0_0_get_current_clk_freq(smu, clk_type, &cur_value);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1209
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1218
if (!smu_v14_0_0_clk_dpm_is_enabled(smu, clk_type))
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1221
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1265
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1275
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1282
ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1286
ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1290
ret = smu_v14_0_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1302
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1309
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
631
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
637
if (!clk_table || clk_type >= SMU_CLK_COUNT)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
640
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
685
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
691
if (!clk_table || clk_type >= SMU_CLK_COUNT)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
694
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
729
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
734
smu_v14_0_1_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
735
else if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
736
smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
742
enum smu_clk_type clk_type)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
746
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
773
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
782
if (!smu_v14_0_0_clk_dpm_is_enabled(smu, clk_type)) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
783
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
821
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
849
if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
850
ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
857
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
883
if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
884
ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
895
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
904
if (!smu_v14_0_0_clk_dpm_is_enabled(smu, clk_type)) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
905
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
941
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
965
if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
966
ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
973
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
997
if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
998
ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
1049
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
1070
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
1098
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
1108
ret = smu_v14_0_2_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
1381
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
1394
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
1421
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
1446
clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
791
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
799
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
926
enum smu_clk_type clk_type,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
934
clk_type);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
650
enum smu_clk_type clk_type)
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
654
switch (clk_type) {
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
135
enum smu_clk_type clk_type);