ce4231_write
ce4231_write(sc, SP_LOWER_BASE_COUNT, 0xff);
ce4231_write(sc, SP_UPPER_BASE_COUNT, 0xff);
ce4231_write(sc, CS_IRQ_STATUS, reg & ~CS_IRQ_PI);
ce4231_write(sc, CS_LOWER_REC_CNT, 0xff);
ce4231_write(sc, CS_UPPER_REC_CNT, 0xff);
ce4231_write(sc, CS_IRQ_STATUS, reg & ~CS_IRQ_CI);
ce4231_write(sc, SP_LOWER_BASE_COUNT, 0xff);
ce4231_write(sc, SP_UPPER_BASE_COUNT, 0xff);
ce4231_write(sc, SP_INTERFACE_CONFIG,
void ce4231_write(struct ce4231_softc *, u_int8_t, u_int8_t);
ce4231_write(sc, CS_LOWER_REC_CNT, 0xff);
ce4231_write(sc, CS_UPPER_REC_CNT, 0xff);
ce4231_write(sc, SP_INTERFACE_CONFIG,
ce4231_write(sc, SP_MISC_INFO, ce4231_read(sc, SP_MISC_INFO) | MODE2);
ce4231_write(sc, SP_PIN_CONTROL,
ce4231_write(sc, SP_PIN_CONTROL,
ce4231_write(sc, SP_INTERFACE_CONFIG,
ce4231_write(sc, SP_INTERFACE_CONFIG,
ce4231_write(sc, CS_MONO_IO_CONTROL, val);
ce4231_write(sc, SP_PIN_CONTROL, val);
ce4231_write(sc, SP_LEFT_OUTPUT_CONTROL, l);
ce4231_write(sc, SP_RIGHT_OUTPUT_CONTROL, r);
ce4231_write(sc, SP_LEFT_OUTPUT_CONTROL, l);
ce4231_write(sc, SP_RIGHT_OUTPUT_CONTROL, r);
ce4231_write(sc, SP_LEFT_AUX1_CONTROL, l);
ce4231_write(sc, SP_RIGHT_AUX1_CONTROL, r);
ce4231_write(sc, SP_LEFT_AUX1_CONTROL, l);
ce4231_write(sc, SP_RIGHT_AUX1_CONTROL, r);
ce4231_write(sc, CS_LEFT_LINE_CONTROL, l);
ce4231_write(sc, CS_RIGHT_LINE_CONTROL, r);
ce4231_write(sc, CS_LEFT_LINE_CONTROL, l);
ce4231_write(sc, CS_RIGHT_LINE_CONTROL, r);
ce4231_write(sc, SP_DIGITAL_MIX, l);
ce4231_write(sc, SP_DIGITAL_MIX, l);
ce4231_write(sc, SP_LEFT_INPUT_CONTROL, l);
ce4231_write(sc, SP_RIGHT_INPUT_CONTROL, r);
ce4231_write(sc, SP_LEFT_INPUT_CONTROL, l);
ce4231_write(sc, SP_RIGHT_INPUT_CONTROL, r);
ce4231_write(sc, SP_LEFT_INPUT_CONTROL, l);
ce4231_write(sc, SP_RIGHT_INPUT_CONTROL, r);