CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 |
adev->pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 |
pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 :
| CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16)