CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);
adev->pm.pcie_mlw_mask |= CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1;
#define AMDGPU_DEFAULT_ASIC_PCIE_MLW_MASK (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1 \