sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10067

mode_lib->ms.cache_display_cfg = *display_cfg;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10099

cache_display_cfg(mode_lib, display_cfg);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10141

cache_display_cfg(mode_lib, display_cfg);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10204

dml_print("DML::%s: pipe_idx=%d UseMALLForPStateChange=%0d\n", __func__, pipe_idx, mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[plane_idx]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10205

return (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[plane_idx] == dml_use_mall_pstate_change_phantom_pipe);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6230

CalculatePrefetchSchedule_params->DPP_RECOUT_WIDTH = (dml_uint_t)(mode_lib->ms.SwathWidthYThisState[k] / mode_lib->ms.cache_display_cfg.plane.HRatio[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6231

CalculatePrefetchSchedule_params->OutputFormat = mode_lib->ms.cache_display_cfg.output.OutputFormat[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6233

CalculatePrefetchSchedule_params->GPUVMPageTableLevels = mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6234

CalculatePrefetchSchedule_params->GPUVMEnable = mode_lib->ms.cache_display_cfg.plane.GPUVMEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6235

CalculatePrefetchSchedule_params->HostVMEnable = mode_lib->ms.cache_display_cfg.plane.HostVMEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6236

CalculatePrefetchSchedule_params->HostVMMaxNonCachedPageTableLevels = mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6238

CalculatePrefetchSchedule_params->DynamicMetadataEnable = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataEnable[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6240

CalculatePrefetchSchedule_params->DynamicMetadataLinesBeforeActiveRequired = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataLinesBeforeActiveRequired[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6241

CalculatePrefetchSchedule_params->DynamicMetadataTransmittedBytes = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataTransmittedBytes[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6313

mode_lib->ms.cache_display_cfg.plane.HostVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6319

if (mode_lib->ms.cache_display_cfg.plane.GPUVMEnable && mode_lib->ms.cache_display_cfg.plane.HostVMEnable)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6331

mode_lib->ms.cache_display_cfg.plane.GPUVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6332

mode_lib->ms.cache_display_cfg.plane.HostVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6338

mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6356

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6358

mode_lib->ms.cache_display_cfg.timing.DRRDisplay[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6367

myPipe->PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6370

myPipe->ScalerEnabled = mode_lib->ms.cache_display_cfg.plane.ScalerEnabled[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6371

myPipe->SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6376

myPipe->InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6377

myPipe->NumberOfCursors = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6378

myPipe->VBlank = mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6379

myPipe->HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6380

myPipe->HActive = mode_lib->ms.cache_display_cfg.timing.HActive[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6381

myPipe->DCCEnable = mode_lib->ms.cache_display_cfg.surface.DCCEnable[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6383

myPipe->SourcePixelFormat = mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6420

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6425

mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6428

mode_lib->ms.cache_display_cfg.plane.CursorWidth[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6429

mode_lib->ms.cache_display_cfg.plane.CursorBPP[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6442

mode_lib->ms.cursor_bw_pre[k] = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k] * mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] *

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6443

mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] / 8.0 / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] /

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6444

mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.VRatioPreY[j][k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6451

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6546

mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6547

mode_lib->ms.cache_display_cfg.plane.HostVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6548

mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6549

mode_lib->ms.cache_display_cfg.plane.GPUVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6556

mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6557

(mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]),

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6558

mode_lib->ms.cache_display_cfg.plane.VRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6559

mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6561

mode_lib->ms.cache_display_cfg.surface.DCCEnable[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6578

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6649

CalculateWatermarks_params->UseMALLForPStateChange = mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6659

CalculateWatermarks_params->DRRDisplay = mode_lib->ms.cache_display_cfg.timing.DRRDisplay;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6671

CalculateWatermarks_params->LBBitPerPixel = mode_lib->ms.cache_display_cfg.plane.LBBitPerPixel;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6674

CalculateWatermarks_params->HRatio = mode_lib->ms.cache_display_cfg.plane.HRatio;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6675

CalculateWatermarks_params->HRatioChroma = mode_lib->ms.cache_display_cfg.plane.HRatioChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6676

CalculateWatermarks_params->VTaps = mode_lib->ms.cache_display_cfg.plane.VTaps;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6677

CalculateWatermarks_params->VTapsChroma = mode_lib->ms.cache_display_cfg.plane.VTapsChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6678

CalculateWatermarks_params->VRatio = mode_lib->ms.cache_display_cfg.plane.VRatio;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6679

CalculateWatermarks_params->VRatioChroma = mode_lib->ms.cache_display_cfg.plane.VRatioChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6680

CalculateWatermarks_params->HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6681

CalculateWatermarks_params->VTotal = mode_lib->ms.cache_display_cfg.timing.VTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6682

CalculateWatermarks_params->VActive = mode_lib->ms.cache_display_cfg.timing.VActive;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6683

CalculateWatermarks_params->PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6684

CalculateWatermarks_params->BlendingAndTiming = mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6690

CalculateWatermarks_params->WritebackEnable = mode_lib->ms.cache_display_cfg.writeback.WritebackEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6691

CalculateWatermarks_params->WritebackPixelFormat = mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6692

CalculateWatermarks_params->WritebackDestinationWidth = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6693

CalculateWatermarks_params->WritebackDestinationHeight = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6694

CalculateWatermarks_params->WritebackSourceHeight = mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6724

mode_lib->ms.num_active_planes = dml_get_num_active_planes(&mode_lib->ms.cache_display_cfg);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6740

PixelClockAdjustmentForProgressiveToInterlaceUnit(&mode_lib->ms.cache_display_cfg, mode_lib->ms.ip.ptoi_supported);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6748

if (mode_lib->ms.cache_display_cfg.plane.ScalerEnabled[k] == false

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6749

&& ((mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_64

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6750

&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_32

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6751

&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_16

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6752

&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_mono_16

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6753

&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_mono_8

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6754

&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6755

&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe_alpha)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6756

|| mode_lib->ms.cache_display_cfg.plane.HRatio[k] != 1.0

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6757

|| mode_lib->ms.cache_display_cfg.plane.HTaps[k] != 1.0

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6758

|| mode_lib->ms.cache_display_cfg.plane.VRatio[k] != 1.0

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6759

|| mode_lib->ms.cache_display_cfg.plane.VTaps[k] != 1.0)) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6761

} else if (mode_lib->ms.cache_display_cfg.plane.VTaps[k] < 1.0 || mode_lib->ms.cache_display_cfg.plane.VTaps[k] > 8.0

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6762

|| mode_lib->ms.cache_display_cfg.plane.HTaps[k] < 1.0 || mode_lib->ms.cache_display_cfg.plane.HTaps[k] > 8.0

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6763

|| (mode_lib->ms.cache_display_cfg.plane.HTaps[k] > 1.0 && (mode_lib->ms.cache_display_cfg.plane.HTaps[k] % 2) == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6764

|| mode_lib->ms.cache_display_cfg.plane.HRatio[k] > mode_lib->ms.ip.max_hscl_ratio

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6765

|| mode_lib->ms.cache_display_cfg.plane.VRatio[k] > mode_lib->ms.ip.max_vscl_ratio

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6766

|| mode_lib->ms.cache_display_cfg.plane.HRatio[k] > mode_lib->ms.cache_display_cfg.plane.HTaps[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6767

|| mode_lib->ms.cache_display_cfg.plane.VRatio[k] > mode_lib->ms.cache_display_cfg.plane.VTaps[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6768

|| (mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_64

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6769

&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_32

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6770

&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_16

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6771

&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_mono_16

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6772

&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_mono_8

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6773

&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6774

&& (mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k] < 1 || mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k] > 8 || mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k] < 1 || mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k] > 8 ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6775

(mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k] > 1 && mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k] % 2 == 1) ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6776

mode_lib->ms.cache_display_cfg.plane.HRatioChroma[k] > mode_lib->ms.ip.max_hscl_ratio ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6777

mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k] > mode_lib->ms.ip.max_vscl_ratio ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6778

mode_lib->ms.cache_display_cfg.plane.HRatioChroma[k] > mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k] ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6779

mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k] > mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k]))) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6787

if (mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k] == dml_sw_linear && (!(!dml_is_vertical_rotation(mode_lib->ms.cache_display_cfg.plane.SourceScan[k])) || mode_lib->ms.cache_display_cfg.surface.DCCEnable[k] == true)) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6794

mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6795

mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6814

if (!dml_is_vertical_rotation(mode_lib->ms.cache_display_cfg.plane.SourceScan[k])) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6815

mode_lib->ms.SwathWidthYSingleDPP[k] = mode_lib->ms.cache_display_cfg.plane.ViewportWidth[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6816

mode_lib->ms.SwathWidthCSingleDPP[k] = mode_lib->ms.cache_display_cfg.plane.ViewportWidthChroma[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6818

mode_lib->ms.SwathWidthYSingleDPP[k] = mode_lib->ms.cache_display_cfg.plane.ViewportHeight[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6819

mode_lib->ms.SwathWidthCSingleDPP[k] = mode_lib->ms.cache_display_cfg.plane.ViewportHeightChroma[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6823

mode_lib->ms.ReadBandwidthLuma[k] = mode_lib->ms.SwathWidthYSingleDPP[k] * dml_ceil(mode_lib->ms.BytePerPixelInDETY[k], 1.0) / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6824

mode_lib->ms.ReadBandwidthChroma[k] = mode_lib->ms.SwathWidthYSingleDPP[k] / 2 * dml_ceil(mode_lib->ms.BytePerPixelInDETC[k], 2.0) / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k] / 2.0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6827

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6828

&& mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k] == dml_444_64) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6829

mode_lib->ms.WriteBandwidth[k] = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6830

* mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6831

/ (mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6832

* mode_lib->ms.cache_display_cfg.timing.HTotal[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6833

/ mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * 8.0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6834

} else if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6835

mode_lib->ms.WriteBandwidth[k] = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6836

* mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6837

/ (mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6838

* mode_lib->ms.cache_display_cfg.timing.HTotal[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6839

/ mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * 4.0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6848

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6857

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6870

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6871

if (mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k] > mode_lib->ms.ip.writeback_max_hscl_ratio

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6872

|| mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k] > mode_lib->ms.ip.writeback_max_vscl_ratio

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6873

|| mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k] < mode_lib->ms.ip.writeback_min_hscl_ratio

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6874

|| mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k] < mode_lib->ms.ip.writeback_min_vscl_ratio

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6875

|| mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k] > (dml_uint_t) mode_lib->ms.ip.writeback_max_hscl_taps

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6876

|| mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k] > (dml_uint_t) mode_lib->ms.ip.writeback_max_vscl_taps

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6877

|| mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k] > (dml_uint_t) mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6878

|| mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k] > (dml_uint_t) mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6879

|| (mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k] > 2.0 && ((mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k] % 2) == 1))) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6882

if (2.0 * mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k] * (mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k] - 1) * 57 > mode_lib->ms.ip.writeback_line_buffer_buffer_size) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6890

mode_lib->ms.cache_display_cfg.plane.HRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6891

mode_lib->ms.cache_display_cfg.plane.HRatioChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6892

mode_lib->ms.cache_display_cfg.plane.VRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6893

mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6896

mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6897

mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6898

mode_lib->ms.cache_display_cfg.plane.HTaps[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6899

mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6900

mode_lib->ms.cache_display_cfg.plane.VTaps[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6901

mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6909

if (mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k] == dml_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6911

} else if (!dml_is_vertical_rotation(mode_lib->ms.cache_display_cfg.plane.SourceScan[k]) && mode_lib->ms.BytePerPixelC[k] > 0 && mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe_alpha) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6913

} else if (dml_is_vertical_rotation(mode_lib->ms.cache_display_cfg.plane.SourceScan[k]) && mode_lib->ms.BytePerPixelC[k] > 0 && mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe_alpha) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6915

} else if (mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_rgbe_alpha) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6917

} else if (dml_is_vertical_rotation(mode_lib->ms.cache_display_cfg.plane.SourceScan[k]) && mode_lib->ms.BytePerPixelY[k] == 8 && mode_lib->ms.cache_display_cfg.surface.DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6923

if (mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_420_8 || mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_420_10 || mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_420_12) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6928

mode_lib->ms.MaximumSwathWidthInLineBufferLuma = mode_lib->ms.ip.line_buffer_size_bits * dml_max(mode_lib->ms.cache_display_cfg.plane.HRatio[k], 1.0) / mode_lib->ms.cache_display_cfg.plane.LBBitPerPixel[k] /

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6929

(mode_lib->ms.cache_display_cfg.plane.VTaps[k] + dml_max(dml_ceil(mode_lib->ms.cache_display_cfg.plane.VRatio[k], 1.0) - 2, 0.0));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6935

* dml_max(mode_lib->ms.cache_display_cfg.plane.HRatioChroma[k], 1.0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6936

/ mode_lib->ms.cache_display_cfg.plane.LBBitPerPixel[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6937

/ (mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6938

+ dml_max(dml_ceil(mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k], 1.0) - 2, 0.0));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6946

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6947

mode_lib->ms.cache_display_cfg.output.DSCEnable[k] != dml_dsc_disable) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6948

mode_lib->ms.support.NumberOfDSCSlices[k] = mode_lib->ms.cache_display_cfg.output.DSCSlices[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6951

if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] > 4800) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6952

mode_lib->ms.support.NumberOfDSCSlices[k] = (dml_uint_t)(dml_ceil(mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 600, 4));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6953

} else if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] > 2400) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6955

} else if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] > 1200) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6957

} else if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] > 340) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6968

CalculateSwathAndDETConfiguration_params->DETSizeOverride = mode_lib->ms.cache_display_cfg.plane.DETSizeOverride;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6969

CalculateSwathAndDETConfiguration_params->UseMALLForPStateChange = mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6981

CalculateSwathAndDETConfiguration_params->Output = mode_lib->ms.cache_display_cfg.output.OutputEncoder;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6986

CalculateSwathAndDETConfiguration_params->SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6987

CalculateSwathAndDETConfiguration_params->ViewportStationary = mode_lib->ms.cache_display_cfg.plane.ViewportStationary;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6988

CalculateSwathAndDETConfiguration_params->SourcePixelFormat = mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6989

CalculateSwathAndDETConfiguration_params->SurfaceTiling = mode_lib->ms.cache_display_cfg.surface.SurfaceTiling;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6990

CalculateSwathAndDETConfiguration_params->ViewportWidth = mode_lib->ms.cache_display_cfg.plane.ViewportWidth;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6991

CalculateSwathAndDETConfiguration_params->ViewportHeight = mode_lib->ms.cache_display_cfg.plane.ViewportHeight;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6992

CalculateSwathAndDETConfiguration_params->ViewportXStart = mode_lib->ms.cache_display_cfg.plane.ViewportXStart;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6993

CalculateSwathAndDETConfiguration_params->ViewportYStart = mode_lib->ms.cache_display_cfg.plane.ViewportYStart;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6994

CalculateSwathAndDETConfiguration_params->ViewportXStartC = mode_lib->ms.cache_display_cfg.plane.ViewportXStartC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6995

CalculateSwathAndDETConfiguration_params->ViewportYStartC = mode_lib->ms.cache_display_cfg.plane.ViewportYStartC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6996

CalculateSwathAndDETConfiguration_params->SurfaceWidthY = mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6997

CalculateSwathAndDETConfiguration_params->SurfaceWidthC = mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6998

CalculateSwathAndDETConfiguration_params->SurfaceHeightY = mode_lib->ms.cache_display_cfg.surface.SurfaceHeightY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6999

CalculateSwathAndDETConfiguration_params->SurfaceHeightC = mode_lib->ms.cache_display_cfg.surface.SurfaceHeightC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7005

CalculateSwathAndDETConfiguration_params->BlendingAndTiming = mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7010

CalculateSwathAndDETConfiguration_params->HActive = mode_lib->ms.cache_display_cfg.timing.HActive;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7011

CalculateSwathAndDETConfiguration_params->HRatio = mode_lib->ms.cache_display_cfg.plane.HRatio;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7012

CalculateSwathAndDETConfiguration_params->HRatioChroma = mode_lib->ms.cache_display_cfg.plane.HRatioChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7050

mode_lib->ms.cache_display_cfg.timing.HActive[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7051

mode_lib->ms.cache_display_cfg.output.OutputEncoder[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7052

mode_lib->ms.cache_display_cfg.output.OutputFormat[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7059

mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7073

mode_lib->ms.cache_display_cfg.timing.HActive[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7074

mode_lib->ms.cache_display_cfg.output.OutputEncoder[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7075

mode_lib->ms.cache_display_cfg.output.OutputFormat[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7082

mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7099

(mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k),

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7100

mode_lib->ms.cache_display_cfg.output.OutputEncoder[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7101

mode_lib->ms.cache_display_cfg.output.OutputFormat[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7102

mode_lib->ms.cache_display_cfg.timing.HTotal[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7103

mode_lib->ms.cache_display_cfg.timing.HActive[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7104

mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7105

mode_lib->ms.cache_display_cfg.output.ForcedOutputLinkBPP[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7106

mode_lib->ms.cache_display_cfg.output.DSCInputBitPerComponent[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7108

mode_lib->ms.cache_display_cfg.output.AudioSampleRate[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7109

mode_lib->ms.cache_display_cfg.output.AudioSampleLayout[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7112

mode_lib->ms.cache_display_cfg.output.DSCEnable[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7113

mode_lib->ms.cache_display_cfg.output.OutputLinkDPLanes[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7114

mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7170

if (mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_420_8

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7171

|| mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_420_10

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7172

|| mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_420_12

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7173

|| mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_rgbe_alpha

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7174

|| mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k] == dml_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7181

mode_lib->ms.cache_display_cfg.output.OutputEncoder[0])) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7204

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k]) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7206

CalculateWriteBackDISPCLK(mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7207

mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7208

mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7209

mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7210

mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7211

mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7212

mode_lib->ms.cache_display_cfg.writeback.WritebackSourceWidth[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7213

mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7214

mode_lib->ms.cache_display_cfg.timing.HTotal[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7256

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7258

if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7260

if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7262

if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == k || mode_lib->ms.cache_display_cfg.output.OutputMultistreamEn[k] == false) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7276

if (mode_lib->ms.cache_display_cfg.output.OutputDisabled[k] == false &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7277

!(mode_lib->ms.cache_display_cfg.output.DSCInputBitPerComponent[k] == 12.0

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7278

|| mode_lib->ms.cache_display_cfg.output.DSCInputBitPerComponent[k] == 10.0

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7279

|| mode_lib->ms.cache_display_cfg.output.DSCInputBitPerComponent[k] == 8.0

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7280

|| mode_lib->ms.cache_display_cfg.output.DSCInputBitPerComponent[k] > (dml_uint_t) mode_lib->ms.ip.maximum_dsc_bits_per_component

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7288

if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7291

if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[j] == k)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7294

if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp && s->TotalSlots > 63)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7296

if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0 && s->TotalSlots > 64)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7302

if (mode_lib->ms.cache_display_cfg.output.OutputDisabled[k] == false &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7303

mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k && (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0 || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_edp ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7304

mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmi || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl) && mode_lib->ms.OutputBppPerState[k] == 0) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7320

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k && (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0 || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_edp ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7321

mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmi || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl)) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7322

if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_420 && mode_lib->ms.cache_display_cfg.timing.Interlace[k] == 1 && mode_lib->ms.ip.ptoi_supported == true)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7325

if (mode_lib->ms.cache_display_cfg.output.DSCEnable[k] == dml_dsc_enable_if_necessary && mode_lib->ms.cache_display_cfg.output.ForcedOutputLinkBPP[k] != 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7327

if ((mode_lib->ms.cache_display_cfg.output.DSCEnable[k] == dml_dsc_enable || mode_lib->ms.cache_display_cfg.output.DSCEnable[k] == dml_dsc_enable_if_necessary) && mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_n422 && !mode_lib->ms.ip.dsc422_native_support)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7330

if (((mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k] == dml_dp_rate_hbr || mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k] == dml_dp_rate_hbr2 || mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k] == dml_dp_rate_hbr3) &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7331

mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] != dml_dp && mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] != dml_edp) ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7332

((mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k] == dml_dp_rate_uhbr10 || mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k] == dml_dp_rate_uhbr13p5 || mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k] == dml_dp_rate_uhbr20) &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7333

mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] != dml_dp2p0))

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7336

if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamEn[k] == 1) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7337

if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == k && mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k] == dml_dp_rate_na)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7339

if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == k && mode_lib->ms.cache_display_cfg.output.ForcedOutputLinkBPP[k] == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7342

if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == j && mode_lib->ms.cache_display_cfg.output.ForcedOutputLinkBPP[k] == 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7347

if ((mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_edp || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmi || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl)) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7348

if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamEn[k] == 1 && mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == k)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7351

if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamEn[k] == 1 && mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == j)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7355

if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] != dml_dp && (mode_lib->ms.policy.ODMUse[k] == dml_odm_use_policy_split_1to2 ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7359

if ((mode_lib->ms.policy.ODMUse[k] == dml_odm_use_policy_mso_1to2 && mode_lib->ms.cache_display_cfg.output.OutputLinkDPLanes[k] < 2) ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7360

(mode_lib->ms.policy.ODMUse[k] == dml_odm_use_policy_mso_1to4 && mode_lib->ms.cache_display_cfg.output.OutputLinkDPLanes[k] < 4))

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7367

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7368

mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7371

mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7372

mode_lib->ms.cache_display_cfg.output.OutputFormat[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7375

mode_lib->ms.cache_display_cfg.timing.HTotal[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7376

mode_lib->ms.cache_display_cfg.timing.HActive[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7377

mode_lib->ms.cache_display_cfg.output.AudioSampleRate[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7378

mode_lib->ms.cache_display_cfg.output.AudioSampleLayout[k]) > mode_lib->ms.state.dtbclk_mhz) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7386

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k && mode_lib->ms.ODMModePerState[k] == dml_odm_mode_combine_2to1 && mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmi) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7389

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k && mode_lib->ms.ODMModePerState[k] == dml_odm_mode_combine_4to1 && (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7390

mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_edp || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmi)) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7397

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7398

if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7399

mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0 ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7400

mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_edp ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7401

mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7402

if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_420) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7404

} else if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_444) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7406

} else if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_n422 || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7416

if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 12.0 / (dml_float_t)s->DSCFormatFactor > (1.0 - mode_lib->ms.soc.dcn_downspread_percent / 100.0) * mode_lib->ms.state.dscclk_mhz) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7418

dml_print("DML::%s: k=%u, PixelClockBackEnd = %f\n", __func__, k, mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7425

if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 6.0 / (dml_float_t)s->DSCFormatFactor > (1.0 - mode_lib->ms.soc.dcn_downspread_percent / 100.0) * mode_lib->ms.state.dscclk_mhz) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7429

if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 3.0 / (dml_float_t)s->DSCFormatFactor > (1.0 - mode_lib->ms.soc.dcn_downspread_percent / 100.0) * mode_lib->ms.state.dscclk_mhz) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7449

if (mode_lib->ms.cache_display_cfg.timing.HActive[k] > 4 * (dml_uint_t) mode_lib->ms.ip.maximum_pixels_per_line_per_dsc_unit)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7455

if (mode_lib->ms.cache_display_cfg.timing.HActive[k] > 2 * (dml_uint_t) mode_lib->ms.ip.maximum_pixels_per_line_per_dsc_unit)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7461

if (mode_lib->ms.cache_display_cfg.timing.HActive[k] > (dml_uint_t) mode_lib->ms.ip.maximum_pixels_per_line_per_dsc_unit)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7477

mode_lib->ms.cache_display_cfg.output.DSCInputBitPerComponent[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7479

mode_lib->ms.cache_display_cfg.timing.HActive[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7480

mode_lib->ms.cache_display_cfg.timing.HTotal[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7482

mode_lib->ms.cache_display_cfg.output.OutputFormat[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7483

mode_lib->ms.cache_display_cfg.output.OutputEncoder[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7484

mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7485

mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7491

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == m && mode_lib->ms.RequiresDSC[m] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7507

CalculateSwathAndDETConfiguration_params->DETSizeOverride = mode_lib->ms.cache_display_cfg.plane.DETSizeOverride;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7508

CalculateSwathAndDETConfiguration_params->UseMALLForPStateChange = mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7520

CalculateSwathAndDETConfiguration_params->Output = mode_lib->ms.cache_display_cfg.output.OutputEncoder;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7525

CalculateSwathAndDETConfiguration_params->SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7526

CalculateSwathAndDETConfiguration_params->ViewportStationary = mode_lib->ms.cache_display_cfg.plane.ViewportStationary;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7527

CalculateSwathAndDETConfiguration_params->SourcePixelFormat = mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7528

CalculateSwathAndDETConfiguration_params->SurfaceTiling = mode_lib->ms.cache_display_cfg.surface.SurfaceTiling;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7529

CalculateSwathAndDETConfiguration_params->ViewportWidth = mode_lib->ms.cache_display_cfg.plane.ViewportWidth;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7530

CalculateSwathAndDETConfiguration_params->ViewportHeight = mode_lib->ms.cache_display_cfg.plane.ViewportHeight;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7531

CalculateSwathAndDETConfiguration_params->ViewportXStart = mode_lib->ms.cache_display_cfg.plane.ViewportXStart;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7532

CalculateSwathAndDETConfiguration_params->ViewportYStart = mode_lib->ms.cache_display_cfg.plane.ViewportYStart;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7533

CalculateSwathAndDETConfiguration_params->ViewportXStartC = mode_lib->ms.cache_display_cfg.plane.ViewportXStartC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7534

CalculateSwathAndDETConfiguration_params->ViewportYStartC = mode_lib->ms.cache_display_cfg.plane.ViewportYStartC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7535

CalculateSwathAndDETConfiguration_params->SurfaceWidthY = mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7536

CalculateSwathAndDETConfiguration_params->SurfaceWidthC = mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7537

CalculateSwathAndDETConfiguration_params->SurfaceHeightY = mode_lib->ms.cache_display_cfg.surface.SurfaceHeightY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7538

CalculateSwathAndDETConfiguration_params->SurfaceHeightC = mode_lib->ms.cache_display_cfg.surface.SurfaceHeightC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7544

CalculateSwathAndDETConfiguration_params->BlendingAndTiming = mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7549

CalculateSwathAndDETConfiguration_params->HActive = mode_lib->ms.cache_display_cfg.timing.HActive;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7550

CalculateSwathAndDETConfiguration_params->HRatio = mode_lib->ms.cache_display_cfg.plane.HRatio;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7551

CalculateSwathAndDETConfiguration_params->HRatioChroma = mode_lib->ms.cache_display_cfg.plane.HRatioChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7588

mode_lib->ms.cursor_bw[k] = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k] * mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] * mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] / 8.0 / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7594

mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7595

mode_lib->ms.cache_display_cfg.surface.DCCEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7596

mode_lib->ms.cache_display_cfg.plane.ViewportStationary,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7597

mode_lib->ms.cache_display_cfg.plane.ViewportXStart,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7598

mode_lib->ms.cache_display_cfg.plane.ViewportYStart,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7599

mode_lib->ms.cache_display_cfg.plane.ViewportXStartC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7600

mode_lib->ms.cache_display_cfg.plane.ViewportYStartC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7601

mode_lib->ms.cache_display_cfg.plane.ViewportWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7602

mode_lib->ms.cache_display_cfg.plane.ViewportHeight,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7604

mode_lib->ms.cache_display_cfg.plane.ViewportWidthChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7605

mode_lib->ms.cache_display_cfg.plane.ViewportHeightChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7607

mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7608

mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7609

mode_lib->ms.cache_display_cfg.surface.SurfaceHeightY,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7610

mode_lib->ms.cache_display_cfg.surface.SurfaceHeightC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7641

if (mode_lib->ms.cache_display_cfg.surface.DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7647

s->SurfParameters[k].PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7649

s->SurfParameters[k].SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7650

s->SurfParameters[k].ViewportHeight = mode_lib->ms.cache_display_cfg.plane.ViewportHeight[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7651

s->SurfParameters[k].ViewportHeightChroma = mode_lib->ms.cache_display_cfg.plane.ViewportHeightChroma[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7660

s->SurfParameters[k].InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7661

s->SurfParameters[k].HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7662

s->SurfParameters[k].DCCEnable = mode_lib->ms.cache_display_cfg.surface.DCCEnable[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7663

s->SurfParameters[k].SourcePixelFormat = mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7664

s->SurfParameters[k].SurfaceTiling = mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7668

s->SurfParameters[k].VRatio = mode_lib->ms.cache_display_cfg.plane.VRatio[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7669

s->SurfParameters[k].VRatioChroma = mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7670

s->SurfParameters[k].VTaps = mode_lib->ms.cache_display_cfg.plane.VTaps[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7671

s->SurfParameters[k].VTapsChroma = mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7672

s->SurfParameters[k].PitchY = mode_lib->ms.cache_display_cfg.surface.PitchY[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7673

s->SurfParameters[k].DCCMetaPitchY = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchY[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7674

s->SurfParameters[k].PitchC = mode_lib->ms.cache_display_cfg.surface.PitchC[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7675

s->SurfParameters[k].DCCMetaPitchC = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7676

s->SurfParameters[k].ViewportStationary = mode_lib->ms.cache_display_cfg.plane.ViewportStationary[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7677

s->SurfParameters[k].ViewportXStart = mode_lib->ms.cache_display_cfg.plane.ViewportXStart[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7678

s->SurfParameters[k].ViewportYStart = mode_lib->ms.cache_display_cfg.plane.ViewportYStart[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7679

s->SurfParameters[k].ViewportXStartC = mode_lib->ms.cache_display_cfg.plane.ViewportXStartC[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7680

s->SurfParameters[k].ViewportYStartC = mode_lib->ms.cache_display_cfg.plane.ViewportYStartC[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7681

s->SurfParameters[k].FORCE_ONE_ROW_FOR_FRAME = mode_lib->ms.cache_display_cfg.plane.ForceOneRowForFrame[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7692

CalculateVMRowAndSwath_params->UseMALLForStaticScreen = mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7693

CalculateVMRowAndSwath_params->UseMALLForPStateChange = mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7697

CalculateVMRowAndSwath_params->GPUVMEnable = mode_lib->ms.cache_display_cfg.plane.GPUVMEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7698

CalculateVMRowAndSwath_params->HostVMEnable = mode_lib->ms.cache_display_cfg.plane.HostVMEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7699

CalculateVMRowAndSwath_params->HostVMMaxNonCachedPageTableLevels = mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7700

CalculateVMRowAndSwath_params->GPUVMMaxPageTableLevels = mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7701

CalculateVMRowAndSwath_params->GPUVMMinPageSizeKBytes = mode_lib->ms.cache_display_cfg.plane.GPUVMMinPageSizeKBytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7703

CalculateVMRowAndSwath_params->PTEBufferModeOverrideEn = mode_lib->ms.cache_display_cfg.plane.PTEBufferModeOverrideEn;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7704

CalculateVMRowAndSwath_params->PTEBufferModeOverrideVal = mode_lib->ms.cache_display_cfg.plane.PTEBufferMode;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7797

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7802

(dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7805

mode_lib->ms.cache_display_cfg.plane.CursorWidth[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7806

mode_lib->ms.cache_display_cfg.plane.CursorBPP[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7807

mode_lib->ms.cache_display_cfg.plane.VRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7808

mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7824

mode_lib->ms.cache_display_cfg.plane.VRatio,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7825

mode_lib->ms.cache_display_cfg.plane.VRatioChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7829

mode_lib->ms.cache_display_cfg.plane.HRatio,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7830

mode_lib->ms.cache_display_cfg.plane.HRatioChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7831

mode_lib->ms.cache_display_cfg.timing.PixelClock,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7846

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7847

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7849

mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7850

mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7851

mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7852

mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7853

mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7854

mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7855

mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7856

mode_lib->ms.cache_display_cfg.timing.HTotal[k]) / mode_lib->ms.RequiredDISPCLK[j];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7861

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[m] == k && mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[m] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7864

mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[m],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7865

mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[m],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7866

mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[m],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7867

mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[m],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7868

mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[m],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7869

mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[m],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7870

mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[m],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7871

mode_lib->ms.cache_display_cfg.timing.HTotal[m]) / mode_lib->ms.RequiredDISPCLK[j]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7878

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == m) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7889

&mode_lib->ms.cache_display_cfg.timing,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7925

mode_lib->ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe || ((mode_lib->ms.cache_display_cfg.plane.HostVMEnable == true || mode_lib->ms.policy.ImmediateFlipRequirement[k] != dml_immediate_flip_not_required) &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7926

(mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_full_frame || mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7932

((mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen[k] == dml_use_mall_static_screen_enable || mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen[k] == dml_use_mall_static_screen_optimize) && (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe)) ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7933

((mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen[k] == dml_use_mall_static_screen_disable || mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen[k] == dml_use_mall_static_screen_optimize) && (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_full_frame));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7941

if (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_full_frame)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7943

if (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_sub_viewport) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7945

if (mode_lib->ms.cache_display_cfg.timing.RefreshRate[k] > 120)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7948

if (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7955

UseMinimumDCFCLK_params->UseMALLForPStateChange = mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7956

UseMinimumDCFCLK_params->DRRDisplay = mode_lib->ms.cache_display_cfg.timing.DRRDisplay;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7968

UseMinimumDCFCLK_params->GPUVMEnable = mode_lib->ms.cache_display_cfg.plane.GPUVMEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7969

UseMinimumDCFCLK_params->GPUVMMaxPageTableLevels = mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7970

UseMinimumDCFCLK_params->HostVMEnable = mode_lib->ms.cache_display_cfg.plane.HostVMEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7973

UseMinimumDCFCLK_params->HostVMMaxNonCachedPageTableLevels = mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7979

UseMinimumDCFCLK_params->VTotal = mode_lib->ms.cache_display_cfg.timing.VTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7980

UseMinimumDCFCLK_params->VActive = mode_lib->ms.cache_display_cfg.timing.VActive;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7981

UseMinimumDCFCLK_params->DynamicMetadataTransmittedBytes = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataTransmittedBytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7982

UseMinimumDCFCLK_params->DynamicMetadataLinesBeforeActiveRequired = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataLinesBeforeActiveRequired;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7983

UseMinimumDCFCLK_params->Interlace = mode_lib->ms.cache_display_cfg.timing.Interlace;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7999

UseMinimumDCFCLK_params->HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8000

UseMinimumDCFCLK_params->PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8004

UseMinimumDCFCLK_params->DynamicMetadataEnable = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8017

mode_lib->ms.cache_display_cfg.plane.HostVMEnable, mode_lib->ms.DCFCLKState[j], mode_lib->ms.state.fabricclk_mhz,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8020

mode_lib->ms.cache_display_cfg.plane.HostVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8045

((mode_lib->ms.state.use_ideal_dram_bw_strobe && !mode_lib->ms.cache_display_cfg.plane.HostVMEnable) ?

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8064

if (mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] > 0.0) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8065

if (mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] == 64 && mode_lib->ms.ip.cursor_64bpp_support == false) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8075

dml_max(mode_lib->ms.cache_display_cfg.surface.PitchY[k], mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY[k]),

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8077

if (mode_lib->ms.cache_display_cfg.surface.DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8078

mode_lib->ms.support.AlignedDCCMetaPitchY[k] = dml_ceil(dml_max(mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchY[k], mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY[k]), 64.0 * mode_lib->ms.Read256BlockWidthY[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8080

mode_lib->ms.support.AlignedDCCMetaPitchY[k] = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchY[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8082

if (mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_64

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8083

&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_32

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8084

&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_16

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8085

&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_mono_16

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8086

&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8087

&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_mono_8) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8088

mode_lib->ms.support.AlignedCPitch[k] = dml_ceil(dml_max(mode_lib->ms.cache_display_cfg.surface.PitchC[k], mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC[k]), mode_lib->ms.MacroTileWidthC[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8089

if (mode_lib->ms.cache_display_cfg.surface.DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8090

mode_lib->ms.support.AlignedDCCMetaPitchC[k] = dml_ceil(dml_max(mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k], mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC[k]), 64.0 * mode_lib->ms.Read256BlockWidthC[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8092

mode_lib->ms.support.AlignedDCCMetaPitchC[k] = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8095

mode_lib->ms.support.AlignedCPitch[k] = mode_lib->ms.cache_display_cfg.surface.PitchC[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8096

mode_lib->ms.support.AlignedDCCMetaPitchC[k] = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8098

if (mode_lib->ms.support.AlignedYPitch[k] > mode_lib->ms.cache_display_cfg.surface.PitchY[k] || mode_lib->ms.support.AlignedCPitch[k] > mode_lib->ms.cache_display_cfg.surface.PitchC[k] ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8099

mode_lib->ms.support.AlignedDCCMetaPitchY[k] > mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchY[k] || mode_lib->ms.support.AlignedDCCMetaPitchC[k] > mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k]) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8106

if (mode_lib->ms.cache_display_cfg.plane.ViewportWidth[k] > mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY[k] || mode_lib->ms.cache_display_cfg.plane.ViewportHeight[k] > mode_lib->ms.cache_display_cfg.surface.SurfaceHeightY[k]) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8108

if (mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_64 && mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_32 &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8109

mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_16 && mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_8 && mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8110

if (mode_lib->ms.cache_display_cfg.plane.ViewportWidthChroma[k] > mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC[k] || mode_lib->ms.cache_display_cfg.plane.ViewportHeightChroma[k] > mode_lib->ms.cache_display_cfg.surface.SurfaceHeightC[k]) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8179

&& ((mode_lib->ms.cache_display_cfg.plane.HostVMEnable == false && !s->ImmediateFlipRequiredFinal) || mode_lib->ms.support.ImmediateFlipSupportedForState[j])

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8245

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8278

PixelClockAdjustmentForProgressiveToInterlaceUnit(&mode_lib->ms.cache_display_cfg, mode_lib->ms.ip.ptoi_supported);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8282

mode_lib->ms.cache_display_cfg.plane.HostVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8306

mode_lib->ms.num_active_planes = dml_get_num_active_planes(&mode_lib->ms.cache_display_cfg);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8307

mode_lib->mp.num_active_pipes = dml_get_num_active_pipes(&mode_lib->ms.cache_display_cfg);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8308

dml_calc_pipe_plane_mapping(&mode_lib->ms.cache_display_cfg.hw, mode_lib->mp.pipe_plane);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8341

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k]) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8346

mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8347

mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8348

mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8349

mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8350

mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8351

mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8352

mode_lib->ms.cache_display_cfg.writeback.WritebackSourceWidth[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8353

mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8354

mode_lib->ms.cache_display_cfg.timing.HTotal[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8363

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8365

mode_lib->ms.cache_display_cfg.hw.ODMMode[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8366

mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8385

mode_lib->ms.cache_display_cfg.plane.HRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8386

mode_lib->ms.cache_display_cfg.plane.HRatioChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8387

mode_lib->ms.cache_display_cfg.plane.VRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8388

mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8391

mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8392

mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8393

mode_lib->ms.cache_display_cfg.plane.HTaps[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8394

mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8395

mode_lib->ms.cache_display_cfg.plane.VTaps[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8396

mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8408

mode_lib->ms.cache_display_cfg.hw.DPPPerSurface,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8427

mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8428

mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8450

mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8451

mode_lib->ms.cache_display_cfg.plane.SourceScan,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8452

mode_lib->ms.cache_display_cfg.plane.ViewportStationary,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8453

mode_lib->ms.cache_display_cfg.plane.ViewportWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8454

mode_lib->ms.cache_display_cfg.plane.ViewportHeight,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8455

mode_lib->ms.cache_display_cfg.plane.ViewportXStart,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8456

mode_lib->ms.cache_display_cfg.plane.ViewportYStart,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8457

mode_lib->ms.cache_display_cfg.plane.ViewportXStartC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8458

mode_lib->ms.cache_display_cfg.plane.ViewportYStartC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8459

mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8460

mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8461

mode_lib->ms.cache_display_cfg.surface.SurfaceHeightY,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8462

mode_lib->ms.cache_display_cfg.surface.SurfaceHeightC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8463

mode_lib->ms.cache_display_cfg.hw.ODMMode,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8470

mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8471

mode_lib->ms.cache_display_cfg.timing.HActive,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8472

mode_lib->ms.cache_display_cfg.plane.HRatio,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8473

mode_lib->ms.cache_display_cfg.hw.DPPPerSurface,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8486

locals->ReadBandwidthSurfaceLuma[k] = locals->SwathWidthSingleDPPY[k] * locals->BytePerPixelY[k] / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8487

locals->ReadBandwidthSurfaceChroma[k] = locals->SwathWidthSingleDPPC[k] * locals->BytePerPixelC[k] / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8492

CalculateSwathAndDETConfiguration_params->DETSizeOverride = mode_lib->ms.cache_display_cfg.plane.DETSizeOverride;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8493

CalculateSwathAndDETConfiguration_params->UseMALLForPStateChange = mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8510

CalculateSwathAndDETConfiguration_params->SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8511

CalculateSwathAndDETConfiguration_params->ViewportStationary = mode_lib->ms.cache_display_cfg.plane.ViewportStationary;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8512

CalculateSwathAndDETConfiguration_params->SourcePixelFormat = mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8513

CalculateSwathAndDETConfiguration_params->SurfaceTiling = mode_lib->ms.cache_display_cfg.surface.SurfaceTiling;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8514

CalculateSwathAndDETConfiguration_params->ViewportWidth = mode_lib->ms.cache_display_cfg.plane.ViewportWidth;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8515

CalculateSwathAndDETConfiguration_params->ViewportHeight = mode_lib->ms.cache_display_cfg.plane.ViewportHeight;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8516

CalculateSwathAndDETConfiguration_params->ViewportXStart = mode_lib->ms.cache_display_cfg.plane.ViewportXStart;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8517

CalculateSwathAndDETConfiguration_params->ViewportYStart = mode_lib->ms.cache_display_cfg.plane.ViewportYStart;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8518

CalculateSwathAndDETConfiguration_params->ViewportXStartC = mode_lib->ms.cache_display_cfg.plane.ViewportXStartC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8519

CalculateSwathAndDETConfiguration_params->ViewportYStartC = mode_lib->ms.cache_display_cfg.plane.ViewportYStartC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8520

CalculateSwathAndDETConfiguration_params->SurfaceWidthY = mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8521

CalculateSwathAndDETConfiguration_params->SurfaceWidthC = mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8522

CalculateSwathAndDETConfiguration_params->SurfaceHeightY = mode_lib->ms.cache_display_cfg.surface.SurfaceHeightY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8523

CalculateSwathAndDETConfiguration_params->SurfaceHeightC = mode_lib->ms.cache_display_cfg.surface.SurfaceHeightC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8528

CalculateSwathAndDETConfiguration_params->ODMMode = mode_lib->ms.cache_display_cfg.hw.ODMMode;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8529

CalculateSwathAndDETConfiguration_params->BlendingAndTiming = mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8534

CalculateSwathAndDETConfiguration_params->HActive = mode_lib->ms.cache_display_cfg.timing.HActive;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8535

CalculateSwathAndDETConfiguration_params->HRatio = mode_lib->ms.cache_display_cfg.plane.HRatio;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8536

CalculateSwathAndDETConfiguration_params->HRatioChroma = mode_lib->ms.cache_display_cfg.plane.HRatioChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8537

CalculateSwathAndDETConfiguration_params->DPPPerSurface = mode_lib->ms.cache_display_cfg.hw.DPPPerSurface;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8564

mode_lib->ms.cache_display_cfg.plane.VRatio,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8565

mode_lib->ms.cache_display_cfg.plane.VRatioChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8568

mode_lib->ms.cache_display_cfg.hw.DPPPerSurface,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8569

mode_lib->ms.cache_display_cfg.plane.HRatio,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8570

mode_lib->ms.cache_display_cfg.plane.HRatioChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8571

mode_lib->ms.cache_display_cfg.timing.PixelClock,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8584

if ((mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] != k) || !mode_lib->ms.cache_display_cfg.hw.DSCEnabled[k]) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8587

if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_420)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8589

else if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_444)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8591

else if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_n422 || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8595

if (mode_lib->ms.cache_display_cfg.hw.ODMMode[k] == dml_odm_mode_combine_4to1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8596

locals->DSCCLK_calculated[k] = mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 12 / s->DSCFormatFactor / (1 - mode_lib->ms.soc.dcn_downspread_percent / 100);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8597

else if (mode_lib->ms.cache_display_cfg.hw.ODMMode[k] == dml_odm_mode_combine_2to1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8598

locals->DSCCLK_calculated[k] = mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 6 / s->DSCFormatFactor / (1 - mode_lib->ms.soc.dcn_downspread_percent / 100);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8600

locals->DSCCLK_calculated[k] = mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 3 / s->DSCFormatFactor / (1 - mode_lib->ms.soc.dcn_downspread_percent / 100);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8606

locals->DSCDelay[k] = DSCDelayRequirement(mode_lib->ms.cache_display_cfg.hw.DSCEnabled[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8607

mode_lib->ms.cache_display_cfg.hw.ODMMode[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8608

mode_lib->ms.cache_display_cfg.output.DSCInputBitPerComponent[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8609

mode_lib->ms.cache_display_cfg.output.OutputBpp[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8610

mode_lib->ms.cache_display_cfg.timing.HActive[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8611

mode_lib->ms.cache_display_cfg.timing.HTotal[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8612

mode_lib->ms.cache_display_cfg.hw.NumberOfDSCSlices[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8613

mode_lib->ms.cache_display_cfg.output.OutputFormat[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8614

mode_lib->ms.cache_display_cfg.output.OutputEncoder[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8615

mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8616

mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8621

if (j != k && mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == j && mode_lib->ms.cache_display_cfg.hw.DSCEnabled[j])

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8628

mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8629

mode_lib->ms.cache_display_cfg.surface.DCCEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8630

mode_lib->ms.cache_display_cfg.plane.ViewportStationary,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8631

mode_lib->ms.cache_display_cfg.plane.ViewportXStart,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8632

mode_lib->ms.cache_display_cfg.plane.ViewportYStart,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8633

mode_lib->ms.cache_display_cfg.plane.ViewportXStartC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8634

mode_lib->ms.cache_display_cfg.plane.ViewportYStartC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8635

mode_lib->ms.cache_display_cfg.plane.ViewportWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8636

mode_lib->ms.cache_display_cfg.plane.ViewportHeight,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8638

mode_lib->ms.cache_display_cfg.plane.ViewportWidthChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8639

mode_lib->ms.cache_display_cfg.plane.ViewportHeightChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8641

mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8642

mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8643

mode_lib->ms.cache_display_cfg.surface.SurfaceHeightY,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8644

mode_lib->ms.cache_display_cfg.surface.SurfaceHeightC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8659

s->SurfaceParameters[k].PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8660

s->SurfaceParameters[k].DPPPerSurface = mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8661

s->SurfaceParameters[k].SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8662

s->SurfaceParameters[k].ViewportHeight = mode_lib->ms.cache_display_cfg.plane.ViewportHeight[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8663

s->SurfaceParameters[k].ViewportHeightChroma = mode_lib->ms.cache_display_cfg.plane.ViewportHeightChroma[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8672

s->SurfaceParameters[k].InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8673

s->SurfaceParameters[k].HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8674

s->SurfaceParameters[k].DCCEnable = mode_lib->ms.cache_display_cfg.surface.DCCEnable[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8675

s->SurfaceParameters[k].SourcePixelFormat = mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8676

s->SurfaceParameters[k].SurfaceTiling = mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8680

s->SurfaceParameters[k].VRatio = mode_lib->ms.cache_display_cfg.plane.VRatio[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8681

s->SurfaceParameters[k].VRatioChroma = mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8682

s->SurfaceParameters[k].VTaps = mode_lib->ms.cache_display_cfg.plane.VTaps[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8683

s->SurfaceParameters[k].VTapsChroma = mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8684

s->SurfaceParameters[k].PitchY = mode_lib->ms.cache_display_cfg.surface.PitchY[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8685

s->SurfaceParameters[k].DCCMetaPitchY = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchY[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8686

s->SurfaceParameters[k].PitchC = mode_lib->ms.cache_display_cfg.surface.PitchC[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8687

s->SurfaceParameters[k].DCCMetaPitchC = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8688

s->SurfaceParameters[k].ViewportStationary = mode_lib->ms.cache_display_cfg.plane.ViewportStationary[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8689

s->SurfaceParameters[k].ViewportXStart = mode_lib->ms.cache_display_cfg.plane.ViewportXStart[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8690

s->SurfaceParameters[k].ViewportYStart = mode_lib->ms.cache_display_cfg.plane.ViewportYStart[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8691

s->SurfaceParameters[k].ViewportXStartC = mode_lib->ms.cache_display_cfg.plane.ViewportXStartC[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8692

s->SurfaceParameters[k].ViewportYStartC = mode_lib->ms.cache_display_cfg.plane.ViewportYStartC[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8693

s->SurfaceParameters[k].FORCE_ONE_ROW_FOR_FRAME = mode_lib->ms.cache_display_cfg.plane.ForceOneRowForFrame[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8704

CalculateVMRowAndSwath_params->UseMALLForStaticScreen = mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8705

CalculateVMRowAndSwath_params->UseMALLForPStateChange = mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8709

CalculateVMRowAndSwath_params->GPUVMEnable = mode_lib->ms.cache_display_cfg.plane.GPUVMEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8710

CalculateVMRowAndSwath_params->HostVMEnable = mode_lib->ms.cache_display_cfg.plane.HostVMEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8711

CalculateVMRowAndSwath_params->HostVMMaxNonCachedPageTableLevels = mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8712

CalculateVMRowAndSwath_params->GPUVMMaxPageTableLevels = mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8713

CalculateVMRowAndSwath_params->GPUVMMinPageSizeKBytes = mode_lib->ms.cache_display_cfg.plane.GPUVMMinPageSizeKBytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8715

CalculateVMRowAndSwath_params->PTEBufferModeOverrideEn = mode_lib->ms.cache_display_cfg.plane.PTEBufferModeOverrideEn;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8716

CalculateVMRowAndSwath_params->PTEBufferModeOverrideVal = mode_lib->ms.cache_display_cfg.plane.PTEBufferMode;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8772

mode_lib->ms.cache_display_cfg.plane.HostVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8794

if (mode_lib->ms.cache_display_cfg.plane.GPUVMEnable && mode_lib->ms.cache_display_cfg.plane.HostVMEnable)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8800

s->TotalActiveDPP = s->TotalActiveDPP + mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8801

if (mode_lib->ms.cache_display_cfg.surface.DCCEnable[k])

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8802

s->TotalDCCActiveDPP = s->TotalDCCActiveDPP + mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8814

mode_lib->ms.cache_display_cfg.plane.GPUVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8815

mode_lib->ms.cache_display_cfg.plane.HostVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8817

mode_lib->ms.cache_display_cfg.hw.DPPPerSurface,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8821

mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8826

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8827

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8831

mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8832

mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8833

mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8834

mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8835

mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8836

mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8837

mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8838

mode_lib->ms.cache_display_cfg.timing.HTotal[k]) / locals->Dispclk;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8842

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[j] == k

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8843

&& mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[j] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8849

mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[j],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8850

mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[j],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8851

mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[j],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8852

mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[j],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8853

mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[j],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8854

mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[j],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8855

mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[j],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8856

mode_lib->ms.cache_display_cfg.timing.HTotal[k]) / locals->Dispclk);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8864

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == j)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8876

CalculateUrgentBurstFactor(mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8881

mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8884

mode_lib->ms.cache_display_cfg.plane.CursorWidth[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8885

mode_lib->ms.cache_display_cfg.plane.CursorBPP[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8886

mode_lib->ms.cache_display_cfg.plane.VRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8887

mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8899

locals->cursor_bw[k] = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k] * mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] * mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] / 8.0 /

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8900

((dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8910

&mode_lib->ms.cache_display_cfg.timing,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8954

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8956

mode_lib->ms.cache_display_cfg.timing.DRRDisplay[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8965

myPipe->PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8967

myPipe->DPPPerSurface = mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8968

myPipe->ScalerEnabled = mode_lib->ms.cache_display_cfg.plane.ScalerEnabled[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8969

myPipe->SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8974

myPipe->InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8975

myPipe->NumberOfCursors = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8976

myPipe->VBlank = mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8977

myPipe->HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8978

myPipe->HActive = mode_lib->ms.cache_display_cfg.timing.HActive[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8979

myPipe->DCCEnable = mode_lib->ms.cache_display_cfg.surface.DCCEnable[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8980

myPipe->ODMMode = mode_lib->ms.cache_display_cfg.hw.ODMMode[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8981

myPipe->SourcePixelFormat = mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9001

CalculatePrefetchSchedule_params->DPP_RECOUT_WIDTH = (dml_uint_t)(locals->SwathWidthY[k] / mode_lib->ms.cache_display_cfg.plane.HRatio[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9002

CalculatePrefetchSchedule_params->OutputFormat = mode_lib->ms.cache_display_cfg.output.OutputFormat[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9006

CalculatePrefetchSchedule_params->GPUVMPageTableLevels = mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9007

CalculatePrefetchSchedule_params->GPUVMEnable = mode_lib->ms.cache_display_cfg.plane.GPUVMEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9008

CalculatePrefetchSchedule_params->HostVMEnable = mode_lib->ms.cache_display_cfg.plane.HostVMEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9009

CalculatePrefetchSchedule_params->HostVMMaxNonCachedPageTableLevels = mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9011

CalculatePrefetchSchedule_params->DynamicMetadataEnable = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataEnable[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9013

CalculatePrefetchSchedule_params->DynamicMetadataLinesBeforeActiveRequired = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataLinesBeforeActiveRequired[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9014

CalculatePrefetchSchedule_params->DynamicMetadataTransmittedBytes = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataTransmittedBytes[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9064

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9069

mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9072

mode_lib->ms.cache_display_cfg.plane.CursorWidth[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9073

mode_lib->ms.cache_display_cfg.plane.CursorBPP[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9086

locals->cursor_bw_pre[k] = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k] * mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] * mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] / 8.0 / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * locals->VRatioPrefetchY[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9089

dml_print("DML::%s: k=%0u DPPPerSurface=%u\n", __func__, k, mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9096

dml_print("DML::%s: k=%0u VRatioY=%f\n", __func__, k, mode_lib->ms.cache_display_cfg.plane.VRatio[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9140

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9151

mode_lib->ms.cache_display_cfg.hw.DPPPerSurface,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9170

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9181

mode_lib->ms.cache_display_cfg.hw.DPPPerSurface,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9222

mode_lib->ms.cache_display_cfg.hw.DPPPerSurface,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9233

locals->TotImmediateFlipBytes = locals->TotImmediateFlipBytes + mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k] * (locals->PDEAndMetaPTEBytesFrame[k] + locals->MetaRowByte[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9235

locals->TotImmediateFlipBytes = locals->TotImmediateFlipBytes + mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k] * (2 * locals->PixelPTEBytesPerRow[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9237

locals->TotImmediateFlipBytes = locals->TotImmediateFlipBytes + mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k] * locals->PixelPTEBytesPerRow[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9241

dml_print("DML::%s: DPPPerSurface = %u\n", __func__, mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9254

mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9255

mode_lib->ms.cache_display_cfg.plane.HostVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9256

mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9257

mode_lib->ms.cache_display_cfg.plane.GPUVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9264

mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9265

mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9266

mode_lib->ms.cache_display_cfg.plane.VRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9267

mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9269

mode_lib->ms.cache_display_cfg.surface.DCCEnable[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9285

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9297

mode_lib->ms.cache_display_cfg.hw.DPPPerSurface,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9313

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9325

mode_lib->ms.cache_display_cfg.hw.DPPPerSurface,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9357

((!mode_lib->ms.support.ImmediateFlipSupport && !mode_lib->ms.cache_display_cfg.plane.HostVMEnable && !s->ImmediateFlipRequirementFinal) ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9364

dml_print("DML::%s: HostVMEnable = %u\n", __func__, mode_lib->ms.cache_display_cfg.plane.HostVMEnable);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9414

CalculateWatermarks_params->UseMALLForPStateChange = mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9424

CalculateWatermarks_params->DRRDisplay = mode_lib->ms.cache_display_cfg.timing.DRRDisplay;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9436

CalculateWatermarks_params->LBBitPerPixel = mode_lib->ms.cache_display_cfg.plane.LBBitPerPixel;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9439

CalculateWatermarks_params->HRatio = mode_lib->ms.cache_display_cfg.plane.HRatio;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9440

CalculateWatermarks_params->HRatioChroma = mode_lib->ms.cache_display_cfg.plane.HRatioChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9441

CalculateWatermarks_params->VTaps = mode_lib->ms.cache_display_cfg.plane.VTaps;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9442

CalculateWatermarks_params->VTapsChroma = mode_lib->ms.cache_display_cfg.plane.VTapsChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9443

CalculateWatermarks_params->VRatio = mode_lib->ms.cache_display_cfg.plane.VRatio;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9444

CalculateWatermarks_params->VRatioChroma = mode_lib->ms.cache_display_cfg.plane.VRatioChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9445

CalculateWatermarks_params->HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9446

CalculateWatermarks_params->VTotal = mode_lib->ms.cache_display_cfg.timing.VTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9447

CalculateWatermarks_params->VActive = mode_lib->ms.cache_display_cfg.timing.VActive;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9448

CalculateWatermarks_params->PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9449

CalculateWatermarks_params->BlendingAndTiming = mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9450

CalculateWatermarks_params->DPPPerSurface = mode_lib->ms.cache_display_cfg.hw.DPPPerSurface;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9455

CalculateWatermarks_params->WritebackEnable = mode_lib->ms.cache_display_cfg.writeback.WritebackEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9456

CalculateWatermarks_params->WritebackPixelFormat = mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9457

CalculateWatermarks_params->WritebackDestinationWidth = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9458

CalculateWatermarks_params->WritebackDestinationHeight = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9459

CalculateWatermarks_params->WritebackSourceHeight = mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9484

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9485

locals->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(0, locals->VStartupMin[k] * mode_lib->ms.cache_display_cfg.timing.HTotal[k] /

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9486

mode_lib->ms.cache_display_cfg.timing.PixelClock[k] - locals->Watermark.WritebackDRAMClockChangeWatermark);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9487

locals->WritebackAllowFCLKChangeEndPosition[k] = dml_max(0, locals->VStartupMin[k] * mode_lib->ms.cache_display_cfg.timing.HTotal[k] /

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9488

mode_lib->ms.cache_display_cfg.timing.PixelClock[k] - locals->Watermark.WritebackFCLKChangeWatermark);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9499

mode_lib->ms.cache_display_cfg.plane.VRatio,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9500

mode_lib->ms.cache_display_cfg.plane.VRatioChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9505

mode_lib->ms.cache_display_cfg.hw.DPPPerSurface,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9506

mode_lib->ms.cache_display_cfg.plane.HRatio,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9507

mode_lib->ms.cache_display_cfg.plane.HRatioChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9508

mode_lib->ms.cache_display_cfg.timing.PixelClock,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9513

mode_lib->ms.cache_display_cfg.plane.SourceScan,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9514

mode_lib->ms.cache_display_cfg.plane.NumberOfCursors,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9515

mode_lib->ms.cache_display_cfg.plane.CursorWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9516

mode_lib->ms.cache_display_cfg.plane.CursorBPP,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9537

mode_lib->ms.cache_display_cfg.plane.GPUVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9540

mode_lib->ms.cache_display_cfg.timing.HTotal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9541

mode_lib->ms.cache_display_cfg.plane.VRatio,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9542

mode_lib->ms.cache_display_cfg.plane.VRatioChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9545

mode_lib->ms.cache_display_cfg.surface.DCCEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9546

mode_lib->ms.cache_display_cfg.timing.PixelClock,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9549

mode_lib->ms.cache_display_cfg.plane.SourceScan,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9590

mode_lib->ms.cache_display_cfg.plane.GPUVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9591

mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9592

mode_lib->ms.cache_display_cfg.timing.HTotal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9596

mode_lib->ms.cache_display_cfg.surface.DCCEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9597

mode_lib->ms.cache_display_cfg.timing.PixelClock,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9632

if (!mode_lib->ms.cache_display_cfg.plane.DynamicMetadataEnable[k])

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9642

mode_lib->ms.cache_display_cfg.surface.DCCEnable[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9644

mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9645

mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9646

mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9647

mode_lib->ms.cache_display_cfg.surface.SurfaceHeightY[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9648

mode_lib->ms.cache_display_cfg.surface.SurfaceHeightC[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9652

mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9657

mode_lib->ms.cache_display_cfg.plane.SourceScan[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9669

s->Tvstartup_margin = (s->MaxVStartupLines[k] - locals->VStartupMin[k]) * mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9683

if (mode_lib->ms.cache_display_cfg.plane.DynamicMetadataEnable[k] && mode_lib->ms.ip.dynamic_metadata_vm_enabled) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9687

isInterlaceTiming = (mode_lib->ms.cache_display_cfg.timing.Interlace[k] && !mode_lib->ms.ip.ptoi_supported);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9692

s->dlg_vblank_start = ((isInterlaceTiming ? dml_floor((mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k]) / 2.0, 1.0) :

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9693

mode_lib->ms.cache_display_cfg.timing.VTotal[k]) - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9694

s->LSetup = dml_floor(4.0 * locals->TSetup[k] / ((dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]), 1.0) / 4.0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9695

s->blank_lines_remaining = (mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k]) - locals->VStartup[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9705

s->old_MIN_DST_Y_NEXT_START = ((isInterlaceTiming ? dml_floor((mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k]) / 2.0, 1.0) :

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9706

mode_lib->ms.cache_display_cfg.timing.VTotal[k]) - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k])

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9707

+ dml_max(1.0, dml_ceil((dml_float_t) locals->WritebackDelay[k] / ((dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]), 1.0))

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9708

+ dml_floor(4.0 * locals->TSetup[k] / ((dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]), 1.0) / 4.0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9710

if (((locals->VUpdateOffsetPix[k] + locals->VUpdateWidthPix[k] + locals->VReadyOffsetPix[k]) / (double) mode_lib->ms.cache_display_cfg.timing.HTotal[k]) <=

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9712

dml_floor((mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k] - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k] - locals->VStartup[k]) / 2.0, 1.0) :

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9713

(int) (mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k] - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k] - locals->VStartup[k]))) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9724

dml_print("DML::%s: k=%u, HTotal = %u\n", __func__, k, mode_lib->ms.cache_display_cfg.timing.HTotal[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9725

dml_print("DML::%s: k=%u, VTotal = %u\n", __func__, k, mode_lib->ms.cache_display_cfg.timing.VTotal[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9726

dml_print("DML::%s: k=%u, VActive = %u\n", __func__, k, mode_lib->ms.cache_display_cfg.timing.VActive[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9727

dml_print("DML::%s: k=%u, VFrontPorch = %u\n", __func__, k, mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9739

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true && mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k] == dml_444_32) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9740

s->WRBandwidth = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k] * mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k] /

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9741

(mode_lib->ms.cache_display_cfg.timing.HTotal[k] * mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * 4;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9742

} else if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9743

s->WRBandwidth = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k] * mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k] /

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9744

(mode_lib->ms.cache_display_cfg.timing.HTotal[k] * mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * 8;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9762

if (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9769

CalculateStutterEfficiency_params->UseMALLForPStateChange = mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9784

CalculateStutterEfficiency_params->BlendingAndTiming = mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9788

CalculateStutterEfficiency_params->Interlace = mode_lib->ms.cache_display_cfg.timing.Interlace;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9790

CalculateStutterEfficiency_params->DPPPerSurface = mode_lib->ms.cache_display_cfg.hw.DPPPerSurface;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9797

CalculateStutterEfficiency_params->NetDCCRateLuma = mode_lib->ms.cache_display_cfg.surface.DCCRateLuma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9798

CalculateStutterEfficiency_params->NetDCCRateChroma = mode_lib->ms.cache_display_cfg.surface.DCCRateChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9799

CalculateStutterEfficiency_params->DCCFractionOfZeroSizeRequestsLuma = mode_lib->ms.cache_display_cfg.surface.DCCFractionOfZeroSizeRequestsLuma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9800

CalculateStutterEfficiency_params->DCCFractionOfZeroSizeRequestsChroma = mode_lib->ms.cache_display_cfg.surface.DCCFractionOfZeroSizeRequestsChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9801

CalculateStutterEfficiency_params->HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9802

CalculateStutterEfficiency_params->VTotal = mode_lib->ms.cache_display_cfg.timing.VTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9803

CalculateStutterEfficiency_params->PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9804

CalculateStutterEfficiency_params->VRatio = mode_lib->ms.cache_display_cfg.plane.VRatio;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9805

CalculateStutterEfficiency_params->SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9812

CalculateStutterEfficiency_params->VActive = mode_lib->ms.cache_display_cfg.timing.VActive;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9813

CalculateStutterEfficiency_params->DCCEnable = mode_lib->ms.cache_display_cfg.surface.DCCEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9814

CalculateStutterEfficiency_params->WritebackEnable = mode_lib->ms.cache_display_cfg.writeback.WritebackEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9841

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9856

mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9860

mode_lib->ms.cache_display_cfg.timing.Interlace,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9862

mode_lib->ms.cache_display_cfg.hw.DPPPerSurface,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9869

mode_lib->ms.cache_display_cfg.surface.DCCRateLuma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9870

mode_lib->ms.cache_display_cfg.surface.DCCRateChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9871

mode_lib->ms.cache_display_cfg.surface.DCCFractionOfZeroSizeRequestsLuma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9872

mode_lib->ms.cache_display_cfg.surface.DCCFractionOfZeroSizeRequestsChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9873

mode_lib->ms.cache_display_cfg.timing.HTotal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9874

mode_lib->ms.cache_display_cfg.timing.VTotal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9875

mode_lib->ms.cache_display_cfg.timing.PixelClock,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9876

mode_lib->ms.cache_display_cfg.plane.VRatio,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9877

mode_lib->ms.cache_display_cfg.plane.SourceScan,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9884

mode_lib->ms.cache_display_cfg.timing.VActive,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9885

mode_lib->ms.cache_display_cfg.surface.DCCEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9886

mode_lib->ms.cache_display_cfg.writeback.WritebackEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

820

struct dml_display_cfg_st cache_display_cfg; // <brief A copy of the current display cfg in consideration

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

404

dml_print("DML: MODE SUPPORT: Host VM or Immediate Flip Supported : %s\n", ((mode_lib->ms.cache_display_cfg.plane.HostVMEnable == false && !mode_lib->scratch.dml_core_mode_support_locals.ImmediateFlipRequiredFinal) || mode_lib->ms.support.ImmediateFlipSupportedForState[j]) ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

203

enum dml_source_format_class source_format = mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[plane_idx];

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

204

struct dml_timing_cfg_st *timing = &mode_lib->ms.cache_display_cfg.timing;

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

205

struct dml_plane_cfg_st *plane = &mode_lib->ms.cache_display_cfg.plane;

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

206

struct dml_hw_resource_st *hw = &mode_lib->ms.cache_display_cfg.hw;

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

293

dml_uint_t num_active_pipes = dml_get_num_active_pipes(&mode_lib->ms.cache_display_cfg);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

44

enum dml_source_format_class source_format = mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[plane_idx];

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

45

enum dml_swizzle_mode sw_mode = mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[plane_idx];