sys/dev/pci/drm/i915/gt/gen7_renderclear.c

406

batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1));

sys/dev/pci/drm/i915/gt/intel_workarounds.c

358

CACHE_MODE_1,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

395

wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

481

wa_masked_en(wal, CACHE_MODE_1,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

808

wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

856

wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);

sys/dev/pci/drm/i915/gvt/handlers.c

2267

MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/mmio_context.c

108

{RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

76

{RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

109

MMIO_D(CACHE_MODE_1);