sys/dev/pci/drm/i915/gt/gen7_renderclear.c

400

batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7));

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2513

CACHE_MODE_0_GEN7,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2554

CACHE_MODE_0_GEN7,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

350

wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

392

wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

694

wa_masked_en(wal, CACHE_MODE_0_GEN7,

sys/dev/pci/drm/i915/gvt/handlers.c

2265

MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,

sys/dev/pci/drm/i915/gvt/mmio_context.c

110

{RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

78

{RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

108

MMIO_D(CACHE_MODE_0_GEN7);