CACHELINE_BYTES
!IS_ALIGNED(dsb->free_pos * 4, CACHELINE_BYTES));
aligned_tail = ALIGN(tail, CACHELINE_BYTES);
aligned_tail = ALIGN(tail, CACHELINE_BYTES);
size = ALIGN(max_cmds * 8, CACHELINE_BYTES);
#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
while ((unsigned long)cs % CACHELINE_BYTES)
while ((unsigned long)batch % CACHELINE_BYTES)
while ((unsigned long)batch % CACHELINE_BYTES)
CACHELINE_BYTES))) {
GEM_BUG_ON(!IS_ALIGNED(size, CACHELINE_BYTES));
ctx_bb_ggtt_addr | (size / CACHELINE_BYTES);
ring->effective_size -= 2 * CACHELINE_BYTES;
#define cacheline(a) round_down(a, CACHELINE_BYTES)
return (head - tail - CACHELINE_BYTES) & (size - 1);
#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
u8 unused[CACHELINE_BYTES - sizeof(u32)];
BUILD_BUG_ON(sizeof(struct sync_semaphore) != CACHELINE_BYTES);
ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
roundup(ctx_size + CACHELINE_BYTES,
memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
CACHELINE_BYTES;
CACHELINE_BYTES)) {
0, CACHELINE_BYTES, 0);
memset(per_ctx_va, 0, CACHELINE_BYTES);