CACHELINESIZE
by = CACHELINESIZE;
status = bus_dmamem_alloc(fb->fb_dmat, fb->fb_len, CACHELINESIZE, 0,
cn30xxfpa_store(paddr, fb->fb_poolno, fb->fb_size / CACHELINESIZE);
SET(first_next_ptr_back, (sc->sc_first_mbuff_skip / CACHELINESIZE)
SET(second_next_ptr_back, (sc->sc_not_first_mbuff_skip / CACHELINESIZE)
CTASSERT(MCLBYTES >= OCTEON_POOL_SIZE_PKT + CACHELINESIZE);
OCTEON_POOL_SIZE_PKT + CACHELINESIZE);
m->m_data = (void *)(((vaddr_t)m->m_data + CACHELINESIZE) &
~(CACHELINESIZE - 1));
OCTEON_POOL_SIZE_PKT / CACHELINESIZE);
pktbuf = (addr & ~(CACHELINESIZE - 1)) - back * CACHELINESIZE;
pktbuf = (addr & ~(CACHELINESIZE - 1)) - back * CACHELINESIZE;
OCTEON_POOL_SIZE_PKT / CACHELINESIZE);
pktbuf = pktdata & ~(CACHELINESIZE - 1);
m->m_data += (pktdata - pktbuf) & (CACHELINESIZE - 1);
pktbuf = pktdata & ~(CACHELINESIZE - 1);
m->m_data = (void *)(((vaddr_t)m->m_data + CACHELINESIZE) &
~(CACHELINESIZE - 1));
if (bus_dmamem_alloc(node->node_dmat, segsize, CACHELINESIZE,
FPA3_WR_8(node, FPA3_POOL_START_ADDR(poolid), CACHELINESIZE);
KASSERT(size % CACHELINESIZE == 0);
if (bus_dmamem_alloc(node->node_dmat, totsize, CACHELINESIZE, 0,
val |= ((MCLBYTES - CACHELINESIZE) / sizeof(uint64_t)) <<
#ifndef CACHELINESIZE
by = CACHELINESIZE;
len = len + (((u_int32_t) from) & (CACHELINESIZE - 1));
p += CACHELINESIZE;
} while ((l -= CACHELINESIZE) > 0);
len = len + (((u_int32_t) from) & (CACHELINESIZE - 1));
p += CACHELINESIZE;
} while ((l -= CACHELINESIZE) > 0);
for (i = 0; i < PAGE_SIZE; i += CACHELINESIZE)
CACHELINESIZE, IPL_TTY, 0, "amdgpu_mux_chunk", NULL);
CACHELINESIZE, IPL_TTY, 0, "amdgpu_sync", NULL);
CACHELINESIZE, IPL_TTY, 0, "amdgpu_userq_fence", NULL);
CACHELINESIZE, IPL_NONE, 0, "drmbb", NULL);
CACHELINESIZE, IPL_NONE, 0, "drmobj", NULL);
CACHELINESIZE, IPL_TTY, 0, "ictx", NULL);
CACHELINESIZE, IPL_TTY, 0, "drmsc", NULL);
CACHELINESIZE, IPL_TTY, 0, "i915_request", NULL);
CACHELINESIZE, IPL_TTY, 0, "i915_exec", NULL);
CACHELINESIZE, IPL_TTY, 0, "gsdep", NULL);
CACHELINESIZE, IPL_TTY, 0, "gspri", NULL);
CACHELINESIZE, IPL_NONE, 0, "drmvma", NULL);
#ifndef CACHELINESIZE
#define ARCH_KMALLOC_MINALIGN CACHELINESIZE
CACHELINESIZE, IPL_TTY, 0, "drm_sched_fence", NULL);
} __aligned(CACHELINESIZE);
} __aligned(CACHELINESIZE);
sz = roundup(sz, CACHELINESIZE);
sz = roundup(sz, CACHELINESIZE);
sz = roundup(sz, CACHELINESIZE);
CACHELINESIZE, IPL_NONE, PR_WAITOK | PR_RWLOCK,
} __aligned(CACHELINESIZE);
} __aligned(CACHELINESIZE);
} __aligned(CACHELINESIZE);
static struct sec_bucket sec_map[256] __aligned(CACHELINESIZE);
static struct tdb *sec_tdbh[256] __aligned(CACHELINESIZE);
pool_init(&pf_state_pl, sizeof(struct pf_state), CACHELINESIZE,
pool_init(&pf_state_key_pl, sizeof(struct pf_state_key), CACHELINESIZE,
#ifndef CACHELINESIZE
} __aligned(CACHELINESIZE) _name##_boot_cpumem = { \