Symbol: C20_MPLLB_TX_CLK_DIV_MASK
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2407
tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]);
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
384
#define MPLL_TX_CLK_DIV(val) REG_FIELD_PREP16(C20_MPLLB_TX_CLK_DIV_MASK, val)