bits_per_pixel
efifb_console.depth = cb_fb->bits_per_pixel;
uint8_t bits_per_pixel;
stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16;
params[i].timing->dsc_cfg.bits_per_pixel,
return dsc_config.bits_per_pixel;
stream->timing.dsc_cfg.bits_per_pixel = 128;
uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */
struct fixed31_32 bits_per_pixel;
bits_per_pixel = dc_fixpt_from_fraction(crtc_info->dsc_bits_per_pixel, 16);
bits_per_pixel = dc_fixpt_from_int(6);
bits_per_pixel = dc_fixpt_from_int(8);
bits_per_pixel = dc_fixpt_from_int(10);
bits_per_pixel = dc_fixpt_from_int(12);
bits_per_pixel = dc_fixpt_from_int(8);
bits_per_pixel = dc_fixpt_mul_int(bits_per_pixel, 3);
bits_per_pixel = dc_fixpt_div_int(bits_per_pixel, 3);
bits_per_pixel = dc_fixpt_mul_int(bits_per_pixel, 2);
bits_per_pixel = dc_fixpt_div_int(bits_per_pixel, 2);
peak_stream_bw_kbps = dc_fixpt_mul(peak_stream_bw_kbps, bits_per_pixel);
pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
timing->dsc.dsc_compressed_bpp_x16 = stream->timing.dsc_cfg.bits_per_pixel;
out->OutputBpp[location] = in->timing.dsc_cfg.bits_per_pixel / 16.0;
timing->dsc_cfg.bits_per_pixel,
dsc_cfg->bits_per_pixel = target_bpp;
config->dc_dsc_cfg.bits_per_pixel,
config->dc_dsc_cfg.bits_per_pixel / 16,
((config->dc_dsc_cfg.bits_per_pixel % 16) * 10000) / 16);
int bits_per_pixel = pps->bits_per_pixel;
DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16);
ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375
!(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff)) {
dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1;
dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32;
dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1;
u16 drm_bpp = pps->bits_per_pixel;
to->bits_per_pixel = from->bits_per_pixel;
bpp = crtc_timing->dsc_cfg.bits_per_pixel;
stream->timing.dsc_cfg.bits_per_pixel;
((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
if (WARN_ON_ONCE(!vdsc_cfg->bits_per_pixel ||
vdsc_cfg->bits_per_pixel,
(dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK);
vdsc_cfg->bits_per_pixel,
vdsc_cfg->bits_per_pixel,
vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
vdsc_cfg->bits_per_pixel, 16) +
hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
WARN_ON_ONCE(vdsc_cfg->bits_per_pixel & 0xf);
return vdsc_cfg->bits_per_pixel >> 4;
cfg->bits_per_component, FXP_Q4_ARGS(cfg->bits_per_pixel), cfg->line_buf_depth);
if (vdsc_cfg->bits_per_pixel == 6 << 4) {
return var_1->bits_per_pixel == var_2->bits_per_pixel &&
var->bits_per_pixel = drm_format_info_bpp(fb->format, 0);
if (var->bits_per_pixel > bpp ||
var->xres, var->yres, var->bits_per_pixel,
x1 = bit_off / info->var.bits_per_pixel;
x2 = DIV_ROUND_UP(bit_end, info->var.bits_per_pixel);
bits_per_pixel, timeslots,
bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(display, bits_per_pixel, pipe_bpp);
return bits_per_pixel;
int bits_per_pixel;
bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
if (!bits_per_pixel)
pps_param[4] = bits_per_pixel & 0xFF;
pps_param[5] = (bits_per_pixel >> 8) & 0x3;
u32 bits_per_pixel = bpp;
if (bits_per_pixel < valid_dsc_bpp[0]) {
bits_per_pixel, valid_dsc_bpp[0]);
bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
if (bits_per_pixel < 8) {
bits_per_pixel);
bits_per_pixel = min_t(u32, bits_per_pixel, 27);
if (bits_per_pixel < valid_dsc_bpp[i + 1])
bits_per_pixel, valid_dsc_bpp[i]);
bits_per_pixel = valid_dsc_bpp[i];
return bits_per_pixel;
u32 bits_per_pixel, joiner_max_bpp;
bits_per_pixel = ((link_clock * lane_count) * timeslots) /
bits_per_pixel *= 2;
bits_per_pixel = min_t(u32, bits_per_pixel, 31);
int fractional_bits = fxp_q4_to_frac(vdsc_cfg->bits_per_pixel);
vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp_x16;
vdsc_cfg->bits_per_pixel <<= 1;
pps_val = DSC_PPS1_BPP(vdsc_cfg->bits_per_pixel);
int bpp = fxp_q4_to_int(vdsc_cfg->bits_per_pixel);
vdsc_cfg->bits_per_pixel = REG_FIELD_GET(DSC_PPS1_BPP_MASK, pps_temp);
vdsc_cfg->bits_per_pixel >>= 1;
crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;
u16 bits_per_pixel;