Symbol: array_size
lib/libcbor/src/cbor/serialization.c
112
size_t array_size = cbor_array_is_definite(item)
lib/libcbor/src/cbor/serialization.c
117
array_size = _cbor_safe_signaling_add(array_size,
lib/libcbor/src/cbor/serialization.c
120
return array_size;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1613
const u32 array_size);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1515
const u32 array_size)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1520
if (array_size % 3)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1523
for (i = 0; i < array_size; i += 3) {
sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c
326
const u32 array_size)
sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c
332
for (i = 0; i < array_size; ++i) {
sys/dev/pci/drm/amd/amdgpu/imu_v11_0_3.c
109
const u32 array_size)
sys/dev/pci/drm/amd/amdgpu/imu_v11_0_3.c
115
for (i = 0; i < array_size; ++i) {
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
259
const u32 array_size)
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
265
for (i = 0; i < array_size; ++i) {
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
344
const u32 array_size)
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
349
if (array_size % 3)
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
352
for (i = 0; i < array_size; i += 3) {
sys/dev/pci/drm/amd/amdgpu/soc15.c
473
const u32 array_size)
sys/dev/pci/drm/amd/amdgpu/soc15.c
479
for (i = 0; i < array_size; ++i) {
sys/dev/pci/drm/amd/amdgpu/soc15.h
115
const u32 array_size);
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
3295
size_t array_size = num_queues * sizeof(uint32_t);
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
3300
return memdup_user(usr_queue_id_array, array_size);
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
221
uint32_t *array_size)
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
232
*array_size = 12;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
435
static unsigned int count_elements_in_span(int *array, unsigned int array_size, unsigned int span)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
442
if (array_size == 0)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
446
return array_size > 0 ? 1 : 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
452
while (span_start_index < array_size) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
453
for (i = span_start_index; i < array_size; i++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
464
if (span_start_index < array_size) {
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
494
uint32_t *array_size);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
103
const u32 array_size)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
108
for (i = 0; i < array_size; i++) {
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
84
const u32 array_size)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
88
for (i = 0; i < array_size; i++) {
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h
59
const u32 array_size);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h
62
const u32 array_size);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c
52
uint32_t array_size, i;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c
55
array_size = sizeof(uint32_t) * power_saving_clock_count;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c
56
table = kzalloc(array_size, GFP_KERNEL);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c
74
uint32_t array_size, i;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c
77
array_size = sizeof(uint32_t) * od_setting_count;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c
78
table = kzalloc(array_size, GFP_KERNEL);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c
117
uint32_t array_size, i;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c
121
array_size = sizeof(uint8_t) * od_feature_count;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c
122
table = kzalloc(array_size, GFP_KERNEL);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
480
uint32_t array_size = sizeof(struct SMU7_Discrete_GraphicsLevel) *
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
506
(u8 *)levels, array_size,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
1012
uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) *
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
1087
(uint32_t)array_size, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
1228
uint32_t array_size = sizeof(SMU73_Discrete_MemoryLevel) *
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
1266
(uint32_t)array_size, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
1048
uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
1147
(uint32_t)array_size, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
1217
uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
1247
(uint32_t)array_size, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1043
uint32_t array_size = sizeof(SMU75_Discrete_MemoryLevel) *
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1080
(uint32_t)array_size, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
876
uint32_t array_size = sizeof(struct SMU75_Discrete_GraphicsLevel) *
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
958
(uint32_t)array_size, SMC_RAM_END);
sys/dev/pci/drm/drm_plane.c
1812
array_size(sizeof(hints[0]), num_hints),
sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c
538
array_size(data->k, sizeof(*data->streams)));
sys/dev/pci/drm/i915/gvt/gtt.c
1853
vzalloc(array_size(nr_entries,
sys/dev/pci/drm/radeon/radeon.h
2865
const u32 array_size);
sys/dev/pci/drm/radeon/radeon_device.c
204
const u32 array_size)
sys/dev/pci/drm/radeon/radeon_device.c
209
if (array_size % 3)
sys/dev/pci/drm/radeon/radeon_device.c
212
for (i = 0; i < array_size; i +=3) {
sys/dev/pv/viogpu.h
270
__le32 array_size;