sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

126

struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

128

struct drm_crtc *crtc = &amdgpu_crtc->base;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

140

if (amdgpu_crtc->enabled &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1445

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1451

amdgpu_crtc->h_border = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1452

amdgpu_crtc->v_border = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1462

amdgpu_crtc->rmx_type = RMX_OFF;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1465

amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1467

amdgpu_crtc->rmx_type = RMX_OFF;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1469

memcpy(&amdgpu_crtc->native_mode,

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1473

dst_v = amdgpu_crtc->native_mode.vdisplay;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1475

dst_h = amdgpu_crtc->native_mode.hdisplay;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1484

amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1486

amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1488

amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1490

amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1491

amdgpu_crtc->rmx_type = RMX_FULL;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1493

dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1495

dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1498

if (amdgpu_crtc->rmx_type != RMX_OFF) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1503

amdgpu_crtc->vsc.full = dfixed_div(a, b);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1506

amdgpu_crtc->hsc.full = dfixed_div(a, b);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1508

amdgpu_crtc->vsc.full = dfixed_const(1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1509

amdgpu_crtc->hsc.full = dfixed_const(1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

159

amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

165

amdgpu_crtc->crtc_id, amdgpu_crtc, work);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1720

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1724

if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1725

struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1759

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1761

if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1762

struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1770

amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

199

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

216

work->crtc_id = amdgpu_crtc->crtc_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

270

if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

277

amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

278

amdgpu_crtc->pflip_works = work;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

282

amdgpu_crtc->crtc_id, amdgpu_crtc, work);

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

645

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

647

ui32 = amdgpu_crtc->crtc_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

314

struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

56

#define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

273

struct amdgpu_crtc *test_amdgpu_crtc;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

300

struct amdgpu_crtc *test_amdgpu_crtc;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

326

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

329

struct amdgpu_crtc *test_amdgpu_crtc;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

332

adjusted_clock = amdgpu_crtc->adjusted_clock;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

344

if (test_amdgpu_crtc->connector == amdgpu_crtc->connector) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

353

(amdgpu_crtc->ss_enabled == test_amdgpu_crtc->ss_enabled) &&

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

114

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

123

args.ucCRTC = amdgpu_crtc->crtc_id;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

131

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

139

args.ucCRTC = amdgpu_crtc->crtc_id;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

147

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

155

args.ucCRTC = amdgpu_crtc->crtc_id;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

163

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

171

args.ucDispPipeId = amdgpu_crtc->crtc_id;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

192

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

200

args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (amdgpu_crtc->h_border * 2));

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

202

cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (amdgpu_crtc->h_border * 2));

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

203

args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (amdgpu_crtc->v_border * 2));

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

205

cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (amdgpu_crtc->v_border * 2));

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

207

cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + amdgpu_crtc->h_border);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

211

cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + amdgpu_crtc->v_border);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

214

args.ucH_Border = amdgpu_crtc->h_border;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

215

args.ucV_Border = amdgpu_crtc->v_border;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

229

args.ucCRTC = amdgpu_crtc->crtc_id;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

307

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

310

struct drm_encoder *encoder = amdgpu_crtc->encoder;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

317

int bpc = amdgpu_crtc->bpc;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

323

amdgpu_crtc->pll_flags = AMDGPU_PLL_USE_FRAC_FB_DIV;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

338

if (amdgpu_crtc->ss_enabled) {

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

339

if (amdgpu_crtc->ss.refdiv) {

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

340

amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_REF_DIV;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

341

amdgpu_crtc->pll_reference_div = amdgpu_crtc->ss.refdiv;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

342

amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

351

amdgpu_crtc->pll_flags |= AMDGPU_PLL_PREFER_CLOSEST_LOWER;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

353

amdgpu_crtc->pll_flags |= AMDGPU_PLL_IS_LCD;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

393

if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage)

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

406

if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage)

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

434

amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

435

amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_REF_DIV;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

436

amdgpu_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

439

amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

44

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

440

amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_POST_DIV;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

441

amdgpu_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

51

args.ucCRTC = amdgpu_crtc->crtc_id;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

53

switch (amdgpu_crtc->rmx_type) {

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

74

args.usOverscanRight = cpu_to_le16(amdgpu_crtc->h_border);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

749

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

75

args.usOverscanLeft = cpu_to_le16(amdgpu_crtc->h_border);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

753

to_amdgpu_encoder(amdgpu_crtc->encoder);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

754

int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

756

amdgpu_crtc->bpc = 8;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

757

amdgpu_crtc->ss_enabled = false;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

76

args.usOverscanBottom = cpu_to_le16(amdgpu_crtc->v_border);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

760

(amdgpu_encoder_get_dp_bridge_encoder_id(amdgpu_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

763

amdgpu_get_connector_for_encoder(amdgpu_crtc->encoder);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

77

args.usOverscanTop = cpu_to_le16(amdgpu_crtc->v_border);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

772

amdgpu_crtc->bpc = amdgpu_connector_get_monitor_bpc(connector);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

779

amdgpu_crtc->ss_enabled =

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

780

amdgpu_atombios_get_asic_ss_info(adev, &amdgpu_crtc->ss,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

785

amdgpu_crtc->ss_enabled =

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

787

&amdgpu_crtc->ss,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

792

amdgpu_crtc->ss_enabled =

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

794

&amdgpu_crtc->ss,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

799

amdgpu_crtc->ss_enabled =

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

801

&amdgpu_crtc->ss,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

811

amdgpu_crtc->adjusted_clock = amdgpu_atombios_crtc_adjust_pll(crtc, mode);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

818

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

822

to_amdgpu_encoder(amdgpu_crtc->encoder);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

827

int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

831

(amdgpu_crtc->bpc > 8))

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

832

clock = amdgpu_crtc->adjusted_clock;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

834

switch (amdgpu_crtc->pll_id) {

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

849

pll->flags = amdgpu_crtc->pll_flags;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

850

pll->reference_div = amdgpu_crtc->pll_reference_div;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

851

pll->post_div = amdgpu_crtc->pll_post_div;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

853

amdgpu_pll_compute(adev, pll, amdgpu_crtc->adjusted_clock, &pll_clock,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

856

amdgpu_atombios_crtc_program_ss(adev, ATOM_DISABLE, amdgpu_crtc->pll_id,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

857

amdgpu_crtc->crtc_id, &amdgpu_crtc->ss);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

859

amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

862

amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

864

if (amdgpu_crtc->ss_enabled) {

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

868

(u32)amdgpu_crtc->ss.percentage) /

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

869

(100 * (u32)amdgpu_crtc->ss.percentage_divider);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

87

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

870

amdgpu_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

871

amdgpu_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

873

if (amdgpu_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

874

step_size = (4 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) /

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

877

step_size = (2 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) /

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

879

amdgpu_crtc->ss.step = step_size;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

881

amdgpu_atombios_crtc_program_ss(adev, ATOM_ENABLE, amdgpu_crtc->pll_id,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

882

amdgpu_crtc->crtc_id, &amdgpu_crtc->ss);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

93

args.ucScaler = amdgpu_crtc->crtc_id;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

95

switch (amdgpu_crtc->rmx_type) {

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1438

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1454

args.v1.ucCRTC = amdgpu_crtc->crtc_id;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1493

args.v2.ucCRTC = amdgpu_crtc->crtc_id;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1561

args.v3.ucCRTC = amdgpu_crtc->crtc_id;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

347

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

348

bpc = amdgpu_crtc->bpc;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

790

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

791

pll_id = amdgpu_crtc->pll_id;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1027

struct amdgpu_crtc *amdgpu_crtc,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1030

struct drm_display_mode *mode = &amdgpu_crtc->base.mode;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1037

if (amdgpu_crtc->base.enabled && num_heads && mode) {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1062

wm_high.vsc = amdgpu_crtc->vsc;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1064

if (amdgpu_crtc->rmx_type != RMX_OFF)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1101

wm_low.vsc = amdgpu_crtc->vsc;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1103

if (amdgpu_crtc->rmx_type != RMX_OFF)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1125

wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1127

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1128

tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1131

WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1134

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1135

tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1138

WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1140

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1143

amdgpu_crtc->line_time = line_time;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1146

amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1537

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1552

amdgpu_crtc->crtc_id);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1584

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1585

bpc = amdgpu_crtc->bpc;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1815

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1820

vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1822

WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1824

WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1829

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1834

WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1836

WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1843

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2013

tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2016

WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2018

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2020

WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2022

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2024

WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2026

WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2027

WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2034

tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2039

WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2044

WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2045

WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2046

WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2047

WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2048

WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2049

WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2052

WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2056

WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2061

WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2065

WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2069

WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2091

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2094

tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2099

WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2104

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2111

DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2113

tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2116

WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2118

tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2120

WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2122

tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2124

WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2126

tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2129

WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2131

WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2133

WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2134

WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2135

WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2137

WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2138

WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2139

WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2141

WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2142

WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2144

WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2149

WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2155

tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2159

WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2161

tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2164

WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2166

tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2169

WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2171

tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2174

WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2177

WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2181

tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2183

WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2239

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2245

if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2277

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2280

cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2285

WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2290

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2294

tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2296

WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2301

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2305

WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2306

upper_32_bits(amdgpu_crtc->cursor_addr));

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2307

WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2308

lower_32_bits(amdgpu_crtc->cursor_addr));

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2310

tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2313

WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2319

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2323

amdgpu_crtc->cursor_x = x;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2324

amdgpu_crtc->cursor_y = y;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2332

xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2336

yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2340

WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2341

WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2342

WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2343

((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2368

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

237

struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

238

struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2380

if ((width > amdgpu_crtc->max_cursor_width) ||

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2381

(height > amdgpu_crtc->max_cursor_height)) {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2388

DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2407

amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2411

if (width != amdgpu_crtc->cursor_width ||

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2412

height != amdgpu_crtc->cursor_height ||

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2413

hot_x != amdgpu_crtc->cursor_hot_x ||

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2414

hot_y != amdgpu_crtc->cursor_hot_y) {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2417

x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2418

y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

242

tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2422

amdgpu_crtc->cursor_width = width;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2423

amdgpu_crtc->cursor_height = height;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2424

amdgpu_crtc->cursor_hot_x = hot_x;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2425

amdgpu_crtc->cursor_hot_y = hot_y;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2432

if (amdgpu_crtc->cursor_bo) {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2433

struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2439

drm_gem_object_put(amdgpu_crtc->cursor_bo);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2442

amdgpu_crtc->cursor_bo = obj;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2448

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

245

WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2450

if (amdgpu_crtc->cursor_bo) {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2453

dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2454

amdgpu_crtc->cursor_y);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

247

WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2473

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2476

kfree(amdgpu_crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2496

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

250

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2501

amdgpu_crtc->enabled = true;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2508

amdgpu_crtc->crtc_id);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2518

if (amdgpu_crtc->enabled) {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2524

amdgpu_crtc->enabled = false;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

253

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2547

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

256

RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2575

i != amdgpu_crtc->crtc_id &&

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2576

amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2584

switch (amdgpu_crtc->pll_id) {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2589

amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2596

amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2597

amdgpu_crtc->adjusted_clock = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2598

amdgpu_crtc->encoder = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2599

amdgpu_crtc->connector = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2607

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2609

if (!amdgpu_crtc->adjusted_clock)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2619

amdgpu_crtc->hw_mode = *adjusted_mode;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2628

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2635

amdgpu_crtc->encoder = encoder;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2636

amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2640

if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2641

amdgpu_crtc->encoder = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2642

amdgpu_crtc->connector = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2650

amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2652

if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2653

!ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2687

struct amdgpu_crtc *amdgpu_crtc;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2695

amdgpu_crtc = to_amdgpu_crtc(plane->crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2699

fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2701

WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2712

struct amdgpu_crtc *amdgpu_crtc;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2714

amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2716

if (amdgpu_crtc == NULL)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2719

drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2721

drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2722

amdgpu_crtc->crtc_id = index;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2723

adev->mode_info.crtcs[index] = amdgpu_crtc;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2725

amdgpu_crtc->max_cursor_width = 128;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2726

amdgpu_crtc->max_cursor_height = 128;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2727

adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2728

adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2730

switch (amdgpu_crtc->crtc_id) {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2733

amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2736

amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2739

amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2742

amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2745

amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2748

amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2752

amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2753

amdgpu_crtc->adjusted_clock = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2754

amdgpu_crtc->encoder = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2755

amdgpu_crtc->connector = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2756

drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2757

drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v10_0_drm_primary_plane_helper_funcs);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3171

struct amdgpu_crtc *amdgpu_crtc;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3175

amdgpu_crtc = adev->mode_info.crtcs[crtc_id];

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3188

if (amdgpu_crtc == NULL)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3192

works = amdgpu_crtc->pflip_works;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3193

if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3196

amdgpu_crtc->pflip_status,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3203

amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3204

amdgpu_crtc->pflip_works = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3208

drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3212

drm_crtc_vblank_put(&amdgpu_crtc->base);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

509

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

577

WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

595

struct amdgpu_crtc *amdgpu_crtc,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

599

u32 pipe_offset = amdgpu_crtc->crtc_id;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

608

if (amdgpu_crtc->base.enabled && mode) {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

628

tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

630

WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

643

if (amdgpu_crtc->base.enabled && mode) {

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1001

c.full = dfixed_mul(c, amdgpu_crtc->hsc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1012

arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1016

WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1017

WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1021

tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1024

WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1025

WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1029

WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1032

WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1033

WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1036

amdgpu_crtc->line_time = line_time;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1039

amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1058

struct amdgpu_crtc *amdgpu_crtc,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1063

u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1077

if (amdgpu_crtc->base.enabled && mode) {

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1090

WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1102

if (amdgpu_crtc->base.enabled && mode) {

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1562

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1574

DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1752

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1753

bpc = amdgpu_crtc->bpc;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1859

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1864

vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1865

WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1870

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1874

WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1881

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2034

WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2036

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2038

WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

204

struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2040

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2042

WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2044

WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2045

WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

205

struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2052

WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2059

WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2060

WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2061

WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2062

WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2063

WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2064

WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2067

WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2071

WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2075

WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

208

WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2080

WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2084

WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2107

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

211

WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2110

WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2113

WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2118

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2124

DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2126

WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2129

WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2131

WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2133

WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2137

WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2139

WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

214

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2140

WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2141

WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2143

WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2144

WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2145

WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2147

WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2148

WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2150

WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2155

WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2161

WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2166

WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2169

WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

217

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2172

WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2176

WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

220

RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2218

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2224

if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2250

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2253

cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2258

WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2263

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2266

WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2273

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2276

WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2277

upper_32_bits(amdgpu_crtc->cursor_addr));

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2278

WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2279

lower_32_bits(amdgpu_crtc->cursor_addr));

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2281

WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2290

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2294

int w = amdgpu_crtc->cursor_width;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2296

amdgpu_crtc->cursor_x = x;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2297

amdgpu_crtc->cursor_y = y;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2305

xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2309

yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2313

WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2314

WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2315

WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2316

((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1));

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2341

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2353

if ((width > amdgpu_crtc->max_cursor_width) ||

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2354

(height > amdgpu_crtc->max_cursor_height)) {

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2361

DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2380

amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2384

if (width != amdgpu_crtc->cursor_width ||

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2385

height != amdgpu_crtc->cursor_height ||

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2386

hot_x != amdgpu_crtc->cursor_hot_x ||

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2387

hot_y != amdgpu_crtc->cursor_hot_y) {

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2390

x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2391

y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2395

amdgpu_crtc->cursor_width = width;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2396

amdgpu_crtc->cursor_height = height;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2397

amdgpu_crtc->cursor_hot_x = hot_x;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2398

amdgpu_crtc->cursor_hot_y = hot_y;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2405

if (amdgpu_crtc->cursor_bo) {

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2406

struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2412

drm_gem_object_put(amdgpu_crtc->cursor_bo);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2415

amdgpu_crtc->cursor_bo = obj;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2421

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2423

if (amdgpu_crtc->cursor_bo) {

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2426

dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2427

amdgpu_crtc->cursor_y);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2445

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2448

kfree(amdgpu_crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2468

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2473

amdgpu_crtc->enabled = true;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2478

amdgpu_crtc->crtc_id);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2488

if (amdgpu_crtc->enabled)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2491

amdgpu_crtc->enabled = false;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2515

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2543

i != amdgpu_crtc->crtc_id &&

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2544

amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2552

switch (amdgpu_crtc->pll_id) {

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2556

amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2563

amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2564

amdgpu_crtc->adjusted_clock = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2565

amdgpu_crtc->encoder = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2566

amdgpu_crtc->connector = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2574

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2576

if (!amdgpu_crtc->adjusted_clock)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2586

amdgpu_crtc->hw_mode = *adjusted_mode;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2595

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2602

amdgpu_crtc->encoder = encoder;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2603

amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2607

if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2608

amdgpu_crtc->encoder = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2609

amdgpu_crtc->connector = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2617

amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2619

if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2620

!ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2654

struct amdgpu_crtc *amdgpu_crtc;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2662

amdgpu_crtc = to_amdgpu_crtc(plane->crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2666

fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2668

WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2679

struct amdgpu_crtc *amdgpu_crtc;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2681

amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2683

if (amdgpu_crtc == NULL)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2686

drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v6_0_crtc_funcs);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2688

drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2689

amdgpu_crtc->crtc_id = index;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2690

adev->mode_info.crtcs[index] = amdgpu_crtc;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2692

amdgpu_crtc->max_cursor_width = CURSOR_WIDTH;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2693

amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2694

adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2695

adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2697

amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2699

amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2700

amdgpu_crtc->adjusted_clock = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2701

amdgpu_crtc->encoder = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2702

amdgpu_crtc->connector = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2703

drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2704

drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v6_0_drm_primary_plane_helper_funcs);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3146

struct amdgpu_crtc *amdgpu_crtc;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3150

amdgpu_crtc = adev->mode_info.crtcs[crtc_id];

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3163

if (amdgpu_crtc == NULL)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3167

works = amdgpu_crtc->pflip_works;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3168

if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3171

amdgpu_crtc->pflip_status,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3178

amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3179

amdgpu_crtc->pflip_works = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3183

drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3187

drm_crtc_vblank_put(&amdgpu_crtc->base);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

462

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

509

WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

880

struct amdgpu_crtc *amdgpu_crtc,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

883

struct drm_display_mode *mode = &amdgpu_crtc->base.mode;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

895

if (amdgpu_crtc->base.enabled && num_heads && mode) {

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

924

wm_high.vsc = amdgpu_crtc->vsc;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

926

if (amdgpu_crtc->rmx_type != RMX_OFF)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

951

wm_low.vsc = amdgpu_crtc->vsc;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

953

if (amdgpu_crtc->rmx_type != RMX_OFF)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

989

c.full = dfixed_mul(c, amdgpu_crtc->hsc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1015

wm_high.vsc = amdgpu_crtc->vsc;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1017

if (amdgpu_crtc->rmx_type != RMX_OFF)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1054

wm_low.vsc = amdgpu_crtc->vsc;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1056

if (amdgpu_crtc->rmx_type != RMX_OFF)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1078

wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1082

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1083

WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1087

tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1090

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1091

WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1095

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1098

amdgpu_crtc->line_time = line_time;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1101

amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1506

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1518

WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1551

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1552

bpc = amdgpu_crtc->bpc;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1762

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1767

vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1769

WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1771

WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1776

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1781

WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1783

WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1790

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

188

struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

189

struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

192

WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1946

WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1948

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

195

WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1950

WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1952

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1954

WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1956

WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1957

WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1964

WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1971

WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1972

WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1973

WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1974

WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1975

WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1976

WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1979

WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

198

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1983

WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1988

WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1992

WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1996

WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

201

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2018

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2021

WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2024

WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2029

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2035

DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2037

WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

204

RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2040

WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2042

WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2044

WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2048

WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2050

WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2051

WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2052

WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2054

WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2055

WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2056

WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2058

WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2059

WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2061

WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2066

WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2072

WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2076

WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2079

WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2082

WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2086

WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2090

WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2147

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2153

if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2198

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2201

cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2206

WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2211

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2214

WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2221

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2224

WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2225

upper_32_bits(amdgpu_crtc->cursor_addr));

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2226

WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2227

lower_32_bits(amdgpu_crtc->cursor_addr));

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2229

WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2238

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2242

amdgpu_crtc->cursor_x = x;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2243

amdgpu_crtc->cursor_y = y;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2251

xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2255

yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2259

WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2260

WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2261

WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2262

((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2287

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2299

if ((width > amdgpu_crtc->max_cursor_width) ||

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2300

(height > amdgpu_crtc->max_cursor_height)) {

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2307

DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2326

amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2330

if (width != amdgpu_crtc->cursor_width ||

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2331

height != amdgpu_crtc->cursor_height ||

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2332

hot_x != amdgpu_crtc->cursor_hot_x ||

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2333

hot_y != amdgpu_crtc->cursor_hot_y) {

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2336

x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2337

y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2341

amdgpu_crtc->cursor_width = width;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2342

amdgpu_crtc->cursor_height = height;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2343

amdgpu_crtc->cursor_hot_x = hot_x;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2344

amdgpu_crtc->cursor_hot_y = hot_y;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2351

if (amdgpu_crtc->cursor_bo) {

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2352

struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2358

drm_gem_object_put(amdgpu_crtc->cursor_bo);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2361

amdgpu_crtc->cursor_bo = obj;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2367

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2369

if (amdgpu_crtc->cursor_bo) {

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2372

dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2373

amdgpu_crtc->cursor_y);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2392

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2395

kfree(amdgpu_crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2415

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2420

amdgpu_crtc->enabled = true;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2427

amdgpu_crtc->crtc_id);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2437

if (amdgpu_crtc->enabled) {

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2443

amdgpu_crtc->enabled = false;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2466

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2494

i != amdgpu_crtc->crtc_id &&

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2495

amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2503

switch (amdgpu_crtc->pll_id) {

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2507

amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2515

amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2522

amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2523

amdgpu_crtc->adjusted_clock = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2524

amdgpu_crtc->encoder = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2525

amdgpu_crtc->connector = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2533

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2535

if (!amdgpu_crtc->adjusted_clock)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2545

amdgpu_crtc->hw_mode = *adjusted_mode;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2554

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2561

amdgpu_crtc->encoder = encoder;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2562

amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2566

if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2567

amdgpu_crtc->encoder = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2568

amdgpu_crtc->connector = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2576

amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2578

if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2579

!ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2613

struct amdgpu_crtc *amdgpu_crtc;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2621

amdgpu_crtc = to_amdgpu_crtc(plane->crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2625

fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2627

WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2637

struct amdgpu_crtc *amdgpu_crtc;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2639

amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2641

if (amdgpu_crtc == NULL)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2644

drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2646

drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2647

amdgpu_crtc->crtc_id = index;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2648

adev->mode_info.crtcs[index] = amdgpu_crtc;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2650

amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2651

amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2652

adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2653

adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2655

amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2657

amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2658

amdgpu_crtc->adjusted_clock = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2659

amdgpu_crtc->encoder = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2660

amdgpu_crtc->connector = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2661

drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2662

drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v8_0_drm_primary_plane_helper_funcs);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3162

struct amdgpu_crtc *amdgpu_crtc;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3166

amdgpu_crtc = adev->mode_info.crtcs[crtc_id];

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3179

if (amdgpu_crtc == NULL)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3183

works = amdgpu_crtc->pflip_works;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3184

if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3187

amdgpu_crtc->pflip_status,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3194

amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3195

amdgpu_crtc->pflip_works = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3199

drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3203

drm_crtc_vblank_put(&amdgpu_crtc->base);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

467

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

532

WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

550

struct amdgpu_crtc *amdgpu_crtc,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

554

u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

563

if (amdgpu_crtc->base.enabled && mode) {

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

583

WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

596

if (amdgpu_crtc->base.enabled && mode) {

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

980

struct amdgpu_crtc *amdgpu_crtc,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

983

struct drm_display_mode *mode = &amdgpu_crtc->base.mode;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

990

if (amdgpu_crtc->base.enabled && num_heads && mode) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10207

struct amdgpu_crtc *acrtc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10233

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10249

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10355

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10398

struct amdgpu_crtc *acrtc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10504

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10681

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10789

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10870

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10953

struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11018

struct amdgpu_crtc *disconnected_acrtc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11213

struct amdgpu_crtc *acrtc = NULL;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11631

static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11704

struct amdgpu_crtc *new_acrtc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12589

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

267

struct amdgpu_crtc *acrtc = NULL;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

287

struct amdgpu_crtc *acrtc = NULL;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3034

struct amdgpu_crtc *acrtc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

343

static struct amdgpu_crtc *

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

349

struct amdgpu_crtc *amdgpu_crtc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

355

amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

357

if (amdgpu_crtc->otg_inst == otg_inst)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

358

return amdgpu_crtc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

439

struct amdgpu_crtc *amdgpu_crtc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

448

amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

452

if (amdgpu_crtc == NULL) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

459

if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

462

amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

463

amdgpu_crtc->crtc_id, amdgpu_crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

469

e = amdgpu_crtc->event;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

470

amdgpu_crtc->event = NULL;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

474

vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

478

!dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

485

drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

491

drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

494

drm_crtc_vblank_put(&amdgpu_crtc->base);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

511

e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

512

e->pipe = amdgpu_crtc->crtc_id;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

523

amdgpu_crtc->dm_irq_params.last_flip_vblank =

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

524

amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

526

amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

531

amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int)!e);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

582

struct amdgpu_crtc *acrtc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

654

struct amdgpu_crtc *acrtc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

774

struct amdgpu_crtc *acrtc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9088

struct amdgpu_crtc *acrtc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9186

struct amdgpu_crtc *acrtc)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9337

struct amdgpu_crtc *acrtc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9346

static void prepare_flip_isr(struct amdgpu_crtc *acrtc)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9375

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9468

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9579

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9589

amdgpu_crtc->crtc_id, plane->state->crtc_w,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9606

amdgpu_crtc->cursor_width = plane->state->crtc_w;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9607

amdgpu_crtc->cursor_height = plane->state->crtc_h;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9643

static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9705

struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

141

struct amdgpu_crtc *acrtc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

82

struct amdgpu_crtc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

299

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

470

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

554

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

729

struct amdgpu_crtc *acrtc = NULL;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

775

struct amdgpu_crtc *acrtc = NULL;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

292

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

41

void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

68

bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

726

struct amdgpu_crtc *acrtc = NULL;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

738

acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

80

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h

30

void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h

38

bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3578

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3595

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3615

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3632

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3651

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3668

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3687

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3704

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3721

struct amdgpu_crtc *acrtc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

712

struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc_id];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

505

struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1295

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1303

if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1304

(plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1315

if (x <= -amdgpu_crtc->max_cursor_width ||

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1316

y <= -amdgpu_crtc->max_cursor_height)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1320

xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1324

yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1346

struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1356

amdgpu_crtc->crtc_id, plane->state->crtc_w,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1374

amdgpu_crtc->cursor_width = plane->state->crtc_w;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1375

amdgpu_crtc->cursor_height = plane->state->crtc_h;

sys/dev/pci/drm/amd/pm/amdgpu_dpm_internal.c

36

struct amdgpu_crtc *amdgpu_crtc;

sys/dev/pci/drm/amd/pm/amdgpu_dpm_internal.c

46

amdgpu_crtc = to_amdgpu_crtc(crtc);

sys/dev/pci/drm/amd/pm/amdgpu_dpm_internal.c

49

if (!amdgpu_crtc->enabled)

sys/dev/pci/drm/amd/pm/amdgpu_dpm_internal.c

52

conn = to_amdgpu_connector(amdgpu_crtc->connector);

sys/dev/pci/drm/amd/pm/amdgpu_dpm_internal.c

55

if (amdgpu_crtc->hw_mode.clock) {

sys/dev/pci/drm/amd/pm/amdgpu_dpm_internal.c

56

vrefresh = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);

sys/dev/pci/drm/amd/pm/amdgpu_dpm_internal.c

59

amdgpu_crtc->hw_mode.crtc_htotal *

sys/dev/pci/drm/amd/pm/amdgpu_dpm_internal.c

60

(amdgpu_crtc->hw_mode.crtc_vblank_end -

sys/dev/pci/drm/amd/pm/amdgpu_dpm_internal.c

61

amdgpu_crtc->hw_mode.crtc_vdisplay +

sys/dev/pci/drm/amd/pm/amdgpu_dpm_internal.c

62

(amdgpu_crtc->v_border * 2));

sys/dev/pci/drm/amd/pm/amdgpu_dpm_internal.c

65

vblank_in_pixels * 1000 / amdgpu_crtc->hw_mode.clock;

sys/dev/pci/drm/amd/pm/amdgpu_dpm_internal.c

82

if (amdgpu_crtc->crtc_id < cfg->crtc_index) {

sys/dev/pci/drm/amd/pm/amdgpu_dpm_internal.c

84

cfg->crtc_index = amdgpu_crtc->crtc_id;

sys/dev/pci/drm/amd/pm/amdgpu_dpm_internal.c

85

cfg->line_time_in_us = amdgpu_crtc->line_time;

sys/dev/pci/drm/amd/pm/amdgpu_dpm_internal.c

88

display_cfg->controller_id = amdgpu_crtc->crtc_id;