sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4725

adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

485

checksum = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->checksum;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

497

((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->vf2pf_update_interval_ms;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

499

((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->feature_flags.all;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

501

((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->reg_access_flags.all;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

509

tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_dimension_pixels;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

512

tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_frame_pixels;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

515

tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_dimension_pixels;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

518

tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_frame_pixels;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

525

((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

526

adev->virt.ras_en_caps.all = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->ras_en_caps.all;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

528

((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->ras_telemetry_en_caps.all;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

701

struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

729

pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

443

sizeof(struct amd_sriov_msg_pf2vf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,