aci
int aci, qid;
for (aci = 0; aci < EDCA_NUM_AC; aci++) {
ac = &ic->ic_edca_ac[aci];
qid = athn_ac2qid[aci];
#define MTW_EDCA_AC_CFG(aci) (0x1300 + (aci) * 4)
int aci;
for (aci = 0; aci < EDCA_NUM_AC; aci++) {
RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci),
ic->ic_edca_ac[aci].ac_ecwmax << 16 |
ic->ic_edca_ac[aci].ac_ecwmin << 12 |
ic->ic_edca_ac[aci].ac_aifsn << 8 |
ic->ic_edca_ac[aci].ac_txoplimit);
#define RT2860_EDCA_AC_CFG(aci) (0x1300 + (aci) * 4)
int s, aci, aifs, slottime;
for (aci = 0; aci < EDCA_NUM_AC; aci++) {
ac = &ic->ic_edca_ac[aci];
rtwn_write_4(sc, aci2reg[aci],
switch (aci) {
int mode, aci;
for (aci = 0; aci < EDCA_NUM_AC; aci++)
memcpy(&ic->ic_edca_ac[aci], &ieee80211_edca_table[mode][aci],
int aci;
for (aci = 0; aci < EDCA_NUM_AC; aci++) {
qos->cwmin[aci] = IWI_EXP2(iwi_cck[aci].ac_ecwmin);
qos->cwmax[aci] = IWI_EXP2(iwi_cck[aci].ac_ecwmax);
qos->txop [aci] = IWI_TXOP(iwi_cck[aci].ac_txoplimit);
qos->aifsn[aci] = iwi_cck[aci].ac_aifsn;
qos->acm [aci] = 0;
for (aci = 0; aci < EDCA_NUM_AC; aci++) {
qos->cwmin[aci] = IWI_EXP2(iwi_ofdm[aci].ac_ecwmin);
qos->cwmax[aci] = IWI_EXP2(iwi_ofdm[aci].ac_ecwmax);
qos->txop [aci] = IWI_TXOP(iwi_ofdm[aci].ac_txoplimit);
qos->aifsn[aci] = iwi_ofdm[aci].ac_aifsn;
qos->acm [aci] = 0;
for (aci = 0; aci < EDCA_NUM_AC; aci++) {
qos->cwmin[aci] = IWI_EXP2(edca[aci].ac_ecwmin);
qos->cwmax[aci] = IWI_EXP2(edca[aci].ac_ecwmax);
qos->txop [aci] = IWI_TXOP(edca[aci].ac_txoplimit);
qos->aifsn[aci] = edca[aci].ac_aifsn;
qos->acm [aci] = 0;
int aci;
for (aci = 0; aci < EDCA_NUM_AC; aci++) {
&ic->ic_edca_ac[aci];
cmd.ac[aci].aifsn = ac->ac_aifsn;
cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->ac_ecwmin));
cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->ac_ecwmax));
cmd.ac[aci].txoplimit =
int aci;
for (aci = 0; aci < EDCA_NUM_AC; aci++) {
&ic->ic_edca_ac[aci];
cmd.ac[aci].aifsn = ac->ac_aifsn;
cmd.ac[aci].cwmin = htole16(WPI_EXP2(ac->ac_ecwmin));
cmd.ac[aci].cwmax = htole16(WPI_EXP2(ac->ac_ecwmax));
cmd.ac[aci].txoplimit =
if (!status || hw->aci.last_status == IXGBE_ACI_RC_EBUSY)
hw->aci.last_status == IXGBE_ACI_RC_EINVAL) {
ixgbe_init_lock(&hw->aci.lock);
ixgbe_destroy_lock(&hw->aci.lock);
hw->aci.last_status = IXGBE_ACI_RC_OK;
hw->aci.last_status = IXGBE_ACI_RC_EBUSY;
hw->aci.last_status = (enum ixgbe_aci_err)desc->retval;
ixgbe_acquire_lock(&hw->aci.lock);
last_status = hw->aci.last_status;
ixgbe_release_lock(&hw->aci.lock);
ixgbe_acquire_lock(&hw->aci.lock);
ixgbe_release_lock(&hw->aci.lock);
struct ixgbe_aci_info aci;
int s, aci;
for (aci = 0; aci < EDCA_NUM_AC; aci++) {
mtw_write(sc, MTW_EDCA_AC_CFG(aci),
ic->ic_edca_ac[aci].ac_ecwmax << 16 |
ic->ic_edca_ac[aci].ac_ecwmin << 12 |
ic->ic_edca_ac[aci].ac_aifsn << 8 |
ic->ic_edca_ac[aci].ac_txoplimit);
int s, aci;
for (aci = 0; aci < EDCA_NUM_AC; aci++) {
run_write(sc, RT2860_EDCA_AC_CFG(aci),
ic->ic_edca_ac[aci].ac_ecwmax << 16 |
ic->ic_edca_ac[aci].ac_ecwmin << 12 |
ic->ic_edca_ac[aci].ac_aifsn << 8 |
ic->ic_edca_ac[aci].ac_txoplimit);
int aci;
for (aci = 0; aci < EDCA_NUM_AC; aci++) {
struct ieee80211_edca_ac_params *ac = &ic->ic_edca_ac[aci];
int aci;
for (aci = 0; aci < EDCA_NUM_AC; aci++) {
ac = &ic->ic_edca_ac[aci];
ac_qap = &ieee80211_qap_edca_table[ic->ic_curmode][aci];
int aci;
for (aci = 0; aci < EDCA_NUM_AC; aci++) {
const struct ieee80211_edca_ac_params *ac = &edca[aci];
*frm++ = (aci << 5) | ((ac->ac_acm & 0x1) << 4) |
int aci;
for (aci = 0; aci < EDCA_NUM_AC; aci++) {
const struct ieee80211_edca_ac_params *ac = &edca[aci];
*frm++ = (aci << 5) | ((ac->ac_acm & 0x1) << 4) |
if (aci->attribute != NULL) {
if (strcasecmp(aci->attribute, attr) != 0)
struct aci *aci;
SIMPLEQ_FOREACH(aci, &conf->acl, entry) {
if (aci_matches(aci, conn, ns, dn, rights,
type = aci->type;
aci->type == ACI_ALLOW ? "allow" : "deny",
aci->rights,
aci->target ? aci->target : "any",
aci->attribute ? " attribute " : "",
aci->attribute ? aci->attribute : "",
aci->subject ? aci->subject : "any");
SIMPLEQ_FOREACH(aci, &ns->acl, entry) {
if (aci_matches(aci, conn, ns, dn, rights,
type = aci->type;
aci->type == ACI_ALLOW ? "allow" : "deny",
aci->rights,
aci->target ? aci->target : "any",
aci->attribute ? " attribute " : "",
aci->attribute ? aci->attribute : "",
aci->subject ? aci->subject : "any");
aci_matches(struct aci *aci, struct conn *conn, struct namespace *ns,
if ((rights & aci->rights) != rights)
if (aci->target != NULL) {
switch (aci->scope) {
if (strcmp(dn, aci->target) != 0)
if (!is_child_of(&key, aci->target))
if (!has_suffix(&key, aci->target))
switch (aci->scope) {
if (strcmp(dn, aci->target) != 0)
if (!has_suffix(&key, aci->target))
switch (aci->scope) {
if (!has_suffix(&key, aci->target))
if (aci->subject != NULL) {
if (strcmp(aci->subject, "@") == 0) {
} else if (strcmp(aci->subject, conn->binddn) != 0)
SIMPLEQ_ENTRY(aci) entry;
SIMPLEQ_HEAD(acl, aci);
static struct aci *mk_aci(int type, int rights, enum scope scope,
struct aci *aci;
static struct aci *
struct aci *aci;
if ((aci = calloc(1, sizeof(*aci))) == NULL) {
aci->type = type;
aci->rights = rights;
aci->scope = scope;
aci->target = target;
aci->attribute = attr;
aci->subject = subject;
aci->type == ACI_DENY ? "deny" : "allow",
aci->rights,
aci->target ? aci->target : "any",
aci->attribute ? " attribute " : "",
aci->attribute ? aci->attribute : "",
aci->scope,
aci->subject ? aci->subject : "any");
return aci;
%type <v.aci> aci
| grammar aci '\n' {
| aci {
aci : aci_type aci_access TO aci_scope aci_target aci_attr aci_subject {