__SHIFTIN
#define MVNETA_PTFUT_IPGINTTX_V1(x) __SHIFTIN(x, MVNETA_PTFUT_IPGINTTX_V1_MASK)
#define MVNETA_PTFUT_IPGINTTX_V2(x) __SHIFTIN(x, MVNETA_PTFUT_IPGINTTX_V2_MASK)
__SHIFTIN(phy, GENET_MDIO_PMD) |
__SHIFTIN(reg, GENET_MDIO_REG));
__SHIFTIN(phy, GENET_MDIO_PMD) |
__SHIFTIN(reg, GENET_MDIO_REG));
val |= __SHIFTIN(speed, GENET_UMAC_CMD_SPEED);
status = flags | __SHIFTIN(len, GENET_TX_DESC_STATUS_BUFLEN);
__SHIFTIN(TX_DESC_COUNT, GENET_TX_DMA_RING_BUF_SIZE_DESC_COUNT) |
__SHIFTIN(MCLBYTES, GENET_TX_DMA_RING_BUF_SIZE_BUF_LENGTH));
__SHIFTIN(RX_DESC_COUNT, GENET_RX_DMA_RING_BUF_SIZE_DESC_COUNT) |
__SHIFTIN(MCLBYTES, GENET_RX_DMA_RING_BUF_SIZE_BUF_LENGTH));
__SHIFTIN(5, GENET_RX_DMA_XON_XOFF_THRES_LO) |
__SHIFTIN(RX_DESC_COUNT >> 4, GENET_RX_DMA_XON_XOFF_THRES_HI));
__SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |
__SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));
state_lo &= ~__SHIFTIN(BWI_STATE_LO_FLAG_PHYRST,
__SHIFTIN(tpctl->tp_ctrl1, BWI_RFR_TXPWR1_MASK));
__SHIFTIN(bbp_atten, mask));
__SHIFTIN(bbp_atten, mask));
thr = __SHIFTIN((uint32_t)thr1, NRSSI_THR1_MASK) |
__SHIFTIN((uint32_t)thr2, NRSSI_THR2_MASK);
val = __SHIFTIN(BWI_INVALID_TSSI, BWI_LO_TSSI_MASK) |
__SHIFTIN(BWI_INVALID_TSSI, BWI_HI_TSSI_MASK);
addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) |
__SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK);
ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |
__SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK);
info = __SHIFTIN(revid, BWI_INFO_BBPREV_MASK) |
__SHIFTIN(0, BWI_INFO_BBPPKG_MASK);
__SHIFTIN(BWI_CONF_LO_SERVTO,
__SHIFTIN(BWI_CONF_LO_REQTO,
val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
__SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
__SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
__SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_MODE_11G),
__SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);
hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
__SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
__SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
__SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
__SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
__SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
__SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
_v |= __SHIFTIN((val), (mask)); \
val = __SHIFTIN(56, ET_IPG_NONB2B_1) |
__SHIFTIN(88, ET_IPG_NONB2B_2) |
__SHIFTIN(80, ET_IPG_MINIFG) |
__SHIFTIN(96, ET_IPG_B2B);
val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) |
__SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) |
__SHIFTIN(55, ET_MAC_HDX_COLLWIN) |
val = __SHIFTIN(16, ET_RXMAC_MC_SEGSZ_MAX) |
val = __SHIFTIN(ETHER_MIN_LEN, ET_PKTFILT_MINLEN) | ET_PKTFILT_FRAG;
val |= __SHIFTIN(sc->sc_rx_data[0].rbd_bufsize,
val |= __SHIFTIN(sc->sc_rx_data[1].rbd_bufsize,
rxstat_pos = __SHIFTIN(rxst_ring->rsr_index,
rxring_pos = __SHIFTIN(rx_ring->rr_index, ET_RX_RING_POS_INDEX);
__SHIFTIN(map->dm_segs[i].ds_len, ET_TDCTRL1_LEN);
tx_ready_pos = __SHIFTIN(tx_ring->tr_ready_index,
desc->rd_ctrl = __SHIFTIN(buf_idx, ET_RDCTRL_BUFIDX);
val = __SHIFTIN(phy, ET_MII_ADDR_PHY) |
__SHIFTIN(reg, ET_MII_ADDR_REG);
val = __SHIFTIN(phy, ET_MII_ADDR_PHY) |
__SHIFTIN(reg, ET_MII_ADDR_REG);
CSR_WRITE_4(sc, ET_MII_CTRL, __SHIFTIN(val0, ET_MII_CTRL_VALUE));
__SHIFTIN(7, ET_MAC_CFG2_PREAMBLE_LEN);
val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) |
__SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) |
__SHIFTIN(55, ET_MAC_HDX_COLLWIN) |