__DML_NUM_PLANES__
for (dml_uint_t k = 0; k < __DML_NUM_PLANES__; ++k)
dml_float_t DCFClkDeepSleepPerSurface[__DML_NUM_PLANES__];
dml_uint_t MaximumSwathHeightY[__DML_NUM_PLANES__];
dml_uint_t MaximumSwathHeightC[__DML_NUM_PLANES__];
dml_uint_t RoundedUpMaxSwathSizeBytesY[__DML_NUM_PLANES__];
dml_uint_t RoundedUpMaxSwathSizeBytesC[__DML_NUM_PLANES__];
dml_uint_t RoundedUpSwathSizeBytesY[__DML_NUM_PLANES__];
dml_uint_t RoundedUpSwathSizeBytesC[__DML_NUM_PLANES__];
dml_uint_t SwathWidthSingleDPP[__DML_NUM_PLANES__];
dml_uint_t SwathWidthSingleDPPChroma[__DML_NUM_PLANES__];
dml_bool_t DETPieceAssignedToThisSurfaceAlready[__DML_NUM_PLANES__];
dml_uint_t SubViewportLinesNeededInMALL[__DML_NUM_PLANES__];
dml_uint_t VInitPreFillY[__DML_NUM_PLANES__];
dml_uint_t VInitPreFillC[__DML_NUM_PLANES__];
dml_uint_t MaxNumSwathY[__DML_NUM_PLANES__];
dml_uint_t MaxNumSwathC[__DML_NUM_PLANES__];
dml_float_t BytePerPixelDETY[__DML_NUM_PLANES__];
dml_float_t BytePerPixelDETC[__DML_NUM_PLANES__];
dml_uint_t BytePerPixelY[__DML_NUM_PLANES__];
dml_uint_t BytePerPixelC[__DML_NUM_PLANES__];
dml_uint_t SwathWidthY[__DML_NUM_PLANES__];
dml_uint_t SwathWidthC[__DML_NUM_PLANES__];
dml_uint_t SwathWidthSingleDPPY[__DML_NUM_PLANES__];
dml_uint_t SwathWidthSingleDPPC[__DML_NUM_PLANES__];
dml_float_t ReadBandwidthSurfaceLuma[__DML_NUM_PLANES__];
dml_float_t ReadBandwidthSurfaceChroma[__DML_NUM_PLANES__];
dml_uint_t PixelPTEBytesPerRow[__DML_NUM_PLANES__];
dml_uint_t PDEAndMetaPTEBytesFrame[__DML_NUM_PLANES__];
dml_uint_t MetaRowByte[__DML_NUM_PLANES__];
dml_uint_t PrefetchSourceLinesY[__DML_NUM_PLANES__];
dml_float_t RequiredPrefetchPixDataBWLuma[__DML_NUM_PLANES__];
dml_float_t RequiredPrefetchPixDataBWChroma[__DML_NUM_PLANES__];
dml_uint_t PrefetchSourceLinesC[__DML_NUM_PLANES__];
dml_float_t PSCL_THROUGHPUT[__DML_NUM_PLANES__];
dml_float_t PSCL_THROUGHPUT_CHROMA[__DML_NUM_PLANES__];
dml_uint_t DSCDelay[__DML_NUM_PLANES__];
dml_float_t DPPCLKUsingSingleDPP[__DML_NUM_PLANES__];
dml_uint_t MacroTileWidthY[__DML_NUM_PLANES__];
dml_uint_t MacroTileWidthC[__DML_NUM_PLANES__];
dml_uint_t BlockHeight256BytesY[__DML_NUM_PLANES__];
dml_uint_t BlockHeight256BytesC[__DML_NUM_PLANES__];
dml_uint_t BlockWidth256BytesY[__DML_NUM_PLANES__];
dml_uint_t BlockWidth256BytesC[__DML_NUM_PLANES__];
dml_uint_t BlockHeightY[__DML_NUM_PLANES__];
dml_uint_t BlockHeightC[__DML_NUM_PLANES__];
dml_uint_t BlockWidthY[__DML_NUM_PLANES__];
dml_uint_t BlockWidthC[__DML_NUM_PLANES__];
dml_uint_t SurfaceSizeInTheMALL[__DML_NUM_PLANES__];
dml_float_t VRatioPrefetchY[__DML_NUM_PLANES__];
dml_float_t VRatioPrefetchC[__DML_NUM_PLANES__];
dml_float_t Tno_bw[__DML_NUM_PLANES__];
dml_float_t final_flip_bw[__DML_NUM_PLANES__];
dml_float_t prefetch_vmrow_bw[__DML_NUM_PLANES__];
dml_float_t cursor_bw[__DML_NUM_PLANES__];
dml_float_t cursor_bw_pre[__DML_NUM_PLANES__];
dml_float_t WritebackDelay[__DML_NUM_PLANES__];
dml_uint_t dpte_row_height[__DML_NUM_PLANES__];
dml_uint_t dpte_row_height_linear[__DML_NUM_PLANES__];
dml_uint_t meta_req_width[__DML_NUM_PLANES__];
dml_uint_t meta_req_height[__DML_NUM_PLANES__];
dml_uint_t meta_row_width[__DML_NUM_PLANES__];
dml_uint_t meta_row_height[__DML_NUM_PLANES__];
dml_uint_t dpte_row_width_luma_ub[__DML_NUM_PLANES__];
dml_uint_t dpte_row_width_chroma_ub[__DML_NUM_PLANES__];
dml_uint_t dpte_row_height_chroma[__DML_NUM_PLANES__];
dml_uint_t dpte_row_height_linear_chroma[__DML_NUM_PLANES__];
dml_uint_t meta_req_width_chroma[__DML_NUM_PLANES__];
dml_uint_t meta_req_height_chroma[__DML_NUM_PLANES__];
dml_uint_t meta_row_width_chroma[__DML_NUM_PLANES__];
dml_uint_t meta_row_height_chroma[__DML_NUM_PLANES__];
dml_uint_t vm_group_bytes[__DML_NUM_PLANES__];
dml_uint_t dpte_group_bytes[__DML_NUM_PLANES__];
dml_float_t meta_row_bw[__DML_NUM_PLANES__];
dml_float_t dpte_row_bw[__DML_NUM_PLANES__];
dml_float_t UrgBurstFactorCursor[__DML_NUM_PLANES__];
dml_float_t UrgBurstFactorCursorPre[__DML_NUM_PLANES__];
dml_float_t UrgBurstFactorLuma[__DML_NUM_PLANES__];
dml_float_t UrgBurstFactorLumaPre[__DML_NUM_PLANES__];
dml_float_t UrgBurstFactorChroma[__DML_NUM_PLANES__];
dml_float_t UrgBurstFactorChromaPre[__DML_NUM_PLANES__];
dml_uint_t swath_width_luma_ub[__DML_NUM_PLANES__];
dml_uint_t swath_width_chroma_ub[__DML_NUM_PLANES__];
dml_uint_t PixelPTEReqWidthY[__DML_NUM_PLANES__];
dml_uint_t PixelPTEReqHeightY[__DML_NUM_PLANES__];
dml_uint_t PTERequestSizeY[__DML_NUM_PLANES__];
dml_uint_t PixelPTEReqWidthC[__DML_NUM_PLANES__];
dml_uint_t PixelPTEReqHeightC[__DML_NUM_PLANES__];
dml_uint_t PTERequestSizeC[__DML_NUM_PLANES__];
dml_float_t Tdmdl_vm[__DML_NUM_PLANES__];
dml_float_t Tdmdl[__DML_NUM_PLANES__];
dml_float_t TSetup[__DML_NUM_PLANES__];
dml_uint_t dpde0_bytes_per_frame_ub_l[__DML_NUM_PLANES__];
dml_uint_t meta_pte_bytes_per_frame_ub_l[__DML_NUM_PLANES__];
dml_uint_t dpde0_bytes_per_frame_ub_c[__DML_NUM_PLANES__];
dml_uint_t meta_pte_bytes_per_frame_ub_c[__DML_NUM_PLANES__];
dml_bool_t NoUrgentLatencyHiding[__DML_NUM_PLANES__];
dml_bool_t NoUrgentLatencyHidingPre[__DML_NUM_PLANES__];
dml_bool_t NotEnoughTimeForDynamicMetadata[__DML_NUM_PLANES__];
dml_float_t ReadBandwidthLuma[__DML_NUM_PLANES__];
dml_float_t ReadBandwidthChroma[__DML_NUM_PLANES__];
dml_bool_t use_one_row_for_frame[__DML_NUM_PLANES__];
dml_bool_t use_one_row_for_frame_flip[__DML_NUM_PLANES__];
dml_uint_t pipe_plane[__DML_NUM_PLANES__]; // <brief used mainly by dv to map the pipe inst to plane index within DML core; the plane idx of a pipe
dml_bool_t NoTimeToPrefetch[__DML_NUM_PLANES__]; /// <brief Prefetch schedule calculation result
dml_uint_t PrefetchMode[__DML_NUM_PLANES__]; /// <brief prefetch mode used for prefetch support check in mode programming step
dml_bool_t ImmediateFlipSupportedForPipe[__DML_NUM_PLANES__];
dml_float_t Dppclk[__DML_NUM_PLANES__]; /// <brief dppclk being used in mode programming
dml_float_t Dppclk_calculated[__DML_NUM_PLANES__];
dml_float_t DSCCLK_calculated[__DML_NUM_PLANES__]; //< brief Required DSCCLK freq. Backend; not used in any subsequent calculations for now
dml_uint_t DCCYMaxUncompressedBlock[__DML_NUM_PLANES__];
dml_uint_t DCCYMaxCompressedBlock[__DML_NUM_PLANES__];
dml_uint_t DCCYIndependentBlock[__DML_NUM_PLANES__];
dml_uint_t DCCCMaxUncompressedBlock[__DML_NUM_PLANES__];
dml_uint_t DCCCMaxCompressedBlock[__DML_NUM_PLANES__];
dml_uint_t DCCCIndependentBlock[__DML_NUM_PLANES__];
dml_float_t MIN_DST_Y_NEXT_START[__DML_NUM_PLANES__];
dml_bool_t VREADY_AT_OR_AFTER_VSYNC[__DML_NUM_PLANES__];
dml_uint_t DSTYAfterScaler[__DML_NUM_PLANES__];
dml_uint_t DSTXAfterScaler[__DML_NUM_PLANES__];
dml_float_t DestinationLinesForPrefetch[__DML_NUM_PLANES__];
dml_float_t DestinationLinesToRequestVMInVBlank[__DML_NUM_PLANES__];
dml_float_t DestinationLinesToRequestRowInVBlank[__DML_NUM_PLANES__];
dml_float_t DestinationLinesToRequestVMInImmediateFlip[__DML_NUM_PLANES__];
dml_float_t DestinationLinesToRequestRowInImmediateFlip[__DML_NUM_PLANES__];
dml_float_t MinTTUVBlank[__DML_NUM_PLANES__];
dml_float_t DisplayPipeLineDeliveryTimeLuma[__DML_NUM_PLANES__];
dml_float_t DisplayPipeLineDeliveryTimeChroma[__DML_NUM_PLANES__];
dml_float_t DisplayPipeLineDeliveryTimeLumaPrefetch[__DML_NUM_PLANES__];
dml_float_t DisplayPipeLineDeliveryTimeChromaPrefetch[__DML_NUM_PLANES__];
dml_float_t DisplayPipeRequestDeliveryTimeLuma[__DML_NUM_PLANES__];
dml_float_t DisplayPipeRequestDeliveryTimeChroma[__DML_NUM_PLANES__];
dml_float_t DisplayPipeRequestDeliveryTimeLumaPrefetch[__DML_NUM_PLANES__];
dml_float_t DisplayPipeRequestDeliveryTimeChromaPrefetch[__DML_NUM_PLANES__];
dml_float_t CursorRequestDeliveryTime[__DML_NUM_PLANES__];
dml_float_t CursorRequestDeliveryTimePrefetch[__DML_NUM_PLANES__];
dml_float_t DST_Y_PER_PTE_ROW_NOM_L[__DML_NUM_PLANES__];
dml_float_t DST_Y_PER_PTE_ROW_NOM_C[__DML_NUM_PLANES__];
dml_float_t DST_Y_PER_META_ROW_NOM_L[__DML_NUM_PLANES__];
dml_float_t DST_Y_PER_META_ROW_NOM_C[__DML_NUM_PLANES__];
dml_float_t TimePerMetaChunkNominal[__DML_NUM_PLANES__];
dml_float_t TimePerChromaMetaChunkNominal[__DML_NUM_PLANES__];
dml_float_t TimePerMetaChunkVBlank[__DML_NUM_PLANES__];
dml_float_t TimePerChromaMetaChunkVBlank[__DML_NUM_PLANES__];
dml_float_t TimePerMetaChunkFlip[__DML_NUM_PLANES__];
dml_float_t TimePerChromaMetaChunkFlip[__DML_NUM_PLANES__];
dml_float_t time_per_pte_group_nom_luma[__DML_NUM_PLANES__];
dml_float_t time_per_pte_group_nom_chroma[__DML_NUM_PLANES__];
dml_float_t time_per_pte_group_vblank_luma[__DML_NUM_PLANES__];
dml_float_t time_per_pte_group_vblank_chroma[__DML_NUM_PLANES__];
dml_float_t time_per_pte_group_flip_luma[__DML_NUM_PLANES__];
dml_float_t time_per_pte_group_flip_chroma[__DML_NUM_PLANES__];
dml_float_t TimePerVMGroupVBlank[__DML_NUM_PLANES__];
dml_float_t TimePerVMGroupFlip[__DML_NUM_PLANES__];
dml_float_t TimePerVMRequestVBlank[__DML_NUM_PLANES__];
dml_float_t TimePerVMRequestFlip[__DML_NUM_PLANES__];
dml_bool_t PTE_BUFFER_MODE[__DML_NUM_PLANES__];
dml_uint_t BIGK_FRAGMENT_SIZE[__DML_NUM_PLANES__];
dml_uint_t SubViewportLinesNeededInMALL[__DML_NUM_PLANES__];
dml_bool_t UsesMALLForStaticScreen[__DML_NUM_PLANES__];
dml_uint_t VStartupMin[__DML_NUM_PLANES__]; /// <brief Minimum vstartup to meet the prefetch schedule (i.e. the prefetch solution can be found at this vstartup time); not the actual global sync vstartup pos.
dml_uint_t VStartup[__DML_NUM_PLANES__]; /// <brief The vstartup value for OTG programming (will set to max vstartup; but now bounded by min(vblank_nom. actual vblank))
dml_uint_t VUpdateOffsetPix[__DML_NUM_PLANES__];
dml_uint_t VUpdateWidthPix[__DML_NUM_PLANES__];
dml_uint_t VReadyOffsetPix[__DML_NUM_PLANES__];
dml_float_t MaxActiveDRAMClockChangeLatencySupported[__DML_NUM_PLANES__];
dml_float_t WritebackAllowFCLKChangeEndPosition[__DML_NUM_PLANES__];
dml_float_t WritebackAllowDRAMClockChangeEndPosition[__DML_NUM_PLANES__];
dml_uint_t DETBufferSizeInKByte[__DML_NUM_PLANES__]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value.
dml_uint_t DETBufferSizeY[__DML_NUM_PLANES__];
dml_uint_t DETBufferSizeC[__DML_NUM_PLANES__];
dml_uint_t SwathHeightY[__DML_NUM_PLANES__];
dml_uint_t SwathHeightC[__DML_NUM_PLANES__];
dml_float_t (*RequiredDPPCLKPerSurface)[__DML_NUM_PLANES__];
dml_uint_t (*NoOfDPP)[__DML_NUM_PLANES__];
dml_uint_t (*MaximumVStartup)[__DML_NUM_PLANES__];
dml_uint_t (*PrefetchLinesY)[__DML_NUM_PLANES__];
dml_uint_t (*PrefetchLinesC)[__DML_NUM_PLANES__];
dml_uint_t (*swath_width_luma_ub_all_states)[__DML_NUM_PLANES__];
dml_uint_t (*swath_width_chroma_ub_all_states)[__DML_NUM_PLANES__];
dml_uint_t (*PDEAndMetaPTEBytesPerFrame)[__DML_NUM_PLANES__];
dml_uint_t (*DPTEBytesPerRow)[__DML_NUM_PLANES__];
dml_uint_t (*MetaRowBytes)[__DML_NUM_PLANES__];
dml_uint_t dummy_integer_array[22][__DML_NUM_PLANES__];
enum dml_odm_mode dummy_odm_mode[__DML_NUM_PLANES__];
dml_bool_t dummy_boolean_array[2][__DML_NUM_PLANES__];
dml_uint_t MaximumVStartup[2][__DML_NUM_PLANES__];
dml_uint_t DSTYAfterScaler[__DML_NUM_PLANES__];
dml_uint_t DSTXAfterScaler[__DML_NUM_PLANES__];
dml_uint_t NextPrefetchMode[__DML_NUM_PLANES__];
dml_uint_t MinPrefetchMode[__DML_NUM_PLANES__];
dml_uint_t MaxPrefetchMode[__DML_NUM_PLANES__];
dml_float_t dummy_single_array[__DML_NUM_PLANES__];
struct DmlPipe SurfParameters[__DML_NUM_PLANES__];
dml_uint_t dummy_integer_array[2][__DML_NUM_PLANES__];
enum dml_output_encoder_class dummy_output_encoder_array[__DML_NUM_PLANES__];
dml_float_t dummy_single_array[2][__DML_NUM_PLANES__];
dml_uint_t dummy_long_array[4][__DML_NUM_PLANES__];
dml_bool_t dummy_boolean_array[2][__DML_NUM_PLANES__];
struct DmlPipe SurfaceParameters[__DML_NUM_PLANES__];
dml_uint_t MaxVStartupLines[__DML_NUM_PLANES__]; /// <brief more like vblank for the plane's OTG
dml_uint_t NextPrefetchMode[__DML_NUM_PLANES__];
dml_uint_t MinPrefetchMode[__DML_NUM_PLANES__];
dml_uint_t MaxPrefetchMode[__DML_NUM_PLANES__];
dml_float_t dummy_unit_vector[__DML_NUM_PLANES__];
dml_float_t ActiveDRAMClockChangeLatencyMargin[__DML_NUM_PLANES__];
dml_float_t ActiveFCLKChangeLatencyMargin[__DML_NUM_PLANES__];
dml_float_t USRRetrainingLatencyMargin[__DML_NUM_PLANES__];
dml_bool_t SynchronizedSurfaces[__DML_NUM_PLANES__][__DML_NUM_PLANES__];
dml_float_t LinesInDETY[__DML_NUM_PLANES__];
dml_float_t LinesInDETC[__DML_NUM_PLANES__];
dml_uint_t LinesInDETYRoundedDownToSwath[__DML_NUM_PLANES__];
dml_uint_t LinesInDETCRoundedDownToSwath[__DML_NUM_PLANES__];
dml_uint_t LBLatencyHidingSourceLinesY[__DML_NUM_PLANES__];
dml_uint_t LBLatencyHidingSourceLinesC[__DML_NUM_PLANES__];
dml_uint_t PTEBufferSizeInRequestsForLuma[__DML_NUM_PLANES__];
dml_uint_t PTEBufferSizeInRequestsForChroma[__DML_NUM_PLANES__];
dml_uint_t MetaRowByteY[__DML_NUM_PLANES__];
dml_uint_t MetaRowByteC[__DML_NUM_PLANES__];
dml_uint_t PixelPTEBytesPerRowY[__DML_NUM_PLANES__];
dml_uint_t PixelPTEBytesPerRowC[__DML_NUM_PLANES__];
dml_uint_t PixelPTEBytesPerRowStorageY[__DML_NUM_PLANES__];
dml_uint_t PixelPTEBytesPerRowStorageC[__DML_NUM_PLANES__];
dml_uint_t PixelPTEBytesPerRowY_one_row_per_frame[__DML_NUM_PLANES__];
dml_uint_t PixelPTEBytesPerRowC_one_row_per_frame[__DML_NUM_PLANES__];
dml_uint_t dpte_row_width_luma_ub_one_row_per_frame[__DML_NUM_PLANES__];
dml_uint_t dpte_row_height_luma_one_row_per_frame[__DML_NUM_PLANES__];
dml_uint_t dpte_row_width_chroma_ub_one_row_per_frame[__DML_NUM_PLANES__];
dml_uint_t dpte_row_height_chroma_one_row_per_frame[__DML_NUM_PLANES__];
dml_bool_t one_row_per_frame_fits_in_buffer[__DML_NUM_PLANES__];
dml_float_t PixelDCFCLKCyclesRequiredInPrefetch[__DML_NUM_PLANES__];
dml_float_t PrefetchPixelLinesTime[__DML_NUM_PLANES__];
dml_float_t DCFCLKRequiredForPeakBandwidthPerSurface[__DML_NUM_PLANES__];
dml_float_t DynamicMetadataVMExtraLatency[__DML_NUM_PLANES__];
dml_uint_t NoOfDPPState[__DML_NUM_PLANES__];
dml_uint_t GPUVMMinPageSizeKBytes[__DML_NUM_PLANES__];
dml_bool_t ForceOneRowForFrame[__DML_NUM_PLANES__];
dml_bool_t PTEBufferModeOverrideEn[__DML_NUM_PLANES__]; //< brief when override enable; the DML will only check the given pte buffer and will use the pte buffer mode as is
dml_bool_t PTEBufferMode[__DML_NUM_PLANES__];
dml_uint_t ViewportWidth[__DML_NUM_PLANES__];
dml_uint_t ViewportHeight[__DML_NUM_PLANES__];
dml_uint_t ViewportWidthChroma[__DML_NUM_PLANES__];
dml_uint_t ViewportHeightChroma[__DML_NUM_PLANES__];
dml_uint_t ViewportXStart[__DML_NUM_PLANES__];
dml_uint_t ViewportXStartC[__DML_NUM_PLANES__];
dml_uint_t ViewportYStart[__DML_NUM_PLANES__];
dml_uint_t ViewportYStartC[__DML_NUM_PLANES__];
dml_bool_t ViewportStationary[__DML_NUM_PLANES__];
dml_bool_t ScalerEnabled[__DML_NUM_PLANES__];
dml_float_t HRatio[__DML_NUM_PLANES__];
dml_float_t VRatio[__DML_NUM_PLANES__];
dml_float_t HRatioChroma[__DML_NUM_PLANES__];
dml_float_t VRatioChroma[__DML_NUM_PLANES__];
dml_uint_t HTaps[__DML_NUM_PLANES__];
dml_uint_t VTaps[__DML_NUM_PLANES__];
dml_uint_t HTapsChroma[__DML_NUM_PLANES__];
dml_uint_t VTapsChroma[__DML_NUM_PLANES__];
dml_uint_t LBBitPerPixel[__DML_NUM_PLANES__];
enum dml_rotation_angle SourceScan[__DML_NUM_PLANES__];
dml_uint_t ScalerRecoutWidth[__DML_NUM_PLANES__];
dml_bool_t DynamicMetadataEnable[__DML_NUM_PLANES__];
dml_uint_t DynamicMetadataLinesBeforeActiveRequired[__DML_NUM_PLANES__];
dml_uint_t DynamicMetadataTransmittedBytes[__DML_NUM_PLANES__];
dml_uint_t DETSizeOverride[__DML_NUM_PLANES__]; /// <brief user can specify the desire DET buffer usage per-plane
dml_uint_t NumberOfCursors[__DML_NUM_PLANES__];
dml_uint_t CursorWidth[__DML_NUM_PLANES__];
dml_uint_t CursorBPP[__DML_NUM_PLANES__];
dml_bool_t setup_for_tdlut[__DML_NUM_PLANES__];
enum dml2_tdlut_addressing_mode tdlut_addressing_mode[__DML_NUM_PLANES__];
enum dml2_tdlut_width_mode tdlut_width_mode[__DML_NUM_PLANES__];
enum dml_use_mall_for_static_screen_mode UseMALLForStaticScreen[__DML_NUM_PLANES__];
enum dml_use_mall_for_pstate_change_mode UseMALLForPStateChange[__DML_NUM_PLANES__];
dml_uint_t BlendingAndTiming[__DML_NUM_PLANES__]; /// <brief From which timing group (like OTG) that this plane is getting its timing from. Mode check also need this info for example to check num OTG; encoder; dsc etc.
enum dml_swizzle_mode SurfaceTiling[__DML_NUM_PLANES__];
enum dml_source_format_class SourcePixelFormat[__DML_NUM_PLANES__];
dml_uint_t PitchY[__DML_NUM_PLANES__];
dml_uint_t SurfaceWidthY[__DML_NUM_PLANES__];
dml_uint_t SurfaceHeightY[__DML_NUM_PLANES__];
dml_uint_t PitchC[__DML_NUM_PLANES__];
dml_uint_t SurfaceWidthC[__DML_NUM_PLANES__];
dml_uint_t SurfaceHeightC[__DML_NUM_PLANES__];
dml_bool_t DCCEnable[__DML_NUM_PLANES__];
dml_uint_t DCCMetaPitchY[__DML_NUM_PLANES__];
dml_uint_t DCCMetaPitchC[__DML_NUM_PLANES__];
dml_float_t DCCRateLuma[__DML_NUM_PLANES__];
dml_float_t DCCRateChroma[__DML_NUM_PLANES__];
dml_float_t DCCFractionOfZeroSizeRequestsLuma[__DML_NUM_PLANES__];
dml_float_t DCCFractionOfZeroSizeRequestsChroma[__DML_NUM_PLANES__];
dml_uint_t HTotal[__DML_NUM_PLANES__];
dml_uint_t VTotal[__DML_NUM_PLANES__];
dml_uint_t HBlankEnd[__DML_NUM_PLANES__];
dml_uint_t VBlankEnd[__DML_NUM_PLANES__];
dml_uint_t RefreshRate[__DML_NUM_PLANES__];
dml_uint_t VFrontPorch[__DML_NUM_PLANES__];
dml_float_t PixelClock[__DML_NUM_PLANES__];
dml_uint_t HActive[__DML_NUM_PLANES__];
dml_uint_t VActive[__DML_NUM_PLANES__];
dml_bool_t Interlace[__DML_NUM_PLANES__];
dml_bool_t DRRDisplay[__DML_NUM_PLANES__];
dml_uint_t VBlankNom[__DML_NUM_PLANES__];
dml_uint_t DSCInputBitPerComponent[__DML_NUM_PLANES__];
enum dml_output_format_class OutputFormat[__DML_NUM_PLANES__];
enum dml_output_encoder_class OutputEncoder[__DML_NUM_PLANES__];
dml_uint_t OutputMultistreamId[__DML_NUM_PLANES__];
dml_bool_t OutputMultistreamEn[__DML_NUM_PLANES__];
dml_float_t OutputBpp[__DML_NUM_PLANES__]; //< brief Use by mode_programming to specify a output bpp; user can use the output from mode_support (support.OutputBpp)
dml_float_t PixelClockBackEnd[__DML_NUM_PLANES__];
enum dml_dsc_enable DSCEnable[__DML_NUM_PLANES__]; //< brief for mode support check; use to determine if dsc is required
dml_uint_t OutputLinkDPLanes[__DML_NUM_PLANES__];
enum dml_output_link_dp_rate OutputLinkDPRate[__DML_NUM_PLANES__];
dml_float_t ForcedOutputLinkBPP[__DML_NUM_PLANES__];
dml_uint_t AudioSampleRate[__DML_NUM_PLANES__];
dml_uint_t AudioSampleLayout[__DML_NUM_PLANES__];
dml_bool_t OutputDisabled[__DML_NUM_PLANES__];
dml_uint_t DSCSlices[__DML_NUM_PLANES__];
enum dml_source_format_class WritebackPixelFormat[__DML_NUM_PLANES__];
dml_bool_t WritebackEnable[__DML_NUM_PLANES__];
dml_uint_t ActiveWritebacksPerSurface[__DML_NUM_PLANES__];
dml_uint_t WritebackDestinationWidth[__DML_NUM_PLANES__];
dml_uint_t WritebackDestinationHeight[__DML_NUM_PLANES__];
dml_uint_t WritebackSourceWidth[__DML_NUM_PLANES__];
dml_uint_t WritebackSourceHeight[__DML_NUM_PLANES__];
dml_uint_t WritebackHTaps[__DML_NUM_PLANES__];
dml_uint_t WritebackVTaps[__DML_NUM_PLANES__];
dml_float_t WritebackHRatio[__DML_NUM_PLANES__];
dml_float_t WritebackVRatio[__DML_NUM_PLANES__];
enum dml_odm_mode ODMMode[__DML_NUM_PLANES__]; /// <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage
dml_uint_t DPPPerSurface[__DML_NUM_PLANES__]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4.
dml_bool_t DSCEnabled[__DML_NUM_PLANES__]; /// <brief Indicate if the DSC is enabled; used in mode_programming
dml_uint_t NumberOfDSCSlices[__DML_NUM_PLANES__]; /// <brief Indicate how many slices needed to support the given mode
enum dml_clk_cfg_policy dppclk_option[__DML_NUM_PLANES__];
dml_float_t dppclk_mhz[__DML_NUM_PLANES__];
enum dml_mpc_use_policy MPCCombineUse[__DML_NUM_PLANES__]; /// <brief MPC Combine mode as selected by the user; used in mode check stage
enum dml_odm_use_policy ODMUse[__DML_NUM_PLANES__]; /// <brief ODM mode as selected by the user; used in mode check stage
enum dml_immediate_flip_requirement ImmediateFlipRequirement[__DML_NUM_PLANES__]; /// <brief Is immediate flip a requirement for this plane. When host vm is present iflip is needed regardless
enum dml_prefetch_modes AllowForPStateChangeOrStutterInVBlank[__DML_NUM_PLANES__]; /// <brief To specify if the DML should calculate the values for support different pwr saving features (cstate; pstate; etc.) during vblank
dml_float_t ActiveDRAMClockChangeLatencyMargin[__DML_NUM_PLANES__];
dml_uint_t SubViewportLinesNeededInMALL[__DML_NUM_PLANES__];
dml_bool_t NoTimeForPrefetch[2][__DML_NUM_PLANES__];
dml_bool_t NoTimeForDynamicMetadata[2][__DML_NUM_PLANES__];
dml_bool_t MPCCombineEnable[__DML_NUM_PLANES__]; /// <brief Indicate if the MPC Combine enable in the given state and optimize mpc combine setting
enum dml_odm_mode ODMMode[__DML_NUM_PLANES__]; /// <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage
dml_uint_t DPPPerSurface[__DML_NUM_PLANES__]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4.
dml_bool_t DSCEnabled[__DML_NUM_PLANES__]; /// <brief Indicate if the DSC is actually required; used in mode_programming
dml_bool_t FECEnabled[__DML_NUM_PLANES__]; /// <brief Indicate if the FEC is actually required
dml_uint_t NumberOfDSCSlices[__DML_NUM_PLANES__]; /// <brief Indicate how many slices needed to support the given mode
dml_float_t OutputBpp[__DML_NUM_PLANES__];
enum dml_output_type_and_rate__type OutputType[__DML_NUM_PLANES__];
enum dml_output_type_and_rate__rate OutputRate[__DML_NUM_PLANES__];
dml_float_t AlignedDCCMetaPitchY[__DML_NUM_PLANES__]; /// <brief Pitch value that is aligned to tiling setting
dml_float_t AlignedDCCMetaPitchC[__DML_NUM_PLANES__];
dml_float_t AlignedYPitch[__DML_NUM_PLANES__];
dml_float_t AlignedCPitch[__DML_NUM_PLANES__];
dml_float_t RequiredDPPCLKThisState[__DML_NUM_PLANES__];
dml_float_t RequiredDISPCLKPerSurface[2][__DML_NUM_PLANES__];
dml_float_t RequiredDPPCLKPerSurface[2][__DML_NUM_PLANES__];
dml_uint_t DETBufferSizeInKByte[__DML_NUM_PLANES__]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value.
dml_uint_t DETBufferSizeY[__DML_NUM_PLANES__];
dml_uint_t DETBufferSizeC[__DML_NUM_PLANES__];
dml_uint_t SwathHeightY[__DML_NUM_PLANES__];
dml_uint_t SwathHeightC[__DML_NUM_PLANES__];
dml_uint_t SwathWidthYAllStates[2][__DML_NUM_PLANES__];
dml_uint_t SwathWidthCAllStates[2][__DML_NUM_PLANES__];
dml_uint_t SwathHeightYAllStates[2][__DML_NUM_PLANES__];
dml_uint_t SwathHeightCAllStates[2][__DML_NUM_PLANES__];
dml_uint_t SwathWidthYThisState[__DML_NUM_PLANES__];
dml_uint_t SwathWidthCThisState[__DML_NUM_PLANES__];
dml_uint_t SwathHeightYThisState[__DML_NUM_PLANES__];
dml_uint_t SwathHeightCThisState[__DML_NUM_PLANES__];
dml_uint_t DETBufferSizeInKByteAllStates[2][__DML_NUM_PLANES__];
dml_uint_t DETBufferSizeYAllStates[2][__DML_NUM_PLANES__];
dml_uint_t DETBufferSizeCAllStates[2][__DML_NUM_PLANES__];
dml_uint_t DETBufferSizeInKByteThisState[__DML_NUM_PLANES__];
dml_uint_t DETBufferSizeYThisState[__DML_NUM_PLANES__];
dml_uint_t DETBufferSizeCThisState[__DML_NUM_PLANES__];
dml_float_t VRatioPreY[2][__DML_NUM_PLANES__];
dml_float_t VRatioPreC[2][__DML_NUM_PLANES__];
dml_uint_t swath_width_luma_ub_all_states[2][__DML_NUM_PLANES__];
dml_uint_t swath_width_chroma_ub_all_states[2][__DML_NUM_PLANES__];
dml_uint_t swath_width_luma_ub_this_state[__DML_NUM_PLANES__];
dml_uint_t swath_width_chroma_ub_this_state[__DML_NUM_PLANES__];
dml_uint_t RequiredSlots[__DML_NUM_PLANES__];
dml_uint_t PDEAndMetaPTEBytesPerFrame[2][__DML_NUM_PLANES__];
dml_uint_t MetaRowBytes[2][__DML_NUM_PLANES__];
dml_uint_t DPTEBytesPerRow[2][__DML_NUM_PLANES__];
dml_uint_t PrefetchLinesY[2][__DML_NUM_PLANES__];
dml_uint_t PrefetchLinesC[2][__DML_NUM_PLANES__];
dml_uint_t MaxNumSwY[__DML_NUM_PLANES__]; /// <brief Max number of swath for prefetch
dml_uint_t MaxNumSwC[__DML_NUM_PLANES__]; /// <brief Max number of swath for prefetch
dml_uint_t PrefillY[__DML_NUM_PLANES__];
dml_uint_t PrefillC[__DML_NUM_PLANES__];
dml_uint_t PrefetchLinesYThisState[__DML_NUM_PLANES__];
dml_uint_t PrefetchLinesCThisState[__DML_NUM_PLANES__];
dml_uint_t DPTEBytesPerRowThisState[__DML_NUM_PLANES__];
dml_uint_t PDEAndMetaPTEBytesPerFrameThisState[__DML_NUM_PLANES__];
dml_uint_t MetaRowBytesThisState[__DML_NUM_PLANES__];
dml_bool_t use_one_row_for_frame[2][__DML_NUM_PLANES__];
dml_bool_t use_one_row_for_frame_flip[2][__DML_NUM_PLANES__];
dml_bool_t use_one_row_for_frame_this_state[__DML_NUM_PLANES__];
dml_bool_t use_one_row_for_frame_flip_this_state[__DML_NUM_PLANES__];
dml_float_t LineTimesForPrefetch[__DML_NUM_PLANES__];
dml_float_t LinesForMetaPTE[__DML_NUM_PLANES__];
dml_float_t LinesForMetaAndDPTERow[__DML_NUM_PLANES__];
dml_float_t SwathWidthYSingleDPP[__DML_NUM_PLANES__];
dml_float_t SwathWidthCSingleDPP[__DML_NUM_PLANES__];
dml_uint_t BytePerPixelY[__DML_NUM_PLANES__];
dml_uint_t BytePerPixelC[__DML_NUM_PLANES__];
dml_float_t BytePerPixelInDETY[__DML_NUM_PLANES__];
dml_float_t BytePerPixelInDETC[__DML_NUM_PLANES__];
dml_uint_t Read256BlockHeightY[__DML_NUM_PLANES__];
dml_uint_t Read256BlockWidthY[__DML_NUM_PLANES__];
dml_uint_t Read256BlockHeightC[__DML_NUM_PLANES__];
dml_uint_t Read256BlockWidthC[__DML_NUM_PLANES__];
dml_uint_t MacroTileHeightY[__DML_NUM_PLANES__];
dml_uint_t MacroTileHeightC[__DML_NUM_PLANES__];
dml_uint_t MacroTileWidthY[__DML_NUM_PLANES__];
dml_uint_t MacroTileWidthC[__DML_NUM_PLANES__];
dml_float_t PSCL_FACTOR[__DML_NUM_PLANES__];
dml_float_t PSCL_FACTOR_CHROMA[__DML_NUM_PLANES__];
dml_float_t MaximumSwathWidthLuma[__DML_NUM_PLANES__];
dml_float_t MaximumSwathWidthChroma[__DML_NUM_PLANES__];
dml_float_t Tno_bw[__DML_NUM_PLANES__];
dml_float_t DestinationLinesToRequestVMInImmediateFlip[__DML_NUM_PLANES__];
dml_float_t DestinationLinesToRequestRowInImmediateFlip[__DML_NUM_PLANES__];
dml_float_t WritebackDelayTime[__DML_NUM_PLANES__];
dml_uint_t dpte_group_bytes[__DML_NUM_PLANES__];
dml_uint_t dpte_row_height[__DML_NUM_PLANES__];
dml_uint_t dpte_row_height_chroma[__DML_NUM_PLANES__];
dml_uint_t meta_row_height[__DML_NUM_PLANES__];
dml_uint_t meta_row_height_chroma[__DML_NUM_PLANES__];
dml_float_t UrgentBurstFactorCursor[2][__DML_NUM_PLANES__];
dml_float_t UrgentBurstFactorCursorPre[__DML_NUM_PLANES__];
dml_float_t UrgentBurstFactorLuma[2][__DML_NUM_PLANES__];
dml_float_t UrgentBurstFactorLumaPre[__DML_NUM_PLANES__];
dml_float_t UrgentBurstFactorChroma[2][__DML_NUM_PLANES__];
dml_float_t UrgentBurstFactorChromaPre[__DML_NUM_PLANES__];
dml_bool_t RequiresDSC[__DML_NUM_PLANES__];
dml_bool_t RequiresFEC[__DML_NUM_PLANES__];
dml_float_t OutputBppPerState[__DML_NUM_PLANES__];
dml_uint_t DSCDelayPerState[__DML_NUM_PLANES__];
enum dml_output_type_and_rate__type OutputTypePerState[__DML_NUM_PLANES__];
enum dml_output_type_and_rate__rate OutputRatePerState[__DML_NUM_PLANES__];
dml_float_t ReadBandwidthLuma[__DML_NUM_PLANES__];
dml_float_t ReadBandwidthChroma[__DML_NUM_PLANES__];
dml_float_t WriteBandwidth[__DML_NUM_PLANES__];
dml_float_t RequiredPrefetchPixelDataBWLuma[__DML_NUM_PLANES__];
dml_float_t RequiredPrefetchPixelDataBWChroma[__DML_NUM_PLANES__];
dml_float_t cursor_bw[__DML_NUM_PLANES__];
dml_float_t cursor_bw_pre[__DML_NUM_PLANES__];
dml_float_t prefetch_vmrow_bw[__DML_NUM_PLANES__];
dml_float_t final_flip_bw[__DML_NUM_PLANES__];
dml_float_t meta_row_bandwidth_this_state[__DML_NUM_PLANES__];
dml_float_t dpte_row_bandwidth_this_state[__DML_NUM_PLANES__];
dml_float_t meta_row_bandwidth[2][__DML_NUM_PLANES__];
dml_float_t dpte_row_bandwidth[2][__DML_NUM_PLANES__];
enum dml_odm_mode ODMModePerState[__DML_NUM_PLANES__];
enum dml_odm_mode ODMModeThisState[__DML_NUM_PLANES__];
dml_uint_t SurfaceSizeInMALL[__DML_NUM_PLANES__];
dml_uint_t NoOfDPP[2][__DML_NUM_PLANES__];
dml_uint_t NoOfDPPThisState[__DML_NUM_PLANES__];
dml_bool_t MPCCombine[2][__DML_NUM_PLANES__];
dml_bool_t MPCCombineThisState[__DML_NUM_PLANES__];
dml_float_t MinDPPCLKUsingSingleDPP[__DML_NUM_PLANES__];
dml_bool_t SingleDPPViewportSizeSupportPerSurface[__DML_NUM_PLANES__];
dml_bool_t ImmediateFlipSupportedForPipe[__DML_NUM_PLANES__];
dml_bool_t NotUrgentLatencyHiding[__DML_NUM_PLANES__];
dml_bool_t NotUrgentLatencyHidingPre[__DML_NUM_PLANES__];
dml_bool_t PTEBufferSizeNotExceededPerState[__DML_NUM_PLANES__];
dml_bool_t DCCMetaBufferSizeNotExceededPerState[__DML_NUM_PLANES__];
dml_uint_t PrefetchMode[__DML_NUM_PLANES__];
for (dml_uint_t k = 0; k < __DML_NUM_PLANES__; k++) {
ASSERT(plane_idx < __DML_NUM_PLANES__);
for (dml_uint_t i = 0; i < __DML_NUM_PLANES__; i++) {
for (dml_uint_t k = 0; k < __DML_NUM_PLANES__; ++k) {
for (dml_uint_t plane_idx = 0; plane_idx < __DML_NUM_PLANES__; plane_idx++) {
disp_cfg_index_max = __DML_NUM_PLANES__;
for (int i = 0; i < __DML_NUM_PLANES__; i++) {
int num_of_planes_per_stream[__DML_NUM_PLANES__] = { 0 };
unsigned int planes_per_timing[__DML_NUM_PLANES__] = {0};
for (i = 0; i < __DML_NUM_PLANES__; i++) {
for (i = 0; i < __DML_NUM_PLANES__; i++) {
dml_uint_t first_pipe_idx_in_plane = __DML_NUM_PLANES__;