__BIT
if (pos & __BIT(n))
if (pos & __BIT(n))
#define MVNETA_SDC_IPGINTRX_V2_MASK (__BIT(25) | __BITS(21, 7))
WR4(sc, GENET_TX_DMA_RING_CFG, __BIT(qid)); /* enable */
WR4(sc, GENET_RX_DMA_RING_CFG, __BIT(qid)); /* enable */
#define GENET_RX_DESC_STATUS_OWN __BIT(15)
#define GENET_RX_DESC_STATUS_EOP __BIT(14)
#define GENET_RX_DESC_STATUS_SOP __BIT(13)
#define GENET_RX_DESC_STATUS_RX_ERROR __BIT(2)
#define GENET_TX_DESC_STATUS_OWN __BIT(15)
#define GENET_TX_DESC_STATUS_EOP __BIT(14)
#define GENET_TX_DESC_STATUS_SOP __BIT(13)
#define GENET_TX_DESC_STATUS_CRC __BIT(6)
#define GENET_RX_DMA_CTRL_RBUF_EN(qid) __BIT((qid) + 1)
#define GENET_RX_DMA_CTRL_EN __BIT(0)
#define GENET_TX_DMA_CTRL_RBUF_EN(qid) __BIT((qid) + 1)
#define GENET_TX_DMA_CTRL_EN __BIT(0)
#define __BITS(__n, __m) ((__BIT((__n) - (__m) + 1) - 1) << (__m))
#define GENET_SYS_RBUF_FLUSH_RESET __BIT(1)
#define GENET_EXT_RGMII_OOB_ID_MODE_DISABLE __BIT(16)
#define GENET_EXT_RGMII_OOB_RGMII_MODE_EN __BIT(6)
#define GENET_EXT_RGMII_OOB_OOB_DISABLE __BIT(5)
#define GENET_EXT_RGMII_OOB_RGMII_LINK __BIT(4)
#define GENET_IRQ_MDIO_ERROR __BIT(24)
#define GENET_IRQ_MDIO_DONE __BIT(23)
#define GENET_IRQ_TXDMA_DONE __BIT(16)
#define GENET_IRQ_RXDMA_DONE __BIT(13)
#define GENET_RBUF_BAD_DIS __BIT(2)
#define GENET_RBUF_ALIGN_2B __BIT(1)
#define GENET_RBUF_64B_EN __BIT(0)
#define GENET_UMAC_CMD_LCL_LOOP_EN __BIT(15)
#define GENET_UMAC_CMD_SW_RESET __BIT(13)
#define GENET_UMAC_CMD_PROMISC __BIT(4)
#define GENET_UMAC_CMD_RXEN __BIT(1)
#define GENET_UMAC_CMD_TXEN __BIT(0)
#define GENET_UMAC_MIB_RESET_TX __BIT(2)
#define GENET_UMAC_MIB_RESET_RUNT __BIT(1)
#define GENET_UMAC_MIB_RESET_RX __BIT(0)
#define GENET_MDIO_START_BUSY __BIT(29)
#define GENET_MDIO_READ __BIT(27)
#define GENET_MDIO_WRITE __BIT(26)
#define HDMI_MC_SWRSTZREQ_CECSWRST_REQ __BIT(6)