sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

17

#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

125

#define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30))

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

126

#define XELPDP_LANE_PHY_CURRENT_STATUS(lane) _PICK(lane, REG_BIT(29), REG_BIT(28))

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

127

#define XELPDP_LANE_POWERDOWN_UPDATE(lane) _PICK(lane, REG_BIT(25), REG_BIT(24))

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

132

#define XELPDP_LANE_POWERDOWN_NEW_STATE(lane, val) _PICK(lane, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1458

#define _CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2514

#define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2595

#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2603

#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2641

#define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \

sys/dev/pci/drm/i915/display/intel_hdcp_regs.h

187

#define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \

sys/dev/pci/drm/i915/display/intel_hdcp_regs.h

238

#define PIPE_HDCP2_STREAM_STATUS(pipe) _MMIO(_PICK((pipe), \

sys/dev/pci/drm/i915/display/intel_hdcp_regs.h

74

#define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

58

#define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

321

#define RING_FAULT_REG(engine) _MMIO(_PICK((engine)->class, \

sys/dev/pci/drm/i915/i915_reg.h

308

#define HECI_FWSTS(base, x) _MMIO((base) + _PICK(x, -(base), \

sys/dev/pci/drm/i915/i915_reg.h

991

#define LATENCY_REPORTING_REMOVED(pipe) _PICK((pipe), \