sys/dev/pci/drm/i915/display/intel_sprite_regs.h

354

#define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

355

#define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

356

#define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

362

#define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

363

#define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

364

#define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

365

#define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

366

#define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

372

#define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

373

#define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

374

#define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

380

#define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

381

#define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

382

#define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)