sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

21

_MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

27

_MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

31

_MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) + _BXT_LANE_OFFSET(lane))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

98

#define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

101

#define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

102

#define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

111

#define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

120

#define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

131

#define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

152

#define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

175

#define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

228

#define WM1_LP_ILK _MMIO(0x45108)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

229

#define WM2_LP_ILK _MMIO(0x4510c)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

230

#define WM3_LP_ILK _MMIO(0x45110)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

24

#define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

242

#define WM1S_LP_ILK _MMIO(0x45120)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

243

#define WM2S_LP_IVB _MMIO(0x45124)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

244

#define WM3S_LP_IVB _MMIO(0x45128)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

249

#define WM_MISC _MMIO(0x45260)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

252

#define WM_DBG _MMIO(0x45280)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

37

#define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

44

#define DSPFW1(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

55

#define DSPFW2(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

71

#define DSPFW3(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

82

#define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

89

#define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

9

#define DSPARB(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

98

#define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)

sys/dev/pci/drm/i915/display/icl_dsi_regs.h

31

#define ADL_MIPIO_DW(port, dw) _MMIO(_ICL_COMBOPHY(port) + _ADL_MIPIO_REG + 4 * (dw))

sys/dev/pci/drm/i915/display/intel_audio_regs.h

11

#define G4X_AUD_CNTL_ST _MMIO(0x620B4)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

112

#define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

113

#define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

124

#define HSW_AUD_CHICKENBIT _MMIO(0x65f10)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

127

#define AUD_FREQ_CNTRL _MMIO(0x65900)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

128

#define AUD_PIN_BUF_CTL _MMIO(0x48414)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

131

#define AUD_TS_CDCLK_M _MMIO(0x65ea0)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

133

#define AUD_TS_CDCLK_N _MMIO(0x65ea4)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

136

#define AUD_CONFIG_BE _MMIO(0x65ef0)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

155

#define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

16

#define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

167

#define AUD_CHICKENBIT_REG3 _MMIO(0x65F1C)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

29

#define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

39

#define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

47

#define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)

sys/dev/pci/drm/i915/display/intel_backlight_regs.h

106

#define UTIL_PIN_CTL _MMIO(0x48400)

sys/dev/pci/drm/i915/display/intel_backlight_regs.h

24

#define BLC_PWM_CTL2 _MMIO(0x61250) /* 965+ only */

sys/dev/pci/drm/i915/display/intel_backlight_regs.h

47

#define BLC_PWM_CTL _MMIO(0x61254)

sys/dev/pci/drm/i915/display/intel_backlight_regs.h

69

#define BLC_HIST_CTL _MMIO(0x61260)

sys/dev/pci/drm/i915/display/intel_backlight_regs.h

74

#define BLC_PWM_CPU_CTL2 _MMIO(0x48250)

sys/dev/pci/drm/i915/display/intel_backlight_regs.h

75

#define BLC_PWM_CPU_CTL _MMIO(0x48254)

sys/dev/pci/drm/i915/display/intel_backlight_regs.h

77

#define HSW_BLC_PWM2_CTL _MMIO(0x48350)

sys/dev/pci/drm/i915/display/intel_backlight_regs.h

81

#define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)

sys/dev/pci/drm/i915/display/intel_backlight_regs.h

85

#define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)

sys/dev/pci/drm/i915/display/intel_cmtg_regs.h

11

#define CMTG_CLK_SEL _MMIO(0x46160)

sys/dev/pci/drm/i915/display/intel_cmtg_regs.h

17

#define TRANS_CMTG_CTL_A _MMIO(0x6fa88)

sys/dev/pci/drm/i915/display/intel_cmtg_regs.h

18

#define TRANS_CMTG_CTL_B _MMIO(0x6fb88)

sys/dev/pci/drm/i915/display/intel_color_regs.h

222

#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) /* u1.16 */

sys/dev/pci/drm/i915/display/intel_color_regs.h

223

#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) /* u3.16 */

sys/dev/pci/drm/i915/display/intel_color_regs.h

224

#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) /* glk+, u3.16 */

sys/dev/pci/drm/i915/display/intel_color_regs.h

308

#define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)

sys/dev/pci/drm/i915/display/intel_color_regs.h

309

#define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)

sys/dev/pci/drm/i915/display/intel_color_regs.h

33

#define PALETTE(dev_priv, pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \

sys/dev/pci/drm/i915/display/intel_color_regs.h

48

#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)

sys/dev/pci/drm/i915/display/intel_color_regs.h

65

#define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)

sys/dev/pci/drm/i915/display/intel_color_regs.h

69

#define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) /* u1.16 */

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

107

#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

108

#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

109

#define ICL_PORT_TX_DW2_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(2, ln, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

119

#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

120

#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

121

#define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

130

#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

131

#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

132

#define ICL_PORT_TX_DW5_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(5, ln, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

143

#define ICL_PORT_TX_DW6_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(6, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

144

#define ICL_PORT_TX_DW6_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(6, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

145

#define ICL_PORT_TX_DW6_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(6, ln, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

150

#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

151

#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

152

#define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

156

#define ICL_PORT_TX_DW8_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(8, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

157

#define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

158

#define ICL_PORT_TX_DW8_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(8, ln, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

164

#define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

27

#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

31

#define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

46

#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

54

#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

57

#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

59

#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

69

#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

72

#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

74

#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

86

#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

87

#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

88

#define ICL_PORT_PCS_DW1_LN(ln, phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy))

sys/dev/pci/drm/i915/display/intel_crt_regs.h

11

#define ADPA _MMIO(0x61100)

sys/dev/pci/drm/i915/display/intel_crt_regs.h

12

#define PCH_ADPA _MMIO(0xe1100)

sys/dev/pci/drm/i915/display/intel_crt_regs.h

13

#define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)

sys/dev/pci/drm/i915/display/intel_crt_regs.h

48

#define _VGA_MSR_WRITE _MMIO(0x3c2)

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

80

#define CUR_WM(pipe, level) _MMIO(_PIPE((pipe), _CUR_WM_A_0, _CUR_WM_B_0) + (level) * 4)

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

116

#define _XELPDP_PORT_BUF_CTL2(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

139

#define _XELPDP_PORT_BUF_CTL3(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

162

#define _XELPDP_PORT_MSGBUS_TIMER(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

179

#define _XELPDP_PORT_CLOCK_CTL(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

220

#define TCSS_DISP_MAILBOX_IN_CMD _MMIO(0x161300)

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

225

#define TCSS_DISP_MAILBOX_IN_DATA _MMIO(0x161304)

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

39

#define _XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

425

#define PICA_PHY_CONFIG_CONTROL _MMIO(0x16FE68)

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

59

#define _XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

90

#define _XELPDP_PORT_BUF_CTL1(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

25

#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

26

#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

27

#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

28

#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

29

#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

30

#define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b))

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

32

#define _MMIO_BASE_PIPE3(base, pipe, a, b, c) _MMIO((base) + _PICK_EVEN_2RANGES(pipe, 1, a, a, b, c))

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

33

#define _MMIO_BASE_PORT3(base, pipe, a, b, c) _MMIO((base) + _PICK_EVEN_2RANGES(pipe, 1, a, a, b, c))

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

39

#define _MMIO_PIPE2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->pipe_offsets[(pipe)] - \

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

42

#define _MMIO_TRANS2(display, tran, reg) _MMIO(DISPLAY_INFO(display)->trans_offsets[(tran)] - \

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

45

#define _MMIO_CURSOR2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->cursor_offsets[(pipe)] - \

sys/dev/pci/drm/i915/display/intel_display_regs.h

100

_MMIO(_PICK_EVEN_2RANGES(x, 2, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1004

#define RR_HW_CTL _MMIO(0x45300)

sys/dev/pci/drm/i915/display/intel_display_regs.h

113

#define IPS_CTL _MMIO(0x43408)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1232

#define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1234

#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1235

#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1236

#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1237

#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))

sys/dev/pci/drm/i915/display/intel_display_regs.h

126

#define VGA0 _MMIO(0x6000)

sys/dev/pci/drm/i915/display/intel_display_regs.h

127

#define VGA1 _MMIO(0x6004)

sys/dev/pci/drm/i915/display/intel_display_regs.h

128

#define VGA_PD _MMIO(0x6010)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1285

#define GEN8_DE_PORT_ISR _MMIO(0x44440)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1286

#define GEN8_DE_PORT_IMR _MMIO(0x44444)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1287

#define GEN8_DE_PORT_IIR _MMIO(0x44448)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1288

#define GEN8_DE_PORT_IER _MMIO(0x4444c)

sys/dev/pci/drm/i915/display/intel_display_regs.h

13

#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1321

#define GEN8_DE_MISC_ISR _MMIO(0x44460)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1322

#define GEN8_DE_MISC_IMR _MMIO(0x44464)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1323

#define GEN8_DE_MISC_IIR _MMIO(0x44468)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1324

#define GEN8_DE_MISC_IER _MMIO(0x4446c)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1336

#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1347

#define GEN11_DE_HPD_ISR _MMIO(0x44470)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1348

#define GEN11_DE_HPD_IMR _MMIO(0x44474)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1349

#define GEN11_DE_HPD_IIR _MMIO(0x44478)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1350

#define GEN11_DE_HPD_IER _MMIO(0x4447c)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1370

#define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1371

#define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1377

#define PICAINTERRUPT_ISR _MMIO(0x16FE50)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1378

#define PICAINTERRUPT_IMR _MMIO(0x16FE54)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1379

#define PICAINTERRUPT_IIR _MMIO(0x16FE58)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1380

#define PICAINTERRUPT_IER _MMIO(0x16FE5C)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1394

#define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1402

#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1417

#define GEN12_DCPR_STATUS_1 _MMIO(0x46440)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1420

#define FUSE_STRAP _MMIO(0x42014)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1431

#define FUSE_STRAP3 _MMIO(0x42020)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1434

#define CHICKEN_MISC_2 _MMIO(0x42084)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1443

#define CHICKEN_MISC_3 _MMIO(0x42088)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1448

#define CHICKEN_MISC_4 _MMIO(0x4208c)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1458

#define _CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1487

#define DISP_ARB_CTL2 _MMIO(0x45004)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1491

#define GEN7_MSG_CTL _MMIO(0x45010)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1497

#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1506

#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1510

#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1514

#define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1520

#define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1523

#define SKL_DFSM _MMIO(0x51000)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1539

#define XE2LPD_DE_CAP _MMIO(0x41100)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1546

#define SKL_DSSM _MMIO(0x51004)

sys/dev/pci/drm/i915/display/intel_display_regs.h

164

#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)

sys/dev/pci/drm/i915/display/intel_display_regs.h

166

#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1676

#define SERR_INT _MMIO(0xc4040)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1681

#define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */

sys/dev/pci/drm/i915/display/intel_display_regs.h

1724

#define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */

sys/dev/pci/drm/i915/display/intel_display_regs.h

1735

#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1744

#define SHOTPLUG_CTL_TC _MMIO(0xc4034)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1749

#define SHPD_FILTER_CNT _MMIO(0xc4038)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1755

#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1759

#define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1764

#define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1766

#define PCH_DPLL_TEST _MMIO(0xc606c)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1768

#define PCH_DREF_CONTROL _MMIO(0xC6200)

sys/dev/pci/drm/i915/display/intel_display_regs.h

177

#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1791

#define PCH_RAWCLK_FREQ _MMIO(0xc6204)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1803

#define PCH_DPLL_TMR_CFG _MMIO(0xc6208)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1805

#define PCH_SSC4_PARMS _MMIO(0xc6210)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1806

#define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1808

#define PCH_DPLL_SEL _MMIO(0xc7000)

sys/dev/pci/drm/i915/display/intel_display_regs.h

19

#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2008

#define PCH_DP_B _MMIO(0xe4100)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2009

#define PCH_DP_C _MMIO(0xe4200)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2010

#define PCH_DP_D _MMIO(0xe4300)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2090

#define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2109

#define HSW_PWR_WELL_CTL1 _MMIO(0x45400)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2110

#define HSW_PWR_WELL_CTL2 _MMIO(0x45404)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2111

#define HSW_PWR_WELL_CTL3 _MMIO(0x45408)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2112

#define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2145

#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2146

#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2147

#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2173

#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2174

#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2175

#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2192

#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2196

#define HSW_PWR_WELL_CTL6 _MMIO(0x45414)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2207

#define SKL_FUSE_STATUS _MMIO(0x42000)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2282

#define TRANS_CMTG_CHICKEN _MMIO(0x6fa90)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2360

#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2362

#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2380

#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2383

#define PIXCLK_GATE _MMIO(0xC6020)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2388

#define SPLL_CTL _MMIO(0x46020)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2456

#define CDCLK_FREQ _MMIO(0x46200)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2474

#define LCPLL_CTL _MMIO(0x130040)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2497

#define CDCLK_CTL _MMIO(0x46000)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2522

#define CDCLK_SQUASH_CTL _MMIO(0x46008)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2530

#define LCPLL1_CTL _MMIO(0x46010)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2531

#define LCPLL2_CTL _MMIO(0x46014)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2535

#define DPLL_CTRL1 _MMIO(0x6C058)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2550

#define DPLL_CTRL2 _MMIO(0x6C05C)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2558

#define DPLL_STATUS _MMIO(0x6C060)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2594

#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)

sys/dev/pci/drm/i915/display/intel_display_regs.h

263

#define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2657

#define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2663

#define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2667

#define TBT_PLL_ENABLE _MMIO(0x46020)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2678

#define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2739

#define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2754

#define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2762

#define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2768

#define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2775

#define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2781

#define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2786

#define BXT_DE_PLL_CTL _MMIO(0x6d000)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2790

#define BXT_DE_PLL_ENABLE _MMIO(0x46070)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2799

#define DC_STATE_EN _MMIO(0x45504)

sys/dev/pci/drm/i915/display/intel_display_regs.h

280

#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2810

#define DC_STATE_DEBUG _MMIO(0x45520)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2814

#define D_COMP_BDW _MMIO(0x138144)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2826

#define SFUSE_STRAP _MMIO(0xc2014)

sys/dev/pci/drm/i915/display/intel_display_regs.h

283

#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2837

#define GEN4_TIMESTAMP _MMIO(0x2358)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2838

#define ILK_TIMESTAMP_HI _MMIO(0x70070)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2839

#define IVB_TIMESTAMP_CTR _MMIO(0x44070)

sys/dev/pci/drm/i915/display/intel_display_regs.h

285

#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2869

#define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2897

#define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

290

#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2906

#define CLKREQ_POLICY _MMIO(0x101038)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2909

#define CLKGATE_DIS_MISC _MMIO(0x46534)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2923

#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2928

#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8 + 4)

sys/dev/pci/drm/i915/display/intel_display_regs.h

297

#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)

sys/dev/pci/drm/i915/display/intel_display_regs.h

299

#define PEG_BAND_GAP_DATA _MMIO(0x14d68)

sys/dev/pci/drm/i915/display/intel_display_regs.h

304

#define OVADD _MMIO(0x30000)

sys/dev/pci/drm/i915/display/intel_display_regs.h

305

#define DOVSTA _MMIO(0x30008)

sys/dev/pci/drm/i915/display/intel_display_regs.h

307

#define OGAMC5 _MMIO(0x30010)

sys/dev/pci/drm/i915/display/intel_display_regs.h

308

#define OGAMC4 _MMIO(0x30014)

sys/dev/pci/drm/i915/display/intel_display_regs.h

309

#define OGAMC3 _MMIO(0x30018)

sys/dev/pci/drm/i915/display/intel_display_regs.h

310

#define OGAMC2 _MMIO(0x3001c)

sys/dev/pci/drm/i915/display/intel_display_regs.h

311

#define OGAMC1 _MMIO(0x30020)

sys/dev/pci/drm/i915/display/intel_display_regs.h

312

#define OGAMC0 _MMIO(0x30024)

sys/dev/pci/drm/i915/display/intel_display_regs.h

314

#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)

sys/dev/pci/drm/i915/display/intel_display_regs.h

318

#define GEN9_CLKGATE_DIS_5 _MMIO(0x46540)

sys/dev/pci/drm/i915/display/intel_display_regs.h

36

_MMIO(_PICK_EVEN_2RANGES(phy, 1, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

41

#define UAIMI_SPR1 _MMIO(0x4F074)

sys/dev/pci/drm/i915/display/intel_display_regs.h

415

#define PORT_HOTPLUG_EN(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)

sys/dev/pci/drm/i915/display/intel_display_regs.h

445

#define PORT_HOTPLUG_STAT(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)

sys/dev/pci/drm/i915/display/intel_display_regs.h

45

#define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)

sys/dev/pci/drm/i915/display/intel_display_regs.h

502

#define GEN3_SDVOB _MMIO(_GEN3_SDVOB)

sys/dev/pci/drm/i915/display/intel_display_regs.h

503

#define GEN3_SDVOC _MMIO(_GEN3_SDVOC)

sys/dev/pci/drm/i915/display/intel_display_regs.h

506

#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)

sys/dev/pci/drm/i915/display/intel_display_regs.h

507

#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)

sys/dev/pci/drm/i915/display/intel_display_regs.h

508

#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)

sys/dev/pci/drm/i915/display/intel_display_regs.h

509

#define PCH_SDVOB _MMIO(0xe1140)

sys/dev/pci/drm/i915/display/intel_display_regs.h

511

#define PCH_HDMIC _MMIO(0xe1150)

sys/dev/pci/drm/i915/display/intel_display_regs.h

512

#define PCH_HDMID _MMIO(0xe1160)

sys/dev/pci/drm/i915/display/intel_display_regs.h

514

#define PORT_DFT_I9XX _MMIO(0x61150)

sys/dev/pci/drm/i915/display/intel_display_regs.h

516

#define PORT_DFT2_G4X(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)

sys/dev/pci/drm/i915/display/intel_display_regs.h

53

#define ILK_GTT_FAULT _MMIO(0x44040) /* ilk/snb */

sys/dev/pci/drm/i915/display/intel_display_regs.h

577

#define VIDEO_DIP_DATA _MMIO(0x61178)

sys/dev/pci/drm/i915/display/intel_display_regs.h

586

#define VIDEO_DIP_CTL _MMIO(0x61170)

sys/dev/pci/drm/i915/display/intel_display_regs.h

624

#define PCH_GTC_CTL _MMIO(0xe7000)

sys/dev/pci/drm/i915/display/intel_display_regs.h

628

#define DP_A _MMIO(0x64000) /* eDP */

sys/dev/pci/drm/i915/display/intel_display_regs.h

629

#define DP_B _MMIO(0x64100)

sys/dev/pci/drm/i915/display/intel_display_regs.h

63

#define DERRMR _MMIO(0x44050)

sys/dev/pci/drm/i915/display/intel_display_regs.h

630

#define DP_C _MMIO(0x64200)

sys/dev/pci/drm/i915/display/intel_display_regs.h

631

#define DP_D _MMIO(0x64300)

sys/dev/pci/drm/i915/display/intel_display_regs.h

632

#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)

sys/dev/pci/drm/i915/display/intel_display_regs.h

633

#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)

sys/dev/pci/drm/i915/display/intel_display_regs.h

634

#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)

sys/dev/pci/drm/i915/display/intel_display_regs.h

86

#define VLV_EIR _MMIO(VLV_DISPLAY_BASE + 0x20b0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

87

#define VLV_EMR _MMIO(VLV_DISPLAY_BASE + 0x20b4)

sys/dev/pci/drm/i915/display/intel_display_regs.h

88

#define VLV_ESR _MMIO(VLV_DISPLAY_BASE + 0x20b8)

sys/dev/pci/drm/i915/display/intel_display_regs.h

885

#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */

sys/dev/pci/drm/i915/display/intel_display_regs.h

915

#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)

sys/dev/pci/drm/i915/display/intel_display_regs.h

919

#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)

sys/dev/pci/drm/i915/display/intel_display_regs.h

986

#define SWF0(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)

sys/dev/pci/drm/i915/display/intel_display_regs.h

987

#define SWF1(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)

sys/dev/pci/drm/i915/display/intel_display_regs.h

988

#define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)

sys/dev/pci/drm/i915/display/intel_display_regs.h

989

#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)

sys/dev/pci/drm/i915/display/intel_display_regs.h

991

#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)

sys/dev/pci/drm/i915/display/intel_dkl_phy_regs.h

202

#define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \

sys/dev/pci/drm/i915/display/intel_dkl_phy_regs.h

29

#define DKL_REG_MMIO(__reg) _MMIO((__reg).reg)

sys/dev/pci/drm/i915/display/intel_dmc.c

1099

dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

277

#define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

287

#define MTL_PIPEDMC_CONTROL _MMIO(0x45250)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

371

_MMIO(_PICK_EVEN_2RANGES((fq_id), INTEL_FLIPQ_PLANE_3, \

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

485

_MMIO(_DMC_REG(i915, dmc_id, _DMC_EVT_HTP_0) + 4 * (handler))

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

490

_MMIO(_DMC_REG(i915, dmc_id, _DMC_EVT_CTL_0) + 4 * (handler))

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

502

#define DMC_SSP_BASE _MMIO(0x8F074)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

503

#define DMC_HTP_SKL _MMIO(0x8F004)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

504

#define DMC_LAST_WRITE _MMIO(0x8F034)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

524

#define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

525

#define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

526

#define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

527

#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

528

#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

529

#define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

531

#define TGL_DMC_DEBUG3 _MMIO(0x101090)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

532

#define DG1_DMC_DEBUG3 _MMIO(0x13415c)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

534

#define DMC_WAKELOCK_CFG _MMIO(0x8F1B0)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

536

#define DMC_WAKELOCK1_CTL _MMIO(0x8F140)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

540

#define DMC_FQ_W2_PTS_CFG_SEL _MMIO(0x8f240)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

551

#define PIPEDMC_FQ_RAM(start_mmioaddr, i) _MMIO((start_mmioaddr) + (i) * 4)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

584

#define PTL_PIPEDMC_EXEC_TIME_LINES(start_mmioaddr) _MMIO((start_mmioaddr) + 0x6b8)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

585

#define PTL_PIPEDMC_END_OF_EXEC_GB(start_mmioaddr) _MMIO((start_mmioaddr) + 0x6c0)

sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h

102

#define XE2LPD_PICA_PW_CTL _MMIO(0x16fe04)

sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h

28

#define VLV_DP_AUX_CH_CTL(aux_ch) _MMIO(VLV_DISPLAY_BASE + \

sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h

38

_MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \

sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h

80

#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, \

sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h

82

#define VLV_DP_AUX_CH_DATA(aux_ch, i) _MMIO(VLV_DISPLAY_BASE + _PORT(aux_ch, _DPA_AUX_CH_DATA1, \

sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h

87

#define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */

sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h

92

_MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

15

#define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

16

#define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

17

#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

25

#define DSB_MMIOCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0xc)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

31

#define DSB_POLLFUNC(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x10)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

37

#define DSB_DEBUG(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x14)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

38

#define DSB_POLLMASK(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x1c)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

39

#define DSB_STATUS(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x24)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

53

#define DSB_INTERRUPT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x28)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

66

#define DSB_CURRENT_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x2c)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

67

#define DSB_RM_TIMEOUT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x30)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

74

#define DSB_RMTIMEOUTREG_CAPTURE(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x34)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

75

#define DSB_PMCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x38)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

79

#define DSB_PMCTRL_2(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x3c)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

84

#define DSB_PF_LN_LOWER(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x40)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

85

#define DSB_PF_LN_UPPER(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x44)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

86

#define DSB_BUFRPT_CNT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x48)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

87

#define DSB_CHICKEN(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0xf0)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

10

#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

11

#define FBC_CONTROL _MMIO(0x3208)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

112

#define ILK_FBC_RT_BASE _MMIO(0x2128)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

116

#define SNB_DPFC_CTL_SA _MMIO(0x100100)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

120

#define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

122

#define IVB_FBC_RT_BASE _MMIO(0x7020)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

123

#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

23

#define FBC_COMMAND _MMIO(0x320c)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

25

#define FBC_STATUS _MMIO(0x3210)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

30

#define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

40

#define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

41

#define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

44

#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

53

#define DPFC_CB_BASE _MMIO(0x3200)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

55

#define DPFC_CONTROL _MMIO(0x3208)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

76

#define DPFC_RECOMP_CTL _MMIO(0x320c)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

81

#define DPFC_STATUS _MMIO(0x3210)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

85

#define DPFC_STATUS2 _MMIO(0x3214)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

88

#define DPFC_FENCE_YOFF _MMIO(0x3218)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

9

#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

90

#define DPFC_CHICKEN _MMIO(0x3224)

sys/dev/pci/drm/i915/display/intel_fdi_regs.h

11

#define FDI_PLL_BIOS_0 _MMIO(0x46000)

sys/dev/pci/drm/i915/display/intel_fdi_regs.h

13

#define FDI_PLL_BIOS_1 _MMIO(0x46004)

sys/dev/pci/drm/i915/display/intel_fdi_regs.h

14

#define FDI_PLL_BIOS_2 _MMIO(0x46008)

sys/dev/pci/drm/i915/display/intel_fdi_regs.h

148

#define FDI_PLL_CTL_1 _MMIO(0xfe000)

sys/dev/pci/drm/i915/display/intel_fdi_regs.h

149

#define FDI_PLL_CTL_2 _MMIO(0xfe004)

sys/dev/pci/drm/i915/display/intel_fdi_regs.h

15

#define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)

sys/dev/pci/drm/i915/display/intel_fdi_regs.h

16

#define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)

sys/dev/pci/drm/i915/display/intel_fdi_regs.h

17

#define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)

sys/dev/pci/drm/i915/display/intel_fdi_regs.h

19

#define FDI_PLL_FREQ_CTL _MMIO(0x46030)

sys/dev/pci/drm/i915/display/intel_gmbus_regs.h

13

#define GPIO(__display, gpio) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5010 + 4 * (gpio))

sys/dev/pci/drm/i915/display/intel_gmbus_regs.h

30

#define GMBUS0(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5100)

sys/dev/pci/drm/i915/display/intel_gmbus_regs.h

40

#define GMBUS1(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5104)

sys/dev/pci/drm/i915/display/intel_gmbus_regs.h

57

#define GMBUS2(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5108)

sys/dev/pci/drm/i915/display/intel_gmbus_regs.h

67

#define GMBUS3(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x510c)

sys/dev/pci/drm/i915/display/intel_gmbus_regs.h

70

#define GMBUS4(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5110)

sys/dev/pci/drm/i915/display/intel_gmbus_regs.h

78

#define GMBUS5(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5120)

sys/dev/pci/drm/i915/display/intel_hdcp_regs.h

14

#define HDCP_KEY_CONF _MMIO(0x66c00)

sys/dev/pci/drm/i915/display/intel_hdcp_regs.h

18

#define HDCP_KEY_STATUS _MMIO(0x66c04)

sys/dev/pci/drm/i915/display/intel_hdcp_regs.h

187

#define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \

sys/dev/pci/drm/i915/display/intel_hdcp_regs.h

238

#define PIPE_HDCP2_STREAM_STATUS(pipe) _MMIO(_PICK((pipe), \

sys/dev/pci/drm/i915/display/intel_hdcp_regs.h

24

#define HDCP_AKSV_LO _MMIO(0x66c10)

sys/dev/pci/drm/i915/display/intel_hdcp_regs.h

25

#define HDCP_AKSV_HI _MMIO(0x66c14)

sys/dev/pci/drm/i915/display/intel_hdcp_regs.h

28

#define HDCP_REP_CTL _MMIO(0x66d00)

sys/dev/pci/drm/i915/display/intel_hdcp_regs.h

59

#define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04)

sys/dev/pci/drm/i915/display/intel_hdcp_regs.h

60

#define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08)

sys/dev/pci/drm/i915/display/intel_hdcp_regs.h

61

#define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C)

sys/dev/pci/drm/i915/display/intel_hdcp_regs.h

62

#define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10)

sys/dev/pci/drm/i915/display/intel_hdcp_regs.h

63

#define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14)

sys/dev/pci/drm/i915/display/intel_hdcp_regs.h

64

#define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4))

sys/dev/pci/drm/i915/display/intel_hdcp_regs.h

65

#define HDCP_SHA_TEXT _MMIO(0x66d18)

sys/dev/pci/drm/i915/display/intel_hdcp_regs.h

74

#define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \

sys/dev/pci/drm/i915/display/intel_hti_regs.h

11

#define HDPORT_STATE _MMIO(0x45050)

sys/dev/pci/drm/i915/display/intel_lvds_regs.h

12

#define LVDS _MMIO(0x61180)

sys/dev/pci/drm/i915/display/intel_lvds_regs.h

62

#define PCH_LVDS _MMIO(0xe1180)

sys/dev/pci/drm/i915/display/intel_mg_phy_regs.h

12

_MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))

sys/dev/pci/drm/i915/display/intel_mg_phy_regs.h

148

#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

10

#define PFIT_CONTROL(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

31

#define PFIT_PGM_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

39

#define PFIT_AUTO_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

17

_MMIO((display)->pps.mmio_base - PPS_BASE + (reg) + (pps_idx) * 0x100)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

102

#define HSW_SRD_STATUS _MMIO(0x64840)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

127

#define HSW_SRD_PERF_CNT _MMIO(0x64844)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

134

#define HSW_SRD_DEBUG _MMIO(0x64860)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

24

#define HSW_SRD_CTL _MMIO(0x64800)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

66

#define EDP_PSR_IMR _MMIO(0x64834)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

67

#define EDP_PSR_IIR _MMIO(0x64838)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

87

#define HSW_SRD_AUX_CTL _MMIO(0x64810)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

97

#define HSW_SRD_AUX_DATA(i) _MMIO(0x64814 + (i) * 4) /* 5 registers */

sys/dev/pci/drm/i915/display/intel_sbi_regs.h

13

#define SBI_ADDR _MMIO(0xC6000)

sys/dev/pci/drm/i915/display/intel_sbi_regs.h

17

#define SBI_DATA _MMIO(0xC6004)

sys/dev/pci/drm/i915/display/intel_sbi_regs.h

19

#define SBI_CTL_STAT _MMIO(0xC6008)

sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h

18

#define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg))

sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h

19

#define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

109

#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

113

#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

219

#define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

223

#define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

227

#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

233

_MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

342

#define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

352

_MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

90

#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */

sys/dev/pci/drm/i915/display/intel_tv_regs.h

12

#define TV_CTL _MMIO(0x68000)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

133

#define TV_CSC_Y _MMIO(0x68010)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

139

#define TV_CSC_Y2 _MMIO(0x68014)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

150

#define TV_CSC_U _MMIO(0x68018)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

156

#define TV_CSC_U2 _MMIO(0x6801c)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

167

#define TV_CSC_V _MMIO(0x68020)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

173

#define TV_CSC_V2 _MMIO(0x68024)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

184

#define TV_CLR_KNOBS _MMIO(0x68028)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

198

#define TV_CLR_LEVEL _MMIO(0x6802c)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

206

#define TV_H_CTL_1 _MMIO(0x68030)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

214

#define TV_H_CTL_2 _MMIO(0x68034)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

224

#define TV_H_CTL_3 _MMIO(0x68038)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

232

#define TV_V_CTL_1 _MMIO(0x6803c)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

243

#define TV_V_CTL_2 _MMIO(0x68040)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

259

#define TV_V_CTL_3 _MMIO(0x68044)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

277

#define TV_V_CTL_4 _MMIO(0x68048)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

291

#define TV_V_CTL_5 _MMIO(0x6804c)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

305

#define TV_V_CTL_6 _MMIO(0x68050)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

319

#define TV_V_CTL_7 _MMIO(0x68054)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

333

#define TV_SC_CTL_1 _MMIO(0x68060)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

355

#define TV_SC_CTL_2 _MMIO(0x68064)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

363

#define TV_SC_CTL_3 _MMIO(0x68068)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

371

#define TV_WIN_POS _MMIO(0x68070)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

379

#define TV_WIN_SIZE _MMIO(0x68074)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

391

#define TV_FILTER_CTL_1 _MMIO(0x68080)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

424

#define TV_FILTER_CTL_2 _MMIO(0x68084)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

440

#define TV_FILTER_CTL_3 _MMIO(0x68088)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

460

#define TV_CC_CONTROL _MMIO(0x68090)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

476

#define TV_CC_DATA _MMIO(0x68094)

sys/dev/pci/drm/i915/display/intel_tv_regs.h

485

#define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */

sys/dev/pci/drm/i915/display/intel_tv_regs.h

486

#define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */

sys/dev/pci/drm/i915/display/intel_tv_regs.h

487

#define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */

sys/dev/pci/drm/i915/display/intel_tv_regs.h

488

#define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */

sys/dev/pci/drm/i915/display/intel_tv_regs.h

82

#define TV_DAC _MMIO(0x68004)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

12

#define DSS_CTL1 _MMIO(0x67400)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

212

#define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

213

#define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

214

#define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

215

#define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

23

#define DSS_CTL2 _MMIO(0x67404)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

237

#define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

238

#define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

239

#define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

240

#define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

263

#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

264

#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

265

#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

266

#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

291

#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

292

#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

293

#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

294

#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

316

#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

317

#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

318

#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

319

#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

341

#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

342

#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

343

#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

344

#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

54

#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

55

#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

58

#define DSCA_PPS(pps) _MMIO(_DSCA_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

59

#define DSCC_PPS(pps) _MMIO(_DSCC_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

81

#define ICL_DSC0_PPS(pipe, pps) _MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4))

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

82

#define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4))

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

83

#define BMG_DSC2_PPS(pipe, pps) _MMIO(_BMG_DSC2_PPS_0(pipe) + ((pps) * 4))

sys/dev/pci/drm/i915/display/intel_vga_regs.h

11

#define VGACNTRL _MMIO(0x71400)

sys/dev/pci/drm/i915/display/intel_vga_regs.h

12

#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)

sys/dev/pci/drm/i915/display/intel_vga_regs.h

13

#define CPU_VGACNTRL _MMIO(0x41000)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

16

_MMIO(_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)))

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

18

_MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)))

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

27

_MMIO(_SEL_FETCH((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

31

#define MBUS_UBOX_CTL _MMIO(0x4503C)

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

32

#define MBUS_BBOX_CTL_S1 _MMIO(0x45040)

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

33

#define MBUS_BBOX_CTL_S2 _MMIO(0x45044)

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

35

#define MBUS_CTL _MMIO(0x4438C)

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

58

#define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

70

#define MTL_LATENCY_LP0_LP1 _MMIO(0x45780)

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

71

#define MTL_LATENCY_LP2_LP3 _MMIO(0x45784)

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

72

#define MTL_LATENCY_LP4_LP5 _MMIO(0x45788)

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

76

#define MTL_LATENCY_SAGV _MMIO(0x4578c)

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

79

#define LNL_PKG_C_LATENCY _MMIO(0x46460)

sys/dev/pci/drm/i915/display/vlv_dsi_pll_regs.h

105

#define BXT_DSI_PLL_ENABLE _MMIO(0x46080)

sys/dev/pci/drm/i915/display/vlv_dsi_pll_regs.h

11

#define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)

sys/dev/pci/drm/i915/display/vlv_dsi_pll_regs.h

13

#define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)

sys/dev/pci/drm/i915/display/vlv_dsi_pll_regs.h

18

#define BXT_MIPI_CLOCK_CTL _MMIO(0x46090)

sys/dev/pci/drm/i915/display/vlv_dsi_pll_regs.h

81

#define BXT_DSI_PLL_CTL _MMIO(0x161000)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

17

#define _MMIO_MIPI(base, port, a, c) _MMIO((base) + _MIPI_PORT(port, a, c))

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

32

#define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

35

#define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054)

sys/dev/pci/drm/i915/gt/agp_intel_gtt.c

200

i915_reg_t hic = _MMIO(I830_HIC);

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

103

#define RING_RESET_CTL(base) _MMIO((base) + 0xd0)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

107

#define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

108

#define RING_BBSTATE(base) _MMIO((base) + 0x110)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

11

#define RING_EXCC(base) _MMIO((base) + 0x28)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

110

#define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

111

#define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

112

#define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

113

#define RING_BBADDR(base) _MMIO((base) + 0x140)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

114

#define RING_BB_OFFSET(base) _MMIO((base) + 0x158)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

115

#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

116

#define CCID(base) _MMIO((base) + 0x180)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

12

#define RING_TAIL(base) _MMIO((base) + 0x30)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

120

#define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

124

#define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

125

#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

126

#define ECOSKPD(base) _MMIO((base) + 0x1d0)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

136

#define BLIT_CCTL(base) _MMIO((base) + 0x204)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

14

#define RING_HEAD(base) _MMIO((base) + 0x34)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

145

#define RING_CSCMDOP(base) _MMIO((base) + 0x20c)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

162

#define RING_PREDICATE_RESULT(base) _MMIO((base) + 0x3b8) /* gen12+ */

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

164

#define MI_PREDICATE_RESULT_2(base) _MMIO((base) + 0x3bc)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

167

#define MI_PREDICATE_SRC0(base) _MMIO((base) + 0x400)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

168

#define MI_PREDICATE_SRC0_UDW(base) _MMIO((base) + 0x400 + 4)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

169

#define MI_PREDICATE_SRC1(base) _MMIO((base) + 0x408)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

170

#define MI_PREDICATE_SRC1_UDW(base) _MMIO((base) + 0x408 + 4)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

171

#define MI_PREDICATE_DATA(base) _MMIO((base) + 0x410)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

172

#define MI_PREDICATE_RESULT(base) _MMIO((base) + 0x418)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

173

#define MI_PREDICATE_RESULT_1(base) _MMIO((base) + 0x41c)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

175

#define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

177

#define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

178

#define RING_ELSP(base) _MMIO((base) + 0x230)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

179

#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

180

#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

181

#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

188

#define RING_CTX_SR_CTL(base) _MMIO((base) + 0x244)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

189

#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

19

#define RING_START(base) _MMIO((base) + 0x38)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

190

#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

191

#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

192

#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

20

#define RING_CTL(base) _MMIO((base) + 0x3c)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

207

#define RING_TIMESTAMP(base) _MMIO((base) + 0x358)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

208

#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

209

#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

210

#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

211

#define RING_PREDICATE_RESULT(base) _MMIO((base) + 0x3b8)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

212

#define MI_PREDICATE_RESULT_2_ENGINE(base) _MMIO((base) + 0x3bc)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

213

#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

232

#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

233

#define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

234

#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

238

#define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

239

#define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

241

#define GEN11_VCS_SFC_FORCED_LOCK(base) _MMIO((base) + 0x88c)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

243

#define GEN11_VCS_SFC_LOCK_STATUS(base) _MMIO((base) + 0x890)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

247

#define GEN11_VECS_SFC_FORCED_LOCK(base) _MMIO((base) + 0x201c)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

249

#define GEN11_VECS_SFC_LOCK_ACK(base) _MMIO((base) + 0x2018)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

251

#define GEN11_VECS_SFC_USAGE(base) _MMIO((base) + 0x2014)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

254

#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

256

#define GEN12_HCP_SFC_LOCK_STATUS(base) _MMIO((base) + 0x2914)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

260

#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

263

#define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

266

#define VDBOX_CGCTL3F1C(base) _MMIO((base) + 0x3f1c)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

32

#define RING_SYNC_0(base) _MMIO((base) + 0x40)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

33

#define RING_SYNC_1(base) _MMIO((base) + 0x44)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

34

#define RING_SYNC_2(base) _MMIO((base) + 0x48)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

47

#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

55

#define RING_MAX_IDLE(base) _MMIO((base) + 0x54)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

56

#define PWRCTX_MAXCNT(base) _MMIO((base) + 0x54)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

58

#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

59

#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

60

#define RING_IPEIR(base) _MMIO((base) + 0x64)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

61

#define RING_IPEHR(base) _MMIO((base) + 0x68)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

62

#define RING_INSTDONE(base) _MMIO((base) + 0x6c)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

63

#define RING_INSTPS(base) _MMIO((base) + 0x70)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

64

#define RING_DMA_FADD(base) _MMIO((base) + 0x78)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

65

#define RING_ACTHD(base) _MMIO((base) + 0x74)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

66

#define RING_HWS_PGA(base) _MMIO((base) + 0x80)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

67

#define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

68

#define IPEIR(base) _MMIO((base) + 0x88)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

69

#define IPEHR(base) _MMIO((base) + 0x8c)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

70

#define RING_ID(base) _MMIO((base) + 0x8c)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

71

#define RING_NOPID(base) _MMIO((base) + 0x94)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

72

#define RING_HWSTAM(base) _MMIO((base) + 0x98)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

73

#define RING_MI_MODE(base) _MMIO((base) + 0x9c)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

80

#define RING_IMR(base) _MMIO((base) + 0xa8)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

81

#define RING_EIR(base) _MMIO((base) + 0xb0)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

82

#define RING_EMR(base) _MMIO((base) + 0xb4)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

83

#define RING_ESR(base) _MMIO((base) + 0xb8)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

84

#define GEN12_STATE_ACK_DEBUG(base) _MMIO((base) + 0xbc)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

85

#define RING_INSTPM(base) _MMIO((base) + 0xc0)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

86

#define RING_CMD_CCTL(base) _MMIO((base) + 0xc4)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

87

#define ACTHD(base) _MMIO((base) + 0xc8)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

88

#define GEN8_R_PWR_CLK_STATE(base) _MMIO((base) + 0xc8)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1776

_MMIO(engine->mmio_base + status));

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

101

#define PWRCTXA _MMIO(0x2088) /* 965GM+ only */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1013

#define GEN11_GLBLINVL _MMIO(0xb404)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1017

#define GEN11_LSN_UNSLCVC _MMIO(0xb43c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1021

#define GUCPMTIMESTAMP _MMIO(0xc3e8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1024

#define GEN9_GFX_MOCS(i) _MMIO(__GEN9_RCS0_MOCS0 + (i) * 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1026

#define GEN9_MFX0_MOCS(i) _MMIO(__GEN9_VCS0_MOCS0 + (i) * 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1028

#define GEN9_MFX1_MOCS(i) _MMIO(__GEN9_VCS1_MOCS0 + (i) * 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1030

#define GEN9_VEBOX_MOCS(i) _MMIO(__GEN9_VECS0_MOCS0 + (i) * 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1032

#define GEN9_BLT_MOCS(i) _MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1034

#define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1036

#define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

104

#define FF_SLICE_CHICKEN _MMIO(0x2088)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1040

#define GEN12_RING_FAULT_REG _MMIO(0xcec4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1042

#define XELPMP_RING_FAULT_REG _MMIO(0xcec4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1045

#define GEN12_GFX_TLB_INV_CR _MMIO(0xced8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1047

#define GEN12_VD_TLB_INV_CR _MMIO(0xcedc)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1049

#define GEN12_VE_TLB_INV_CR _MMIO(0xcee0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1051

#define GEN12_BLT_TLB_INV_CR _MMIO(0xcee4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1053

#define GEN12_COMPCTX_TLB_INV_CR _MMIO(0xcf04)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1055

#define XELPMP_GSC_TLB_INV_CR _MMIO(0xcf04) /* media GT only */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1059

#define XELPMP_GSC_MOD_CTRL _MMIO(0xcf30) /* media GT only */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1061

#define XELPMP_VDBX_MOD_CTRL _MMIO(0xcf34)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1063

#define XELPMP_VEBX_MOD_CTRL _MMIO(0xcf38)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1075

#define GEN12_GAM_DONE _MMIO(0xcf68)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1077

#define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1084

#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1086

#define GEN7_ROW_INSTDONE _MMIO(0xe164)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1092

#define HSW_HALF_SLICE_CHICKEN3 _MMIO(0xe184)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

111

#define _3D_CHICKEN2 _MMIO(0x208c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1139

#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1153

#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

118

#define _3D_CHICKEN3 _MMIO(0x2090)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1195

#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1201

#define GEN11_MFX2_MOCS(i) _MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1203

#define CRSTANDVID _MMIO(0x11100)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1204

#define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1207

#define VIDFREQ_BASE _MMIO(0x11110)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1208

#define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1209

#define VIDFREQ2 _MMIO(0x11114)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1210

#define VIDFREQ3 _MMIO(0x11118)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1211

#define VIDFREQ4 _MMIO(0x1111c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1223

#define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1232

#define MEMSWCTL _MMIO(0x11170) /* Ironlake only */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1247

#define MEMIHYST _MMIO(0x1117c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1248

#define MEMINTREN _MMIO(0x11180) /* 16 bits */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1258

#define MEMINTRSTR _MMIO(0x11182) /* 16 bits */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

126

#define GEN2_INSTDONE _MMIO(0x2090)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

127

#define NOPID _MMIO(0x2094)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1278

#define MEMINTRSTS _MMIO(0x11184)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

128

#define HWSTAM _MMIO(0x2098)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1287

#define MEMMODECTL _MMIO(0x11190)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

130

#define WAIT_FOR_RC6_EXIT _MMIO(0x20cc)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1304

#define RCBMAXAVG _MMIO(0x1119c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1305

#define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1317

#define MEMSTAT_CTG _MMIO(0x111a0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1318

#define RCBMINAVG _MMIO(0x111a0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1319

#define RCUPEI _MMIO(0x111b0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1320

#define RCDNEI _MMIO(0x111b4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1321

#define RSTDBYCTL _MMIO(0x111b8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1365

#define VIDCTL _MMIO(0x111c0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1366

#define VIDSTS _MMIO(0x111c8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1367

#define VIDSTART _MMIO(0x111cc) /* 8 bits */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1368

#define MEMSTAT_ILK _MMIO(0x111f8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1378

#define PMMISC _MMIO(0x11214)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1380

#define SDEW _MMIO(0x1124c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1381

#define CSIEW0 _MMIO(0x11250)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1382

#define CSIEW1 _MMIO(0x11254)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1383

#define CSIEW2 _MMIO(0x11258)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1384

#define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1385

#define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1386

#define MCHAFE _MMIO(0x112c0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1387

#define CSIEC _MMIO(0x112e0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1388

#define DMIEC _MMIO(0x112e4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1389

#define DDREC _MMIO(0x112e8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1390

#define PEG0EC _MMIO(0x112ec)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1391

#define PEG1EC _MMIO(0x112f0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1392

#define GFXEC _MMIO(0x112f4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1393

#define INTTOEXT_BASE_ILK _MMIO(0x11300)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1394

#define RPPREVBSYTUPAVG _MMIO(0x113b8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1395

#define RCPREVBSYTUPAVG _MMIO(0x113b8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1396

#define RCPREVBSYTDNAVG _MMIO(0x113bc)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1397

#define RPPREVBSYTDNAVG _MMIO(0x113bc)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1398

#define ECR _MMIO(0x11600)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1402

#define OGW0 _MMIO(0x11608)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1403

#define OGW1 _MMIO(0x1160c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1404

#define EG0 _MMIO(0x11610)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1405

#define EG1 _MMIO(0x11614)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1406

#define EG2 _MMIO(0x11618)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1407

#define EG3 _MMIO(0x1161c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1408

#define EG4 _MMIO(0x11620)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1409

#define EG5 _MMIO(0x11624)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1410

#define EG6 _MMIO(0x11628)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1411

#define EG7 _MMIO(0x1162c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1412

#define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1413

#define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1414

#define LCFUSE02 _MMIO(0x116c0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1417

#define GAC_ECO_BITS _MMIO(0x14090)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1422

#define GEN12_RCU_MODE _MMIO(0x14800)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1426

#define XEHP_CCS_MODE _MMIO(0x14804)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1431

#define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1439

#define BCS_SWCTRL _MMIO(0x22200)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1443

#define GAB_CTL _MMIO(0x24000)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1446

#define GEN6_PMISR _MMIO(0x44020)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1447

#define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1448

#define GEN6_PMIIR _MMIO(0x44028)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1449

#define GEN6_PMIER _MMIO(0x4402c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1471

#define GEN7_GT_SCRATCH(i) _MMIO(0x4f100 + (i) * 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1474

#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1477

#define GTFIFODBG _MMIO(0x120000)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1488

#define GTFIFOCTL _MMIO(0x120008)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1494

#define FORCEWAKE_MT_ACK _MMIO(0x130040)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1495

#define FORCEWAKE_ACK_HSW _MMIO(0x130044)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1496

#define FORCEWAKE_ACK_GT_GEN9 _MMIO(0x130044)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1500

#define FORCEWAKE_ACK _MMIO(0x130090)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1501

#define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1505

#define VLV_GTLC_PW_STATUS _MMIO(0x130094)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1510

#define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1513

#define FORCEWAKE_VLV _MMIO(0x1300b0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1514

#define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1515

#define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1516

#define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1518

#define MTL_MEDIA_MC6 _MMIO(0x138048)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

152

#define GEN6_GT_MODE _MMIO(0x20d0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1520

#define MTL_GT_ACTIVITY_FACTOR _MMIO(0x138010)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1523

#define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1526

#define GEN6_GT_CORE_STATUS _MMIO(0x138060)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1534

#define GEN8_GT_SLICE_INFO _MMIO(0x138064)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1537

#define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1538

#define VLV_COUNTER_CONTROL _MMIO(0x138104)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1544

#define GEN6_GT_GFX_RC6 _MMIO(0x138108)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1545

#define VLV_GT_MEDIA_RC6 _MMIO(0x13810c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1547

#define GEN6_GT_GFX_RC6p _MMIO(0x13810c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1548

#define GEN6_GT_GFX_RC6pp _MMIO(0x138110)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1549

#define VLV_RENDER_C0_COUNT _MMIO(0x138118)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1550

#define VLV_MEDIA_C0_COUNT _MMIO(0x13811c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1552

#define PCU_PWM_FAN_SPEED _MMIO(0x138140)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1554

#define GEN12_RPSTAT1 _MMIO(0x1381b4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1558

#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1584

#define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1585

#define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1586

#define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1589

#define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1590

#define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1591

#define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1592

#define GEN12_CCS_RSVD_INTR_ENABLE _MMIO(0x190048)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1594

#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1608

#define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

161

#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20d4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1610

#define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1611

#define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1612

#define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1613

#define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1614

#define GEN12_VCS4_VCS5_INTR_MASK _MMIO(0x1900b0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1615

#define GEN12_VCS6_VCS7_INTR_MASK _MMIO(0x1900b4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1616

#define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1617

#define GEN12_VECS2_VECS3_INTR_MASK _MMIO(0x1900d4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1618

#define GEN12_HECI2_RSVD_INTR_MASK _MMIO(0x1900e4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1619

#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1620

#define MTL_GUC_MGUC_INTR_MASK _MMIO(0x1900e8) /* MTL+ */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1621

#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1622

#define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1623

#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1624

#define GEN12_CCS0_CCS1_INTR_MASK _MMIO(0x190100)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1625

#define GEN12_CCS2_CCS3_INTR_MASK _MMIO(0x190104)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1626

#define XEHPC_BCS1_BCS2_INTR_MASK _MMIO(0x190110)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1627

#define XEHPC_BCS3_BCS4_INTR_MASK _MMIO(0x190114)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1628

#define XEHPC_BCS5_BCS6_INTR_MASK _MMIO(0x190118)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1629

#define XEHPC_BCS7_BCS8_INTR_MASK _MMIO(0x19011c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1631

#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

164

#define GEN12_CS_DEBUG_MODE2 _MMIO(0x20d8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

167

#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

170

#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

175

#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

177

#define GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON _MMIO(0x20ec)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

181

#define GEN8_STATE_ACK _MMIO(0x20f0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

182

#define GEN9_STATE_ACK_SLICE1 _MMIO(0x20f8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

183

#define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

192

#define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

202

#define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

22

#define PERF_REG(offset) _MMIO(offset)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

220

#define CXT_SIZE _MMIO(0x21a0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

229

#define GEN7_CXT_SIZE _MMIO(0x21a8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

239

#define HSW_MI_PREDICATE_RESULT_2 _MMIO(0x2214)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

241

#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

244

#define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

245

#define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

247

#define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

248

#define GEN6_RCS_PWR_FSM _MMIO(0x22ac)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

25

#define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

250

#define HS_INVOCATION_COUNT _MMIO(0x2300)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

251

#define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

252

#define DS_INVOCATION_COUNT _MMIO(0x2308)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

253

#define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

254

#define IA_VERTICES_COUNT _MMIO(0x2310)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

255

#define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

256

#define IA_PRIMITIVES_COUNT _MMIO(0x2318)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

257

#define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

258

#define VS_INVOCATION_COUNT _MMIO(0x2320)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

259

#define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

260

#define GS_INVOCATION_COUNT _MMIO(0x2328)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

261

#define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

262

#define GS_PRIMITIVES_COUNT _MMIO(0x2330)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

263

#define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

264

#define CL_INVOCATION_COUNT _MMIO(0x2338)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

265

#define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

266

#define CL_PRIMITIVES_COUNT _MMIO(0x2340)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

267

#define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

268

#define PS_INVOCATION_COUNT _MMIO(0x2348)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

269

#define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

270

#define PS_DEPTH_COUNT _MMIO(0x2350)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

271

#define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

272

#define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

273

#define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

274

#define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

275

#define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

276

#define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

277

#define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

278

#define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

279

#define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

280

#define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

282

#define GFX_MODE _MMIO(0x2520)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

284

#define GEN8_CS_CHICKEN1 _MMIO(0x2580)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

292

#define DRAW_WATERMARK _MMIO(0x26c0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

295

#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

297

#define RENDER_HWS_PGA_GEN7 _MMIO(0x4080)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

299

#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

303

#define GAM_ECOCHK _MMIO(0x4090)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

316

#define GEN8_RING_FAULT_REG _MMIO(0x4094)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

32

#define RPM_CONFIG0 _MMIO(0xd00)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

321

#define RING_FAULT_REG(engine) _MMIO(_PICK((engine)->class, \

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

333

#define ERROR_GEN6 _MMIO(0x40a0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

335

#define DONE_REG _MMIO(0x40b0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

336

#define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

337

#define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

338

#define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

339

#define BSD_HWS_PGA_GEN7 _MMIO(0x4180)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

341

#define GEN12_CCS_AUX_INV _MMIO(0x4208)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

342

#define GEN12_VD0_AUX_INV _MMIO(0x4218)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

343

#define GEN12_VE0_AUX_INV _MMIO(0x4238)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

344

#define GEN12_BCS0_AUX_INV _MMIO(0x4248)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

346

#define GEN8_RTCR _MMIO(0x4260)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

347

#define GEN8_M1TCR _MMIO(0x4264)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

348

#define GEN8_M2TCR _MMIO(0x4268)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

349

#define GEN8_BTCR _MMIO(0x426c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

350

#define GEN8_VTCR _MMIO(0x4270)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

352

#define BLT_HWS_PGA_GEN7 _MMIO(0x4280)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

354

#define GEN12_VD2_AUX_INV _MMIO(0x4298)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

355

#define GEN12_CCS0_AUX_INV _MMIO(0x42c8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

358

#define VEBOX_HWS_PGA_GEN7 _MMIO(0x4380)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

360

#define GEN12_AUX_ERR_DBG _MMIO(0x43f4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

362

#define GEN7_TLB_RD_ADDR _MMIO(0x4700)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

364

#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

369

#define XELPMP_PAT_INDEX(index) _MMIO(_PAT_INDEX(index))

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

377

#define GAMTARBMODE _MMIO(0x4a08)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

381

#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

384

#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

389

#define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

390

#define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

394

#define GEN11_GACB_PERF_CTRL _MMIO(0x4b80)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

400

#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

406

#define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

411

#define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

412

#define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

414

#define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

415

#define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

420

#define GEN9_WM_CHICKEN3 _MMIO(0x5588)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

43

#define RPM_CONFIG1 _MMIO(0xd04)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

433

#define GEN12_FF_MODE2 _MMIO(0x6604)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

442

#define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

446

#define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

452

#define GEN7_GT_MODE _MMIO(0x7008)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

457

#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

461

#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

467

#define HIZ_CHICKEN _MMIO(0x7018)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

47

#define RCP_CONFIG _MMIO(0xd08)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

475

#define GEN8_L3CNTLREG _MMIO(0x7034)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

484

#define GEN7_SC_INSTDONE _MMIO(0x7100)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

485

#define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

486

#define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

489

#define HDC_CHICKEN0 _MMIO(0x7300)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

49

#define RC6_LOCATION _MMIO(0xd40)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

497

#define COMMON_SLICE_CHICKEN4 _MMIO(0x7300)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

500

#define GEN8_HDC_CHICKEN1 _MMIO(0x7304)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

502

#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

509

#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

51

#define RC6_CTX_BASE _MMIO(0xd48)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

514

#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

518

#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

522

#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

523

#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

525

#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

526

#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

537

#define VF_PREEMPTION _MMIO(0x83a4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

54

#define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0xd50 + (n) * 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

540

#define VFG_PREEMPTION_CHICKEN _MMIO(0x83b4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

543

#define GEN8_RC6_CTX_INFO _MMIO(0x8504)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

545

#define GEN12_SQCNT1 _MMIO(0x8718)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

55

#define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0xd70 + (n) * 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

553

#define MTL_GSCPSMI_BASEADDR_LSB _MMIO(0x880c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

554

#define MTL_GSCPSMI_BASEADDR_MSB _MMIO(0x8810)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

556

#define HSW_IDICR _MMIO(0x9008)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

559

#define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

56

#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

567

#define VLV_G3DCTL _MMIO(0x9024)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

568

#define VLV_GSCKGCTL _MMIO(0x9028)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

57

#define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0xd88)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

571

#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

574

#define FBC_LLC_READ_CTRL _MMIO(0x9044)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

577

#define GEN6_MBCTL _MMIO(0x907c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

585

#define XEHP_FUSE4 _MMIO(0x9114)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

587

#define GEN10_MIRROR_FUSE3 _MMIO(0x9118)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

59

#define FORCEWAKE_ACK_GSC _MMIO(0xdf8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

594

#define HSW_PAVP_FUSE1 _MMIO(0x911c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

60

#define FORCEWAKE_ACK_GT_MTL _MMIO(0xdfc)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

601

#define GEN8_FUSE2 _MMIO(0x9120)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

608

#define GEN8_EU_DISABLE0 _MMIO(0x9134)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

609

#define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

610

#define GEN11_EU_DISABLE _MMIO(0x9134)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

614

#define XEHP_EU_ENABLE _MMIO(0x9134)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

617

#define GEN8_EU_DISABLE1 _MMIO(0x9138)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

62

#define GMD_ID_GRAPHICS _MMIO(0xd8c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

621

#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

624

#define GEN8_EU_DISABLE2 _MMIO(0x913c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

627

#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

628

#define GEN12_GT_GEOMETRY_DSS_ENABLE _MMIO(0x913c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

63

#define GMD_ID_MEDIA _MMIO(MTL_MEDIA_GSI_BASE + 0xd8c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

630

#define GEN10_EU_DISABLE3 _MMIO(0x9140)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

632

#define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

636

#define GEN12_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

637

#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT _MMIO(0x9148)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

639

#define GEN6_UCGCTL1 _MMIO(0x9400)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

645

#define GEN6_UCGCTL2 _MMIO(0x9404)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

65

#define MCFG_MCR_SELECTOR _MMIO(0xfd0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

653

#define GEN6_UCGCTL3 _MMIO(0x9408)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

656

#define GEN7_UCGCTL4 _MMIO(0x940c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

66

#define MTL_STEER_SEMAPHORE _MMIO(0xfd0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

660

#define GEN6_RCGCTL1 _MMIO(0x9410)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

661

#define GEN6_RCGCTL2 _MMIO(0x9414)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

663

#define GEN6_GDRST _MMIO(0x941c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

67

#define MTL_MCR_SELECTOR _MMIO(0xfd4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

68

#define SF_MCR_SELECTOR _MMIO(0xfd8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

69

#define GEN8_MCR_SELECTOR _MMIO(0xfdc)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

70

#define GAM_MCR_SELECTOR _MMIO(0xfe0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

704

#define GEN6_RSTCTL _MMIO(0x9420)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

706

#define GEN7_MISCCPCTL _MMIO(0x9424)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

713

#define GEN8_UCGCTL6 _MMIO(0x9430)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

718

#define UNSLCGCTL9430 _MMIO(0x9430)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

721

#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

728

#define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

737

#define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

754

#define MICRO_BP0_0 _MMIO(0x9800)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

755

#define MICRO_BP0_2 _MMIO(0x9804)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

756

#define MICRO_BP0_1 _MMIO(0x9808)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

757

#define MICRO_BP1_0 _MMIO(0x980c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

758

#define MICRO_BP1_2 _MMIO(0x9810)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

759

#define MICRO_BP1_1 _MMIO(0x9814)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

760

#define MICRO_BP2_0 _MMIO(0x9818)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

761

#define MICRO_BP2_2 _MMIO(0x981c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

762

#define MICRO_BP2_1 _MMIO(0x9820)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

763

#define MICRO_BP3_0 _MMIO(0x9824)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

764

#define MICRO_BP3_2 _MMIO(0x9828)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

765

#define MICRO_BP3_1 _MMIO(0x982c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

766

#define MICRO_BP_TRIGGER _MMIO(0x9830)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

767

#define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

768

#define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

769

#define MICRO_BP_FIRED_ARMED _MMIO(0x983c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

771

#define GEN6_GFXPAUSE _MMIO(0xa000)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

772

#define GEN6_RPNSWREQ _MMIO(0xa008)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

783

#define GEN6_RC_VIDEO_FREQ _MMIO(0xa00c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

793

#define GEN6_RP_DOWN_TIMEOUT _MMIO(0xa010)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

794

#define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xa014)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

795

#define GEN6_RPSTAT1 _MMIO(0xa01c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

799

#define GEN6_RP_CONTROL _MMIO(0xa024)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

816

#define GEN6_RP_UP_THRESHOLD _MMIO(0xa02c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

817

#define GEN6_RP_DOWN_THRESHOLD _MMIO(0xa030)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

818

#define GEN6_RP_CUR_UP_EI _MMIO(0xa050)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

821

#define GEN6_RP_CUR_UP _MMIO(0xa054)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

823

#define GEN6_RP_PREV_UP _MMIO(0xa058)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

824

#define GEN6_RP_CUR_DOWN_EI _MMIO(0xa05c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

826

#define GEN6_RP_CUR_DOWN _MMIO(0xa060)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

827

#define GEN6_RP_PREV_DOWN _MMIO(0xa064)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

828

#define GEN6_RP_UP_EI _MMIO(0xa068)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

829

#define GEN6_RP_DOWN_EI _MMIO(0xa06c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

83

#define IPEIR_I965 _MMIO(0x2064)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

830

#define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xa070)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

831

#define GEN6_RPDEUHWTC _MMIO(0xa080)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

832

#define GEN6_RPDEUC _MMIO(0xa084)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

833

#define GEN6_RPDEUCSW _MMIO(0xa088)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

834

#define GEN6_RC_CONTROL _MMIO(0xa090)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

835

#define GEN6_RC_STATE _MMIO(0xa094)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

838

#define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xa098)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

839

#define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xa09c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

84

#define IPEHR_I965 _MMIO(0x2068)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

840

#define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xa0a0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

841

#define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xa0a0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

842

#define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xa0a8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

843

#define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xa0ac)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

844

#define GEN6_RC_SLEEP _MMIO(0xa0b0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

845

#define GEN6_RCUBMABDTMR _MMIO(0xa0b0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

846

#define GEN6_RC1e_THRESHOLD _MMIO(0xa0b4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

847

#define GEN6_RC6_THRESHOLD _MMIO(0xa0b8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

848

#define GEN6_RC6p_THRESHOLD _MMIO(0xa0bc)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

849

#define VLV_RCEDATA _MMIO(0xa0bc)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

850

#define GEN6_RC6pp_THRESHOLD _MMIO(0xa0c0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

851

#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xa0c4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

852

#define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xa0c8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

854

#define GEN6_PMINTRMSK _MMIO(0xa168)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

858

#define GEN8_MISC_CTRL0 _MMIO(0xa180)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

860

#define ECOBUS _MMIO(0xa180)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

863

#define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

864

#define FORCEWAKE_GT_GEN9 _MMIO(0xa188)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

865

#define FORCEWAKE _MMIO(0xa18c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

867

#define VLV_SPAREG2H _MMIO(0xa194)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

869

#define GEN9_PG_ENABLE _MMIO(0xa210)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

876

#define GEN8_PUSHBUS_CONTROL _MMIO(0xa248)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

877

#define GEN8_PUSHBUS_ENABLE _MMIO(0xa250)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

878

#define GEN8_PUSHBUS_SHIFT _MMIO(0xa25c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

881

#define CTC_MODE _MMIO(0xa26c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

888

#define MSG_IDLE_CS _MMIO(0x8000)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

889

#define MSG_IDLE_VCS0 _MMIO(0x8004)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

890

#define MSG_IDLE_VCS1 _MMIO(0x8008)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

891

#define MSG_IDLE_BCS _MMIO(0x800C)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

892

#define MSG_IDLE_VECS0 _MMIO(0x8010)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

893

#define MSG_IDLE_VCS2 _MMIO(0x80C0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

894

#define MSG_IDLE_VCS3 _MMIO(0x80C4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

895

#define MSG_IDLE_VCS4 _MMIO(0x80C8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

896

#define MSG_IDLE_VCS5 _MMIO(0x80CC)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

897

#define MSG_IDLE_VCS6 _MMIO(0x80D0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

898

#define MSG_IDLE_VCS7 _MMIO(0x80D4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

899

#define MSG_IDLE_VECS1 _MMIO(0x80D8)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

900

#define MSG_IDLE_VECS2 _MMIO(0x80DC)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

901

#define MSG_IDLE_VECS3 _MMIO(0x80E0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

905

#define RC_PSMI_CTRL_GSCCS _MMIO(0x11a050)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

907

#define PWRCTX_MAXCNT_GSCCS _MMIO(0x11a054)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

909

#define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

91

#define INSTPS _MMIO(0x2070) /* 965+ only */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

910

#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

912

#define VLV_PWRDWNUPCTL _MMIO(0xa294)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

914

#define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xa2a0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

918

#define MISC_STATUS0 _MMIO(0xa500)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

919

#define MISC_STATUS1 _MMIO(0xa504)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

92

#define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

921

#define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

922

#define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

924

#define FORCEWAKE_REQ_GSC _MMIO(0xa618)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

926

#define CHV_POWER_SS0_SIG1 _MMIO(0xa720)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

927

#define CHV_POWER_SS0_SIG2 _MMIO(0xa724)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

928

#define CHV_POWER_SS1_SIG1 _MMIO(0xa728)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

93

#define ACTHD_I965 _MMIO(0x2074)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

933

#define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

936

#define GEN7_SARCHKMD _MMIO(0xb000)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

94

#define HWS_PGA _MMIO(0x2080)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

940

#define GEN8_GARBCNTL _MMIO(0xb004)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

947

#define GEN9_SCRATCH_LNCF1 _MMIO(0xb008)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

950

#define GEN7_L3SQCREG1 _MMIO(0xb010)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

953

#define GEN7_L3CNTLREG1 _MMIO(0xb01c)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

957

#define GEN7_L3CNTLREG2 _MMIO(0xb020)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

960

#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

964

#define GEN7_L3CNTLREG3 _MMIO(0xb024)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

966

#define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xb030)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

969

#define GEN7_L3SQCREG4 _MMIO(0xb034)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

972

#define HSW_SCRATCH1 _MMIO(0xb038)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

975

#define GEN7_L3LOG(slice, i) _MMIO(0xb070 + (slice) * 0x200 + (i) * 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

98

#define _3D_CHICKEN _MMIO(0x2084)

sys/dev/pci/drm/i915/gt/intel_gtt.c

558

fw = intel_uncore_forcewake_for_reg(gt->uncore, _MMIO(XEHP_PAT_INDEX(0).reg),

sys/dev/pci/drm/i915/gt/intel_mocs.c

563

intel_uncore_write_fw(uncore, _MMIO(addr + i * 4), mocs);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2042

whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2045

whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2048

whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

978

{ _MMIO(0xb118), 9 }, /* GEN8_L3SQCREG4 */

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

63

return _MMIO(guc->send_regs.base + 4 * i);

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

266

ext->reg = _MMIO(i915_mmio_reg_offset(extlist->reg));

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

103

#define GUC_SEND_INTERRUPT _MMIO(0xc4c8)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

105

#define GEN11_GUC_HOST_INTERRUPT _MMIO(0x1901f0)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

106

#define MEDIA_GUC_HOST_INTERRUPT _MMIO(0x190304)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

108

#define GEN12_GUC_SEM_INTR_ENABLES _MMIO(0xc71c)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

124

#define GEN8_DRBREGL(x) _MMIO(0x1000 + (x) * 8)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

126

#define GEN8_DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

128

#define GEN12_DIST_DBS_POPULATED _MMIO(0xd08)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

133

#define DE_GUCRMR _MMIO(0x44054)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

135

#define GUC_BCS_RCS_IER _MMIO(0xC550)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

136

#define GUC_VCS2_VCS1_IER _MMIO(0xC554)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

137

#define GUC_WD_VECS_IER _MMIO(0xC558)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

138

#define GUC_PM_P24C_IER _MMIO(0xC55C)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

16

#define GUC_STATUS _MMIO(0xc000)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

33

#define GUC_HEADER_INFO _MMIO(0xc014)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

35

#define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

38

#define GEN11_SOFT_SCRATCH(n) _MMIO(0x190240 + (n) * 4)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

39

#define MEDIA_SOFT_SCRATCH(n) _MMIO(0x190310 + (n) * 4)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

42

#define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

45

#define DMA_ADDR_0_LOW _MMIO(0xc300)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

46

#define DMA_ADDR_0_HIGH _MMIO(0xc304)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

47

#define DMA_ADDR_1_LOW _MMIO(0xc308)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

48

#define DMA_ADDR_1_HIGH _MMIO(0xc30c)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

51

#define DMA_COPY_SIZE _MMIO(0xc310)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

52

#define DMA_CTRL _MMIO(0xc314)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

56

#define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

62

#define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

64

#define HUC_STATUS2 _MMIO(0xD3B0)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

67

#define GEN11_HUC_KERNEL_LOAD_INFO _MMIO(0xC1DC)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

70

#define GUC_WOPCM_SIZE _MMIO(0xc050)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

75

#define GEN8_GT_PM_CONFIG _MMIO(0x138140)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

76

#define GEN9LP_GT_PM_CONFIG _MMIO(0x138140)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

77

#define GEN9_GT_PM_CONFIG _MMIO(0x13816c)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

80

#define GEN8_GTCR _MMIO(0x4274)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

83

#define GEN12_GUC_TLB_INV_CR _MMIO(0xcee8)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

86

#define GUC_ARAT_C6DIS _MMIO(0xA178)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

88

#define GUC_SHIM_CONTROL _MMIO(0xc064)

sys/dev/pci/drm/i915/gt/uc/intel_guc_reg.h

98

#define GUC_SHIM_CONTROL2 _MMIO(0xc068)

sys/dev/pci/drm/i915/gvt/cmd_parser.c

857

return i915_mmio_reg_equal(_MMIO(offset), GEN8_RING_PDP_UDW(base, 0));

sys/dev/pci/drm/i915/gvt/debugfs.c

65

preg = intel_uncore_read_notrace(gvt->gt->uncore, _MMIO(offset));

sys/dev/pci/drm/i915/gvt/handlers.c

1986

intel_uncore_read(gvt->gt->uncore, _MMIO(offset));

sys/dev/pci/drm/i915/gvt/handlers.c

2225

#define RING_REG(base) _MMIO((base) + 0x28)

sys/dev/pci/drm/i915/gvt/handlers.c

2229

#define RING_REG(base) _MMIO((base) + 0x134)

sys/dev/pci/drm/i915/gvt/handlers.c

2233

#define RING_REG(base) _MMIO((base) + 0x6c)

sys/dev/pci/drm/i915/gvt/handlers.c

2238

MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2240

MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2249

#define RING_REG(base) _MMIO((base) + 0x29c)

sys/dev/pci/drm/i915/gvt/handlers.c

2269

MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2271

MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2273

MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2276

MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2282

MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2283

MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2284

MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2285

MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2286

MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2287

MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2288

MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2289

MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2334

MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);

sys/dev/pci/drm/i915/gvt/handlers.c

2335

MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);

sys/dev/pci/drm/i915/gvt/handlers.c

2347

MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2348

MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2349

MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2350

MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2351

MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2352

MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2388

MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2389

MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2390

MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2391

MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2418

MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2419

MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2420

MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2421

MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2422

MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2424

MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2425

MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2426

MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2427

MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2429

MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2430

MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2444

MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);

sys/dev/pci/drm/i915/gvt/handlers.c

2445

MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);

sys/dev/pci/drm/i915/gvt/handlers.c

2446

MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);

sys/dev/pci/drm/i915/gvt/handlers.c

2447

MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);

sys/dev/pci/drm/i915/gvt/handlers.c

2448

MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);

sys/dev/pci/drm/i915/gvt/handlers.c

2449

MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2453

MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2454

MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2455

MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2458

MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2459

MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2460

MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2461

MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2529

#define RING_REG(base) _MMIO((base) + 0xd0)

sys/dev/pci/drm/i915/gvt/handlers.c

2535

#define RING_REG(base) _MMIO((base) + 0x230)

sys/dev/pci/drm/i915/gvt/handlers.c

2539

#define RING_REG(base) _MMIO((base) + 0x234)

sys/dev/pci/drm/i915/gvt/handlers.c

2544

#define RING_REG(base) _MMIO((base) + 0x244)

sys/dev/pci/drm/i915/gvt/handlers.c

2548

#define RING_REG(base) _MMIO((base) + 0x370)

sys/dev/pci/drm/i915/gvt/handlers.c

2552

#define RING_REG(base) _MMIO((base) + 0x3a0)

sys/dev/pci/drm/i915/gvt/handlers.c

2558

#define RING_REG(base) _MMIO((base) + 0x270)

sys/dev/pci/drm/i915/gvt/handlers.c

2572

MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2573

MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2575

MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2576

MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2578

MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,

sys/dev/pci/drm/i915/gvt/handlers.c

2581

MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2583

MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2585

MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2586

MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2588

MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2590

MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2592

MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2593

MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2594

MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2595

MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2596

MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2597

MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2598

MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2599

MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2600

MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2601

MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2755

MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,

sys/dev/pci/drm/i915/gvt/handlers.c

2761

#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)

sys/dev/pci/drm/i915/gvt/handlers.c

2771

MMIO_DFH(_MMIO(0xe4cc), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2807

MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

2922

block->offset = _MMIO(offset);

sys/dev/pci/drm/i915/gvt/handlers.c

3233

intel_uncore_write(&dev_priv->uncore, _MMIO(offset), vgpu_vreg(vgpu, offset));

sys/dev/pci/drm/i915/gvt/handlers.c

70

#define PCH_PP_STATUS _MMIO(0xc7200)

sys/dev/pci/drm/i915/gvt/handlers.c

71

#define PCH_PP_CONTROL _MMIO(0xc7204)

sys/dev/pci/drm/i915/gvt/handlers.c

72

#define PCH_PP_ON_DELAYS _MMIO(0xc7208)

sys/dev/pci/drm/i915/gvt/handlers.c

73

#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)

sys/dev/pci/drm/i915/gvt/handlers.c

733

_MMIO(0xd80),

sys/dev/pci/drm/i915/gvt/handlers.c

74

#define PCH_PP_DIVISOR _MMIO(0xc7210)

sys/dev/pci/drm/i915/gvt/handlers.c

740

_MMIO(0x2690),

sys/dev/pci/drm/i915/gvt/handlers.c

741

_MMIO(0x2694),

sys/dev/pci/drm/i915/gvt/handlers.c

742

_MMIO(0x2698),

sys/dev/pci/drm/i915/gvt/handlers.c

743

_MMIO(0x2754),

sys/dev/pci/drm/i915/gvt/handlers.c

744

_MMIO(0x28a0),

sys/dev/pci/drm/i915/gvt/handlers.c

745

_MMIO(0x4de0),

sys/dev/pci/drm/i915/gvt/handlers.c

746

_MMIO(0x4de4),

sys/dev/pci/drm/i915/gvt/handlers.c

747

_MMIO(0x4dfc),

sys/dev/pci/drm/i915/gvt/handlers.c

749

_MMIO(0x7014),

sys/dev/pci/drm/i915/gvt/handlers.c

752

_MMIO(0x7700),

sys/dev/pci/drm/i915/gvt/handlers.c

753

_MMIO(0x7704),

sys/dev/pci/drm/i915/gvt/handlers.c

754

_MMIO(0x7708),

sys/dev/pci/drm/i915/gvt/handlers.c

755

_MMIO(0x770c),

sys/dev/pci/drm/i915/gvt/handlers.c

756

_MMIO(0x83a8),

sys/dev/pci/drm/i915/gvt/handlers.c

757

_MMIO(0xb110),

sys/dev/pci/drm/i915/gvt/handlers.c

758

_MMIO(0xb118),

sys/dev/pci/drm/i915/gvt/handlers.c

759

_MMIO(0xe100),

sys/dev/pci/drm/i915/gvt/handlers.c

760

_MMIO(0xe18c),

sys/dev/pci/drm/i915/gvt/handlers.c

761

_MMIO(0xe48c),

sys/dev/pci/drm/i915/gvt/handlers.c

762

_MMIO(0xe5f4),

sys/dev/pci/drm/i915/gvt/handlers.c

763

_MMIO(0x64844),

sys/dev/pci/drm/i915/gvt/mmio_context.c

120

{RCS0, _MMIO(0xb118), 0, false}, /* GEN8_L3SQCREG4 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

121

{RCS0, _MMIO(0xb11c), 0, false}, /* GEN9_SCRATCH1 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

124

{RCS0, _MMIO(0xe180), 0xffff, true}, /* HALF_SLICE_CHICKEN2 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

125

{RCS0, _MMIO(0xe184), 0xffff, true}, /* GEN8_HALF_SLICE_CHICKEN3 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

126

{RCS0, _MMIO(0xe188), 0xffff, true}, /* GEN9_HALF_SLICE_CHICKEN5 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

127

{RCS0, _MMIO(0xe194), 0xffff, true}, /* GEN9_HALF_SLICE_CHICKEN7 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

128

{RCS0, _MMIO(0xe4f0), 0xffff, true}, /* GEN8_ROW_CHICKEN */

sys/dev/pci/drm/i915/gvt/mmio_context.c

135

{RCS0, _MMIO(0x4dfc), 0, true},

sys/dev/pci/drm/i915/gvt/mmio_context.c

154

{RCS0, _MMIO(0x20D8), 0xffff, true}, /* 0x20d8 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

382

reg = _MMIO(regs[engine->id]);

sys/dev/pci/drm/i915/gvt/reg.h

114

#define PCH_GPIO_BASE _MMIO(0xc5010)

sys/dev/pci/drm/i915/gvt/reg.h

116

#define PCH_GMBUS0 _MMIO(0xc5100)

sys/dev/pci/drm/i915/gvt/reg.h

117

#define PCH_GMBUS1 _MMIO(0xc5104)

sys/dev/pci/drm/i915/gvt/reg.h

118

#define PCH_GMBUS2 _MMIO(0xc5108)

sys/dev/pci/drm/i915/gvt/reg.h

119

#define PCH_GMBUS3 _MMIO(0xc510c)

sys/dev/pci/drm/i915/gvt/reg.h

120

#define PCH_GMBUS4 _MMIO(0xc5110)

sys/dev/pci/drm/i915/gvt/reg.h

121

#define PCH_GMBUS5 _MMIO(0xc5120)

sys/dev/pci/drm/i915/gvt/reg.h

123

#define TRVATTL3PTRDW(i) _MMIO(0x4de0 + (i) * 4)

sys/dev/pci/drm/i915/gvt/reg.h

124

#define TRNULLDETCT _MMIO(0x4de8)

sys/dev/pci/drm/i915/gvt/reg.h

125

#define TRINVTILEDETCT _MMIO(0x4dec)

sys/dev/pci/drm/i915/gvt/reg.h

126

#define TRVADR _MMIO(0x4df0)

sys/dev/pci/drm/i915/gvt/reg.h

127

#define TRTTE _MMIO(0x4df4)

sys/dev/pci/drm/i915/gvt/reg.h

128

#define RING_EXCC(base) _MMIO((base) + 0x28)

sys/dev/pci/drm/i915/gvt/reg.h

129

#define RING_GFX_MODE(base) _MMIO((base) + 0x29c)

sys/dev/pci/drm/i915/gvt/reg.h

130

#define VF_GUARDBAND _MMIO(0x83a4)

sys/dev/pci/drm/i915/gvt/reg.h

135

#define PCH_PP_STATUS _MMIO(0xc7200)

sys/dev/pci/drm/i915/gvt/reg.h

136

#define PCH_PP_CONTROL _MMIO(0xc7204)

sys/dev/pci/drm/i915/gvt/reg.h

137

#define PCH_PP_ON_DELAYS _MMIO(0xc7208)

sys/dev/pci/drm/i915/gvt/reg.h

138

#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)

sys/dev/pci/drm/i915/gvt/reg.h

139

#define PCH_PP_DIVISOR _MMIO(0xc7210)

sys/dev/pci/drm/i915/gvt/reg.h

68

(((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \

sys/dev/pci/drm/i915/gvt/reg.h

69

(_MMIO(0x50090))) : \

sys/dev/pci/drm/i915/gvt/reg.h

70

(((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \

sys/dev/pci/drm/i915/gvt/reg.h

71

(_MMIO(0x50098))) : \

sys/dev/pci/drm/i915/gvt/reg.h

72

(((p) == PIPE_C) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x5008C)) : \

sys/dev/pci/drm/i915/gvt/reg.h

73

(_MMIO(0x5009C))) : \

sys/dev/pci/drm/i915/gvt/reg.h

74

(_MMIO(0x50080))))); })

sys/dev/pci/drm/i915/i915_gpu_error.c

1859

_MMIO(guc_hw_reg_state[range].start + count * sizeof(u32)));

sys/dev/pci/drm/i915/i915_perf.c

4586

oa_regs[i].addr = _MMIO(addr);

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

100

#define GEN12_OACTXCONTROL(base) _MMIO((base) + 0x360)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

101

#define GEN12_OAR_OASTATUS _MMIO(0x2968)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

104

#define GEN12_OAG_OAHEADPTR _MMIO(0xdb00)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

106

#define GEN12_OAG_OATAILPTR _MMIO(0xdb04)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

109

#define GEN12_OAG_OABUFFER _MMIO(0xdb08)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

11

#define GEN7_OACONTROL _MMIO(0x2360)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

114

#define GEN12_OAG_OAGLBCTXCTRL _MMIO(0x2b28)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

119

#define GEN12_OAG_OACONTROL _MMIO(0xdaf4)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

123

#define GEN12_OAG_OA_DEBUG _MMIO(0xdaf8)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

129

#define GEN12_OAG_OASTATUS _MMIO(0xdafc)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

134

#define GDT_CHICKEN_BITS _MMIO(0x9840)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

173

_MMIO((base) + GEN12_OAM_MMIO_TRG_OFFSET)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

176

_MMIO((base) + GEN12_OAM_HEAD_POINTER_OFFSET)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

178

_MMIO((base) + GEN12_OAM_TAIL_POINTER_OFFSET)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

180

_MMIO((base) + GEN12_OAM_BUFFER_OFFSET)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

182

_MMIO((base) + GEN12_OAM_CONTEXT_CONTROL_OFFSET)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

184

_MMIO((base) + GEN12_OAM_CONTROL_OFFSET)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

186

_MMIO((base) + GEN12_OAM_DEBUG_OFFSET)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

188

_MMIO((base) + GEN12_OAM_STATUS_OFFSET)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

193

_MMIO((base) + GEN12_OAM_CEC0_0_OFFSET)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

195

_MMIO((base) + GEN12_OAM_CEC7_1_OFFSET)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

200

_MMIO((base) + GEN12_OAM_STARTTRIG1_OFFSET)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

202

_MMIO((base) + GEN12_OAM_STARTTRIG8_OFFSET)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

207

_MMIO((base) + GEN12_OAM_REPORTTRIG1_OFFSET)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

209

_MMIO((base) + GEN12_OAM_REPORTTRIG8_OFFSET)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

213

_MMIO((base) + GEN12_OAM_PERF_COUNTER_B0_OFFSET + 4 * (idx))

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

28

#define GEN8_OACTXID _MMIO(0x2364)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

30

#define GEN8_OA_DEBUG _MMIO(0x2B04)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

36

#define GEN8_OACONTROL _MMIO(0x2B00)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

45

#define GEN8_OACTXCONTROL _MMIO(0x2360)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

51

#define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

57

#define GEN8_OABUFFER_UDW _MMIO(0x23b4)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

58

#define GEN8_OABUFFER _MMIO(0x2b14)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

61

#define GEN7_OASTATUS1 _MMIO(0x2364)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

67

#define GEN7_OASTATUS2 _MMIO(0x2368)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

71

#define GEN8_OASTATUS _MMIO(0x2b08)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

79

#define GEN8_OAHEADPTR _MMIO(0x2B0C)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

81

#define GEN8_OATAILPTR _MMIO(0x2B10)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

93

#define GEN12_OA_TLB_INV_CR _MMIO(0xceec)

sys/dev/pci/drm/i915/i915_perf_oa_regs.h

96

#define GEN12_OAR_OACONTROL _MMIO(0x2960)

sys/dev/pci/drm/i915/i915_pvinfo.h

117

#define vgtif_reg(x) _MMIO(VGT_PVINFO_PAGE + vgtif_offset(x))

sys/dev/pci/drm/i915/i915_reg.h

1001

#define GMD_ID_DISPLAY _MMIO(0x510a0)

sys/dev/pci/drm/i915/i915_reg.h

1008

#define SDEISR _MMIO(0xc4000)

sys/dev/pci/drm/i915/i915_reg.h

1009

#define SDEIMR _MMIO(0xc4004)

sys/dev/pci/drm/i915/i915_reg.h

1010

#define SDEIIR _MMIO(0xc4008)

sys/dev/pci/drm/i915/i915_reg.h

1011

#define SDEIER _MMIO(0xc400c)

sys/dev/pci/drm/i915/i915_reg.h

1035

#define SOUTH_CHICKEN1 _MMIO(0xc2000)

sys/dev/pci/drm/i915/i915_reg.h

1056

#define SOUTH_CHICKEN2 _MMIO(0xc2004)

sys/dev/pci/drm/i915/i915_reg.h

1062

#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)

sys/dev/pci/drm/i915/i915_reg.h

1071

#define VLV_PMWGICZ _MMIO(0x1300a4)

sys/dev/pci/drm/i915/i915_reg.h

1073

#define HSW_EDRAM_CAP _MMIO(0x120010)

sys/dev/pci/drm/i915/i915_reg.h

1079

#define GEN6_PCODE_MAILBOX _MMIO(0x138124)

sys/dev/pci/drm/i915/i915_reg.h

1179

#define GEN6_PCODE_DATA _MMIO(0x138128)

sys/dev/pci/drm/i915/i915_reg.h

1182

#define GEN6_PCODE_DATA1 _MMIO(0x13812C)

sys/dev/pci/drm/i915/i915_reg.h

1184

#define MTL_PCODE_STOLEN_ACCESS _MMIO(0x138914)

sys/dev/pci/drm/i915/i915_reg.h

1188

#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */

sys/dev/pci/drm/i915/i915_reg.h

119

#define GU_CNTL_PROTECTED _MMIO(0x10100C)

sys/dev/pci/drm/i915/i915_reg.h

1205

#define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)

sys/dev/pci/drm/i915/i915_reg.h

1207

#define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)

sys/dev/pci/drm/i915/i915_reg.h

1213

#define GGC _MMIO(0x108040)

sys/dev/pci/drm/i915/i915_reg.h

1217

#define GEN6_GSMBASE _MMIO(0x108100)

sys/dev/pci/drm/i915/i915_reg.h

1218

#define GEN6_DSMBASE _MMIO(0x1080C0)

sys/dev/pci/drm/i915/i915_reg.h

122

#define GU_CNTL _MMIO(0x101010)

sys/dev/pci/drm/i915/i915_reg.h

1222

#define XEHP_CLOCK_GATE_DIS _MMIO(0x101014)

sys/dev/pci/drm/i915/i915_reg.h

1227

#define PRIMARY_SPI_TRIGGER _MMIO(0x102040)

sys/dev/pci/drm/i915/i915_reg.h

1228

#define PRIMARY_SPI_ADDRESS _MMIO(0x102080)

sys/dev/pci/drm/i915/i915_reg.h

1229

#define PRIMARY_SPI_REGIONID _MMIO(0x102084)

sys/dev/pci/drm/i915/i915_reg.h

1230

#define SPI_STATIC_REGIONS _MMIO(0x102090)

sys/dev/pci/drm/i915/i915_reg.h

1232

#define OROM_OFFSET _MMIO(0x1020c0)

sys/dev/pci/drm/i915/i915_reg.h

1235

#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)

sys/dev/pci/drm/i915/i915_reg.h

125

#define GU_DEBUG _MMIO(0x101018)

sys/dev/pci/drm/i915/i915_reg.h

128

#define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)

sys/dev/pci/drm/i915/i915_reg.h

150

#define DEBUG_RESET_I830 _MMIO(0x6070)

sys/dev/pci/drm/i915/i915_reg.h

158

#define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)

sys/dev/pci/drm/i915/i915_reg.h

180

#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)

sys/dev/pci/drm/i915/i915_reg.h

181

#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)

sys/dev/pci/drm/i915/i915_reg.h

196

#define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)

sys/dev/pci/drm/i915/i915_reg.h

209

#define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)

sys/dev/pci/drm/i915/i915_reg.h

210

#define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)

sys/dev/pci/drm/i915/i915_reg.h

216

#define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)

sys/dev/pci/drm/i915/i915_reg.h

217

#define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)

sys/dev/pci/drm/i915/i915_reg.h

223

#define TILECTL _MMIO(0x101000)

sys/dev/pci/drm/i915/i915_reg.h

232

#define PGTBL_CTL _MMIO(0x02020)

sys/dev/pci/drm/i915/i915_reg.h

235

#define PGTBL_ER _MMIO(0x02024)

sys/dev/pci/drm/i915/i915_reg.h

281

#define HECI_H_CSR(base) _MMIO((base) + 0x4)

sys/dev/pci/drm/i915/i915_reg.h

288

#define HECI_H_GS1(base) _MMIO((base) + 0xc4c)

sys/dev/pci/drm/i915/i915_reg.h

308

#define HECI_FWSTS(base, x) _MMIO((base) + _PICK(x, -(base), \

sys/dev/pci/drm/i915/i915_reg.h

316

#define HSW_GTT_CACHE_EN _MMIO(0x4024)

sys/dev/pci/drm/i915/i915_reg.h

318

#define GEN7_WR_WATERMARK _MMIO(0x4028)

sys/dev/pci/drm/i915/i915_reg.h

319

#define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)

sys/dev/pci/drm/i915/i915_reg.h

320

#define ARB_MODE _MMIO(0x4030)

sys/dev/pci/drm/i915/i915_reg.h

323

#define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)

sys/dev/pci/drm/i915/i915_reg.h

324

#define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)

sys/dev/pci/drm/i915/i915_reg.h

326

#define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)

sys/dev/pci/drm/i915/i915_reg.h

328

#define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)

sys/dev/pci/drm/i915/i915_reg.h

329

#define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)

sys/dev/pci/drm/i915/i915_reg.h

331

#define GEN7_ERR_INT _MMIO(0x44040)

sys/dev/pci/drm/i915/i915_reg.h

354

#define FPGA_DBG _MMIO(0x42300)

sys/dev/pci/drm/i915/i915_reg.h

357

#define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)

sys/dev/pci/drm/i915/i915_reg.h

362

#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)

sys/dev/pci/drm/i915/i915_reg.h

363

#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)

sys/dev/pci/drm/i915/i915_reg.h

364

#define SCPD0 _MMIO(0x209c) /* 915+ only */

sys/dev/pci/drm/i915/i915_reg.h

367

#define GEN2_IER _MMIO(0x20a0)

sys/dev/pci/drm/i915/i915_reg.h

368

#define GEN2_IIR _MMIO(0x20a4)

sys/dev/pci/drm/i915/i915_reg.h

369

#define GEN2_IMR _MMIO(0x20a8)

sys/dev/pci/drm/i915/i915_reg.h

370

#define GEN2_ISR _MMIO(0x20ac)

sys/dev/pci/drm/i915/i915_reg.h

376

#define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)

sys/dev/pci/drm/i915/i915_reg.h

379

#define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)

sys/dev/pci/drm/i915/i915_reg.h

380

#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)

sys/dev/pci/drm/i915/i915_reg.h

381

#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)

sys/dev/pci/drm/i915/i915_reg.h

382

#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)

sys/dev/pci/drm/i915/i915_reg.h

383

#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)

sys/dev/pci/drm/i915/i915_reg.h

384

#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)

sys/dev/pci/drm/i915/i915_reg.h

385

#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)

sys/dev/pci/drm/i915/i915_reg.h

388

#define EIR _MMIO(0x20b0)

sys/dev/pci/drm/i915/i915_reg.h

389

#define EMR _MMIO(0x20b4)

sys/dev/pci/drm/i915/i915_reg.h

390

#define ESR _MMIO(0x20b8)

sys/dev/pci/drm/i915/i915_reg.h

400

#define INSTPM _MMIO(0x20c0)

sys/dev/pci/drm/i915/i915_reg.h

408

#define MEM_MODE _MMIO(0x20cc)

sys/dev/pci/drm/i915/i915_reg.h

412

#define FW_BLC _MMIO(0x20d8)

sys/dev/pci/drm/i915/i915_reg.h

413

#define FW_BLC2 _MMIO(0x20dc)

sys/dev/pci/drm/i915/i915_reg.h

414

#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */

sys/dev/pci/drm/i915/i915_reg.h

422

#define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */

sys/dev/pci/drm/i915/i915_reg.h

487

#define MI_STATE _MMIO(0x20e4) /* gen2 only */

sys/dev/pci/drm/i915/i915_reg.h

563

#define GEN6_BSD_RNCID _MMIO(0x12198)

sys/dev/pci/drm/i915/i915_reg.h

565

#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)

sys/dev/pci/drm/i915/i915_reg.h

583

#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)

sys/dev/pci/drm/i915/i915_reg.h

598

#define DPLL_TEST _MMIO(0x606c)

sys/dev/pci/drm/i915/i915_reg.h

610

#define D_STATE _MMIO(0x6104)

sys/dev/pci/drm/i915/i915_reg.h

616

#define DSPCLK_GATE_D _MMIO(0x6200)

sys/dev/pci/drm/i915/i915_reg.h

617

#define VLV_DSPCLK_GATE_D _MMIO(VLV_DISPLAY_BASE + 0x6200)

sys/dev/pci/drm/i915/i915_reg.h

657

#define RENCLK_GATE_D1 _MMIO(0x6204)

sys/dev/pci/drm/i915/i915_reg.h

721

#define RENCLK_GATE_D2 _MMIO(0x6208)

sys/dev/pci/drm/i915/i915_reg.h

726

#define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */

sys/dev/pci/drm/i915/i915_reg.h

729

#define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */

sys/dev/pci/drm/i915/i915_reg.h

730

#define DEUC _MMIO(0x6214) /* CRL only */

sys/dev/pci/drm/i915/i915_reg.h

732

#define BXT_RP_STATE_CAP _MMIO(0x138170)

sys/dev/pci/drm/i915/i915_reg.h

733

#define GEN9_RP_STATE_LIMITS _MMIO(0x138148)

sys/dev/pci/drm/i915/i915_reg.h

735

#define MTL_RP_STATE_CAP _MMIO(0x138000)

sys/dev/pci/drm/i915/i915_reg.h

736

#define MTL_MEDIAP_STATE_CAP _MMIO(0x138020)

sys/dev/pci/drm/i915/i915_reg.h

740

#define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c)

sys/dev/pci/drm/i915/i915_reg.h

741

#define MTL_MPE_FREQUENCY _MMIO(0x13802c)

sys/dev/pci/drm/i915/i915_reg.h

744

#define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)

sys/dev/pci/drm/i915/i915_reg.h

755

#define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030)

sys/dev/pci/drm/i915/i915_reg.h

757

#define CHV_CLK_CTL1 _MMIO(0x101100)

sys/dev/pci/drm/i915/i915_reg.h

758

#define VLV_CLK_CTL2 _MMIO(0x101104)

sys/dev/pci/drm/i915/i915_reg.h

764

#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)

sys/dev/pci/drm/i915/i915_reg.h

770

#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)

sys/dev/pci/drm/i915/i915_reg.h

774

#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)

sys/dev/pci/drm/i915/i915_reg.h

795

#define PCH_3DCGDIS0 _MMIO(0x46020)

sys/dev/pci/drm/i915/i915_reg.h

799

#define PCH_3DCGDIS1 _MMIO(0x46024)

sys/dev/pci/drm/i915/i915_reg.h

803

#define RM_TIMEOUT _MMIO(0x42060)

sys/dev/pci/drm/i915/i915_reg.h

804

#define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0)

sys/dev/pci/drm/i915/i915_reg.h

840

#define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */

sys/dev/pci/drm/i915/i915_reg.h

843

#define DEISR _MMIO(0x44000)

sys/dev/pci/drm/i915/i915_reg.h

844

#define DEIMR _MMIO(0x44004)

sys/dev/pci/drm/i915/i915_reg.h

845

#define DEIIR _MMIO(0x44008)

sys/dev/pci/drm/i915/i915_reg.h

846

#define DEIER _MMIO(0x4400c)

sys/dev/pci/drm/i915/i915_reg.h

852

#define GTISR _MMIO(0x44010)

sys/dev/pci/drm/i915/i915_reg.h

853

#define GTIMR _MMIO(0x44014)

sys/dev/pci/drm/i915/i915_reg.h

854

#define GTIIR _MMIO(0x44018)

sys/dev/pci/drm/i915/i915_reg.h

855

#define GTIER _MMIO(0x4401c)

sys/dev/pci/drm/i915/i915_reg.h

861

#define GEN8_MASTER_IRQ _MMIO(0x44200)

sys/dev/pci/drm/i915/i915_reg.h

879

#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))

sys/dev/pci/drm/i915/i915_reg.h

880

#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))

sys/dev/pci/drm/i915/i915_reg.h

881

#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))

sys/dev/pci/drm/i915/i915_reg.h

882

#define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))

sys/dev/pci/drm/i915/i915_reg.h

895

#define GEN8_PCU_ISR _MMIO(0x444e0)

sys/dev/pci/drm/i915/i915_reg.h

896

#define GEN8_PCU_IMR _MMIO(0x444e4)

sys/dev/pci/drm/i915/i915_reg.h

897

#define GEN8_PCU_IIR _MMIO(0x444e8)

sys/dev/pci/drm/i915/i915_reg.h

898

#define GEN8_PCU_IER _MMIO(0x444ec)

sys/dev/pci/drm/i915/i915_reg.h

904

#define GEN11_GU_MISC_ISR _MMIO(0x444f0)

sys/dev/pci/drm/i915/i915_reg.h

905

#define GEN11_GU_MISC_IMR _MMIO(0x444f4)

sys/dev/pci/drm/i915/i915_reg.h

906

#define GEN11_GU_MISC_IIR _MMIO(0x444f8)

sys/dev/pci/drm/i915/i915_reg.h

907

#define GEN11_GU_MISC_IER _MMIO(0x444fc)

sys/dev/pci/drm/i915/i915_reg.h

914

#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)

sys/dev/pci/drm/i915/i915_reg.h

923

#define DG1_MSTR_TILE_INTR _MMIO(0x190008)

sys/dev/pci/drm/i915/i915_reg.h

927

#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)

sys/dev/pci/drm/i915/i915_reg.h

933

#define ILK_DSPCLK_GATE_D _MMIO(0x42020)

sys/dev/pci/drm/i915/i915_reg.h

940

#define IVB_CHICKEN3 _MMIO(0x4200c)

sys/dev/pci/drm/i915/i915_reg.h

944

#define CHICKEN_PAR1_1 _MMIO(0x42080)

sys/dev/pci/drm/i915/i915_reg.h

954

#define CHICKEN_PAR2_1 _MMIO(0x42090)

sys/dev/pci/drm/i915/i915_reg.h

980

#define DISP_ARB_CTL _MMIO(0x45000)

sys/dev/pci/drm/i915/i915_reg.h

985

#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)

sys/dev/pci/drm/i915/i915_reg_defs.h

189

#define INVALID_MMIO_REG _MMIO(0)

sys/dev/pci/drm/i915/intel_gvt.c

90

_MMIO(i));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1057

MMIO_D(_MMIO(0xd08));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1068

MMIO_D(_MMIO(0x4dfc));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1069

MMIO_D(_MMIO(0x46430));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1070

MMIO_D(_MMIO(0x46520));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1071

MMIO_D(_MMIO(0xc403c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1074

MMIO_D(_MMIO(0x65900));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1076

MMIO_D(_MMIO(0x4068));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1077

MMIO_D(_MMIO(0x67054));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1078

MMIO_D(_MMIO(0x6e560));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1079

MMIO_D(_MMIO(0x6e554));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1080

MMIO_D(_MMIO(0x2b20));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1081

MMIO_D(_MMIO(0x65f00));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1082

MMIO_D(_MMIO(0x65f08));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1083

MMIO_D(_MMIO(0x320f0));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1084

MMIO_D(_MMIO(0x70034));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1085

MMIO_D(_MMIO(0x71034));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1086

MMIO_D(_MMIO(0x72034));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1096

MMIO_D(_MMIO(0x44500));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1097

#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1108

MMIO_F(_MMIO(DMC_MMIO_START_RANGE), 0x3000);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

111

MMIO_D(_MMIO(0x2124));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1117

MMIO_F(_MMIO(0x80000), 0x3000);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

112

MMIO_D(_MMIO(0x20dc));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1126

MMIO_D(_MMIO(0x4194));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1127

MMIO_D(_MMIO(0x4294));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1128

MMIO_D(_MMIO(0x4494));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

114

MMIO_D(_MMIO(0x2088));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

116

MMIO_D(_MMIO(0x2470));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

120

MMIO_D(_MMIO(0x9030));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

121

MMIO_D(_MMIO(0x20a0));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

122

MMIO_D(_MMIO(0x2420));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

123

MMIO_D(_MMIO(0x2430));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

124

MMIO_D(_MMIO(0x2434));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

125

MMIO_D(_MMIO(0x2438));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1257

MMIO_D(_MMIO(0x20D8));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

126

MMIO_D(_MMIO(0x243c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

127

MMIO_D(_MMIO(0x7018));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

131

MMIO_F(_MMIO(0x60220), 0x20);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

132

MMIO_D(_MMIO(0x602a0));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

133

MMIO_D(_MMIO(0x65050));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

134

MMIO_D(_MMIO(0x650b4));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

135

MMIO_D(_MMIO(0xc4040));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

169

MMIO_D(_MMIO(0x700ac));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

170

MMIO_D(_MMIO(0x710ac));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

171

MMIO_D(_MMIO(0x720ac));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

172

MMIO_D(_MMIO(0x70090));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

173

MMIO_D(_MMIO(0x70094));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

174

MMIO_D(_MMIO(0x70098));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

175

MMIO_D(_MMIO(0x7009c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

337

MMIO_D(_MMIO(0x48268));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

340

MMIO_F(_MMIO(0xe4f00), 0x28);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

341

MMIO_D(_MMIO(_PCH_TRANSACONF));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

342

MMIO_D(_MMIO(_PCH_TRANSBCONF));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

352

MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

353

MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

354

MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

355

MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

356

MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

357

MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

358

MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

359

MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

360

MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

361

MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

362

MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

363

MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

364

MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

365

MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

366

MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

367

MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

368

MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

369

MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

370

MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

371

MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

372

MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

373

MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

386

MMIO_D(_MMIO(_FDI_RXA_MISC));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

387

MMIO_D(_MMIO(_FDI_RXB_MISC));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

388

MMIO_D(_MMIO(_FDI_RXA_TUSIZE1));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

389

MMIO_D(_MMIO(_FDI_RXA_TUSIZE2));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

390

MMIO_D(_MMIO(_FDI_RXB_TUSIZE1));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

391

MMIO_D(_MMIO(_FDI_RXB_TUSIZE2));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

396

MMIO_D(_MMIO(_PCH_DPLL_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

397

MMIO_D(_MMIO(_PCH_DPLL_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

398

MMIO_D(_MMIO(_PCH_FPA0));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

399

MMIO_D(_MMIO(_PCH_FPA1));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

400

MMIO_D(_MMIO(_PCH_FPB0));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

401

MMIO_D(_MMIO(_PCH_FPB1));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

405

MMIO_D(_MMIO(0x61208));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

406

MMIO_D(_MMIO(0x6120c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

409

MMIO_D(_MMIO(0xe651c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

410

MMIO_D(_MMIO(0xe661c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

411

MMIO_D(_MMIO(0xe671c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

412

MMIO_D(_MMIO(0xe681c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

413

MMIO_D(_MMIO(0xe6c04));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

414

MMIO_D(_MMIO(0xe6e1c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

426

MMIO_D(_MMIO(_TRANSA_CHICKEN1));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

427

MMIO_D(_MMIO(_TRANSB_CHICKEN1));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

429

MMIO_D(_MMIO(_TRANSA_CHICKEN2));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

430

MMIO_D(_MMIO(_TRANSB_CHICKEN2));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

487

MMIO_D(_MMIO(0x60110));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

488

MMIO_D(_MMIO(0x61110));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

489

MMIO_F(_MMIO(0x70400), 0x40);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

490

MMIO_F(_MMIO(0x71400), 0x40);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

491

MMIO_F(_MMIO(0x72400), 0x40);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

496

MMIO_D(_MMIO(_WRPLL_CTL1));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

497

MMIO_D(_MMIO(_WRPLL_CTL2));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

507

MMIO_D(_MMIO(0x46508));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

508

MMIO_D(_MMIO(0x49080));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

509

MMIO_D(_MMIO(0x49180));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

510

MMIO_D(_MMIO(0x49280));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

511

MMIO_F(_MMIO(0x49090), 0x14);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

512

MMIO_F(_MMIO(0x49190), 0x14);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

513

MMIO_F(_MMIO(0x49290), 0x14);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

544

MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

545

MMIO_F(_MMIO(0x64e60), 0x50);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

546

MMIO_F(_MMIO(0x64eC0), 0x50);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

547

MMIO_F(_MMIO(0x64f20), 0x50);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

548

MMIO_F(_MMIO(0x64f80), 0x50);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

552

MMIO_D(_MMIO(_TRANS_DDI_FUNC_CTL_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

553

MMIO_D(_MMIO(_TRANS_DDI_FUNC_CTL_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

554

MMIO_D(_MMIO(_TRANS_DDI_FUNC_CTL_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

555

MMIO_D(_MMIO(_TRANS_DDI_FUNC_CTL_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

556

MMIO_D(_MMIO(_TRANSA_MSA_MISC));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

557

MMIO_D(_MMIO(_TRANSB_MSA_MISC));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

558

MMIO_D(_MMIO(_TRANSC_MSA_MISC));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

559

MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

605

MMIO_F(_MMIO(0x4f000), 0x90);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

607

MMIO_D(_MMIO(0x13812c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

612

MMIO_D(_MMIO(0x3c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

613

MMIO_D(_MMIO(0x860));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

615

MMIO_D(_MMIO(0x121d0));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

617

MMIO_D(_MMIO(0x41d0));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

619

MMIO_D(_MMIO(0x6200));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

620

MMIO_D(_MMIO(0x6204));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

621

MMIO_D(_MMIO(0x6208));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

622

MMIO_D(_MMIO(0x7118));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

623

MMIO_D(_MMIO(0x7180));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

624

MMIO_D(_MMIO(0x7408));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

625

MMIO_D(_MMIO(0x7c00));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

627

MMIO_D(_MMIO(0x911c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

628

MMIO_D(_MMIO(0x9120));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

631

MMIO_D(_MMIO(0x48800));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

632

MMIO_D(_MMIO(0xce044));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

633

MMIO_D(_MMIO(0xe6500));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

634

MMIO_D(_MMIO(0xe6504));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

635

MMIO_D(_MMIO(0xe6600));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

636

MMIO_D(_MMIO(0xe6604));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

637

MMIO_D(_MMIO(0xe6700));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

638

MMIO_D(_MMIO(0xe6704));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

639

MMIO_D(_MMIO(0xe6800));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

640

MMIO_D(_MMIO(0xe6804));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

643

MMIO_D(_MMIO(0x902c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

644

MMIO_D(_MMIO(0xec008));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

645

MMIO_D(_MMIO(0xec00c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

646

MMIO_D(_MMIO(0xec008 + 0x18));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

647

MMIO_D(_MMIO(0xec00c + 0x18));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

648

MMIO_D(_MMIO(0xec008 + 0x18 * 2));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

649

MMIO_D(_MMIO(0xec00c + 0x18 * 2));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

650

MMIO_D(_MMIO(0xec008 + 0x18 * 3));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

651

MMIO_D(_MMIO(0xec00c + 0x18 * 3));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

652

MMIO_D(_MMIO(0xec408));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

653

MMIO_D(_MMIO(0xec40c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

654

MMIO_D(_MMIO(0xec408 + 0x18));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

655

MMIO_D(_MMIO(0xec40c + 0x18));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

656

MMIO_D(_MMIO(0xec408 + 0x18 * 2));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

657

MMIO_D(_MMIO(0xec40c + 0x18 * 2));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

658

MMIO_D(_MMIO(0xec408 + 0x18 * 3));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

659

MMIO_D(_MMIO(0xec40c + 0x18 * 3));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

660

MMIO_D(_MMIO(0xfc810));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

661

MMIO_D(_MMIO(0xfc81c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

662

MMIO_D(_MMIO(0xfc828));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

663

MMIO_D(_MMIO(0xfc834));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

664

MMIO_D(_MMIO(0xfcc00));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

665

MMIO_D(_MMIO(0xfcc0c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

666

MMIO_D(_MMIO(0xfcc18));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

667

MMIO_D(_MMIO(0xfcc24));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

668

MMIO_D(_MMIO(0xfd000));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

669

MMIO_D(_MMIO(0xfd00c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

670

MMIO_D(_MMIO(0xfd018));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

671

MMIO_D(_MMIO(0xfd024));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

672

MMIO_D(_MMIO(0xfd034));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

674

MMIO_D(_MMIO(0x2054));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

675

MMIO_D(_MMIO(0x12054));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

676

MMIO_D(_MMIO(0x22054));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

677

MMIO_D(_MMIO(0x1a054));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

678

MMIO_D(_MMIO(0x44070));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

679

MMIO_D(_MMIO(0x2178));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

680

MMIO_D(_MMIO(0x217c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

681

MMIO_D(_MMIO(0x12178));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

682

MMIO_D(_MMIO(0x1217c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

683

MMIO_F(_MMIO(0x5200), 32);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

684

MMIO_F(_MMIO(0x5240), 32);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

685

MMIO_F(_MMIO(0x5280), 16);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

700

MMIO_D(_MMIO(0x2220));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

701

MMIO_D(_MMIO(0x12220));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

702

MMIO_D(_MMIO(0x22220));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

707

MMIO_F(_MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

708

MMIO_F(_MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

726

MMIO_D(_MMIO(_SRD_CTL_EDP));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

728

MMIO_D(_MMIO(0xb1f0));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

729

MMIO_D(_MMIO(0xb1c0));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

730

MMIO_D(_MMIO(0xb100));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

731

MMIO_D(_MMIO(0xb10c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

732

MMIO_D(_MMIO(0xb110));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

733

MMIO_D(_MMIO(0x83a4));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

734

MMIO_D(_MMIO(0x8430));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

735

MMIO_D(_MMIO(0x2248));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

77

#define RING_REG(base) _MMIO((base) + 0x28)

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

788

#define RING_REG(base) _MMIO((base) + 0xd0)

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

792

#define RING_REG(base) _MMIO((base) + 0x230)

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

796

#define RING_REG(base) _MMIO((base) + 0x234)

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

800

#define RING_REG(base) _MMIO((base) + 0x244)

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

804

#define RING_REG(base) _MMIO((base) + 0x370)

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

808

#define RING_REG(base) _MMIO((base) + 0x3a0)

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

81

#define RING_REG(base) _MMIO((base) + 0x134)

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

815

MMIO_D(_MMIO(0x1c1d0));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

818

MMIO_D(_MMIO(0x1c054));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

825

#define RING_REG(base) _MMIO((base) + 0x270)

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

834

MMIO_D(_MMIO(0x6671c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

835

MMIO_D(_MMIO(0x66c00));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

836

MMIO_D(_MMIO(0x66c04));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

841

MMIO_D(_MMIO(0xfdc));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

847

MMIO_F(_MMIO(0x24d0), 48);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

848

MMIO_D(_MMIO(0x44484));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

849

MMIO_D(_MMIO(0x4448c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

85

#define RING_REG(base) _MMIO((base) + 0x6c)

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

851

MMIO_D(_MMIO(0x110000));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

852

MMIO_D(_MMIO(0x48400));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

853

MMIO_D(_MMIO(0x6e570));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

854

MMIO_D(_MMIO(0x65f10));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

855

MMIO_D(_MMIO(0xe194));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

856

MMIO_D(_MMIO(0xe188));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

858

MMIO_D(_MMIO(0x2580));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

859

MMIO_D(_MMIO(0xe220));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

860

MMIO_D(_MMIO(0xe230));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

861

MMIO_D(_MMIO(0xe240));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

862

MMIO_D(_MMIO(0xe260));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

863

MMIO_D(_MMIO(0xe270));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

864

MMIO_D(_MMIO(0xe280));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

865

MMIO_D(_MMIO(0xe2a0));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

866

MMIO_D(_MMIO(0xe2b0));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

867

MMIO_D(_MMIO(0xe2c0));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

868

MMIO_D(_MMIO(0x21f0));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

870

MMIO_D(_MMIO(0x215c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

871

MMIO_F(_MMIO(0x2290), 8);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

872

MMIO_D(_MMIO(0x2b00));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

873

MMIO_D(_MMIO(0x2360));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

874

MMIO_D(_MMIO(0x1c17c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

875

MMIO_D(_MMIO(0x1c178));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

876

MMIO_D(_MMIO(0x4260));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

877

MMIO_D(_MMIO(0x4264));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

878

MMIO_D(_MMIO(0x4268));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

879

MMIO_D(_MMIO(0x426c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

88

MMIO_D(_MMIO(0x2148));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

880

MMIO_D(_MMIO(0x4270));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

881

MMIO_D(_MMIO(0x4094));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

882

MMIO_D(_MMIO(0x22178));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

883

MMIO_D(_MMIO(0x1a178));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

884

MMIO_D(_MMIO(0x1a17c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

885

MMIO_D(_MMIO(0x2217c));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

888

MMIO_D(_MMIO(0xe4cc));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

90

MMIO_D(_MMIO(0x12198));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

903

MMIO_F(_MMIO(0x70440), 0xc);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

904

MMIO_F(_MMIO(0x71440), 0xc);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

905

MMIO_F(_MMIO(0x72440), 0xc);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

906

MMIO_F(_MMIO(0x7044c), 0xc);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

907

MMIO_F(_MMIO(0x7144c), 0xc);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

908

MMIO_F(_MMIO(0x7244c), 0xc);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

940

MMIO_D(_MMIO(_DPLL1_CFGCR1));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

941

MMIO_D(_MMIO(_DPLL2_CFGCR1));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

942

MMIO_D(_MMIO(_DPLL3_CFGCR1));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

943

MMIO_D(_MMIO(_DPLL1_CFGCR2));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

944

MMIO_D(_MMIO(_DPLL2_CFGCR2));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

945

MMIO_D(_MMIO(_DPLL3_CFGCR2));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

99

#define RING_REG(base) _MMIO((base) + 0x29c)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

125

#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

128

#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4004)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

132

#define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

140

#define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

141

#define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

142

#define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

161

#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

162

#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

188

#define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

195

#define PCU_PACKAGE_POWER_SKU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5930)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

203

#define PCU_PACKAGE_POWER_SKU_UNIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5938)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

207

#define PCU_PACKAGE_ENERGY_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x593c)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

209

#define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

211

#define PCU_PACKAGE_TEMPERATURE _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5978)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

214

#define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

215

#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

220

#define GEN10_FREQ_INFO_REC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

222

#define PCU_PACKAGE_RAPL_LIMIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x59a0)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

230

#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

243

#define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

244

#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

25

#define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

251

#define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5f0c)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

256

#define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

26

#define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

32

#define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

36

#define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

43

#define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

47

#define C0DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x206)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

48

#define C1DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x606)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

51

#define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

68

#define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

69

#define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

71

#define TSC1 _MMIO(MCHBAR_MIRROR_BASE + 0x1001)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

73

#define TR1 _MMIO(MCHBAR_MIRROR_BASE + 0x1006)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

74

#define TSFS _MMIO(MCHBAR_MIRROR_BASE + 0x1020)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

80

#define MLTR_ILK _MMIO(MCHBAR_MIRROR_BASE + 0x1222)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

85

#define CSIPLL0 _MMIO(MCHBAR_MIRROR_BASE + 0x2c10)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

86

#define DDRMPLL1 _MMIO(MCHBAR_MIRROR_BASE + 0x2c20)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

88

#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

99

#define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \

sys/dev/pci/drm/i915/pxp/intel_pxp_regs.h

16

#define KCR_INIT(base) _MMIO((base) + 0xf0)

sys/dev/pci/drm/i915/pxp/intel_pxp_regs.h

22

#define KCR_SIP(base) _MMIO((base) + 0x260)

sys/dev/pci/drm/i915/pxp/intel_pxp_regs.h

25

#define KCR_GLOBAL_TERMINATE(base) _MMIO((base) + 0xf8)

sys/dev/pci/drm/i915/selftests/intel_uncore.c

211

i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset);