_MASKED_BIT_ENABLE
val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
_MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
_MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
engine->tlb_inv.request = _MASKED_BIT_ENABLE(val);
intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
_MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
_MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE);
mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE);
_MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
_MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
_MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
*cs++ = _MASKED_BIT_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE);
ctl = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH);
ctl |= _MASKED_BIT_ENABLE(GEN12_CTX_CTRL_RUNALONE_MODE);
_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request));
_MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
_MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
_MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
*cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE);
*cs++ = _MASKED_BIT_ENABLE(
_MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
_MASKED_BIT_ENABLE(DIS_ATOMIC_CHAINING_TYPED_WRITES),
0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),
0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE),
_MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
_MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE),
_MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
_MASKED_BIT_ENABLE(dma_flags | START_DMA));
(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1);
(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2);
(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18);
~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
(((_val) & _MASKED_BIT_ENABLE(_b)) == _MASKED_BIT_ENABLE(_b))
_MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
_MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
_MASKED_BIT_ENABLE(GEN12_DISABLE_DOP_GATING));
_MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE);
val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE);
_MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
_MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
_MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
_MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
_MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
intel_uncore_write(&i915->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
_MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
_MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
intel_uncore_write(&i915->uncore, MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
_MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
_MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D));
_MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
_MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
#define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
u32 val = enable ? _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) :