Symbol: _DPLL1_CFGCR2
sys/dev/pci/drm/i915/display/intel_display_regs.h
2574
#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
943
MMIO_D(_MMIO(_DPLL1_CFGCR2));