Symbol: _DPLL1_CFGCR1
sys/dev/pci/drm/i915/display/intel_display_regs.h
2565
#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
940
MMIO_D(_MMIO(_DPLL1_CFGCR1));