_DKL_REG
#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _DKL_REG(tc_port, \
#define DKL_REFCLKIN_CTL(tc_port) _DKL_REG(tc_port, \
#define DKL_CLKTOP2_HSCLKCTL(rc_port) _DKL_REG(tc_port, \
#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _DKL_REG(tc_port, \
#define DKL_CMN_UC_DW_27(tc_port) _DKL_REG(tc_port, \
_DKL_REG(tc_port, (ln0_offs) + (ln_idx) * ((ln1_offs) - (ln0_offs)))
#define DKL_PLL_DIV0(tc_port) _DKL_REG(tc_port, \
#define DKL_PLL_DIV1(tc_port) _DKL_REG(tc_port, \
#define DKL_PLL_SSC(tc_port) _DKL_REG(tc_port, \
#define DKL_PLL_BIAS(tc_port) _DKL_REG(tc_port, \