sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1051

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1054

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1058

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1072

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1074

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_CNTL,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1077

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXA0,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1083

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXB0,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1089

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUX,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1096

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1097

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1100

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1103

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL2,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1108

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1113

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1125

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1126

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1129

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SYS_INT_EN,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

430

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

433

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

436

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

440

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

442

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

445

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

449

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

452

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

454

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

456

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

458

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

462

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

465

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

468

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

469

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

473

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

475

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

477

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

479

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

481

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

483

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

485

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

487

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

489

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

491

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

708

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

710

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

739

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

742

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

745

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

748

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel);