sys/dev/pci/drm/amd/amdgpu/si.c

1886

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);

sys/dev/pci/drm/amd/amdgpu/si.c

1891

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);

sys/dev/pci/drm/amd/amdgpu/si.c

1903

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);

sys/dev/pci/drm/amd/amdgpu/si.c

1919

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,

sys/dev/pci/drm/amd/amdgpu/si.c

1924

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_BYPASS_EN_MASK,

sys/dev/pci/drm/amd/amdgpu/si.c

1929

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,

sys/dev/pci/drm/amd/amdgpu/si.c

1941

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);

sys/dev/pci/drm/amd/amdgpu/si.c

1944

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_VCO_MODE_MASK,

sys/dev/pci/drm/amd/amdgpu/si.c

1948

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,

sys/dev/pci/drm/amd/amdgpu/si.c

1950

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK);

sys/dev/pci/drm/amd/amdgpu/si.c

1953

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);

sys/dev/pci/drm/amd/amdgpu/si.c

1962

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, ~VCEPLL_RESET_MASK);

sys/dev/pci/drm/amd/amdgpu/si.c

1965

WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);

sys/dev/pci/drm/amd/amdgpu/si.c

1968

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3,

sys/dev/pci/drm/amd/amdgpu/si.c

1973

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK);

sys/dev/pci/drm/amd/amdgpu/si.c

1976

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,

sys/dev/pci/drm/amd/amdgpu/si.c

1984

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);

sys/dev/pci/drm/amd/amdgpu/si.c

1989

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK);

sys/dev/pci/drm/amd/amdgpu/si.c

1996

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,

sys/dev/pci/drm/radeon/si.c

7436

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);

sys/dev/pci/drm/radeon/si.c

7441

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);

sys/dev/pci/drm/radeon/si.c

7452

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);

sys/dev/pci/drm/radeon/si.c

7468

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,

sys/dev/pci/drm/radeon/si.c

7473

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_BYPASS_EN_MASK,

sys/dev/pci/drm/radeon/si.c

7478

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,

sys/dev/pci/drm/radeon/si.c

7490

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);

sys/dev/pci/drm/radeon/si.c

7493

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_VCO_MODE_MASK,

sys/dev/pci/drm/radeon/si.c

7497

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,

sys/dev/pci/drm/radeon/si.c

7499

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK);

sys/dev/pci/drm/radeon/si.c

7502

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);

sys/dev/pci/drm/radeon/si.c

7511

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, ~VCEPLL_RESET_MASK);

sys/dev/pci/drm/radeon/si.c

7514

WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);

sys/dev/pci/drm/radeon/si.c

7517

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3, VCEPLL_FB_DIV(fb_div), ~VCEPLL_FB_DIV_MASK);

sys/dev/pci/drm/radeon/si.c

7520

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK);

sys/dev/pci/drm/radeon/si.c

7523

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,

sys/dev/pci/drm/radeon/si.c

7531

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);

sys/dev/pci/drm/radeon/si.c

7536

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK);

sys/dev/pci/drm/radeon/si.c

7543

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,