sys/dev/pci/drm/radeon/sumo_dpm.c

183

WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x10103210);

sys/dev/pci/drm/radeon/sumo_dpm.c

184

WREG32_RCU(RCU_PWR_GATING_SEQ1, 0x10101010);

sys/dev/pci/drm/radeon/sumo_dpm.c

186

WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x76543210);

sys/dev/pci/drm/radeon/sumo_dpm.c

187

WREG32_RCU(RCU_PWR_GATING_SEQ1, 0xFEDCBA98);

sys/dev/pci/drm/radeon/sumo_dpm.c

198

WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);

sys/dev/pci/drm/radeon/sumo_dpm.c

203

WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);

sys/dev/pci/drm/radeon/sumo_dpm.c

208

WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);

sys/dev/pci/drm/radeon/sumo_dpm.c

213

WREG32_RCU(RCU_PWR_GATING_CNTL_4, rcu_pwr_gating_cntl);

sys/dev/pci/drm/radeon/sumo_dpm.c

216

WREG32_RCU(RCU_PWR_GATING_CNTL_5, 0xA02);

sys/dev/pci/drm/radeon/sumo_dpm.c

228

WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);

sys/dev/pci/drm/radeon/sumo_dpm.c

234

WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);

sys/dev/pci/drm/radeon/sumo_dpm.c

239

WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);

sys/dev/pci/drm/radeon/sumo_dpm.c

255

WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);

sys/dev/pci/drm/radeon/sumo_dpm.c

261

WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);

sys/dev/pci/drm/radeon/sumo_dpm.c

266

WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);

sys/dev/pci/drm/radeon/sumo_smc.c

120

WREG32_RCU(RCU_ALTVDDNB_NOTIFY, param);

sys/dev/pci/drm/radeon/sumo_smc.c

154

WREG32_RCU(RCU_GNB_PWR_REP_TIMER_CNTL, timer_value);

sys/dev/pci/drm/radeon/sumo_smc.c

155

WREG32_RCU(RCU_BOOST_MARGIN, pi->sys_info.sclk_dpm_boost_margin);

sys/dev/pci/drm/radeon/sumo_smc.c

156

WREG32_RCU(RCU_THROTTLE_MARGIN, pi->sys_info.sclk_dpm_throttle_margin);

sys/dev/pci/drm/radeon/sumo_smc.c

157

WREG32_RCU(GNB_TDP_LIMIT, pi->sys_info.gnb_tdp_limit);

sys/dev/pci/drm/radeon/sumo_smc.c

158

WREG32_RCU(RCU_SclkDpmTdpLimitPG, pi->sys_info.sclk_dpm_tdp_limit_pg);

sys/dev/pci/drm/radeon/sumo_smc.c

202

WREG32_RCU(regoffset, sclk_dpm_tdp_limit);

sys/dev/pci/drm/radeon/sumo_smc.c

211

WREG32_RCU(RCU_GPU_BOOST_DISABLE, boost_disable);

sys/dev/pci/drm/radeon/sumo_smc.c

78

WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4),

sys/dev/pci/drm/radeon/sumo_smc.c

82

WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4),

sys/dev/pci/drm/radeon/sumo_smc.c

86

WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4),