Symbol: WREG32
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1510
WREG32(reg, tmp_); \
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1543
WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1546
WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
137
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
152
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
157
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
158
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
160
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
163
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
165
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
167
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
170
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
172
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
175
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
177
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
178
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
180
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
182
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
187
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
256
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
269
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
270
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
331
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CONFIG), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
358
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
384
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
101
WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_WPTR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
103
WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_WPTR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
106
WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_WPTR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
108
WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_WPTR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
111
WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_MINOR_PTR_UPDATE, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
113
WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
114
WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_BASE_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
116
WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR_ADDR_LO,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
118
WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR_ADDR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
123
WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
197
WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
210
WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_DOORBELL, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
211
WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
242
WREG32(SOC15_REG_OFFSET(ATHUB, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
256
WREG32(SOC15_REG_OFFSET(ATHUB, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
266
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_LUT_INDEX),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
268
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
270
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_LUT_INDEX),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
272
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
274
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_LUT_INDEX), reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
73
WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
88
WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_DOORBELL_OFFSET,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
93
WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_DOORBELL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
94
WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
96
WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
99
WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_MINOR_PTR_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
1056
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
1058
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
1065
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
1067
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_HI),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
111
WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
123
WREG32(SOC15_REG_OFFSET(ATHUB, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
130
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
387
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
402
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
407
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
408
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
410
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
413
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
415
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
417
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
420
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
422
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
425
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
427
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
428
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
430
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
432
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
437
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
640
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
653
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
654
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
744
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
770
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
771
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
772
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
781
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
798
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
849
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
852
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), wave_cntl_prev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
874
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL2), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
937
WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
945
WREG32((SOC15_REG_OFFSET(GC, 0, mmSQ_WATCH0_CNTL) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
950
WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
953
WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_L) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
957
WREG32((SOC15_REG_OFFSET(GC, 0, mmSQ_WATCH0_ADDR_H) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
960
WREG32((SOC15_REG_OFFSET(GC, 0, mmSQ_WATCH0_ADDR_L) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
969
WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
977
WREG32((SOC15_REG_OFFSET(GC, 0, mmSQ_WATCH0_CNTL) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
991
WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
995
WREG32((SOC15_REG_OFFSET(GC, 0, mmSQ_WATCH0_CNTL) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
104
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, value);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
264
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
373
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
388
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
393
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
394
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
396
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
399
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
401
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
403
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
406
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
408
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
411
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
413
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
414
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
416
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
418
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
423
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
564
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
577
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
578
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
598
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
641
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
643
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
650
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
652
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_HI),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
100
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid, value);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
190
WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_CP_SCHEDULERS), value);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
199
WREG32(reg, mqd_hqd[reg - hqd_base]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
205
WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
234
WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_LO),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
236
WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
238
WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
240
WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
244
WREG32(SOC15_REG_OFFSET(GC, 0, regCP_PQ_WPTR_POLL_CNTL1),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
249
WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_EOP_RPTR),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
254
WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
358
WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
373
WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_DOORBELL_OFFSET,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
378
WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_DOORBELL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
379
WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_RPTR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
381
WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_RPTR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
384
WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_MINOR_PTR_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
386
WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_WPTR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
388
WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_WPTR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
391
WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_WPTR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
393
WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_WPTR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
396
WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_MINOR_PTR_UPDATE, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
398
WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_BASE, m->sdmax_rlcx_rb_base);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
399
WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_BASE_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
401
WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_RPTR_ADDR_LO,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
403
WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_RPTR_ADDR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
408
WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
515
WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_DEQUEUE_REQUEST), type);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
549
WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
562
WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_DOORBELL, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
563
WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
582
WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), gfx_index_val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
583
WREG32(SOC15_REG_OFFSET(GC, 0, regSQ_CMD), sq_cmd);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
592
WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
86
WREG32(SOC15_REG_OFFSET(GC, 0, regSH_MEM_CONFIG), sh_mem_config);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
87
WREG32(SOC15_REG_OFFSET(GC, 0, regSH_MEM_BASES), sh_mem_bases);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
171
WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), gfx_index_val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
172
WREG32(SOC15_REG_OFFSET(GC, 0, regSQ_CMD), sq_cmd);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
181
WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
105
WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
109
WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
112
WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
128
WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
177
WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
184
WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
194
WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
197
WREG32(mmCP_HQD_ACTIVE, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
250
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
267
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
268
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
272
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
274
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
277
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
279
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
280
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
282
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
284
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
289
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
373
WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
441
WREG32(mmCP_HQD_DEQUEUE_REQUEST, type);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
473
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
486
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
487
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
504
WREG32(mmGRBM_GFX_INDEX, gfx_index_val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
505
WREG32(mmSQ_CMD, sq_cmd);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
513
WREG32(mmGRBM_GFX_INDEX, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
535
WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
54
WREG32(mmSRBM_GFX_CNTL, value);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
546
WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
59
WREG32(mmSRBM_GFX_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
85
WREG32(mmSH_MEM_CONFIG, sh_mem_config);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
86
WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
87
WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
88
WREG32(mmSH_MEM_BASES, sh_mem_bases);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
100
WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
104
WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
107
WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
123
WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
180
WREG32(mmRLC_CP_SCHEDULERS, value);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
187
WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
195
WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
196
WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
197
WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
201
WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
208
WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
218
WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
221
WREG32(mmCP_HQD_ACTIVE, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
273
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
290
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
291
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
295
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
297
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
300
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
302
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
303
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
305
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
307
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
312
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
476
WREG32(mmCP_HQD_DEQUEUE_REQUEST, type);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
48
WREG32(mmSRBM_GFX_CNTL, value);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
508
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
521
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
522
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
53
WREG32(mmSRBM_GFX_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
550
WREG32(mmGRBM_GFX_INDEX, gfx_index_val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
551
WREG32(mmSQ_CMD, sq_cmd);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
560
WREG32(mmGRBM_GFX_INDEX, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
570
WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
581
WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
79
WREG32(mmSH_MEM_CONFIG, sh_mem_config);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
80
WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
81
WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
82
WREG32(mmSH_MEM_BASES, sh_mem_bases);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
120
WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
129
WREG32(SOC15_REG_OFFSET(ATHUB, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
134
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
137
WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID16_PASID_MAPPING) + vmid,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
146
WREG32(SOC15_REG_OFFSET(ATHUB, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
151
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
398
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
413
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
418
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
419
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
421
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
424
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
426
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
428
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
431
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
433
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
436
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
438
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
439
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
441
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
443
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
448
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
590
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
603
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
604
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
685
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
709
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
732
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
783
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
786
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), wave_cntl_prev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
808
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL2), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1572
WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1593
WREG32(adev->bios_scratch_reg_offset + 2, bios_2_scratch);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1594
WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1607
WREG32(adev->bios_scratch_reg_offset + 3, tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1619
WREG32(adev->bios_scratch_reg_offset + 2, tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1786
WREG32(reg, val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
704
WREG32(rom_index_offset, rom_offset);
sys/dev/pci/drm/amd/amdgpu/amdgpu_cgs.c
54
WREG32(offset, value);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1538
WREG32(reg, tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7594
WREG32(address, reg * 4);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7610
WREG32(address, reg * 4);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7612
WREG32(data, v);
sys/dev/pci/drm/amd/amdgpu/amdgpu_hdp.c
56
WREG32((adev->rmmio_remap.reg_offset +
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
142
WREG32(rec->en_clk_reg, val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
155
WREG32(rec->en_data_reg, val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
55
WREG32(rec->mask_clk_reg, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
60
WREG32(rec->a_clk_reg, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
63
WREG32(rec->a_data_reg, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
67
WREG32(rec->en_clk_reg, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
70
WREG32(rec->en_data_reg, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
74
WREG32(rec->mask_clk_reg, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
78
WREG32(rec->mask_data_reg, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
93
WREG32(rec->mask_clk_reg, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
97
WREG32(rec->mask_data_reg, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
167
WREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe], 0xCAFEDEAD);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5149
WREG32(err_status_lo_offset, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5150
WREG32(err_status_hi_offset, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.c
74
WREG32(umsch->rb_wptr, ring->wptr << 2);
sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h
207
WREG32(reg_offset, value); \
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
565
WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1168
WREG32(offset, value);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
137
WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
199
WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_pratio), pratio_ctl); /* PRatio */
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
200
WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_interval), 24000); /* 1ms, unit=1/24MHz */
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
201
WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_decision_threshold), 1200000); /* 50ms */
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
202
WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_busy_clamp_threshold), 1200000);/* 50ms */
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
203
WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_idle_clamp_threshold), 1200000);/* 50ms */
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
215
WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
656
WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 1);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
672
WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
771
WREG32(vpe_get_reg_offset(vpe, i, vpe->regs.queue0_rb_wptr_lo),
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
773
WREG32(vpe_get_reg_offset(vpe, i, vpe->regs.queue0_rb_wptr_hi),
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
895
WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator), context_notify);
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
1955
WREG32(mmBIOS_SCRATCH_0, bios_0_scratch);
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
1956
WREG32(mmBIOS_SCRATCH_3, bios_3_scratch);
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
1957
WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
68
WREG32(mmBIOS_SCRATCH_2, bios_2_scratch);
sys/dev/pci/drm/amd/amdgpu/cik.c
1002
WREG32(mmBUS_CNTL, bus_cntl);
sys/dev/pci/drm/amd/amdgpu/cik.c
1004
WREG32(mmD1VGA_CONTROL, d1vga_control);
sys/dev/pci/drm/amd/amdgpu/cik.c
1005
WREG32(mmD2VGA_CONTROL, d2vga_control);
sys/dev/pci/drm/amd/amdgpu/cik.c
1006
WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
sys/dev/pci/drm/amd/amdgpu/cik.c
1032
WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX);
sys/dev/pci/drm/amd/amdgpu/cik.c
1033
WREG32(mmSMC_IND_DATA_0, 0);
sys/dev/pci/drm/amd/amdgpu/cik.c
1035
WREG32(mmSMC_IND_INDEX_0, ixROM_DATA);
sys/dev/pci/drm/amd/amdgpu/cik.c
1250
WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute &
sys/dev/pci/drm/amd/amdgpu/cik.c
1252
WREG32(mmGMCON_MISC, save->gmcon_misc &
sys/dev/pci/drm/amd/amdgpu/cik.c
1262
WREG32(mmGMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/amd/amdgpu/cik.c
1263
WREG32(mmGMCON_PGFSM_CONFIG, 0x200010ff);
sys/dev/pci/drm/amd/amdgpu/cik.c
1266
WREG32(mmGMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/amd/amdgpu/cik.c
1268
WREG32(mmGMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/amd/amdgpu/cik.c
1269
WREG32(mmGMCON_PGFSM_CONFIG, 0x300010ff);
sys/dev/pci/drm/amd/amdgpu/cik.c
1272
WREG32(mmGMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/amd/amdgpu/cik.c
1274
WREG32(mmGMCON_PGFSM_WRITE, 0x210000);
sys/dev/pci/drm/amd/amdgpu/cik.c
1275
WREG32(mmGMCON_PGFSM_CONFIG, 0xa00010ff);
sys/dev/pci/drm/amd/amdgpu/cik.c
1278
WREG32(mmGMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/amd/amdgpu/cik.c
1280
WREG32(mmGMCON_PGFSM_WRITE, 0x21003);
sys/dev/pci/drm/amd/amdgpu/cik.c
1281
WREG32(mmGMCON_PGFSM_CONFIG, 0xb00010ff);
sys/dev/pci/drm/amd/amdgpu/cik.c
1284
WREG32(mmGMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/amd/amdgpu/cik.c
1286
WREG32(mmGMCON_PGFSM_WRITE, 0x2b00);
sys/dev/pci/drm/amd/amdgpu/cik.c
1287
WREG32(mmGMCON_PGFSM_CONFIG, 0xc00010ff);
sys/dev/pci/drm/amd/amdgpu/cik.c
1290
WREG32(mmGMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/amd/amdgpu/cik.c
1292
WREG32(mmGMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/amd/amdgpu/cik.c
1293
WREG32(mmGMCON_PGFSM_CONFIG, 0xd00010ff);
sys/dev/pci/drm/amd/amdgpu/cik.c
1296
WREG32(mmGMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/amd/amdgpu/cik.c
1298
WREG32(mmGMCON_PGFSM_WRITE, 0x420000);
sys/dev/pci/drm/amd/amdgpu/cik.c
1299
WREG32(mmGMCON_PGFSM_CONFIG, 0x100010ff);
sys/dev/pci/drm/amd/amdgpu/cik.c
1302
WREG32(mmGMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/amd/amdgpu/cik.c
1304
WREG32(mmGMCON_PGFSM_WRITE, 0x120202);
sys/dev/pci/drm/amd/amdgpu/cik.c
1305
WREG32(mmGMCON_PGFSM_CONFIG, 0x500010ff);
sys/dev/pci/drm/amd/amdgpu/cik.c
1308
WREG32(mmGMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/amd/amdgpu/cik.c
1310
WREG32(mmGMCON_PGFSM_WRITE, 0x3e3e36);
sys/dev/pci/drm/amd/amdgpu/cik.c
1311
WREG32(mmGMCON_PGFSM_CONFIG, 0x600010ff);
sys/dev/pci/drm/amd/amdgpu/cik.c
1314
WREG32(mmGMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/amd/amdgpu/cik.c
1316
WREG32(mmGMCON_PGFSM_WRITE, 0x373f3e);
sys/dev/pci/drm/amd/amdgpu/cik.c
1317
WREG32(mmGMCON_PGFSM_CONFIG, 0x700010ff);
sys/dev/pci/drm/amd/amdgpu/cik.c
1320
WREG32(mmGMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/amd/amdgpu/cik.c
1322
WREG32(mmGMCON_PGFSM_WRITE, 0x3e1332);
sys/dev/pci/drm/amd/amdgpu/cik.c
1323
WREG32(mmGMCON_PGFSM_CONFIG, 0xe00010ff);
sys/dev/pci/drm/amd/amdgpu/cik.c
1325
WREG32(mmGMCON_MISC3, save->gmcon_misc3);
sys/dev/pci/drm/amd/amdgpu/cik.c
1326
WREG32(mmGMCON_MISC, save->gmcon_misc);
sys/dev/pci/drm/amd/amdgpu/cik.c
1327
WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute);
sys/dev/pci/drm/amd/amdgpu/cik.c
158
WREG32(mmPCIE_INDEX, reg);
sys/dev/pci/drm/amd/amdgpu/cik.c
170
WREG32(mmPCIE_INDEX, reg);
sys/dev/pci/drm/amd/amdgpu/cik.c
172
WREG32(mmPCIE_DATA, v);
sys/dev/pci/drm/amd/amdgpu/cik.c
183
WREG32(mmSMC_IND_INDEX_0, (reg));
sys/dev/pci/drm/amd/amdgpu/cik.c
1861
WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
sys/dev/pci/drm/amd/amdgpu/cik.c
1872
WREG32(mmHDP_DEBUG0, 1);
sys/dev/pci/drm/amd/amdgpu/cik.c
194
WREG32(mmSMC_IND_INDEX_0, (reg));
sys/dev/pci/drm/amd/amdgpu/cik.c
195
WREG32(mmSMC_IND_DATA_0, (v));
sys/dev/pci/drm/amd/amdgpu/cik.c
205
WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
sys/dev/pci/drm/amd/amdgpu/cik.c
216
WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
sys/dev/pci/drm/amd/amdgpu/cik.c
217
WREG32(mmUVD_CTX_DATA, (v));
sys/dev/pci/drm/amd/amdgpu/cik.c
227
WREG32(mmDIDT_IND_INDEX, (reg));
sys/dev/pci/drm/amd/amdgpu/cik.c
238
WREG32(mmDIDT_IND_INDEX, (reg));
sys/dev/pci/drm/amd/amdgpu/cik.c
239
WREG32(mmDIDT_IND_DATA, (v));
sys/dev/pci/drm/amd/amdgpu/cik.c
952
WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
sys/dev/pci/drm/amd/amdgpu/cik.c
964
WREG32(mmCONFIG_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/cik.c
985
WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
sys/dev/pci/drm/amd/amdgpu/cik.c
988
WREG32(mmD1VGA_CONTROL,
sys/dev/pci/drm/amd/amdgpu/cik.c
991
WREG32(mmD2VGA_CONTROL,
sys/dev/pci/drm/amd/amdgpu/cik.c
994
WREG32(mmVGA_RENDER_CONTROL,
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
116
WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
124
WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
126
WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
136
WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
137
WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
139
WREG32(mmIH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
142
WREG32(mmIH_RB_RPTR, 0);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
143
WREG32(mmIH_RB_WPTR, 0);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
152
WREG32(mmIH_CNTL, ih_cntl);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
206
WREG32(mmIH_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
212
WREG32(mmIH_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
283
WREG32(mmIH_RB_RPTR, ih->rptr);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
389
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
395
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
67
WREG32(mmIH_CNTL, ih_cntl);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
68
WREG32(mmIH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
86
WREG32(mmIH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
87
WREG32(mmIH_CNTL, ih_cntl);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
89
WREG32(mmIH_RB_RPTR, 0);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
90
WREG32(mmIH_RB_WPTR, 0);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1056
WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1062
WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1069
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1075
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1098
WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1103
WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1114
WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1119
WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
195
WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
316
WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
317
WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
376
WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
378
WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
386
WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
414
WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
440
WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
441
WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
447
WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
450
WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
451
WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
460
WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
463
WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
464
WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
465
WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
466
WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
469
WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
471
WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
476
WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
477
WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
480
WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
483
WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
491
WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
550
WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
552
WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
553
WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
879
WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
880
WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
885
WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
890
WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
903
WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
908
WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
913
WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
918
WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
116
WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
124
WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
127
WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
138
WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
139
WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
141
WREG32(mmIH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
144
WREG32(mmIH_RB_RPTR, 0);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
145
WREG32(mmIH_RB_WPTR, 0);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
153
WREG32(mmIH_CNTL, ih_cntl);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
217
WREG32(mmIH_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
223
WREG32(mmIH_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
274
WREG32(mmIH_RB_RPTR, ih->rptr);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
385
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
391
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
67
WREG32(mmIH_CNTL, ih_cntl);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
68
WREG32(mmIH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
86
WREG32(mmIH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
87
WREG32(mmIH_CNTL, ih_cntl);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
89
WREG32(mmIH_RB_RPTR, 0);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
90
WREG32(mmIH_RB_WPTR, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1127
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1131
WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1134
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1138
WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1140
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1221
WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1487
WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1490
WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1494
WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1497
WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1501
WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1504
WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1521
WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1523
WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1525
WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1527
WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1553
WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1554
WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1555
WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1596
WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1598
WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1625
WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1631
WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1638
WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1643
WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1648
WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1650
WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1657
WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1662
WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1673
WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1679
WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1683
WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1692
WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1696
WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1722
WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1726
WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1731
WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1733
WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1734
WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1735
WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1736
WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
179
WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1822
WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1824
WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1834
WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1836
WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
192
WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
193
WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2016
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2018
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2020
WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2022
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2024
WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2026
WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2027
WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2039
WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2044
WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2045
WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2046
WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2047
WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2048
WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2049
WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2052
WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2056
WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2061
WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2065
WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2069
WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2099
WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2116
WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2120
WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2124
WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2129
WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2131
WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2133
WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2134
WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2135
WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2137
WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2138
WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2139
WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2141
WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2142
WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2144
WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2149
WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2159
WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2164
WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2169
WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2174
WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2177
WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2183
WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2285
WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2296
WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2305
WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2307
WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2313
WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2340
WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2341
WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2342
WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
245
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
247
WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
250
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
253
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2701
WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2991
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2997
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3022
WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3028
WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3051
WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3057
WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3080
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3085
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3156
WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3159
WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
317
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3184
WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3230
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3245
WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3260
WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
351
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
357
WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
366
WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
400
WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
454
WREG32(mmVGA_HDP_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
462
WREG32(mmVGA_RENDER_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
494
WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
497
WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
498
WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
577
WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
630
WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
634
WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1016
WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1017
WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1024
WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1025
WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1029
WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1032
WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1033
WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1090
WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1093
WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1191
WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
142
WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1474
WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1491
WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1495
WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1498
WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1502
WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1505
WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1509
WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1512
WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1542
WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1544
WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1546
WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1548
WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
155
WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1555
WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
157
WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1582
WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1584
WREG32(mmDCCG_AUDIO_DTO0_PHASE, 24000);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1585
WREG32(mmDCCG_AUDIO_DTO0_MODULE, clock);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1587
WREG32(mmDCCG_AUDIO_DTO1_PHASE, 24000);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1588
WREG32(mmDCCG_AUDIO_DTO1_MODULE, clock);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1602
WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1606
WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1610
WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1619
WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1623
WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1628
WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1633
WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1646
WREG32(mmHDMI_GC + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1663
WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1667
WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1671
WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1678
WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1682
WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1697
WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1701
WREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1708
WREG32(mmDP_SEC_CNTL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1710
WREG32(mmDP_SEC_CNTL + dig->afmt->offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1865
WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0));
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1874
WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2034
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2036
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2038
WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2040
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2042
WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2044
WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2045
WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2059
WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2060
WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2061
WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2062
WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2063
WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2064
WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2067
WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2071
WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2075
WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
208
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2080
WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2084
WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
211
WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2110
WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2113
WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2126
WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2129
WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2131
WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2133
WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2137
WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2139
WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
214
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2140
WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2141
WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2143
WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2144
WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2145
WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2147
WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2148
WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2150
WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2155
WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2161
WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2166
WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2169
WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
217
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2172
WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2176
WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2258
WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2266
WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2276
WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2278
WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2281
WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2313
WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2314
WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2315
WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2668
WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
281
WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2929
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2935
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
296
WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2983
WREG32(mmINT_MASK + reg_block, interrupt_mask);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2988
WREG32(mmINT_MASK + reg_block, interrupt_mask);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3018
WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], dc_hpd_int_cntl);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3023
WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], dc_hpd_int_cntl);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3092
WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_STATUS__VBLANK_ACK_MASK);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3103
WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_STATUS__VLINE_ACK_MASK);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3131
WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3134
WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3159
WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
323
WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
334
WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
369
WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
414
WREG32(mmVGA_RENDER_CONTROL,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
446
WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
449
WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
450
WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
509
WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1082
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1083
WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1090
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1091
WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1095
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1176
WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
130
WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
143
WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
144
WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1466
WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT));
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1467
WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1469
WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1470
WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1472
WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1473
WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1490
WREG32(mmAFMT_AVI_INFO0 + offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1492
WREG32(mmAFMT_AVI_INFO1 + offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1494
WREG32(mmAFMT_AVI_INFO2 + offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1496
WREG32(mmAFMT_AVI_INFO3 + offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1518
WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1519
WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1520
WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1561
WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1564
WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1593
WREG32(mmHDMI_CONTROL + offset, val);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1595
WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1600
WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1604
WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1607
WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1610
WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1612
WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1616
WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1622
WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1625
WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1631
WREG32(mmAFMT_60958_0 + offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1634
WREG32(mmAFMT_60958_1 + offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1637
WREG32(mmAFMT_60958_2 + offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1648
WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1680
WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1681
WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1682
WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1683
WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1769
WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1771
WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1781
WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1783
WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
192
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1946
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1948
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
195
WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1950
WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1952
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1954
WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1956
WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1957
WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1971
WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1972
WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1973
WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1974
WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1975
WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1976
WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1979
WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
198
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1983
WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1988
WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1992
WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1996
WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
201
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2021
WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2024
WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2037
WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2040
WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2042
WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2044
WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2048
WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2050
WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2051
WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2052
WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2054
WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2055
WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2056
WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2058
WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2059
WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2061
WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2066
WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2072
WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2076
WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2079
WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2082
WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2086
WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2090
WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2206
WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2214
WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2224
WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2226
WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2229
WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2259
WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2260
WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2261
WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2627
WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
265
WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
280
WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2901
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2907
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2955
WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2960
WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3006
WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3011
WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3034
WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3039
WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
307
WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3108
WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3119
WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3147
WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3150
WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3175
WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
318
WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
353
WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
405
WREG32(mmVGA_HDP_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
413
WREG32(mmVGA_RENDER_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
452
WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
455
WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
456
WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
532
WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
583
WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
587
WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
106
WREG32(address, lo_addr);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
108
WREG32(address, hi_addr);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
128
WREG32(address, lo_addr);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
129
WREG32(data, lo_val);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
130
WREG32(address, hi_addr);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
131
WREG32(data, hi_val);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
147
WREG32(address, lo_addr);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
148
WREG32(data, lo_val);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
149
WREG32(address, hi_addr);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
150
WREG32(data, hi_val);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
152
WREG32(address, lo_addr);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
154
WREG32(address, hi_addr);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
55
WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
56
WREG32(data, ficaa_val);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
58
WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
61
WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
78
WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
79
WREG32(data, ficaa_val);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
81
WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
82
WREG32(data, ficadl_val);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
84
WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
85
WREG32(data, ficadh_val);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4041
WREG32(scratch, 0xCAFEDEAD);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5190
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5191
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5193
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5194
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8226
WREG32(reg_idx, reg_data);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8234
WREG32(reg_idx, reg_data);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8244
WREG32(reg_idx, reg_data);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2309
WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
571
WREG32(scratch, 0xCAFEDEAD);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1969
WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
458
WREG32(scratch, 0xCAFEDEAD);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1074
WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1298
WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1326
WREG32(mmGRBM_GFX_INDEX, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1459
WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1498
WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1531
WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1564
WREG32(mmSPI_STATIC_THREAD_MGMT_3, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1634
WREG32(mmTCP_ADDR_CONFIG, tcp_addr_config);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1635
WREG32(mmTCP_CHAN_STEER_HI, upper_32_bits(patched_chan_steer));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1636
WREG32(mmTCP_CHAN_STEER_LO, lower_32_bits(patched_chan_steer));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1743
WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1744
WREG32(mmSRBM_INT_CNTL, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1745
WREG32(mmSRBM_INT_ACK, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1747
WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1780
WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1781
WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1782
WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1783
WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1784
WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1785
WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1789
WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1790
WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1791
WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1804
WREG32(mmCP_QUEUE_THRESHOLDS,
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1809
WREG32(mmCP_MEQ_THRESHOLDS,
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1814
WREG32(mmSX_DEBUG_1, sx_debug_1);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1816
WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1818
WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1823
WREG32(mmVGT_NUM_INSTANCES, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1824
WREG32(mmCP_PERFMON_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1825
WREG32(mmSQ_CONFIG, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1826
WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1829
WREG32(mmVGT_CACHE_INVALIDATION,
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1833
WREG32(mmVGT_GS_VERTEX_REUSE, 16);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1834
WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1836
WREG32(mmCB_PERFCOUNTER0_SELECT0, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1837
WREG32(mmCB_PERFCOUNTER0_SELECT1, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1838
WREG32(mmCB_PERFCOUNTER1_SELECT0, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1839
WREG32(mmCB_PERFCOUNTER1_SELECT1, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1840
WREG32(mmCB_PERFCOUNTER2_SELECT0, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1841
WREG32(mmCB_PERFCOUNTER2_SELECT1, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1842
WREG32(mmCB_PERFCOUNTER3_SELECT0, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1843
WREG32(mmCB_PERFCOUNTER3_SELECT1, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1846
WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1848
WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1861
WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1968
WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2005
WREG32(mmCP_ME_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2007
WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2010
WREG32(mmSCRATCH_UMSK, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2040
WREG32(mmCP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2042
WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2043
WREG32(mmCP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2049
WREG32(mmCP_CE_UCODE_ADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2051
WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2052
WREG32(mmCP_CE_UCODE_ADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2058
WREG32(mmCP_ME_RAM_WADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2060
WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2061
WREG32(mmCP_ME_RAM_WADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2063
WREG32(mmCP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2064
WREG32(mmCP_CE_UCODE_ADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2065
WREG32(mmCP_ME_RAM_WADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2066
WREG32(mmCP_ME_RAM_RADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2143
WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2144
WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2147
WREG32(mmCP_RB_WPTR_DELAY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2149
WREG32(mmCP_DEBUG, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2150
WREG32(mmSCRATCH_ADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2161
WREG32(mmCP_RB0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2164
WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2166
WREG32(mmCP_RB0_WPTR, ring->wptr);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2170
WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2171
WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2173
WREG32(mmSCRATCH_UMSK, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2176
WREG32(mmCP_RB0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2178
WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2212
WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2221
WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2224
WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2249
WREG32(mmCP_RB1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2251
WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2253
WREG32(mmCP_RB1_WPTR, ring->wptr);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2256
WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2257
WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2260
WREG32(mmCP_RB1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2261
WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2269
WREG32(mmCP_RB2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2271
WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2273
WREG32(mmCP_RB2_WPTR, ring->wptr);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2275
WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2276
WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2279
WREG32(mmCP_RB2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2280
WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2315
WREG32(mmCP_INT_CNTL_RING0, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2482
WREG32(mmSPI_LB_CU_MASK, 0x00ff);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2509
WREG32(mmRLC_CNTL, rlc);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2520
WREG32(mmRLC_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2530
WREG32(mmRLC_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2538
WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2584
WREG32(mmRLC_RL_BASE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2585
WREG32(mmRLC_RL_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2586
WREG32(mmRLC_LB_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2587
WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2588
WREG32(mmRLC_LB_CNTR_INIT, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2589
WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2591
WREG32(mmRLC_MC_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2592
WREG32(mmRLC_UCODE_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2602
WREG32(mmRLC_UCODE_ADDR, i);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2603
WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2605
WREG32(mmRLC_UCODE_ADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2622
WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2626
WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2627
WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2628
WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2633
WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2648
WREG32(mmRLC_CGCG_CGLS_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2661
WREG32(mmCGTS_SM_CTRL_REG, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2667
WREG32(mmCP_MEM_SLP_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2673
WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2677
WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2678
WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2679
WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2686
WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2691
WREG32(mmCP_MEM_SLP_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2696
WREG32(mmCGTS_SM_CTRL_REG, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2700
WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2701
WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2702
WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2743
WREG32(mmRLC_PG_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2821
WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2834
WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2839
WREG32(mmRLC_MAX_PG_CU, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2853
WREG32(mmRLC_PG_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2867
WREG32(mmRLC_PG_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2874
WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2876
WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2882
WREG32(mmRLC_AUTO_PG_CTRL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2958
WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2959
WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2966
WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2967
WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2992
WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3011
WREG32(mmSQ_IND_INDEX,
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3023
WREG32(mmSQ_IND_INDEX,
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3267
WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3272
WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3289
WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3294
WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3302
WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3307
WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3330
WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3335
WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3355
WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3360
WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
644
WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
850
WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1186
WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1189
WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1369
WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1372
WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1539
WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1542
WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1581
WREG32(mmGRBM_GFX_INDEX, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1741
WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1742
WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1787
WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1788
WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1842
WREG32(mmSH_MEM_CONFIG, sh_mem_config);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1843
WREG32(mmSH_MEM_APE1_BASE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1844
WREG32(mmSH_MEM_APE1_LIMIT, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1845
WREG32(mmSH_MEM_BASES, sh_mem_bases);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1853
WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1854
WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1855
WREG32(amdgpu_gds_reg_offset[i].gws, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1856
WREG32(amdgpu_gds_reg_offset[i].oa, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1871
WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1872
WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1873
WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1874
WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1897
WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1899
WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1900
WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1901
WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1910
WREG32(mmCP_MEQ_THRESHOLDS,
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1937
WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1947
WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1948
WREG32(mmSH_MEM_APE1_BASE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1949
WREG32(mmSH_MEM_APE1_LIMIT, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1950
WREG32(mmSH_MEM_BASES, sh_mem_base);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1958
WREG32(mmSX_DEBUG_1, 0x20);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1960
WREG32(mmTA_CNTL_AUX, 0x00010000);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1964
WREG32(mmSPI_CONFIG_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1966
WREG32(mmSQ_CONFIG, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1968
WREG32(mmDB_DEBUG, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1972
WREG32(mmDB_DEBUG2, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1976
WREG32(mmDB_DEBUG3, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1980
WREG32(mmCB_HW_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1982
WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1984
WREG32(mmPA_SC_FIFO_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1990
WREG32(mmVGT_NUM_INSTANCES, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1992
WREG32(mmCP_PERFMON_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1994
WREG32(mmSQ_CONFIG, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1996
WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2000
WREG32(mmVGT_CACHE_INVALIDATION,
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2004
WREG32(mmVGT_GS_VERTEX_REUSE, 16);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2005
WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2007
WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2009
WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2016
WREG32(mmSPI_ARB_PRIORITY, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2040
WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2307
WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2375
WREG32(mmCP_ME_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2377
WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2423
WREG32(mmCP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2425
WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2426
WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2433
WREG32(mmCP_CE_UCODE_ADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2435
WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2436
WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2443
WREG32(mmCP_ME_RAM_WADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2445
WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2446
WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2468
WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2469
WREG32(mmCP_ENDIAN_SWAP, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2470
WREG32(mmCP_DEVICE_ID, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2544
WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2546
WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2549
WREG32(mmCP_RB_WPTR_DELAY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2552
WREG32(mmCP_RB_VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2554
WREG32(mmSCRATCH_ADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2564
WREG32(mmCP_RB0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2567
WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2569
WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2573
WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2574
WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2577
WREG32(mmSCRATCH_UMSK, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2580
WREG32(mmCP_RB0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2583
WREG32(mmCP_RB0_BASE, rb_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2584
WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2611
WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2641
WREG32(mmCP_MEC_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2643
WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2678
WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2680
WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2681
WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2700
WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2702
WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2703
WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2783
WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2784
WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2787
WREG32(mmCP_HPD_EOP_VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2793
WREG32(mmCP_HPD_EOP_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2805
WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2815
WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2816
WREG32(mmCP_HQD_PQ_RPTR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2817
WREG32(mmCP_HQD_PQ_WPTR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2955
WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2959
WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2963
WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3016
WREG32(mmCP_CPF_DEBUG, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3073
WREG32(mmCP_INT_CNTL_RING0, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3262
WREG32(mmRLC_LB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3301
WREG32(mmRLC_CNTL, rlc);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3314
WREG32(mmRLC_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3338
WREG32(mmRLC_GPR_REG2, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3360
WREG32(mmRLC_GPR_REG2, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3372
WREG32(mmRLC_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3388
WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3400
WREG32(mmGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3403
WREG32(mmGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3436
WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3442
WREG32(mmRLC_LB_CNTR_INIT, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3443
WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3447
WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3448
WREG32(mmRLC_LB_PARAMS, 0x00600408);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3449
WREG32(mmRLC_LB_CNTL, 0x80000004);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3452
WREG32(mmRLC_MC_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3453
WREG32(mmRLC_UCODE_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3458
WREG32(mmRLC_GPM_UCODE_ADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3460
WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3461
WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3467
WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3485
WREG32(mmRLC_SPM_VMID, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3503
WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3504
WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3508
WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3515
WREG32(mmRLC_CGCG_CGLS_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3527
WREG32(mmRLC_CGCG_CGLS_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3543
WREG32(mmCP_MEM_SLP_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3551
WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3557
WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3558
WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3561
WREG32(mmRLC_SERDES_WR_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3579
WREG32(mmCGTS_SM_CTRL_REG, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3585
WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3590
WREG32(mmRLC_MEM_SLP_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3596
WREG32(mmCP_MEM_SLP_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3602
WREG32(mmCGTS_SM_CTRL_REG, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3608
WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3609
WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3611
WREG32(mmRLC_SERDES_WR_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3644
WREG32(mmRLC_PG_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3658
WREG32(mmRLC_PG_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3671
WREG32(mmRLC_PG_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3684
WREG32(mmRLC_PG_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3704
WREG32(mmRLC_PG_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3709
WREG32(mmRLC_AUTO_PG_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3714
WREG32(mmRLC_PG_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3719
WREG32(mmRLC_AUTO_PG_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3736
WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3758
WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3763
WREG32(mmRLC_MAX_PG_CU, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3777
WREG32(mmRLC_PG_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3791
WREG32(mmRLC_PG_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3803
WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3804
WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3805
WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3806
WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3808
WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3810
WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3813
WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3815
WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3821
WREG32(mmRLC_PG_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3823
WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3824
WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3829
WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3832
WREG32(mmRLC_PG_DELAY, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3837
WREG32(mmRLC_PG_DELAY_2, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3842
WREG32(mmRLC_AUTO_PG_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3954
WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4009
WREG32(mmSQ_CMD, value);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4014
WREG32(mmSQ_IND_INDEX,
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4026
WREG32(mmSQ_IND_INDEX,
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4548
WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4551
WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4557
WREG32(mmGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4563
WREG32(mmGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4571
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4577
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4595
WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4600
WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4646
WREG32(mec_int_cntl_reg, mec_int_cntl);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4651
WREG32(mec_int_cntl_reg, mec_int_cntl);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4669
WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4674
WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4694
WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4699
WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1493
WREG32(mmGB_EDC_MODE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1620
WREG32(mmGB_EDC_MODE, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1624
WREG32(mmCC_GC_EDC_CONFIG, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
2245
WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
2249
WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
2435
WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
2439
WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
2624
WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
2628
WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
2827
WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
2831
WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3029
WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3033
WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3200
WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3204
WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3377
WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3381
WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3408
WREG32(mmGRBM_GFX_INDEX, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3574
WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3575
WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3613
WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3614
WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3673
WREG32(mmSH_MEM_CONFIG, sh_mem_config);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3674
WREG32(mmSH_MEM_APE1_BASE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3675
WREG32(mmSH_MEM_APE1_LIMIT, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3676
WREG32(mmSH_MEM_BASES, sh_mem_bases);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3684
WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3685
WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3686
WREG32(amdgpu_gds_reg_offset[i].gws, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3687
WREG32(amdgpu_gds_reg_offset[i].oa, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3702
WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3703
WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3704
WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3705
WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3728
WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3729
WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3730
WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3745
WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3756
WREG32(mmSH_MEM_CONFIG, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3757
WREG32(mmSH_MEM_BASES, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3763
WREG32(mmSH_MEM_CONFIG, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3765
WREG32(mmSH_MEM_BASES, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3768
WREG32(mmSH_MEM_APE1_BASE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3769
WREG32(mmSH_MEM_APE1_LIMIT, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3784
WREG32(mmPA_SC_FIFO_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3799
WREG32(mmSPI_ARB_PRIORITY, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3853
WREG32(mmCP_INT_CNTL_RING0, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3860
WREG32(mmRLC_CSIB_ADDR_HI,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3862
WREG32(mmRLC_CSIB_ADDR_LO,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3864
WREG32(mmRLC_CSIB_LENGTH,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3946
WREG32(mmRLC_SRM_ARAM_ADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3948
WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3951
WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3953
WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3957
WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3958
WREG32(mmRLC_GPM_SCRATCH_DATA, list_size);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3961
WREG32(mmRLC_GPM_SCRATCH_ADDR,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3964
WREG32(mmRLC_GPM_SCRATCH_DATA,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3972
WREG32(temp + i, unique_indices[i] & 0x3FFFF);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3973
WREG32(data + i, unique_indices[i] >> 20);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3996
WREG32(mmRLC_PG_DELAY, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4027
WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4029
WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4097
WREG32(mmCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4138
WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4139
WREG32(mmCP_ENDIAN_SWAP, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4140
WREG32(mmCP_DEVICE_ID, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4213
WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4221
WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4223
WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4235
WREG32(mmCP_RB_WPTR_DELAY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4238
WREG32(mmCP_RB_VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4250
WREG32(mmCP_RB0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4253
WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4255
WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4259
WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4260
WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4263
WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4264
WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4266
WREG32(mmCP_RB0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4269
WREG32(mmCP_RB0_BASE, rb_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4270
WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4283
WREG32(mmCP_MEC_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4285
WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4301
WREG32(mmRLC_CP_SCHEDULERS, tmp | 0x80);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4379
WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4380
WREG32(mmCP_HQD_PQ_RPTR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4381
WREG32(mmCP_HQD_PQ_WPTR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4560
WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4568
WREG32(mmCP_HQD_EOP_RPTR, mqd->cp_hqd_eop_rptr);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4569
WREG32(mmCP_HQD_EOP_WPTR, mqd->cp_hqd_eop_wptr);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4570
WREG32(mmCP_HQD_EOP_WPTR_MEM, mqd->cp_hqd_eop_wptr_mem);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4574
WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4578
WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4656
WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, adev->doorbell_index.kiq << 2);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4657
WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, adev->doorbell_index.mec_ring7 << 2);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5010
WREG32(mmGMCON_DEBUG, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5018
WREG32(mmGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5024
WREG32(mmGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5032
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5038
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5046
WREG32(mmGMCON_DEBUG, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5109
WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5157
WREG32(mmSQ_IND_INDEX,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5169
WREG32(mmSQ_IND_INDEX,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5448
WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5449
WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5479
WREG32(mmRLC_SERDES_WR_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5508
WREG32(mmRLC_SAFE_MODE, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5535
WREG32(mmRLC_SAFE_MODE, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5561
WREG32(mmRLC_SPM_VMID, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5610
WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5631
WREG32(mmCGTS_SM_CTRL_REG, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5645
WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5651
WREG32(mmRLC_MEM_SLP_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5658
WREG32(mmCP_MEM_SLP_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5666
WREG32(mmCGTS_SM_CTRL_REG, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5692
WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5717
WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5723
WREG32(mmRLC_CGCG_CGLS_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5738
WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5762
WREG32(mmRLC_CGCG_CGLS_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5994
WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6356
WREG32(mmSQ_CMD, value);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6405
WREG32(mec_int_cntl_reg, mec_int_cntl);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6410
WREG32(mec_int_cntl_reg, mec_int_cntl);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
7030
WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
845
WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1202
WREG32(scratch, 0xCAFEDEAD);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2577
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2578
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2580
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2581
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2849
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2852
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2855
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2859
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2864
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2892
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2894
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2897
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2900
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2906
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2910
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2936
WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2942
WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2947
WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2962
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2970
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2975
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2980
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2987
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3004
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3018
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3032
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3045
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3058
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3075
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3088
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1522
WREG32(SOC15_REG_ENTRY_OFFSET(
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1538
WREG32(SOC15_REG_ENTRY_OFFSET(
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1625
WREG32(SOC15_REG_ENTRY_OFFSET(blk->idx_reg), j);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1629
WREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1644
WREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1699
WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), value);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1738
WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), reg_value);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
779
WREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_PER_VMID_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
785
WREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_TRAP_DATA0), 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
786
WREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_TRAP_DATA1), 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1788
WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1790
WREG32(mec_ucode_data_offset,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1793
WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
427
WREG32(scratch_reg0_offset, 0xCAFEDEAD);
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
906
WREG32(hub->vm_contexts_disable, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
100
WREG32(mmBIF_FB_EN, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1014
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1020
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1049
WREG32(mmVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1052
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1057
WREG32(mmVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1060
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
173
WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
174
WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
178
WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
179
WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
183
WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
186
WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
187
WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
188
WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
227
WREG32((0xb05 + j), 0x00000000);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
228
WREG32((0xb06 + j), 0x00000000);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
229
WREG32((0xb07 + j), 0x00000000);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
230
WREG32((0xb08 + j), 0x00000000);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
231
WREG32((0xb09 + j), 0x00000000);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
233
WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
248
WREG32(mmVGA_HDP_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
253
WREG32(mmVGA_RENDER_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
256
WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
258
WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
260
WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
262
WREG32(mmMC_VM_AGP_BASE, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
263
WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
264
WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
357
WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
412
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
443
WREG32(mmVM_PRT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
451
WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
452
WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
453
WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
454
WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
455
WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
456
WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
457
WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
458
WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
460
WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
461
WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
462
WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
463
WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
464
WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
465
WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
466
WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
467
WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
486
WREG32(mmMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
494
WREG32(mmVM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
501
WREG32(mmVM_L2_CNTL2,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
506
WREG32(mmVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
511
WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
512
WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
513
WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
514
WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
516
WREG32(mmVM_CONTEXT0_CNTL2, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
517
WREG32(mmVM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
522
WREG32(0x575, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
523
WREG32(0x576, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
524
WREG32(0x577, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
528
WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
529
WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
536
WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
539
WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
544
WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
546
WREG32(mmVM_CONTEXT1_CNTL2, 4);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
547
WREG32(mmVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
594
WREG32(mmVM_CONTEXT0_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
595
WREG32(mmVM_CONTEXT1_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
597
WREG32(mmMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
601
WREG32(mmVM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
606
WREG32(mmVM_L2_CNTL2, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
607
WREG32(mmVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
681
WREG32(mc_cg_registers[i], data);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
698
WREG32(mc_cg_registers[i], data);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
738
WREG32(mmHDP_HOST_PATH_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
754
WREG32(mmHDP_MEM_POWER_LS, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
78
WREG32(mmBIF_FB_EN, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
82
WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
96
WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
102
WREG32(mmBIF_FB_EN, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
106
WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
119
WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1198
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1204
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
123
WREG32(mmBIF_FB_EN, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1235
WREG32(mmVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1239
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1245
WREG32(mmVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1249
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
203
WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
204
WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
208
WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
209
WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
213
WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
216
WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
217
WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
218
WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
270
WREG32((0xb05 + j), 0x00000000);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
271
WREG32((0xb06 + j), 0x00000000);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
272
WREG32((0xb07 + j), 0x00000000);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
273
WREG32((0xb08 + j), 0x00000000);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
274
WREG32((0xb09 + j), 0x00000000);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
276
WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
285
WREG32(mmVGA_HDP_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
290
WREG32(mmVGA_RENDER_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
293
WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
295
WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
297
WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
299
WREG32(mmMC_VM_AGP_BASE, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
300
WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
301
WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
305
WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
309
WREG32(mmHDP_MISC_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
312
WREG32(mmHDP_HOST_PATH_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
449
WREG32(mmVM_INVALIDATE_REQUEST, mask);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
474
WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
540
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
573
WREG32(mmVM_PRT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
581
WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
582
WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
583
WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
584
WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
585
WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
586
WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
587
WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
588
WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
590
WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
591
WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
592
WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
593
WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
594
WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
595
WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
596
WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
597
WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
632
WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
642
WREG32(mmVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
645
WREG32(mmVM_L2_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
652
WREG32(mmVM_L2_CNTL3, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
654
WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
655
WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
656
WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
657
WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
659
WREG32(mmVM_CONTEXT0_CNTL2, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
664
WREG32(mmVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
666
WREG32(0x575, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
667
WREG32(0x576, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
668
WREG32(0x577, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
675
WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
676
WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
679
WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
682
WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
687
WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
689
WREG32(mmVM_CONTEXT1_CNTL2, 4);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
695
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
704
WREG32(mmCHUB_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
743
WREG32(mmVM_CONTEXT0_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
744
WREG32(mmVM_CONTEXT1_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
750
WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
754
WREG32(mmVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
755
WREG32(mmVM_L2_CNTL2, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
839
WREG32(mc_cg_registers[i], data);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
856
WREG32(mc_cg_registers[i], data);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
896
WREG32(mmHDP_HOST_PATH_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
912
WREG32(mmHDP_MEM_POWER_LS, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1360
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1366
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1406
WREG32(mmVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1410
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1416
WREG32(mmVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1420
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1511
WREG32(mmMC_HUB_MISC_HUB_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1515
WREG32(mmMC_HUB_MISC_SIP_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1519
WREG32(mmMC_HUB_MISC_VM_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1523
WREG32(mmMC_XPB_CLK_GAT, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1527
WREG32(mmATC_MISC_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1531
WREG32(mmMC_CITF_MISC_WR_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1535
WREG32(mmMC_CITF_MISC_RD_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1539
WREG32(mmMC_CITF_MISC_VM_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1543
WREG32(mmVM_L2_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1547
WREG32(mmMC_HUB_MISC_HUB_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1551
WREG32(mmMC_HUB_MISC_SIP_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1555
WREG32(mmMC_HUB_MISC_VM_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1559
WREG32(mmMC_XPB_CLK_GAT, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1563
WREG32(mmATC_MISC_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1567
WREG32(mmMC_CITF_MISC_WR_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1571
WREG32(mmMC_CITF_MISC_RD_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1575
WREG32(mmMC_CITF_MISC_VM_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1579
WREG32(mmVM_L2_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1591
WREG32(mmMC_HUB_MISC_HUB_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1595
WREG32(mmMC_HUB_MISC_SIP_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1599
WREG32(mmMC_HUB_MISC_VM_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1603
WREG32(mmMC_XPB_CLK_GAT, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1607
WREG32(mmATC_MISC_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1611
WREG32(mmMC_CITF_MISC_WR_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1615
WREG32(mmMC_CITF_MISC_RD_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1619
WREG32(mmMC_CITF_MISC_VM_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1623
WREG32(mmVM_L2_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1627
WREG32(mmMC_HUB_MISC_HUB_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1631
WREG32(mmMC_HUB_MISC_SIP_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1635
WREG32(mmMC_HUB_MISC_VM_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1639
WREG32(mmMC_XPB_CLK_GAT, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1643
WREG32(mmATC_MISC_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1647
WREG32(mmMC_CITF_MISC_WR_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1651
WREG32(mmMC_CITF_MISC_RD_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1655
WREG32(mmMC_CITF_MISC_VM_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1659
WREG32(mmVM_L2_CG, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
184
WREG32(mmBIF_FB_EN, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
188
WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
201
WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
205
WREG32(mmBIF_FB_EN, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
245
WREG32(mmMC_SEQ_IO_DEBUG_INDEX, ixMC_IO_DEBUG_UP_159);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
313
WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
314
WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
318
WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
319
WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
323
WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
326
WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
327
WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
328
WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
380
WREG32(mmMC_SEQ_MISC0, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
384
WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
385
WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
388
WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
389
WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
393
WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
396
WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
397
WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
398
WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
441
WREG32((0xb05 + j), 0x00000000);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
442
WREG32((0xb06 + j), 0x00000000);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
443
WREG32((0xb07 + j), 0x00000000);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
444
WREG32((0xb08 + j), 0x00000000);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
445
WREG32((0xb09 + j), 0x00000000);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
447
WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
460
WREG32(mmVGA_HDP_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
465
WREG32(mmVGA_RENDER_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
468
WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
470
WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
472
WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
478
WREG32(mmMC_VM_FB_LOCATION, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
480
WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
481
WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
482
WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
485
WREG32(mmMC_VM_AGP_BASE, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
486
WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
487
WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
491
WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
495
WREG32(mmHDP_MISC_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
498
WREG32(mmHDP_HOST_PATH_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
640
WREG32(mmVM_INVALIDATE_REQUEST, mask);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
665
WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
757
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
790
WREG32(mmVM_PRT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
798
WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
799
WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
800
WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
801
WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
802
WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
803
WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
804
WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
805
WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
807
WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
808
WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
809
WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
810
WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
811
WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
812
WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
813
WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
814
WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
849
WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
859
WREG32(mmVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
863
WREG32(mmVM_L2_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
870
WREG32(mmVM_L2_CNTL3, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
885
WREG32(mmVM_L2_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
887
WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
888
WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
889
WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
890
WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
892
WREG32(mmVM_CONTEXT0_CNTL2, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
897
WREG32(mmVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
899
WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
900
WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
901
WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
908
WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
909
WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
912
WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
915
WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
920
WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
922
WREG32(mmVM_CONTEXT1_CNTL2, 4);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
935
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
977
WREG32(mmVM_CONTEXT0_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
978
WREG32(mmVM_CONTEXT1_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
984
WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
988
WREG32(mmVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
989
WREG32(mmVM_L2_CNTL2, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
433
WREG32(reg, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
439
WREG32(reg, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
447
WREG32(reg, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
453
WREG32(reg, tmp);
sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c
100
WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c
116
WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
116
WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
124
WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
127
WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
138
WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
139
WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
141
WREG32(mmIH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
144
WREG32(mmIH_RB_RPTR, 0);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
145
WREG32(mmIH_RB_WPTR, 0);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
153
WREG32(mmIH_CNTL, ih_cntl);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
216
WREG32(mmIH_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
222
WREG32(mmIH_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
273
WREG32(mmIH_RB_RPTR, ih->rptr);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
379
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
385
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
67
WREG32(mmIH_CNTL, ih_cntl);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
68
WREG32(mmIH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
86
WREG32(mmIH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
87
WREG32(mmIH_CNTL, ih_cntl);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
89
WREG32(mmIH_RB_RPTR, 0);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
90
WREG32(mmIH_RB_WPTR, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
174
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
181
WREG32(ih_regs->ih_rb_rptr, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
182
WREG32(ih_regs->ih_rb_wptr, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
274
WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
275
WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
292
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
297
WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
298
WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
302
WREG32(ih_regs->ih_rb_wptr, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
303
WREG32(ih_regs->ih_rb_rptr, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
305
WREG32(ih_regs->ih_doorbell_rptr, ih_v6_0_doorbell_rptr(ih));
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
526
WREG32(ih_regs->ih_rb_rptr, ih->rptr);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
146
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
153
WREG32(ih_regs->ih_rb_rptr, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
154
WREG32(ih_regs->ih_rb_wptr, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
246
WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
247
WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
264
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
269
WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
270
WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
274
WREG32(ih_regs->ih_rb_wptr, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
275
WREG32(ih_regs->ih_rb_rptr, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
277
WREG32(ih_regs->ih_doorbell_rptr, ih_v6_1_doorbell_rptr(ih));
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
495
WREG32(ih_regs->ih_rb_rptr, ih->rptr);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
146
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
153
WREG32(ih_regs->ih_rb_rptr, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
154
WREG32(ih_regs->ih_rb_wptr, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
246
WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
247
WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
264
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
269
WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
270
WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
274
WREG32(ih_regs->ih_rb_wptr, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
275
WREG32(ih_regs->ih_rb_rptr, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
277
WREG32(ih_regs->ih_doorbell_rptr, ih_v7_0_doorbell_rptr(ih));
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
492
WREG32(ih_regs->ih_rb_rptr, ih->rptr);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
236
WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
250
WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
264
WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
267
WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c
294
WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c
329
WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
331
WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
366
WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
377
WREG32(SOC15_REG_OFFSET(JPEG, inst, regUVD_IPX_DLDO_CONFIG),
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
402
WREG32(SOC15_REG_OFFSET(JPEG, inst, regUVD_IPX_DLDO_CONFIG),
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
433
WREG32(SOC15_REG_OFFSET(JPEG, inst_idx, regUVD_IPX_DLDO_CONFIG),
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
293
WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_IPX_DLDO_CONFIG),
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
464
WREG32(reg, value);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
489
WREG32(reg, value);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
1298
WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i]), 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
1344
WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i]),
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
172
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
179
WREG32(ih_regs->ih_rb_rptr, 0);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
180
WREG32(ih_regs->ih_rb_wptr, 0);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
272
WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
273
WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
288
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
293
WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
294
WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
298
WREG32(ih_regs->ih_rb_wptr, 0);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
299
WREG32(ih_regs->ih_rb_rptr, 0);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
301
WREG32(ih_regs->ih_doorbell_rptr, navi10_ih_doorbell_rptr(ih));
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
505
WREG32(ih_regs->ih_rb_rptr, ih->rptr);
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
131
WREG32(reg, doorbell_range);
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
152
WREG32(reg, doorbell_range);
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
102
WREG32(reg, doorbell_range);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
101
WREG32(reg, doorbell_range);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
81
WREG32(reg, doorbell_range);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
176
WREG32(reg, doorbell_range);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
205
WREG32(reg, doorbell_range);
sys/dev/pci/drm/amd/amdgpu/nv.c
287
WREG32(address, (reg));
sys/dev/pci/drm/amd/amdgpu/nv.c
301
WREG32(address, (reg));
sys/dev/pci/drm/amd/amdgpu/nv.c
302
WREG32(data, (v));
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
421
WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c
233
WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
323
WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
1002
WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
1013
WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
1018
WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
221
WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
346
WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
349
WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
389
WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
415
WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
416
WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
421
WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
424
WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
435
WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
438
WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
439
WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
440
WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
441
WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
444
WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
446
WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
451
WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
452
WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
455
WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
459
WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
467
WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
953
WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
960
WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
968
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
974
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
997
WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1306
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1312
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1335
WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1340
WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1351
WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1356
WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1442
WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1457
WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1475
WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1483
WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
396
WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
522
WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
525
WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
586
WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
588
WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
598
WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
626
WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
655
WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
656
WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
661
WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
664
WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
675
WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
679
WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
681
WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
682
WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
685
WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
687
WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
692
WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
693
WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
704
WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
709
WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
711
WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
716
WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
725
WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
729
WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
737
WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
126
WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1262
WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1268
WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1280
WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1286
WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1296
WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4.c
245
WREG32(reg_offset, 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4.c
247
WREG32(reg_offset, 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
101
WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1576
WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1597
WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1601
WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1618
WREG32(sdma_v5_0_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE), freeze);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1650
WREG32(sdma_gfx_preempt, 1);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1666
WREG32(sdma_gfx_preempt, 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1688
WREG32(reg_offset, sdma_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1780
WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1793
WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1810
WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1817
WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
643
WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
674
WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
702
WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
761
WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
763
WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
798
WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
804
WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
811
WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
818
WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
905
WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
910
WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
913
WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1484
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1506
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1510
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1528
WREG32(sdma_v5_2_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE), freeze);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1559
WREG32(sdma_gfx_preempt, 1);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1575
WREG32(sdma_gfx_preempt, 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1594
WREG32(reg_offset, sdma_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1744
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1755
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1777
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1784
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
235
WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
237
WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
248
WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
250
WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
491
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
521
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
609
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
610
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
645
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
665
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
752
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
757
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
760
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1543
WREG32(sdma_gfx_preempt, 1);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1559
WREG32(sdma_gfx_preempt, 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1604
WREG32(reg_offset, sdma_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
439
WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL), f32_cntl);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
693
WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
698
WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
708
WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
713
WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
727
WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
732
WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
735
WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
744
WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
749
WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
752
WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1503
WREG32(sdma_gfx_preempt, 1);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1519
WREG32(sdma_gfx_preempt, 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1538
WREG32(reg_offset, sdma_cntl);
sys/dev/pci/drm/amd/amdgpu/si.c
1038
WREG32(AMDGPU_PCIE_INDEX, reg);
sys/dev/pci/drm/amd/amdgpu/si.c
1050
WREG32(AMDGPU_PCIE_INDEX, reg);
sys/dev/pci/drm/amd/amdgpu/si.c
1052
WREG32(AMDGPU_PCIE_DATA, v);
sys/dev/pci/drm/amd/amdgpu/si.c
1063
WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
sys/dev/pci/drm/amd/amdgpu/si.c
1075
WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
sys/dev/pci/drm/amd/amdgpu/si.c
1077
WREG32(PCIE_PORT_DATA, (v));
sys/dev/pci/drm/amd/amdgpu/si.c
1088
WREG32(mmSMC_IND_INDEX_0, (reg));
sys/dev/pci/drm/amd/amdgpu/si.c
1099
WREG32(mmSMC_IND_INDEX_0, (reg));
sys/dev/pci/drm/amd/amdgpu/si.c
1100
WREG32(mmSMC_IND_DATA_0, (v));
sys/dev/pci/drm/amd/amdgpu/si.c
1110
WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
sys/dev/pci/drm/amd/amdgpu/si.c
1121
WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
sys/dev/pci/drm/amd/amdgpu/si.c
1122
WREG32(mmUVD_CTX_DATA, (v));
sys/dev/pci/drm/amd/amdgpu/si.c
1290
WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
sys/dev/pci/drm/amd/amdgpu/si.c
1293
WREG32(mmD1VGA_CONTROL,
sys/dev/pci/drm/amd/amdgpu/si.c
1296
WREG32(mmD2VGA_CONTROL,
sys/dev/pci/drm/amd/amdgpu/si.c
1299
WREG32(mmVGA_RENDER_CONTROL,
sys/dev/pci/drm/amd/amdgpu/si.c
1302
WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
sys/dev/pci/drm/amd/amdgpu/si.c
1307
WREG32(mmBUS_CNTL, bus_cntl);
sys/dev/pci/drm/amd/amdgpu/si.c
1309
WREG32(mmD1VGA_CONTROL, d1vga_control);
sys/dev/pci/drm/amd/amdgpu/si.c
1310
WREG32(mmD2VGA_CONTROL, d2vga_control);
sys/dev/pci/drm/amd/amdgpu/si.c
1311
WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
sys/dev/pci/drm/amd/amdgpu/si.c
1313
WREG32(R600_ROM_CNTL, rom_cntl);
sys/dev/pci/drm/amd/amdgpu/si.c
1337
WREG32(mmROM_INDEX, 0);
sys/dev/pci/drm/amd/amdgpu/si.c
1350
WREG32(mmCG_SPLL_FUNC_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/si.c
1354
WREG32(mmCG_SPLL_FUNC_CNTL_2, tmp);
sys/dev/pci/drm/amd/amdgpu/si.c
1365
WREG32(mmCG_SPLL_FUNC_CNTL_2, tmp);
sys/dev/pci/drm/amd/amdgpu/si.c
1369
WREG32(MPLL_CNTL_MODE, tmp);
sys/dev/pci/drm/amd/amdgpu/si.c
1378
WREG32(mmSPLL_CNTL_MODE, tmp);
sys/dev/pci/drm/amd/amdgpu/si.c
1382
WREG32(mmCG_SPLL_FUNC_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/si.c
1386
WREG32(mmCG_SPLL_FUNC_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/si.c
1390
WREG32(mmSPLL_CNTL_MODE, tmp);
sys/dev/pci/drm/amd/amdgpu/si.c
1479
WREG32(mmCONFIG_CNTL, temp);
sys/dev/pci/drm/amd/amdgpu/si.c
1501
WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
sys/dev/pci/drm/amd/amdgpu/si.c
1512
WREG32(mmHDP_DEBUG0, 1);
sys/dev/pci/drm/amd/amdgpu/si.c
2390
WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
sys/dev/pci/drm/amd/amdgpu/si.c
2401
WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
sys/dev/pci/drm/amd/amdgpu/si.c
2402
WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
sys/dev/pci/drm/amd/amdgpu/si.c
2412
WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
sys/dev/pci/drm/amd/amdgpu/si.c
2423
WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
sys/dev/pci/drm/amd/amdgpu/si.c
2424
WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
sys/dev/pci/drm/amd/amdgpu/si.c
2575
WREG32(mmTHM_CLK_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/si.c
2581
WREG32(mmMISC_CLK_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/si.c
2586
WREG32(mmCG_CLKPIN_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/si.c
2591
WREG32(mmCG_CLKPIN_CNTL_2, data);
sys/dev/pci/drm/amd/amdgpu/si.c
2597
WREG32(mmMPLL_BYPASSCLK_SEL, data);
sys/dev/pci/drm/amd/amdgpu/si.c
2602
WREG32(mmSPLL_CNTL_MODE, data);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
138
WREG32(mmDMA_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
152
WREG32(mmDMA_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
153
WREG32(mmDMA_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
161
WREG32(mmDMA_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
164
WREG32(mmDMA_GFX_RB_RPTR + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
165
WREG32(mmDMA_GFX_RB_WPTR + sdma_offsets[i], 0);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
169
WREG32(mmDMA_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr));
sys/dev/pci/drm/amd/amdgpu/si_dma.c
170
WREG32(mmDMA_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], upper_32_bits(rptr_addr) & 0xFF);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
174
WREG32(mmDMA_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
181
WREG32(mmDMA_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
185
WREG32(mmDMA_CNTL + sdma_offsets[i], dma_cntl);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
188
WREG32(mmDMA_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
189
WREG32(mmDMA_GFX_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_GFX_RB_CNTL__RB_ENABLE_MASK);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
604
WREG32(mmDMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
609
WREG32(mmDMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
620
WREG32(mmDMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
625
WREG32(mmDMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
667
WREG32(mmDMA_POWER_CNTL + offset, data);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
668
WREG32(mmDMA_CLK_CTRL + offset, 0x00000100);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
679
WREG32(mmDMA_POWER_CNTL + offset, data);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
684
WREG32(mmDMA_CLK_CTRL + offset, data);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
698
WREG32(mmDMA_PGFSM_WRITE, 0x00002000);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
699
WREG32(mmDMA_PGFSM_CONFIG, 0x100010ff);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
702
WREG32(mmDMA_PGFSM_WRITE, 0);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
75
WREG32(mmDMA_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
122
WREG32(IH_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
128
WREG32(IH_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
157
WREG32(IH_RB_RPTR, ih->rptr);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
252
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
258
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
43
WREG32(IH_CNTL, ih_cntl);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
44
WREG32(IH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
55
WREG32(IH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
56
WREG32(IH_CNTL, ih_cntl);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
57
WREG32(IH_RB_RPTR, 0);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
58
WREG32(IH_RB_WPTR, 0);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
71
WREG32(INTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
75
WREG32(INTERRUPT_CNTL, interrupt_cntl);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
77
WREG32(IH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
85
WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
sys/dev/pci/drm/amd/amdgpu/si_ih.c
86
WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
87
WREG32(IH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
88
WREG32(IH_RB_RPTR, 0);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
89
WREG32(IH_RB_WPTR, 0);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
94
WREG32(IH_CNTL, ih_cntl);
sys/dev/pci/drm/amd/amdgpu/soc15.c
1399
WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
sys/dev/pci/drm/amd/amdgpu/soc15.c
1414
WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
sys/dev/pci/drm/amd/amdgpu/soc15.c
249
WREG32(address, ((reg) & 0x1ff));
sys/dev/pci/drm/amd/amdgpu/soc15.c
263
WREG32(address, ((reg) & 0x1ff));
sys/dev/pci/drm/amd/amdgpu/soc15.c
264
WREG32(data, (v));
sys/dev/pci/drm/amd/amdgpu/soc15.c
277
WREG32(address, (reg));
sys/dev/pci/drm/amd/amdgpu/soc15.c
291
WREG32(address, (reg));
sys/dev/pci/drm/amd/amdgpu/soc15.c
292
WREG32(data, (v));
sys/dev/pci/drm/amd/amdgpu/soc15.c
500
WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp);
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
121
WREG32(r0, value); \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
122
WREG32(r1, (reg | 0x80000000)); \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
123
WREG32(spare_int, 0x1); \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
133
WREG32(reg, value); \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
160
WREG32(r2, value); \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
162
WREG32(r3, value); \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
163
WREG32(target_reg, value); \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
165
WREG32(target_reg, value); \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
43
WREG32(reg, value))
sys/dev/pci/drm/amd/amdgpu/soc21.c
202
WREG32(address, (reg));
sys/dev/pci/drm/amd/amdgpu/soc21.c
216
WREG32(address, (reg));
sys/dev/pci/drm/amd/amdgpu/soc21.c
217
WREG32(data, (v));
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
112
WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
120
WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
123
WREG32(mmIH_RB_BASE, ih->gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
135
WREG32(mmIH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
138
WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
139
WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
142
WREG32(mmIH_RB_RPTR, 0);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
143
WREG32(mmIH_RB_WPTR, 0);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
155
WREG32(mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
220
WREG32(mmIH_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
226
WREG32(mmIH_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
282
WREG32(mmIH_RB_RPTR, ih->rptr);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
435
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
441
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
66
WREG32(mmIH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
83
WREG32(mmIH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
85
WREG32(mmIH_RB_RPTR, 0);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
86
WREG32(mmIH_RB_WPTR, 0);
sys/dev/pci/drm/amd/amdgpu/umc_v6_0.c
32
WREG32((i*0x100000 + 0x5010c + j*0x2000)/4, 0x1002);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
146
WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
229
WREG32(mmUVD_CGC_CTRL, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
252
WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
253
WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
257
WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
258
WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
263
WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
264
WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
268
WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
272
WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
274
WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
275
WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
276
WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
297
WREG32(mmUVD_FW_START, keysel);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
344
WREG32(mmUVD_CGC_GATE, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
351
WREG32(mmUVD_VCPU_CNTL, 1 << 9);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
361
WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
362
WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
365
WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
369
WREG32(mmUVD_MPC_CNTL, tmp | 0x10);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
371
WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
372
WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
373
WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
374
WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
375
WREG32(mmUVD_MPC_SET_ALU, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
376
WREG32(mmUVD_MPC_SET_MUX, 0x88);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
424
WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
427
WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
430
WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
434
WREG32(mmUVD_RBC_RB_RPTR, 0x0);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
437
WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
440
WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
462
WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
505
WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
509
WREG32(mmUVD_STATUS, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
618
WREG32(mmUVD_CGC_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
627
WREG32(mmUVD_CGC_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
76
WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
301
WREG32(mmUVD_CGC_GATE, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
308
WREG32(mmUVD_VCPU_CNTL, 1 << 9);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
318
WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
319
WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
322
WREG32(mmUVD_LMI_CTRL, 0x203108);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
325
WREG32(mmUVD_MPC_CNTL, tmp | 0x10);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
327
WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
328
WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
329
WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
330
WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
331
WREG32(mmUVD_MPC_SET_ALU, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
332
WREG32(mmUVD_MPC_SET_MUX, 0x88);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
382
WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
385
WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
388
WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
392
WREG32(mmUVD_RBC_RB_RPTR, 0x0);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
395
WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
398
WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
420
WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
463
WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
467
WREG32(mmUVD_STATUS, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
518
WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
587
WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
588
WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
592
WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
593
WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
598
WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
599
WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
603
WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
607
WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
609
WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
610
WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
611
WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
627
WREG32(mmUVD_CGC_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
636
WREG32(mmUVD_CGC_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
663
WREG32(mmUVD_CGC_CTRL, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
740
WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK |
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
751
WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK |
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
90
WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
286
WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
288
WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
293
WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
294
WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
298
WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
299
WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
304
WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
305
WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
307
WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
308
WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
309
WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
344
WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
356
WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
364
WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
365
WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
367
WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
368
WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
369
WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
370
WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
371
WREG32(mmUVD_MPC_SET_ALU, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
372
WREG32(mmUVD_MPC_SET_MUX, 0x88);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
375
WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
379
WREG32(mmUVD_VCPU_CNTL, 1 << 9);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
385
WREG32(mmUVD_SOFT_RESET, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
428
WREG32(mmUVD_RBC_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
431
WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
434
WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
437
WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
439
WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
443
WREG32(mmUVD_RBC_RB_RPTR, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
446
WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
463
WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
470
WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
474
WREG32(mmUVD_VCPU_CNTL, 0x0);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
479
WREG32(mmUVD_STATUS, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
528
WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
675
WREG32(mmUVD_SUVD_CGC_GATE, data1);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
676
WREG32(mmUVD_CGC_GATE, data3);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
722
WREG32(mmUVD_CGC_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
723
WREG32(mmUVD_SUVD_CGC_CTRL, data2);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
762
WREG32(mmUVD_CGC_GATE, data);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
763
WREG32(mmUVD_SUVD_CGC_GATE, data1);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
780
WREG32(mmUVD_CGC_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
789
WREG32(mmUVD_CGC_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
88
WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1214
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1220
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1334
WREG32(mmUVD_SUVD_CGC_GATE, data1);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1335
WREG32(mmUVD_CGC_GATE, data3);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1382
WREG32(mmUVD_CGC_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1383
WREG32(mmUVD_SUVD_CGC_CTRL, data2);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
142
WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1424
WREG32(mmUVD_CGC_GATE, data);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1425
WREG32(mmUVD_SUVD_CGC_GATE, data1);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1442
WREG32(mmUVD_CGC_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1451
WREG32(mmUVD_CGC_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1489
WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
157
WREG32(mmUVD_RB_WPTR,
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
160
WREG32(mmUVD_RB_WPTR2,
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
612
WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
614
WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
619
WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
620
WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
624
WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
625
WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
630
WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
631
WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
633
WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
634
WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
635
WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
637
WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
714
WREG32(mmUVD_CGC_GATE, data);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
715
WREG32(mmUVD_SUVD_CGC_GATE, data1);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
751
WREG32(mmUVD_SOFT_RESET,
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
767
WREG32(mmUVD_LMI_CTRL,
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
780
WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
781
WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
783
WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
784
WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
785
WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
786
WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
787
WREG32(mmUVD_MPC_SET_ALU, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
788
WREG32(mmUVD_MPC_SET_MUX, 0x88);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
791
WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
795
WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
801
WREG32(mmUVD_SOFT_RESET, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
845
WREG32(mmUVD_RBC_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
848
WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
851
WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
854
WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
856
WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
860
WREG32(mmUVD_RBC_RB_RPTR, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
863
WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
869
WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
870
WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
871
WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
872
WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
873
WREG32(mmUVD_RB_SIZE, ring->ring_size / 4);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
876
WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
877
WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
878
WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
879
WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
880
WREG32(mmUVD_RB_SIZE2, ring->ring_size / 4);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
896
WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
903
WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
907
WREG32(mmUVD_VCPU_CNTL, 0x0);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
912
WREG32(mmUVD_STATUS, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
993
WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
144
WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
155
WREG32(mmVCE_CLOCK_GATING_A, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
160
WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
165
WREG32(mmVCE_CLOCK_GATING_B, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
175
WREG32(mmVCE_CLOCK_GATING_B, 0xf7);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
177
WREG32(mmVCE_LMI_CTRL, 0x00398000);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
179
WREG32(mmVCE_LMI_SWAP_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
180
WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
181
WREG32(mmVCE_LMI_VM_CTRL, 0);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
183
WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
187
WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
188
WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
192
WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
193
WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
197
WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
198
WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
244
WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
245
WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
246
WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
247
WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
248
WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
251
WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
252
WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
253
WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
254
WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
255
WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
311
WREG32(mmVCE_STATUS, 0);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
323
WREG32(mmVCE_CLOCK_GATING_B, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
327
WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
331
WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
333
WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
338
WREG32(mmVCE_CLOCK_GATING_B, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
343
WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
347
WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
364
WREG32(mmVCE_CLOCK_GATING_B, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
368
WREG32(mmVCE_CLOCK_GATING_B, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
375
WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
380
WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
383
WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
386
WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
94
WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
96
WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
117
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
119
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
128
WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
148
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
150
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
153
WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
155
WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
157
WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
159
WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
185
WREG32(mmVCE_CLOCK_GATING_B, data);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
190
WREG32(mmVCE_UENC_CLOCK_GATING, data);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
195
WREG32(mmVCE_UENC_CLOCK_GATING_2, data);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
199
WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
206
WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
211
WREG32(mmVCE_CLOCK_GATING_B, data);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
215
WREG32(mmVCE_UENC_CLOCK_GATING, data);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
219
WREG32(mmVCE_UENC_CLOCK_GATING_2, data);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
223
WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
230
WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
275
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
281
WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
282
WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
283
WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
284
WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
285
WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
288
WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
289
WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
290
WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
291
WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
292
WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
295
WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
296
WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
297
WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
298
WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
299
WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
325
WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
340
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
351
WREG32(mmVCE_STATUS, 0);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
354
WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
556
WREG32(mmVCE_CLOCK_GATING_B, 0x1FF);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
558
WREG32(mmVCE_LMI_CTRL, 0x00398000);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
560
WREG32(mmVCE_LMI_SWAP_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
561
WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
562
WREG32(mmVCE_LMI_VM_CTRL, 0);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
566
WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
567
WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
568
WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
570
WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
573
WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
574
WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
579
WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
580
WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
583
WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
584
WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
588
WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0xfffffff);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
589
WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
592
WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0xfffffff);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
593
WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
648
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
653
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
658
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
685
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
691
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
779
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(i));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
786
WREG32(mmVCE_CLOCK_GATING_A, data);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
792
WREG32(mmVCE_UENC_CLOCK_GATING, data);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
798
WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
85
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
87
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
96
WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
115
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
118
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
121
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
164
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO), lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
165
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI), upper_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
171
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID), data);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
174
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE), size);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
177
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP), 0);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
185
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST), 0x10000001);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
343
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR), lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
344
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
345
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO), ring->gpu_addr);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
346
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
347
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE), ring->ring_size / 4);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
351
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2), lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
352
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
353
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO2), ring->gpu_addr);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
354
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI2), upper_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
355
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE2), ring->ring_size / 4);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
359
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3), lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
360
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3), lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
361
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO3), ring->gpu_addr);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
362
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI3), upper_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
363
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE3), ring->ring_size / 4);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
400
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
638
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), 0x1FF);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
640
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL), 0x00398000);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
642
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL), 0);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
643
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
644
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
651
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
653
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
655
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), 0);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
657
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
659
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
661
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), offset & ~0x0f000000);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
665
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
667
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), (adev->vce.gpu_addr >> 8));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
668
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR1), (adev->vce.gpu_addr >> 40) & 0xff);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
671
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1), (offset & ~0x0f000000) | (1 << 24));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
672
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE1), size);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
674
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), (adev->vce.gpu_addr >> 8));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
675
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR2), (adev->vce.gpu_addr >> 40) & 0xff);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
678
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET2), (offset & ~0x0f000000) | (2 << 24));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
679
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE2), size);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1835
WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
117
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
124
WREG32(ih_regs->ih_rb_rptr, 0);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
125
WREG32(ih_regs->ih_rb_wptr, 0);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
217
WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
218
WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
232
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
237
WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
238
WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
242
WREG32(ih_regs->ih_rb_wptr, 0);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
243
WREG32(ih_regs->ih_rb_rptr, 0);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
245
WREG32(ih_regs->ih_doorbell_rptr, vega10_ih_doorbell_rptr(ih));
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
435
WREG32(ih_regs->ih_rb_rptr, ih->rptr);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
153
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
160
WREG32(ih_regs->ih_rb_rptr, 0);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
161
WREG32(ih_regs->ih_rb_wptr, 0);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
253
WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
254
WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
268
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
273
WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
274
WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
278
WREG32(ih_regs->ih_rb_wptr, 0);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
279
WREG32(ih_regs->ih_rb_rptr, 0);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
281
WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih));
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
520
WREG32(ih_regs->ih_rb_rptr, ih->rptr);
sys/dev/pci/drm/amd/amdgpu/vi.c
1233
WREG32(mmBIF_CLK_CTRL, data);
sys/dev/pci/drm/amd/amdgpu/vi.c
1293
WREG32(mmBIF_DOORBELL_APER_EN, tmp);
sys/dev/pci/drm/amd/amdgpu/vi.c
1313
WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
sys/dev/pci/drm/amd/amdgpu/vi.c
1324
WREG32(mmHDP_DEBUG0, 1);
sys/dev/pci/drm/amd/amdgpu/vi.c
1776
WREG32(mmHDP_HOST_PATH_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/vi.c
1792
WREG32(mmHDP_MEM_POWER_LS, data);
sys/dev/pci/drm/amd/amdgpu/vi.c
1808
WREG32(0x157a, data);
sys/dev/pci/drm/amd/amdgpu/vi.c
354
WREG32(mmMP0PUB_IND_INDEX, (reg));
sys/dev/pci/drm/amd/amdgpu/vi.c
365
WREG32(mmMP0PUB_IND_INDEX, (reg));
sys/dev/pci/drm/amd/amdgpu/vi.c
366
WREG32(mmMP0PUB_IND_DATA, (v));
sys/dev/pci/drm/amd/amdgpu/vi.c
376
WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
sys/dev/pci/drm/amd/amdgpu/vi.c
387
WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
sys/dev/pci/drm/amd/amdgpu/vi.c
388
WREG32(mmUVD_CTX_DATA, (v));
sys/dev/pci/drm/amd/amdgpu/vi.c
398
WREG32(mmDIDT_IND_INDEX, (reg));
sys/dev/pci/drm/amd/amdgpu/vi.c
409
WREG32(mmDIDT_IND_INDEX, (reg));
sys/dev/pci/drm/amd/amdgpu/vi.c
410
WREG32(mmDIDT_IND_DATA, (v));
sys/dev/pci/drm/amd/amdgpu/vi.c
420
WREG32(mmGC_CAC_IND_INDEX, (reg));
sys/dev/pci/drm/amd/amdgpu/vi.c
431
WREG32(mmGC_CAC_IND_INDEX, (reg));
sys/dev/pci/drm/amd/amdgpu/vi.c
432
WREG32(mmGC_CAC_IND_DATA, (v));
sys/dev/pci/drm/amd/amdgpu/vi.c
586
WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
sys/dev/pci/drm/amd/amdgpu/vi.c
607
WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
sys/dev/pci/drm/amd/amdgpu/vi.c
610
WREG32(mmD1VGA_CONTROL,
sys/dev/pci/drm/amd/amdgpu/vi.c
613
WREG32(mmD2VGA_CONTROL,
sys/dev/pci/drm/amd/amdgpu/vi.c
616
WREG32(mmVGA_RENDER_CONTROL,
sys/dev/pci/drm/amd/amdgpu/vi.c
624
WREG32(mmBUS_CNTL, bus_cntl);
sys/dev/pci/drm/amd/amdgpu/vi.c
626
WREG32(mmD1VGA_CONTROL, d1vga_control);
sys/dev/pci/drm/amd/amdgpu/vi.c
627
WREG32(mmD2VGA_CONTROL, d2vga_control);
sys/dev/pci/drm/amd/amdgpu/vi.c
628
WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
sys/dev/pci/drm/amd/amdgpu/vi.c
654
WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX);
sys/dev/pci/drm/amd/amdgpu/vi.c
655
WREG32(mmSMC_IND_DATA_11, 0);
sys/dev/pci/drm/amd/amdgpu/vi.c
657
WREG32(mmSMC_IND_INDEX_11, ixROM_DATA);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
112
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_COLLABORATE_CNTL), vpe_colla_cntl);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
119
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_COLLABORATE_CFG), vpe_colla_cfg);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
143
WREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL_6_1_1), ret);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
145
WREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL), ret);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
186
WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_ADDR), VPE_THREAD1_UCODE_OFFSET);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
188
WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_ADDR), 0);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
196
WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_DATA), le32_to_cpup(data++));
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
222
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
225
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR), 0);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
226
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_HI), 0);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
227
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR), 0);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
228
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR_HI), 0);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
231
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_ADDR_LO),
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
233
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_ADDR_HI),
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
238
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
239
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
244
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_MINOR_PTR_UPDATE), 1);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
245
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
246
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
248
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_MINOR_PTR_UPDATE), 0);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
252
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL_OFFSET), doorbell_offset);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
256
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL), doorbell);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
262
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
266
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_IB_CNTL), ib_cntl);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
291
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ_6_1_1), queue_reset);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
295
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ), queue_reset);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
326
WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL_6_1_1), vpe_cntl);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
328
WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL), vpe_cntl);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
82
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_F32_CNTL), f32_cntl);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
133
WREG32(mmDOUT_SCRATCH3, v);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
439
WREG32(config_regs->offset, data);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c
168
WREG32(mmSMC_IND_DATA_0, data);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c
181
WREG32(mmSMC_IND_DATA_0, data);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c
214
WREG32(mmSMC_IND_DATA_0, data);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c
37
WREG32(mmSMC_MESSAGE_0, id & SMC_MESSAGE_0__SMC_MSG_MASK);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c
72
WREG32(mmSMC_MSG_ARG_0, parameter);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c
85
WREG32(mmSMC_IND_INDEX_0, smc_address);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2781
WREG32(mmCG_CAC_CTRL, reg);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2878
WREG32(config_regs->offset, data);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3136
WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3137
WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3141
WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3142
WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3146
WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3147
WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3151
WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3152
WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3160
WREG32(MC_CG_CONFIG, mc_cg_config);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3738
WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3910
WREG32(mmSMC_SCRATCH0, parameter);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4129
WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4140
WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4226
WREG32(mmCG_DISPLAY_GAP_CNTL, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4236
WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4280
WREG32(mmCG_BSP, pi->dsp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4294
WREG32(mmCG_FFCT_0 + i, (r600_utc[i] << CG_FFCT_0__UTC_0__SHIFT | r600_dtc[i] << CG_FFCT_0__DTC_0__SHIFT));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4310
WREG32(mmCG_TPC, R600_TPC_DFLT);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4315
WREG32(mmCG_SSP, (R600_SSTU_DFLT << CG_SSP__SSTU__SHIFT| R600_SST_DFLT << CG_SSP__SST__SHIFT));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4329
WREG32(mmCG_DISPLAY_GAP_CNTL, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4336
WREG32(mmCG_FTV, pi->vrc);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4341
WREG32(mmCG_FTV, 0);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5316
WREG32(mmCG_ULV_CONTROL, ulv->cg_ulv_control);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5317
WREG32(mmCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6072
WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6073
WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6074
WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6075
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6076
WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6077
WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6078
WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6079
WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6080
WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6081
WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6082
WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6083
WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6084
WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6085
WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6477
WREG32(mmCG_THERMAL_INT, thermal_int);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6485
WREG32(mmCG_THERMAL_INT, thermal_int);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6531
WREG32(mmCG_FDO_CTRL2, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6535
WREG32(mmCG_FDO_CTRL2, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6691
WREG32(mmCG_FDO_CTRL0, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6781
WREG32(mmCG_TACH_CTRL, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6797
WREG32(mmCG_FDO_CTRL2, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6801
WREG32(mmCG_FDO_CTRL2, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6821
WREG32(mmCG_TACH_CTRL, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6826
WREG32(mmCG_FDO_CTRL2, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7615
WREG32(mmCG_THERMAL_INT, cg_thermal_int);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7620
WREG32(mmCG_THERMAL_INT, cg_thermal_int);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7632
WREG32(mmCG_THERMAL_INT, cg_thermal_int);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7637
WREG32(mmCG_THERMAL_INT, cg_thermal_int);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
108
WREG32(mmSMC_IND_DATA_0, data);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
194
WREG32(mmSMC_MESSAGE_0, msg);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
256
WREG32(mmSMC_IND_INDEX_0, ucode_start_address);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
262
WREG32(mmSMC_IND_DATA_0, data);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
297
WREG32(mmSMC_IND_DATA_0, value);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
47
WREG32(mmSMC_IND_INDEX_0, smc_address);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
77
WREG32(mmSMC_IND_DATA_0, data);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
53
WREG32(reg, value << shift);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
58
WREG32(reg, data);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu9_baco.c
39
WREG32(0x12074, 0xFFF0003B);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1654
WREG32(adev->bios_scratch_reg_offset + 6, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1655
WREG32(adev->bios_scratch_reg_offset + 7, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
2187
WREG32(adev->bios_scratch_reg_offset + 6, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
2188
WREG32(adev->bios_scratch_reg_offset + 7, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1815
WREG32(adev->bios_scratch_reg_offset + 6, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1816
WREG32(adev->bios_scratch_reg_offset + 7, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
243
WREG32(smu->resp_reg, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
244
WREG32(smu->param_reg, param);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
245
WREG32(smu->msg_reg, msg);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
302
WREG32(smu->debug_param_reg, param);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
303
WREG32(smu->debug_msg_reg, msg);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
304
WREG32(smu->debug_resp_reg, 0);
sys/dev/pci/drm/radeon/atombios_crtc.c
1359
WREG32(AVIVO_D1VGA_CONTROL, 0);
sys/dev/pci/drm/radeon/atombios_crtc.c
1362
WREG32(AVIVO_D2VGA_CONTROL, 0);
sys/dev/pci/drm/radeon/atombios_crtc.c
1365
WREG32(EVERGREEN_D3VGA_CONTROL, 0);
sys/dev/pci/drm/radeon/atombios_crtc.c
1368
WREG32(EVERGREEN_D4VGA_CONTROL, 0);
sys/dev/pci/drm/radeon/atombios_crtc.c
1371
WREG32(EVERGREEN_D5VGA_CONTROL, 0);
sys/dev/pci/drm/radeon/atombios_crtc.c
1374
WREG32(EVERGREEN_D6VGA_CONTROL, 0);
sys/dev/pci/drm/radeon/atombios_crtc.c
1383
WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/atombios_crtc.c
1385
WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/atombios_crtc.c
1387
WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/atombios_crtc.c
1389
WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/atombios_crtc.c
1391
WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/atombios_crtc.c
1393
WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
sys/dev/pci/drm/radeon/atombios_crtc.c
1394
WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
sys/dev/pci/drm/radeon/atombios_crtc.c
1408
WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/atombios_crtc.c
1409
WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/atombios_crtc.c
1410
WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/atombios_crtc.c
1411
WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/atombios_crtc.c
1412
WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
sys/dev/pci/drm/radeon/atombios_crtc.c
1413
WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
sys/dev/pci/drm/radeon/atombios_crtc.c
1416
WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
sys/dev/pci/drm/radeon/atombios_crtc.c
1417
WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
sys/dev/pci/drm/radeon/atombios_crtc.c
1420
WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/atombios_crtc.c
1423
WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/atombios_crtc.c
1427
WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/atombios_crtc.c
1434
WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/atombios_crtc.c
1438
WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/atombios_crtc.c
1590
WREG32(AVIVO_D1VGA_CONTROL, 0);
sys/dev/pci/drm/radeon/atombios_crtc.c
1592
WREG32(AVIVO_D2VGA_CONTROL, 0);
sys/dev/pci/drm/radeon/atombios_crtc.c
1597
WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/atombios_crtc.c
1601
WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
sys/dev/pci/drm/radeon/atombios_crtc.c
1602
WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
sys/dev/pci/drm/radeon/atombios_crtc.c
1604
WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
sys/dev/pci/drm/radeon/atombios_crtc.c
1605
WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
sys/dev/pci/drm/radeon/atombios_crtc.c
1608
WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/atombios_crtc.c
1610
WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
sys/dev/pci/drm/radeon/atombios_crtc.c
1612
WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
sys/dev/pci/drm/radeon/atombios_crtc.c
1614
WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
sys/dev/pci/drm/radeon/atombios_crtc.c
1623
WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/atombios_crtc.c
1624
WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/atombios_crtc.c
1625
WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/atombios_crtc.c
1626
WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/atombios_crtc.c
1627
WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
sys/dev/pci/drm/radeon/atombios_crtc.c
1628
WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
sys/dev/pci/drm/radeon/atombios_crtc.c
1631
WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
sys/dev/pci/drm/radeon/atombios_crtc.c
1632
WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
sys/dev/pci/drm/radeon/atombios_crtc.c
1634
WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/atombios_crtc.c
1638
WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/atombios_crtc.c
1642
WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/atombios_crtc.c
1646
WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
sys/dev/pci/drm/radeon/atombios_crtc.c
1704
WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
sys/dev/pci/drm/radeon/atombios_crtc.c
1709
WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
sys/dev/pci/drm/radeon/atombios_crtc.c
1710
WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
sys/dev/pci/drm/radeon/atombios_crtc.c
1711
WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
sys/dev/pci/drm/radeon/atombios_crtc.c
2168
WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/atombios_crtc.c
2170
WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/atombios_crtc.c
239
WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
sys/dev/pci/drm/radeon/atombios_crtc.c
248
WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
sys/dev/pci/drm/radeon/atombios_crtc.c
404
WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
sys/dev/pci/drm/radeon/atombios_crtc.c
409
WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
sys/dev/pci/drm/radeon/atombios_crtc.c
420
WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
sys/dev/pci/drm/radeon/atombios_crtc.c
425
WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
sys/dev/pci/drm/radeon/atombios_encoders.c
1546
WREG32(reg, (ATOM_S3_TV1_ACTIVE |
sys/dev/pci/drm/radeon/atombios_encoders.c
1549
WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
sys/dev/pci/drm/radeon/atombios_encoders.c
1551
WREG32(reg, 0);
sys/dev/pci/drm/radeon/atombios_encoders.c
1559
WREG32(reg, temp);
sys/dev/pci/drm/radeon/atombios_encoders.c
1620
WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
sys/dev/pci/drm/radeon/atombios_encoders.c
1622
WREG32(RADEON_BIOS_3_SCRATCH, reg);
sys/dev/pci/drm/radeon/atombios_encoders.c
2011
WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
sys/dev/pci/drm/radeon/atombios_encoders.c
2020
WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/atombios_encoders.c
2023
WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/atombios_encoders.c
2026
WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/atombios_encoders.c
2029
WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/atombios_encoders.c
2032
WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/atombios_encoders.c
2035
WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/atombios_encoders.c
80
WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
sys/dev/pci/drm/radeon/atombios_encoders.c
82
WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
sys/dev/pci/drm/radeon/btc_dpm.c
1316
WREG32(CG_BIF_REQ_AND_RSP, bif);
sys/dev/pci/drm/radeon/btc_dpm.c
1335
WREG32(CG_BIF_REQ_AND_RSP, bif);
sys/dev/pci/drm/radeon/btc_dpm.c
1388
WREG32(CG_ULV_CONTROL, BTC_CGULVCONTROL_DFLT);
sys/dev/pci/drm/radeon/btc_dpm.c
1389
WREG32(CG_ULV_PARAMETER, BTC_CGULVPARAMETER_DFLT);
sys/dev/pci/drm/radeon/btc_dpm.c
1420
WREG32(sequence[i], tmp);
sys/dev/pci/drm/radeon/btc_dpm.c
1741
WREG32(MC_ARB_DRAM_TIMING, arb_registers->mc_arb_dram_timing);
sys/dev/pci/drm/radeon/btc_dpm.c
1742
WREG32(MC_ARB_DRAM_TIMING2, arb_registers->mc_arb_dram_timing2);
sys/dev/pci/drm/radeon/btc_dpm.c
2000
WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
sys/dev/pci/drm/radeon/btc_dpm.c
2001
WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
sys/dev/pci/drm/radeon/btc_dpm.c
2002
WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
sys/dev/pci/drm/radeon/btc_dpm.c
2003
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
sys/dev/pci/drm/radeon/btc_dpm.c
2004
WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
sys/dev/pci/drm/radeon/btc_dpm.c
2005
WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
sys/dev/pci/drm/radeon/btc_dpm.c
2006
WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
sys/dev/pci/drm/radeon/btc_dpm.c
2007
WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
sys/dev/pci/drm/radeon/btc_dpm.c
2008
WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
sys/dev/pci/drm/radeon/btc_dpm.c
2009
WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
sys/dev/pci/drm/radeon/btc_dpm.c
2010
WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
sys/dev/pci/drm/radeon/btc_dpm.c
2046
WREG32(MC_PMG_AUTO_CFG, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1623
WREG32(SMC_MESSAGE_0, msg);
sys/dev/pci/drm/radeon/ci_dpm.c
1639
WREG32(SMC_MSG_ARG_0, parameter);
sys/dev/pci/drm/radeon/ci_dpm.c
1887
WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
sys/dev/pci/drm/radeon/ci_dpm.c
1898
WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
sys/dev/pci/drm/radeon/ci_dpm.c
4567
WREG32(MC_SEQ_IO_DEBUG_INDEX, 3);
sys/dev/pci/drm/radeon/ci_dpm.c
4570
WREG32(MC_SEQ_IO_DEBUG_INDEX, 3);
sys/dev/pci/drm/radeon/ci_dpm.c
4571
WREG32(MC_SEQ_IO_DEBUG_DATA, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
4589
WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
sys/dev/pci/drm/radeon/ci_dpm.c
4590
WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
sys/dev/pci/drm/radeon/ci_dpm.c
4591
WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));
sys/dev/pci/drm/radeon/ci_dpm.c
4592
WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));
sys/dev/pci/drm/radeon/ci_dpm.c
4593
WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));
sys/dev/pci/drm/radeon/ci_dpm.c
4594
WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));
sys/dev/pci/drm/radeon/ci_dpm.c
4595
WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));
sys/dev/pci/drm/radeon/ci_dpm.c
4596
WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));
sys/dev/pci/drm/radeon/ci_dpm.c
4597
WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
sys/dev/pci/drm/radeon/ci_dpm.c
4598
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
sys/dev/pci/drm/radeon/ci_dpm.c
4599
WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
sys/dev/pci/drm/radeon/ci_dpm.c
4600
WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
sys/dev/pci/drm/radeon/ci_dpm.c
4601
WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
sys/dev/pci/drm/radeon/ci_dpm.c
4602
WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
sys/dev/pci/drm/radeon/ci_dpm.c
4603
WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
sys/dev/pci/drm/radeon/ci_dpm.c
4604
WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
sys/dev/pci/drm/radeon/ci_dpm.c
4605
WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
sys/dev/pci/drm/radeon/ci_dpm.c
4606
WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
sys/dev/pci/drm/radeon/ci_dpm.c
4607
WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
sys/dev/pci/drm/radeon/ci_dpm.c
4608
WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
sys/dev/pci/drm/radeon/ci_dpm.c
576
WREG32(config_regs->offset << 2, data);
sys/dev/pci/drm/radeon/ci_smc.c
105
WREG32(SMC_IND_DATA_0, data);
sys/dev/pci/drm/radeon/ci_smc.c
229
WREG32(SMC_IND_INDEX_0, ucode_start_address);
sys/dev/pci/drm/radeon/ci_smc.c
235
WREG32(SMC_IND_DATA_0, data);
sys/dev/pci/drm/radeon/ci_smc.c
270
WREG32(SMC_IND_DATA_0, value);
sys/dev/pci/drm/radeon/ci_smc.c
41
WREG32(SMC_IND_INDEX_0, smc_address);
sys/dev/pci/drm/radeon/ci_smc.c
73
WREG32(SMC_IND_DATA_0, data);
sys/dev/pci/drm/radeon/cik.c
1848
WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl);
sys/dev/pci/drm/radeon/cik.c
185
WREG32(CIK_DIDT_IND_INDEX, (reg));
sys/dev/pci/drm/radeon/cik.c
1906
WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
sys/dev/pci/drm/radeon/cik.c
1907
WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
sys/dev/pci/drm/radeon/cik.c
1912
WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
sys/dev/pci/drm/radeon/cik.c
1913
WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
sys/dev/pci/drm/radeon/cik.c
1915
WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
sys/dev/pci/drm/radeon/cik.c
1916
WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
sys/dev/pci/drm/radeon/cik.c
1922
WREG32(MC_SEQ_IO_DEBUG_INDEX, 5);
sys/dev/pci/drm/radeon/cik.c
1923
WREG32(MC_SEQ_IO_DEBUG_DATA, 0x00000023);
sys/dev/pci/drm/radeon/cik.c
1924
WREG32(MC_SEQ_IO_DEBUG_INDEX, 9);
sys/dev/pci/drm/radeon/cik.c
1925
WREG32(MC_SEQ_IO_DEBUG_DATA, 0x000001f0);
sys/dev/pci/drm/radeon/cik.c
1931
WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
sys/dev/pci/drm/radeon/cik.c
1933
WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/cik.c
1937
WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
sys/dev/pci/drm/radeon/cik.c
1938
WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
sys/dev/pci/drm/radeon/cik.c
1939
WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
sys/dev/pci/drm/radeon/cik.c
196
WREG32(CIK_DIDT_IND_INDEX, (reg));
sys/dev/pci/drm/radeon/cik.c
197
WREG32(CIK_DIDT_IND_DATA, (v));
sys/dev/pci/drm/radeon/cik.c
243
WREG32(PCIE_INDEX, reg);
sys/dev/pci/drm/radeon/cik.c
2494
WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
sys/dev/pci/drm/radeon/cik.c
2496
WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
sys/dev/pci/drm/radeon/cik.c
255
WREG32(PCIE_INDEX, reg);
sys/dev/pci/drm/radeon/cik.c
257
WREG32(PCIE_DATA, v);
sys/dev/pci/drm/radeon/cik.c
2637
WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
sys/dev/pci/drm/radeon/cik.c
2639
WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
sys/dev/pci/drm/radeon/cik.c
2862
WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
sys/dev/pci/drm/radeon/cik.c
2864
WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
sys/dev/pci/drm/radeon/cik.c
3005
WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
sys/dev/pci/drm/radeon/cik.c
3007
WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
sys/dev/pci/drm/radeon/cik.c
3039
WREG32(GRBM_GFX_INDEX, data);
sys/dev/pci/drm/radeon/cik.c
3155
WREG32(PA_SC_RASTER_CONFIG, data);
sys/dev/pci/drm/radeon/cik.c
3251
WREG32((0x2c14 + j), 0x00000000);
sys/dev/pci/drm/radeon/cik.c
3252
WREG32((0x2c18 + j), 0x00000000);
sys/dev/pci/drm/radeon/cik.c
3253
WREG32((0x2c1c + j), 0x00000000);
sys/dev/pci/drm/radeon/cik.c
3254
WREG32((0x2c20 + j), 0x00000000);
sys/dev/pci/drm/radeon/cik.c
3255
WREG32((0x2c24 + j), 0x00000000);
sys/dev/pci/drm/radeon/cik.c
3258
WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
sys/dev/pci/drm/radeon/cik.c
3259
WREG32(SRBM_INT_CNTL, 0x1);
sys/dev/pci/drm/radeon/cik.c
3260
WREG32(SRBM_INT_ACK, 0x1);
sys/dev/pci/drm/radeon/cik.c
3262
WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
sys/dev/pci/drm/radeon/cik.c
3324
WREG32(GB_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/cik.c
3325
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/cik.c
3326
WREG32(DMIF_ADDR_CALC, gb_addr_config);
sys/dev/pci/drm/radeon/cik.c
3327
WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70);
sys/dev/pci/drm/radeon/cik.c
3328
WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70);
sys/dev/pci/drm/radeon/cik.c
3329
WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/cik.c
3330
WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/cik.c
3331
WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/cik.c
3348
WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
sys/dev/pci/drm/radeon/cik.c
3350
WREG32(SX_DEBUG_1, 0x20);
sys/dev/pci/drm/radeon/cik.c
3352
WREG32(TA_CNTL_AUX, 0x00010000);
sys/dev/pci/drm/radeon/cik.c
3356
WREG32(SPI_CONFIG_CNTL, tmp);
sys/dev/pci/drm/radeon/cik.c
3358
WREG32(SQ_CONFIG, 1);
sys/dev/pci/drm/radeon/cik.c
3360
WREG32(DB_DEBUG, 0);
sys/dev/pci/drm/radeon/cik.c
3364
WREG32(DB_DEBUG2, tmp);
sys/dev/pci/drm/radeon/cik.c
3368
WREG32(DB_DEBUG3, tmp);
sys/dev/pci/drm/radeon/cik.c
3372
WREG32(CB_HW_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
3374
WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
sys/dev/pci/drm/radeon/cik.c
3376
WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) |
sys/dev/pci/drm/radeon/cik.c
3381
WREG32(VGT_NUM_INSTANCES, 1);
sys/dev/pci/drm/radeon/cik.c
3383
WREG32(CP_PERFMON_CNTL, 0);
sys/dev/pci/drm/radeon/cik.c
3385
WREG32(SQ_CONFIG, 0);
sys/dev/pci/drm/radeon/cik.c
3387
WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
sys/dev/pci/drm/radeon/cik.c
3390
WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
sys/dev/pci/drm/radeon/cik.c
3393
WREG32(VGT_GS_VERTEX_REUSE, 16);
sys/dev/pci/drm/radeon/cik.c
3394
WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
sys/dev/pci/drm/radeon/cik.c
3398
WREG32(HDP_MISC_CNTL, tmp);
sys/dev/pci/drm/radeon/cik.c
3401
WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
sys/dev/pci/drm/radeon/cik.c
3403
WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
sys/dev/pci/drm/radeon/cik.c
3404
WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER);
sys/dev/pci/drm/radeon/cik.c
3457
WREG32(scratch, 0xCAFEDEAD);
sys/dev/pci/drm/radeon/cik.c
3782
WREG32(scratch, 0xCAFEDEAD);
sys/dev/pci/drm/radeon/cik.c
3866
WREG32(CP_ME_CNTL, 0);
sys/dev/pci/drm/radeon/cik.c
3870
WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
sys/dev/pci/drm/radeon/cik.c
3911
WREG32(CP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/cik.c
3913
WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/cik.c
3914
WREG32(CP_PFP_UCODE_ADDR, le32_to_cpu(pfp_hdr->header.ucode_version));
sys/dev/pci/drm/radeon/cik.c
3920
WREG32(CP_CE_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/cik.c
3922
WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/cik.c
3923
WREG32(CP_CE_UCODE_ADDR, le32_to_cpu(ce_hdr->header.ucode_version));
sys/dev/pci/drm/radeon/cik.c
3929
WREG32(CP_ME_RAM_WADDR, 0);
sys/dev/pci/drm/radeon/cik.c
3931
WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/cik.c
3932
WREG32(CP_ME_RAM_WADDR, le32_to_cpu(me_hdr->header.ucode_version));
sys/dev/pci/drm/radeon/cik.c
3933
WREG32(CP_ME_RAM_RADDR, le32_to_cpu(me_hdr->header.ucode_version));
sys/dev/pci/drm/radeon/cik.c
3939
WREG32(CP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/cik.c
3941
WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/cik.c
3942
WREG32(CP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/cik.c
3946
WREG32(CP_CE_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/cik.c
3948
WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/cik.c
3949
WREG32(CP_CE_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/cik.c
3953
WREG32(CP_ME_RAM_WADDR, 0);
sys/dev/pci/drm/radeon/cik.c
3955
WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/cik.c
3956
WREG32(CP_ME_RAM_WADDR, 0);
sys/dev/pci/drm/radeon/cik.c
3977
WREG32(CP_MAX_CONTEXT, rdev->config.cik.max_hw_contexts - 1);
sys/dev/pci/drm/radeon/cik.c
3978
WREG32(CP_ENDIAN_SWAP, 0);
sys/dev/pci/drm/radeon/cik.c
3979
WREG32(CP_DEVICE_ID, 1);
sys/dev/pci/drm/radeon/cik.c
4054
WREG32(CP_SEM_WAIT_TIMER, 0x0);
sys/dev/pci/drm/radeon/cik.c
4056
WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
sys/dev/pci/drm/radeon/cik.c
4059
WREG32(CP_RB_WPTR_DELAY, 0);
sys/dev/pci/drm/radeon/cik.c
4062
WREG32(CP_RB_VMID, 0);
sys/dev/pci/drm/radeon/cik.c
4064
WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
sys/dev/pci/drm/radeon/cik.c
4074
WREG32(CP_RB0_CNTL, tmp);
sys/dev/pci/drm/radeon/cik.c
4077
WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
sys/dev/pci/drm/radeon/cik.c
4079
WREG32(CP_RB0_WPTR, ring->wptr);
sys/dev/pci/drm/radeon/cik.c
4082
WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
sys/dev/pci/drm/radeon/cik.c
4083
WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
sys/dev/pci/drm/radeon/cik.c
4086
WREG32(SCRATCH_UMSK, 0);
sys/dev/pci/drm/radeon/cik.c
4092
WREG32(CP_RB0_CNTL, tmp);
sys/dev/pci/drm/radeon/cik.c
4095
WREG32(CP_RB0_BASE, rb_addr);
sys/dev/pci/drm/radeon/cik.c
4096
WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr));
sys/dev/pci/drm/radeon/cik.c
4135
WREG32(CP_RB0_WPTR, ring->wptr);
sys/dev/pci/drm/radeon/cik.c
4193
WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
sys/dev/pci/drm/radeon/cik.c
4196
WREG32(CP_HQD_DEQUEUE_REQUEST, 1);
sys/dev/pci/drm/radeon/cik.c
4202
WREG32(CP_HQD_DEQUEUE_REQUEST, 0);
sys/dev/pci/drm/radeon/cik.c
4203
WREG32(CP_HQD_PQ_RPTR, 0);
sys/dev/pci/drm/radeon/cik.c
4204
WREG32(CP_HQD_PQ_WPTR, 0);
sys/dev/pci/drm/radeon/cik.c
4220
WREG32(CP_MEC_CNTL, 0);
sys/dev/pci/drm/radeon/cik.c
4231
WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT));
sys/dev/pci/drm/radeon/cik.c
4267
WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/cik.c
4269
WREG32(CP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/cik.c
4270
WREG32(CP_MEC_ME1_UCODE_ADDR, le32_to_cpu(mec_hdr->header.ucode_version));
sys/dev/pci/drm/radeon/cik.c
4281
WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/cik.c
4283
WREG32(CP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/cik.c
4284
WREG32(CP_MEC_ME2_UCODE_ADDR, le32_to_cpu(mec2_hdr->header.ucode_version));
sys/dev/pci/drm/radeon/cik.c
4291
WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/cik.c
4293
WREG32(CP_MEC_ME1_UCODE_DATA, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/cik.c
4294
WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/cik.c
4299
WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/cik.c
4301
WREG32(CP_MEC_ME2_UCODE_DATA, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/cik.c
4302
WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/cik.c
4527
WREG32(CP_CPF_DEBUG, tmp);
sys/dev/pci/drm/radeon/cik.c
4540
WREG32(CP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
sys/dev/pci/drm/radeon/cik.c
4541
WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
sys/dev/pci/drm/radeon/cik.c
4544
WREG32(CP_HPD_EOP_VMID, 0);
sys/dev/pci/drm/radeon/cik.c
4550
WREG32(CP_HPD_EOP_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
4612
WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
sys/dev/pci/drm/radeon/cik.c
4621
WREG32(CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/radeon/cik.c
4629
WREG32(CP_HQD_DEQUEUE_REQUEST, 1);
sys/dev/pci/drm/radeon/cik.c
4635
WREG32(CP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
sys/dev/pci/drm/radeon/cik.c
4636
WREG32(CP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
sys/dev/pci/drm/radeon/cik.c
4637
WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
sys/dev/pci/drm/radeon/cik.c
4643
WREG32(CP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
sys/dev/pci/drm/radeon/cik.c
4644
WREG32(CP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
sys/dev/pci/drm/radeon/cik.c
4648
WREG32(CP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
sys/dev/pci/drm/radeon/cik.c
4654
WREG32(CP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
sys/dev/pci/drm/radeon/cik.c
4655
WREG32(CP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
sys/dev/pci/drm/radeon/cik.c
4673
WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
sys/dev/pci/drm/radeon/cik.c
4682
WREG32(CP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
sys/dev/pci/drm/radeon/cik.c
4683
WREG32(CP_HQD_PQ_WPTR_POLL_ADDR_HI,
sys/dev/pci/drm/radeon/cik.c
4694
WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR,
sys/dev/pci/drm/radeon/cik.c
4696
WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR_HI,
sys/dev/pci/drm/radeon/cik.c
4713
WREG32(CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/radeon/cik.c
4719
WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
sys/dev/pci/drm/radeon/cik.c
4724
WREG32(CP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
sys/dev/pci/drm/radeon/cik.c
4728
WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
sys/dev/pci/drm/radeon/cik.c
4947
WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
sys/dev/pci/drm/radeon/cik.c
4950
WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);
sys/dev/pci/drm/radeon/cik.c
4956
WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/cik.c
4962
WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/cik.c
5012
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/cik.c
5018
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/cik.c
5026
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/cik.c
5032
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/cik.c
5058
WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute & ~RENG_EXECUTE_ON_PWR_UP);
sys/dev/pci/drm/radeon/cik.c
5059
WREG32(GMCON_MISC, save->gmcon_misc & ~(RENG_EXECUTE_ON_REG_UPDATE |
sys/dev/pci/drm/radeon/cik.c
5068
WREG32(GMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/radeon/cik.c
5069
WREG32(GMCON_PGFSM_CONFIG, 0x200010ff);
sys/dev/pci/drm/radeon/cik.c
5072
WREG32(GMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/radeon/cik.c
5074
WREG32(GMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/radeon/cik.c
5075
WREG32(GMCON_PGFSM_CONFIG, 0x300010ff);
sys/dev/pci/drm/radeon/cik.c
5078
WREG32(GMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/radeon/cik.c
5080
WREG32(GMCON_PGFSM_WRITE, 0x210000);
sys/dev/pci/drm/radeon/cik.c
5081
WREG32(GMCON_PGFSM_CONFIG, 0xa00010ff);
sys/dev/pci/drm/radeon/cik.c
5084
WREG32(GMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/radeon/cik.c
5086
WREG32(GMCON_PGFSM_WRITE, 0x21003);
sys/dev/pci/drm/radeon/cik.c
5087
WREG32(GMCON_PGFSM_CONFIG, 0xb00010ff);
sys/dev/pci/drm/radeon/cik.c
5090
WREG32(GMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/radeon/cik.c
5092
WREG32(GMCON_PGFSM_WRITE, 0x2b00);
sys/dev/pci/drm/radeon/cik.c
5093
WREG32(GMCON_PGFSM_CONFIG, 0xc00010ff);
sys/dev/pci/drm/radeon/cik.c
5096
WREG32(GMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/radeon/cik.c
5098
WREG32(GMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/radeon/cik.c
5099
WREG32(GMCON_PGFSM_CONFIG, 0xd00010ff);
sys/dev/pci/drm/radeon/cik.c
5102
WREG32(GMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/radeon/cik.c
5104
WREG32(GMCON_PGFSM_WRITE, 0x420000);
sys/dev/pci/drm/radeon/cik.c
5105
WREG32(GMCON_PGFSM_CONFIG, 0x100010ff);
sys/dev/pci/drm/radeon/cik.c
5108
WREG32(GMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/radeon/cik.c
5110
WREG32(GMCON_PGFSM_WRITE, 0x120202);
sys/dev/pci/drm/radeon/cik.c
5111
WREG32(GMCON_PGFSM_CONFIG, 0x500010ff);
sys/dev/pci/drm/radeon/cik.c
5114
WREG32(GMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/radeon/cik.c
5116
WREG32(GMCON_PGFSM_WRITE, 0x3e3e36);
sys/dev/pci/drm/radeon/cik.c
5117
WREG32(GMCON_PGFSM_CONFIG, 0x600010ff);
sys/dev/pci/drm/radeon/cik.c
5120
WREG32(GMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/radeon/cik.c
5122
WREG32(GMCON_PGFSM_WRITE, 0x373f3e);
sys/dev/pci/drm/radeon/cik.c
5123
WREG32(GMCON_PGFSM_CONFIG, 0x700010ff);
sys/dev/pci/drm/radeon/cik.c
5126
WREG32(GMCON_PGFSM_WRITE, 0);
sys/dev/pci/drm/radeon/cik.c
5128
WREG32(GMCON_PGFSM_WRITE, 0x3e1332);
sys/dev/pci/drm/radeon/cik.c
5129
WREG32(GMCON_PGFSM_CONFIG, 0xe00010ff);
sys/dev/pci/drm/radeon/cik.c
5131
WREG32(GMCON_MISC3, save->gmcon_misc3);
sys/dev/pci/drm/radeon/cik.c
5132
WREG32(GMCON_MISC, save->gmcon_misc);
sys/dev/pci/drm/radeon/cik.c
5133
WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute);
sys/dev/pci/drm/radeon/cik.c
5151
WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
sys/dev/pci/drm/radeon/cik.c
5154
WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);
sys/dev/pci/drm/radeon/cik.c
5159
WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/cik.c
5163
WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/cik.c
5279
WREG32((0x2c14 + j), 0x00000000);
sys/dev/pci/drm/radeon/cik.c
5280
WREG32((0x2c18 + j), 0x00000000);
sys/dev/pci/drm/radeon/cik.c
5281
WREG32((0x2c1c + j), 0x00000000);
sys/dev/pci/drm/radeon/cik.c
5282
WREG32((0x2c20 + j), 0x00000000);
sys/dev/pci/drm/radeon/cik.c
5283
WREG32((0x2c24 + j), 0x00000000);
sys/dev/pci/drm/radeon/cik.c
5285
WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
sys/dev/pci/drm/radeon/cik.c
5292
WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
sys/dev/pci/drm/radeon/cik.c
5294
WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
sys/dev/pci/drm/radeon/cik.c
5296
WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
sys/dev/pci/drm/radeon/cik.c
5298
WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
sys/dev/pci/drm/radeon/cik.c
5302
WREG32(MC_VM_FB_LOCATION, tmp);
sys/dev/pci/drm/radeon/cik.c
5304
WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
sys/dev/pci/drm/radeon/cik.c
5305
WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
sys/dev/pci/drm/radeon/cik.c
5306
WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
sys/dev/pci/drm/radeon/cik.c
5307
WREG32(MC_VM_AGP_BASE, 0);
sys/dev/pci/drm/radeon/cik.c
5308
WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
sys/dev/pci/drm/radeon/cik.c
5309
WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
sys/dev/pci/drm/radeon/cik.c
5402
WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
sys/dev/pci/drm/radeon/cik.c
5405
WREG32(VM_INVALIDATE_REQUEST, 0x1);
sys/dev/pci/drm/radeon/cik.c
5431
WREG32(MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/radeon/cik.c
5439
WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
sys/dev/pci/drm/radeon/cik.c
5445
WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
sys/dev/pci/drm/radeon/cik.c
5446
WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
sys/dev/pci/drm/radeon/cik.c
5450
WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
sys/dev/pci/drm/radeon/cik.c
5451
WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
sys/dev/pci/drm/radeon/cik.c
5452
WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
sys/dev/pci/drm/radeon/cik.c
5453
WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
sys/dev/pci/drm/radeon/cik.c
5455
WREG32(VM_CONTEXT0_CNTL2, 0);
sys/dev/pci/drm/radeon/cik.c
5456
WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
sys/dev/pci/drm/radeon/cik.c
5459
WREG32(0x15D4, 0);
sys/dev/pci/drm/radeon/cik.c
5460
WREG32(0x15D8, 0);
sys/dev/pci/drm/radeon/cik.c
5461
WREG32(0x15DC, 0);
sys/dev/pci/drm/radeon/cik.c
5465
WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
sys/dev/pci/drm/radeon/cik.c
5466
WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1);
sys/dev/pci/drm/radeon/cik.c
5469
WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
sys/dev/pci/drm/radeon/cik.c
5472
WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
sys/dev/pci/drm/radeon/cik.c
5477
WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
sys/dev/pci/drm/radeon/cik.c
5479
WREG32(VM_CONTEXT1_CNTL2, 4);
sys/dev/pci/drm/radeon/cik.c
5480
WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
sys/dev/pci/drm/radeon/cik.c
5498
WREG32(CHUB_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
5507
WREG32(SH_MEM_CONFIG, SH_MEM_CONFIG_GFX_DEFAULT);
sys/dev/pci/drm/radeon/cik.c
5508
WREG32(SH_MEM_APE1_BASE, 1);
sys/dev/pci/drm/radeon/cik.c
5509
WREG32(SH_MEM_APE1_LIMIT, 0);
sys/dev/pci/drm/radeon/cik.c
5510
WREG32(SH_MEM_BASES, 0);
sys/dev/pci/drm/radeon/cik.c
5512
WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA0_REGISTER_OFFSET, 0);
sys/dev/pci/drm/radeon/cik.c
5513
WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0);
sys/dev/pci/drm/radeon/cik.c
5514
WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA1_REGISTER_OFFSET, 0);
sys/dev/pci/drm/radeon/cik.c
5515
WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0);
sys/dev/pci/drm/radeon/cik.c
5550
WREG32(VM_CONTEXT0_CNTL, 0);
sys/dev/pci/drm/radeon/cik.c
5551
WREG32(VM_CONTEXT1_CNTL, 0);
sys/dev/pci/drm/radeon/cik.c
5553
WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
sys/dev/pci/drm/radeon/cik.c
5556
WREG32(VM_L2_CNTL,
sys/dev/pci/drm/radeon/cik.c
5562
WREG32(VM_L2_CNTL2, 0);
sys/dev/pci/drm/radeon/cik.c
5563
WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
sys/dev/pci/drm/radeon/cik.c
5766
WREG32(CP_INT_CNTL_RING0, tmp);
sys/dev/pci/drm/radeon/cik.c
5778
WREG32(RLC_LB_CNTL, tmp);
sys/dev/pci/drm/radeon/cik.c
5812
WREG32(RLC_CNTL, rlc);
sys/dev/pci/drm/radeon/cik.c
5825
WREG32(RLC_CNTL, data);
sys/dev/pci/drm/radeon/cik.c
5844
WREG32(RLC_GPR_REG2, tmp);
sys/dev/pci/drm/radeon/cik.c
5865
WREG32(RLC_GPR_REG2, tmp);
sys/dev/pci/drm/radeon/cik.c
5877
WREG32(RLC_CNTL, 0);
sys/dev/pci/drm/radeon/cik.c
5893
WREG32(RLC_CNTL, RLC_ENABLE);
sys/dev/pci/drm/radeon/cik.c
5920
WREG32(RLC_CGCG_CGLS_CTRL, tmp);
sys/dev/pci/drm/radeon/cik.c
5928
WREG32(RLC_LB_CNTR_INIT, 0);
sys/dev/pci/drm/radeon/cik.c
5929
WREG32(RLC_LB_CNTR_MAX, 0x00008000);
sys/dev/pci/drm/radeon/cik.c
5932
WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
sys/dev/pci/drm/radeon/cik.c
5933
WREG32(RLC_LB_PARAMS, 0x00600408);
sys/dev/pci/drm/radeon/cik.c
5934
WREG32(RLC_LB_CNTL, 0x80000004);
sys/dev/pci/drm/radeon/cik.c
5936
WREG32(RLC_MC_CNTL, 0);
sys/dev/pci/drm/radeon/cik.c
5937
WREG32(RLC_UCODE_CNTL, 0);
sys/dev/pci/drm/radeon/cik.c
5948
WREG32(RLC_GPM_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/cik.c
5950
WREG32(RLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/cik.c
5951
WREG32(RLC_GPM_UCODE_ADDR, le32_to_cpu(hdr->header.ucode_version));
sys/dev/pci/drm/radeon/cik.c
5973
WREG32(RLC_GPM_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/cik.c
5975
WREG32(RLC_GPM_UCODE_DATA, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/cik.c
5976
WREG32(RLC_GPM_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/cik.c
5983
WREG32(RLC_DRIVER_DMA_STATUS, 0);
sys/dev/pci/drm/radeon/cik.c
6002
WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
sys/dev/pci/drm/radeon/cik.c
6003
WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
sys/dev/pci/drm/radeon/cik.c
6005
WREG32(RLC_SERDES_WR_CTRL, tmp2);
sys/dev/pci/drm/radeon/cik.c
6022
WREG32(RLC_CGCG_CGLS_CTRL, data);
sys/dev/pci/drm/radeon/cik.c
6036
WREG32(CP_MEM_SLP_CNTL, data);
sys/dev/pci/drm/radeon/cik.c
6044
WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
sys/dev/pci/drm/radeon/cik.c
6049
WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
sys/dev/pci/drm/radeon/cik.c
6050
WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
sys/dev/pci/drm/radeon/cik.c
6052
WREG32(RLC_SERDES_WR_CTRL, data);
sys/dev/pci/drm/radeon/cik.c
6069
WREG32(CGTS_SM_CTRL_REG, data);
sys/dev/pci/drm/radeon/cik.c
6075
WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
sys/dev/pci/drm/radeon/cik.c
6080
WREG32(RLC_MEM_SLP_CNTL, data);
sys/dev/pci/drm/radeon/cik.c
6086
WREG32(CP_MEM_SLP_CNTL, data);
sys/dev/pci/drm/radeon/cik.c
6092
WREG32(CGTS_SM_CTRL_REG, data);
sys/dev/pci/drm/radeon/cik.c
6097
WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
sys/dev/pci/drm/radeon/cik.c
6098
WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
sys/dev/pci/drm/radeon/cik.c
6100
WREG32(RLC_SERDES_WR_CTRL, data);
sys/dev/pci/drm/radeon/cik.c
6132
WREG32(mc_cg_registers[i], data);
sys/dev/pci/drm/radeon/cik.c
6149
WREG32(mc_cg_registers[i], data);
sys/dev/pci/drm/radeon/cik.c
6159
WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
sys/dev/pci/drm/radeon/cik.c
6160
WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
sys/dev/pci/drm/radeon/cik.c
6165
WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
sys/dev/pci/drm/radeon/cik.c
6170
WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
sys/dev/pci/drm/radeon/cik.c
6183
WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
sys/dev/pci/drm/radeon/cik.c
6188
WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
sys/dev/pci/drm/radeon/cik.c
6193
WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
sys/dev/pci/drm/radeon/cik.c
6198
WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
sys/dev/pci/drm/radeon/cik.c
6215
WREG32(UVD_CGC_CTRL, data);
sys/dev/pci/drm/radeon/cik.c
6224
WREG32(UVD_CGC_CTRL, data);
sys/dev/pci/drm/radeon/cik.c
6259
WREG32(HDP_HOST_PATH_CNTL, data);
sys/dev/pci/drm/radeon/cik.c
6275
WREG32(HDP_MEM_POWER_LS, data);
sys/dev/pci/drm/radeon/cik.c
6363
WREG32(RLC_PG_CNTL, data);
sys/dev/pci/drm/radeon/cik.c
6377
WREG32(RLC_PG_CNTL, data);
sys/dev/pci/drm/radeon/cik.c
6390
WREG32(RLC_PG_CNTL, data);
sys/dev/pci/drm/radeon/cik.c
6403
WREG32(RLC_PG_CNTL, data);
sys/dev/pci/drm/radeon/cik.c
6503
WREG32(RLC_PG_CNTL, data);
sys/dev/pci/drm/radeon/cik.c
6508
WREG32(RLC_AUTO_PG_CTRL, data);
sys/dev/pci/drm/radeon/cik.c
6513
WREG32(RLC_PG_CNTL, data);
sys/dev/pci/drm/radeon/cik.c
6518
WREG32(RLC_AUTO_PG_CTRL, data);
sys/dev/pci/drm/radeon/cik.c
6572
WREG32(RLC_PG_AO_CU_MASK, tmp);
sys/dev/pci/drm/radeon/cik.c
6577
WREG32(RLC_MAX_PG_CU, tmp);
sys/dev/pci/drm/radeon/cik.c
6591
WREG32(RLC_PG_CNTL, data);
sys/dev/pci/drm/radeon/cik.c
6605
WREG32(RLC_PG_CNTL, data);
sys/dev/pci/drm/radeon/cik.c
6617
WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
sys/dev/pci/drm/radeon/cik.c
6618
WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr));
sys/dev/pci/drm/radeon/cik.c
6619
WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr));
sys/dev/pci/drm/radeon/cik.c
6620
WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_size);
sys/dev/pci/drm/radeon/cik.c
6622
WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
sys/dev/pci/drm/radeon/cik.c
6624
WREG32(RLC_GPM_SCRATCH_DATA, 0);
sys/dev/pci/drm/radeon/cik.c
6627
WREG32(RLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
sys/dev/pci/drm/radeon/cik.c
6629
WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.reg_list[i]);
sys/dev/pci/drm/radeon/cik.c
6635
WREG32(RLC_PG_CNTL, data);
sys/dev/pci/drm/radeon/cik.c
6637
WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
sys/dev/pci/drm/radeon/cik.c
6638
WREG32(RLC_CP_TABLE_RESTORE, rdev->rlc.cp_table_gpu_addr >> 8);
sys/dev/pci/drm/radeon/cik.c
6643
WREG32(CP_RB_WPTR_POLL_CNTL, data);
sys/dev/pci/drm/radeon/cik.c
6646
WREG32(RLC_PG_DELAY, data);
sys/dev/pci/drm/radeon/cik.c
6651
WREG32(RLC_PG_DELAY_2, data);
sys/dev/pci/drm/radeon/cik.c
6656
WREG32(RLC_AUTO_PG_CTRL, data);
sys/dev/pci/drm/radeon/cik.c
6819
WREG32(IH_CNTL, ih_cntl);
sys/dev/pci/drm/radeon/cik.c
6820
WREG32(IH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/radeon/cik.c
6838
WREG32(IH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/radeon/cik.c
6839
WREG32(IH_CNTL, ih_cntl);
sys/dev/pci/drm/radeon/cik.c
6841
WREG32(IH_RB_RPTR, 0);
sys/dev/pci/drm/radeon/cik.c
6842
WREG32(IH_RB_WPTR, 0);
sys/dev/pci/drm/radeon/cik.c
6861
WREG32(CP_INT_CNTL_RING0, tmp);
sys/dev/pci/drm/radeon/cik.c
6864
WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/cik.c
6866
WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/cik.c
6868
WREG32(CP_ME1_PIPE0_INT_CNTL, 0);
sys/dev/pci/drm/radeon/cik.c
6869
WREG32(CP_ME1_PIPE1_INT_CNTL, 0);
sys/dev/pci/drm/radeon/cik.c
6870
WREG32(CP_ME1_PIPE2_INT_CNTL, 0);
sys/dev/pci/drm/radeon/cik.c
6871
WREG32(CP_ME1_PIPE3_INT_CNTL, 0);
sys/dev/pci/drm/radeon/cik.c
6872
WREG32(CP_ME2_PIPE0_INT_CNTL, 0);
sys/dev/pci/drm/radeon/cik.c
6873
WREG32(CP_ME2_PIPE1_INT_CNTL, 0);
sys/dev/pci/drm/radeon/cik.c
6874
WREG32(CP_ME2_PIPE2_INT_CNTL, 0);
sys/dev/pci/drm/radeon/cik.c
6875
WREG32(CP_ME2_PIPE3_INT_CNTL, 0);
sys/dev/pci/drm/radeon/cik.c
6877
WREG32(GRBM_INT_CNTL, 0);
sys/dev/pci/drm/radeon/cik.c
6879
WREG32(SRBM_INT_CNTL, 0);
sys/dev/pci/drm/radeon/cik.c
6881
WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
sys/dev/pci/drm/radeon/cik.c
6882
WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
sys/dev/pci/drm/radeon/cik.c
6884
WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
sys/dev/pci/drm/radeon/cik.c
6885
WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
sys/dev/pci/drm/radeon/cik.c
6888
WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
sys/dev/pci/drm/radeon/cik.c
6889
WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
sys/dev/pci/drm/radeon/cik.c
6893
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
sys/dev/pci/drm/radeon/cik.c
6894
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
sys/dev/pci/drm/radeon/cik.c
6897
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
sys/dev/pci/drm/radeon/cik.c
6898
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
sys/dev/pci/drm/radeon/cik.c
6901
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
sys/dev/pci/drm/radeon/cik.c
6902
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
sys/dev/pci/drm/radeon/cik.c
6906
WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
sys/dev/pci/drm/radeon/cik.c
6910
WREG32(DC_HPD1_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
6912
WREG32(DC_HPD2_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
6914
WREG32(DC_HPD3_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
6916
WREG32(DC_HPD4_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
6918
WREG32(DC_HPD5_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
6920
WREG32(DC_HPD6_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
6958
WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8);
sys/dev/pci/drm/radeon/cik.c
6966
WREG32(INTERRUPT_CNTL, interrupt_cntl);
sys/dev/pci/drm/radeon/cik.c
6968
WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
sys/dev/pci/drm/radeon/cik.c
6979
WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
sys/dev/pci/drm/radeon/cik.c
6980
WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
sys/dev/pci/drm/radeon/cik.c
6982
WREG32(IH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/radeon/cik.c
6985
WREG32(IH_RB_RPTR, 0);
sys/dev/pci/drm/radeon/cik.c
6986
WREG32(IH_RB_WPTR, 0);
sys/dev/pci/drm/radeon/cik.c
6993
WREG32(IH_CNTL, ih_cntl);
sys/dev/pci/drm/radeon/cik.c
7217
WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
sys/dev/pci/drm/radeon/cik.c
7219
WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl);
sys/dev/pci/drm/radeon/cik.c
7220
WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1);
sys/dev/pci/drm/radeon/cik.c
7222
WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0);
sys/dev/pci/drm/radeon/cik.c
7223
WREG32(CP_ME1_PIPE1_INT_CNTL, cp_m1p1);
sys/dev/pci/drm/radeon/cik.c
7224
WREG32(CP_ME1_PIPE2_INT_CNTL, cp_m1p2);
sys/dev/pci/drm/radeon/cik.c
7225
WREG32(CP_ME1_PIPE3_INT_CNTL, cp_m1p3);
sys/dev/pci/drm/radeon/cik.c
7226
WREG32(CP_ME2_PIPE0_INT_CNTL, cp_m2p0);
sys/dev/pci/drm/radeon/cik.c
7227
WREG32(CP_ME2_PIPE1_INT_CNTL, cp_m2p1);
sys/dev/pci/drm/radeon/cik.c
7228
WREG32(CP_ME2_PIPE2_INT_CNTL, cp_m2p2);
sys/dev/pci/drm/radeon/cik.c
7229
WREG32(CP_ME2_PIPE3_INT_CNTL, cp_m2p3);
sys/dev/pci/drm/radeon/cik.c
7231
WREG32(GRBM_INT_CNTL, grbm_int_cntl);
sys/dev/pci/drm/radeon/cik.c
7233
WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
sys/dev/pci/drm/radeon/cik.c
7234
WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
sys/dev/pci/drm/radeon/cik.c
7236
WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
sys/dev/pci/drm/radeon/cik.c
7237
WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
sys/dev/pci/drm/radeon/cik.c
7240
WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
sys/dev/pci/drm/radeon/cik.c
7241
WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
sys/dev/pci/drm/radeon/cik.c
7245
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
sys/dev/pci/drm/radeon/cik.c
7247
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
sys/dev/pci/drm/radeon/cik.c
7251
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
sys/dev/pci/drm/radeon/cik.c
7253
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
sys/dev/pci/drm/radeon/cik.c
7257
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
sys/dev/pci/drm/radeon/cik.c
7259
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
sys/dev/pci/drm/radeon/cik.c
7263
WREG32(DC_HPD1_INT_CONTROL, hpd1);
sys/dev/pci/drm/radeon/cik.c
7264
WREG32(DC_HPD2_INT_CONTROL, hpd2);
sys/dev/pci/drm/radeon/cik.c
7265
WREG32(DC_HPD3_INT_CONTROL, hpd3);
sys/dev/pci/drm/radeon/cik.c
7266
WREG32(DC_HPD4_INT_CONTROL, hpd4);
sys/dev/pci/drm/radeon/cik.c
7267
WREG32(DC_HPD5_INT_CONTROL, hpd5);
sys/dev/pci/drm/radeon/cik.c
7268
WREG32(DC_HPD6_INT_CONTROL, hpd6);
sys/dev/pci/drm/radeon/cik.c
7315
WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,
sys/dev/pci/drm/radeon/cik.c
7318
WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,
sys/dev/pci/drm/radeon/cik.c
7321
WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
sys/dev/pci/drm/radeon/cik.c
7323
WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
sys/dev/pci/drm/radeon/cik.c
7325
WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
sys/dev/pci/drm/radeon/cik.c
7327
WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
sys/dev/pci/drm/radeon/cik.c
7331
WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,
sys/dev/pci/drm/radeon/cik.c
7334
WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,
sys/dev/pci/drm/radeon/cik.c
7337
WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
sys/dev/pci/drm/radeon/cik.c
7339
WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
sys/dev/pci/drm/radeon/cik.c
7341
WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
sys/dev/pci/drm/radeon/cik.c
7343
WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
sys/dev/pci/drm/radeon/cik.c
7348
WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,
sys/dev/pci/drm/radeon/cik.c
7351
WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET,
sys/dev/pci/drm/radeon/cik.c
7354
WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
sys/dev/pci/drm/radeon/cik.c
7356
WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
sys/dev/pci/drm/radeon/cik.c
7358
WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
sys/dev/pci/drm/radeon/cik.c
7360
WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
sys/dev/pci/drm/radeon/cik.c
7366
WREG32(DC_HPD1_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7371
WREG32(DC_HPD2_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7376
WREG32(DC_HPD3_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7381
WREG32(DC_HPD4_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7386
WREG32(DC_HPD5_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7391
WREG32(DC_HPD6_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7396
WREG32(DC_HPD1_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7401
WREG32(DC_HPD2_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7406
WREG32(DC_HPD3_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7411
WREG32(DC_HPD4_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7416
WREG32(DC_HPD5_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7421
WREG32(DC_HPD6_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7501
WREG32(IH_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/cik.c
7890
WREG32(SRBM_INT_ACK, 0x1);
sys/dev/pci/drm/radeon/cik.c
8085
WREG32(IH_RB_RPTR, rptr);
sys/dev/pci/drm/radeon/cik.c
8804
WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/cik.c
8854
WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/cik.c
8857
WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
sys/dev/pci/drm/radeon/cik.c
9356
WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/cik.c
9357
WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/cik.c
9364
WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/cik.c
9365
WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/cik.c
9369
WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask);
sys/dev/pci/drm/radeon/cik.c
9420
WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
sys/dev/pci/drm/radeon/cik_sdma.c
120
WREG32(reg, (ring->wptr << 2) & 0x3fffc);
sys/dev/pci/drm/radeon/cik_sdma.c
265
WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
sys/dev/pci/drm/radeon/cik_sdma.c
266
WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0);
sys/dev/pci/drm/radeon/cik_sdma.c
276
WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1);
sys/dev/pci/drm/radeon/cik_sdma.c
279
WREG32(SRBM_SOFT_RESET, 0);
sys/dev/pci/drm/radeon/cik_sdma.c
318
WREG32(SDMA0_CNTL + reg_offset, value);
sys/dev/pci/drm/radeon/cik_sdma.c
350
WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl);
sys/dev/pci/drm/radeon/cik_sdma.c
383
WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
sys/dev/pci/drm/radeon/cik_sdma.c
384
WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
sys/dev/pci/drm/radeon/cik_sdma.c
392
WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
sys/dev/pci/drm/radeon/cik_sdma.c
395
WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0);
sys/dev/pci/drm/radeon/cik_sdma.c
396
WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0);
sys/dev/pci/drm/radeon/cik_sdma.c
399
WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset,
sys/dev/pci/drm/radeon/cik_sdma.c
401
WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset,
sys/dev/pci/drm/radeon/cik_sdma.c
407
WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8);
sys/dev/pci/drm/radeon/cik_sdma.c
408
WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40);
sys/dev/pci/drm/radeon/cik_sdma.c
411
WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2);
sys/dev/pci/drm/radeon/cik_sdma.c
414
WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE);
sys/dev/pci/drm/radeon/cik_sdma.c
421
WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl);
sys/dev/pci/drm/radeon/cik_sdma.c
483
WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
sys/dev/pci/drm/radeon/cik_sdma.c
485
WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/cik_sdma.c
486
WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
sys/dev/pci/drm/radeon/cik_sdma.c
492
WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
sys/dev/pci/drm/radeon/cik_sdma.c
494
WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/cik_sdma.c
495
WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
sys/dev/pci/drm/radeon/cik_sdma.c
501
WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
sys/dev/pci/drm/radeon/cik_sdma.c
503
WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/cik_sdma.c
504
WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
sys/dev/pci/drm/radeon/cik_sdma.c
508
WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
sys/dev/pci/drm/radeon/cik_sdma.c
510
WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/cik_sdma.c
511
WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
sys/dev/pci/drm/radeon/cik_sdma.c
514
WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
sys/dev/pci/drm/radeon/cik_sdma.c
515
WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
sys/dev/pci/drm/radeon/cypress_dpm.c
1135
WREG32(MC_CONFIG_MCD, 0xf);
sys/dev/pci/drm/radeon/cypress_dpm.c
1136
WREG32(MC_CG_CONFIG_MCD, 0xf);
sys/dev/pci/drm/radeon/cypress_dpm.c
1138
WREG32(MC_CONFIG, 0xf);
sys/dev/pci/drm/radeon/cypress_dpm.c
1139
WREG32(MC_CG_CONFIG, 0xf);
sys/dev/pci/drm/radeon/cypress_dpm.c
1145
WREG32(MC_SEQ_CG, MC_CG_SEQ_YCLK_SUSPEND);
sys/dev/pci/drm/radeon/cypress_dpm.c
1153
WREG32(MC_SEQ_CG, mc_seq_cg);
sys/dev/pci/drm/radeon/cypress_dpm.c
1163
WREG32(MC_SEQ_CG, mc_seq_cg);
sys/dev/pci/drm/radeon/cypress_dpm.c
1176
WREG32(eg_pi->mc_reg_table.mc_reg_address[i].s0 << 2, value);
sys/dev/pci/drm/radeon/cypress_dpm.c
1193
WREG32(MC_CONFIG_MCD, 0xf);
sys/dev/pci/drm/radeon/cypress_dpm.c
1194
WREG32(MC_CG_CONFIG_MCD, 0xf);
sys/dev/pci/drm/radeon/cypress_dpm.c
1196
WREG32(MC_CONFIG, 0xf);
sys/dev/pci/drm/radeon/cypress_dpm.c
1197
WREG32(MC_CG_CONFIG, 0xf);
sys/dev/pci/drm/radeon/cypress_dpm.c
1203
WREG32(MC_SEQ_CG, MC_CG_SEQ_YCLK_SUSPEND);
sys/dev/pci/drm/radeon/cypress_dpm.c
1211
WREG32(MC_SEQ_CG, mc_seq_cg);
sys/dev/pci/drm/radeon/cypress_dpm.c
1221
WREG32(MC_SEQ_CG, mc_seq_cg);
sys/dev/pci/drm/radeon/cypress_dpm.c
125
WREG32(GRBM_GFX_INDEX, 0xC0000000);
sys/dev/pci/drm/radeon/cypress_dpm.c
152
WREG32(GRBM_GFX_INDEX, 0xC0000000);
sys/dev/pci/drm/radeon/cypress_dpm.c
1742
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/pci/drm/radeon/cypress_dpm.c
1761
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/pci/drm/radeon/cypress_dpm.c
1780
WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
sys/dev/pci/drm/radeon/cypress_dpm.c
186
WREG32(GRBM_GFX_INDEX, 0xC0000000);
sys/dev/pci/drm/radeon/cypress_dpm.c
194
WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
sys/dev/pci/drm/radeon/cypress_dpm.c
207
WREG32(GRBM_GFX_INDEX, 0xC0000000);
sys/dev/pci/drm/radeon/cypress_dpm.c
215
WREG32(CGTS_SM_CTRL_REG, 0x81f44bc0);
sys/dev/pci/drm/radeon/cypress_dpm.c
61
WREG32(CG_BIF_REQ_AND_RSP, bif);
sys/dev/pci/drm/radeon/cypress_dpm.c
947
WREG32(MC_ARB_BURST_TIME, mc_arb_burst_time);
sys/dev/pci/drm/radeon/dce3_1_afmt.c
157
WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
sys/dev/pci/drm/radeon/dce3_1_afmt.c
158
WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
sys/dev/pci/drm/radeon/dce3_1_afmt.c
159
WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
sys/dev/pci/drm/radeon/dce3_1_afmt.c
160
WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
sys/dev/pci/drm/radeon/dce3_1_afmt.c
164
WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl);
sys/dev/pci/drm/radeon/dce3_1_afmt.c
165
WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase);
sys/dev/pci/drm/radeon/dce3_1_afmt.c
166
WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
sys/dev/pci/drm/radeon/dce3_1_afmt.c
167
WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
sys/dev/pci/drm/radeon/dce3_1_afmt.c
177
WREG32(DCE3_HDMI0_ACR_PACKET_CONTROL + offset,
sys/dev/pci/drm/radeon/dce3_1_afmt.c
208
WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
sys/dev/pci/drm/radeon/dce3_1_afmt.c
212
WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
sys/dev/pci/drm/radeon/dce6_afmt.c
121
WREG32(AFMT_AUDIO_SRC_CONTROL + dig->afmt->offset,
sys/dev/pci/drm/radeon/dce6_afmt.c
279
WREG32(DCCG_AUDIO_DTO_SOURCE, value);
sys/dev/pci/drm/radeon/dce6_afmt.c
285
WREG32(DCCG_AUDIO_DTO0_PHASE, 24000);
sys/dev/pci/drm/radeon/dce6_afmt.c
286
WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
sys/dev/pci/drm/radeon/dce6_afmt.c
299
WREG32(DCCG_AUDIO_DTO_SOURCE, value);
sys/dev/pci/drm/radeon/dce6_afmt.c
314
WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000);
sys/dev/pci/drm/radeon/dce6_afmt.c
315
WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock);
sys/dev/pci/drm/radeon/dce6_afmt.c
317
WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
sys/dev/pci/drm/radeon/dce6_afmt.c
318
WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
sys/dev/pci/drm/radeon/dce6_afmt.c
41
WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
sys/dev/pci/drm/radeon/dce6_afmt.c
55
WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
sys/dev/pci/drm/radeon/dce6_afmt.c
57
WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,
sys/dev/pci/drm/radeon/dce6_afmt.c
59
WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);
sys/dev/pci/drm/radeon/evergreen.c
107
WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
sys/dev/pci/drm/radeon/evergreen.c
118
WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
sys/dev/pci/drm/radeon/evergreen.c
1184
WREG32(CG_SCRATCH1, cg_scratch);
sys/dev/pci/drm/radeon/evergreen.c
119
WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
sys/dev/pci/drm/radeon/evergreen.c
1345
WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/evergreen.c
1423
WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/evergreen.c
1426
WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/evergreen.c
1429
WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/evergreen.c
1431
WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/evergreen.c
1687
WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/evergreen.c
1712
WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/evergreen.c
1789
WREG32(DC_HPDx_CONTROL(hpd), tmp);
sys/dev/pci/drm/radeon/evergreen.c
1818
WREG32(DC_HPDx_CONTROL(hpd), 0);
sys/dev/pci/drm/radeon/evergreen.c
1870
WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/evergreen.c
1873
WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
sys/dev/pci/drm/radeon/evergreen.c
2291
WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2292
WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
sys/dev/pci/drm/radeon/evergreen.c
2299
WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2300
WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
sys/dev/pci/drm/radeon/evergreen.c
2304
WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
sys/dev/pci/drm/radeon/evergreen.c
2307
WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
sys/dev/pci/drm/radeon/evergreen.c
2308
WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
sys/dev/pci/drm/radeon/evergreen.c
2382
WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
sys/dev/pci/drm/radeon/evergreen.c
2384
WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
sys/dev/pci/drm/radeon/evergreen.c
2413
WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
sys/dev/pci/drm/radeon/evergreen.c
2416
WREG32(VM_L2_CNTL2, 0);
sys/dev/pci/drm/radeon/evergreen.c
2417
WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
sys/dev/pci/drm/radeon/evergreen.c
2424
WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2425
WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2426
WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2428
WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2429
WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2430
WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2435
WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2437
WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2438
WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2439
WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2440
WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2441
WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
sys/dev/pci/drm/radeon/evergreen.c
2442
WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
sys/dev/pci/drm/radeon/evergreen.c
2443
WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
sys/dev/pci/drm/radeon/evergreen.c
2444
WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
sys/dev/pci/drm/radeon/evergreen.c
2446
WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
sys/dev/pci/drm/radeon/evergreen.c
2448
WREG32(VM_CONTEXT1_CNTL, 0);
sys/dev/pci/drm/radeon/evergreen.c
2463
WREG32(VM_CONTEXT0_CNTL, 0);
sys/dev/pci/drm/radeon/evergreen.c
2464
WREG32(VM_CONTEXT1_CNTL, 0);
sys/dev/pci/drm/radeon/evergreen.c
2467
WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
sys/dev/pci/drm/radeon/evergreen.c
2469
WREG32(VM_L2_CNTL2, 0);
sys/dev/pci/drm/radeon/evergreen.c
2470
WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
sys/dev/pci/drm/radeon/evergreen.c
2473
WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2474
WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2475
WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2476
WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2477
WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2478
WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2479
WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2496
WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
sys/dev/pci/drm/radeon/evergreen.c
2499
WREG32(VM_L2_CNTL2, 0);
sys/dev/pci/drm/radeon/evergreen.c
2500
WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
sys/dev/pci/drm/radeon/evergreen.c
2506
WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2507
WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2508
WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2509
WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2510
WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2511
WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2512
WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2513
WREG32(VM_CONTEXT0_CNTL, 0);
sys/dev/pci/drm/radeon/evergreen.c
2514
WREG32(VM_CONTEXT1_CNTL, 0);
sys/dev/pci/drm/radeon/evergreen.c
2643
WREG32(EVERGREEN_DP_VID_STREAM_CNTL +
sys/dev/pci/drm/radeon/evergreen.c
2659
WREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe], fifo_ctrl);
sys/dev/pci/drm/radeon/evergreen.c
2674
WREG32(VGA_RENDER_CONTROL, 0);
sys/dev/pci/drm/radeon/evergreen.c
2685
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
sys/dev/pci/drm/radeon/evergreen.c
2687
WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/evergreen.c
2688
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
sys/dev/pci/drm/radeon/evergreen.c
2694
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
sys/dev/pci/drm/radeon/evergreen.c
2696
WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/evergreen.c
2697
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
sys/dev/pci/drm/radeon/evergreen.c
2719
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
sys/dev/pci/drm/radeon/evergreen.c
2722
WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/evergreen.c
2723
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
sys/dev/pci/drm/radeon/evergreen.c
2736
WREG32(BIF_FB_EN, 0);
sys/dev/pci/drm/radeon/evergreen.c
2739
WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
sys/dev/pci/drm/radeon/evergreen.c
2750
WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/evergreen.c
2755
WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/evergreen.c
2768
WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
sys/dev/pci/drm/radeon/evergreen.c
2770
WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
sys/dev/pci/drm/radeon/evergreen.c
2772
WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
sys/dev/pci/drm/radeon/evergreen.c
2774
WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
sys/dev/pci/drm/radeon/evergreen.c
2779
WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
sys/dev/pci/drm/radeon/evergreen.c
2780
WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
sys/dev/pci/drm/radeon/evergreen.c
2789
WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/evergreen.c
2794
WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/evergreen.c
2799
WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/evergreen.c
2813
WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2815
WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
sys/dev/pci/drm/radeon/evergreen.c
2822
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
sys/dev/pci/drm/radeon/evergreen.c
2823
WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/evergreen.c
2824
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
sys/dev/pci/drm/radeon/evergreen.c
2828
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
sys/dev/pci/drm/radeon/evergreen.c
2829
WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/evergreen.c
2830
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
sys/dev/pci/drm/radeon/evergreen.c
2843
WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
sys/dev/pci/drm/radeon/evergreen.c
2845
WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
sys/dev/pci/drm/radeon/evergreen.c
2857
WREG32((0x2c14 + j), 0x00000000);
sys/dev/pci/drm/radeon/evergreen.c
2858
WREG32((0x2c18 + j), 0x00000000);
sys/dev/pci/drm/radeon/evergreen.c
2859
WREG32((0x2c1c + j), 0x00000000);
sys/dev/pci/drm/radeon/evergreen.c
2860
WREG32((0x2c20 + j), 0x00000000);
sys/dev/pci/drm/radeon/evergreen.c
2861
WREG32((0x2c24 + j), 0x00000000);
sys/dev/pci/drm/radeon/evergreen.c
2863
WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
sys/dev/pci/drm/radeon/evergreen.c
2870
WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
sys/dev/pci/drm/radeon/evergreen.c
2875
WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
sys/dev/pci/drm/radeon/evergreen.c
2877
WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
sys/dev/pci/drm/radeon/evergreen.c
2881
WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
sys/dev/pci/drm/radeon/evergreen.c
2883
WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
sys/dev/pci/drm/radeon/evergreen.c
2887
WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
sys/dev/pci/drm/radeon/evergreen.c
2889
WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
sys/dev/pci/drm/radeon/evergreen.c
2892
WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
sys/dev/pci/drm/radeon/evergreen.c
2900
WREG32(MC_FUS_VM_FB_OFFSET, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2904
WREG32(MC_VM_FB_LOCATION, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2905
WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
sys/dev/pci/drm/radeon/evergreen.c
2906
WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
sys/dev/pci/drm/radeon/evergreen.c
2907
WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
sys/dev/pci/drm/radeon/evergreen.c
2909
WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
sys/dev/pci/drm/radeon/evergreen.c
2910
WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
sys/dev/pci/drm/radeon/evergreen.c
2911
WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
sys/dev/pci/drm/radeon/evergreen.c
2913
WREG32(MC_VM_AGP_BASE, 0);
sys/dev/pci/drm/radeon/evergreen.c
2914
WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
sys/dev/pci/drm/radeon/evergreen.c
2915
WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
sys/dev/pci/drm/radeon/evergreen.c
2973
WREG32(CP_RB_CNTL,
sys/dev/pci/drm/radeon/evergreen.c
2980
WREG32(CP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/evergreen.c
2982
WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/evergreen.c
2983
WREG32(CP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/evergreen.c
2986
WREG32(CP_ME_RAM_WADDR, 0);
sys/dev/pci/drm/radeon/evergreen.c
2988
WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/evergreen.c
2990
WREG32(CP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/evergreen.c
2991
WREG32(CP_ME_RAM_WADDR, 0);
sys/dev/pci/drm/radeon/evergreen.c
2992
WREG32(CP_ME_RAM_RADDR, 0);
sys/dev/pci/drm/radeon/evergreen.c
3017
WREG32(CP_ME_CNTL, cp_me);
sys/dev/pci/drm/radeon/evergreen.c
3070
WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
sys/dev/pci/drm/radeon/evergreen.c
3078
WREG32(GRBM_SOFT_RESET, 0);
sys/dev/pci/drm/radeon/evergreen.c
3087
WREG32(CP_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
3088
WREG32(CP_SEM_WAIT_TIMER, 0x0);
sys/dev/pci/drm/radeon/evergreen.c
3089
WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
sys/dev/pci/drm/radeon/evergreen.c
3092
WREG32(CP_RB_WPTR_DELAY, 0);
sys/dev/pci/drm/radeon/evergreen.c
3095
WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
sys/dev/pci/drm/radeon/evergreen.c
3096
WREG32(CP_RB_RPTR_WR, 0);
sys/dev/pci/drm/radeon/evergreen.c
3098
WREG32(CP_RB_WPTR, ring->wptr);
sys/dev/pci/drm/radeon/evergreen.c
3101
WREG32(CP_RB_RPTR_ADDR,
sys/dev/pci/drm/radeon/evergreen.c
3103
WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
sys/dev/pci/drm/radeon/evergreen.c
3104
WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
sys/dev/pci/drm/radeon/evergreen.c
3107
WREG32(SCRATCH_UMSK, 0xff);
sys/dev/pci/drm/radeon/evergreen.c
3110
WREG32(SCRATCH_UMSK, 0);
sys/dev/pci/drm/radeon/evergreen.c
3114
WREG32(CP_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
3116
WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
sys/dev/pci/drm/radeon/evergreen.c
3117
WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
sys/dev/pci/drm/radeon/evergreen.c
3386
WREG32((0x2c14 + j), 0x00000000);
sys/dev/pci/drm/radeon/evergreen.c
3387
WREG32((0x2c18 + j), 0x00000000);
sys/dev/pci/drm/radeon/evergreen.c
3388
WREG32((0x2c1c + j), 0x00000000);
sys/dev/pci/drm/radeon/evergreen.c
3389
WREG32((0x2c20 + j), 0x00000000);
sys/dev/pci/drm/radeon/evergreen.c
3390
WREG32((0x2c24 + j), 0x00000000);
sys/dev/pci/drm/radeon/evergreen.c
3393
WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
sys/dev/pci/drm/radeon/evergreen.c
3394
WREG32(SRBM_INT_CNTL, 0x1);
sys/dev/pci/drm/radeon/evergreen.c
3395
WREG32(SRBM_INT_ACK, 0x1);
sys/dev/pci/drm/radeon/evergreen.c
3464
WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
sys/dev/pci/drm/radeon/evergreen.c
3465
WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
sys/dev/pci/drm/radeon/evergreen.c
3485
WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
sys/dev/pci/drm/radeon/evergreen.c
3486
WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
sys/dev/pci/drm/radeon/evergreen.c
3494
WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
sys/dev/pci/drm/radeon/evergreen.c
3495
WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
sys/dev/pci/drm/radeon/evergreen.c
3497
WREG32(GB_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/evergreen.c
3498
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/evergreen.c
3499
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/evergreen.c
3500
WREG32(DMA_TILING_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/evergreen.c
3501
WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/evergreen.c
3502
WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/evergreen.c
3503
WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/evergreen.c
3520
WREG32(GB_BACKEND_MAP, tmp);
sys/dev/pci/drm/radeon/evergreen.c
3522
WREG32(CGTS_SYS_TCC_DISABLE, 0);
sys/dev/pci/drm/radeon/evergreen.c
3523
WREG32(CGTS_TCC_DISABLE, 0);
sys/dev/pci/drm/radeon/evergreen.c
3524
WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
sys/dev/pci/drm/radeon/evergreen.c
3525
WREG32(CGTS_USER_TCC_DISABLE, 0);
sys/dev/pci/drm/radeon/evergreen.c
3528
WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
sys/dev/pci/drm/radeon/evergreen.c
3531
WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
sys/dev/pci/drm/radeon/evergreen.c
3533
WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
sys/dev/pci/drm/radeon/evergreen.c
3540
WREG32(SX_DEBUG_1, sx_debug_1);
sys/dev/pci/drm/radeon/evergreen.c
3546
WREG32(SMX_DC_CTL0, smx_dc_ctl0);
sys/dev/pci/drm/radeon/evergreen.c
3549
WREG32(SMX_SAR_CTL0, 0x00010000);
sys/dev/pci/drm/radeon/evergreen.c
3551
WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
sys/dev/pci/drm/radeon/evergreen.c
3555
WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
sys/dev/pci/drm/radeon/evergreen.c
3559
WREG32(VGT_NUM_INSTANCES, 1);
sys/dev/pci/drm/radeon/evergreen.c
3560
WREG32(SPI_CONFIG_CNTL, 0);
sys/dev/pci/drm/radeon/evergreen.c
3561
WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
sys/dev/pci/drm/radeon/evergreen.c
3562
WREG32(CP_PERFMON_CNTL, 0);
sys/dev/pci/drm/radeon/evergreen.c
3564
WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
sys/dev/pci/drm/radeon/evergreen.c
3630
WREG32(SQ_CONFIG, sq_config);
sys/dev/pci/drm/radeon/evergreen.c
3631
WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
sys/dev/pci/drm/radeon/evergreen.c
3632
WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
sys/dev/pci/drm/radeon/evergreen.c
3633
WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
sys/dev/pci/drm/radeon/evergreen.c
3634
WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
sys/dev/pci/drm/radeon/evergreen.c
3635
WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
sys/dev/pci/drm/radeon/evergreen.c
3636
WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
sys/dev/pci/drm/radeon/evergreen.c
3637
WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
sys/dev/pci/drm/radeon/evergreen.c
3638
WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
sys/dev/pci/drm/radeon/evergreen.c
3639
WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
sys/dev/pci/drm/radeon/evergreen.c
3640
WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
sys/dev/pci/drm/radeon/evergreen.c
3642
WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
sys/dev/pci/drm/radeon/evergreen.c
3658
WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
sys/dev/pci/drm/radeon/evergreen.c
3660
WREG32(VGT_GS_VERTEX_REUSE, 16);
sys/dev/pci/drm/radeon/evergreen.c
3661
WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
sys/dev/pci/drm/radeon/evergreen.c
3662
WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
sys/dev/pci/drm/radeon/evergreen.c
3664
WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
sys/dev/pci/drm/radeon/evergreen.c
3665
WREG32(VGT_OUT_DEALLOC_CNTL, 16);
sys/dev/pci/drm/radeon/evergreen.c
3667
WREG32(CB_PERF_CTR0_SEL_0, 0);
sys/dev/pci/drm/radeon/evergreen.c
3668
WREG32(CB_PERF_CTR0_SEL_1, 0);
sys/dev/pci/drm/radeon/evergreen.c
3669
WREG32(CB_PERF_CTR1_SEL_0, 0);
sys/dev/pci/drm/radeon/evergreen.c
3670
WREG32(CB_PERF_CTR1_SEL_1, 0);
sys/dev/pci/drm/radeon/evergreen.c
3671
WREG32(CB_PERF_CTR2_SEL_0, 0);
sys/dev/pci/drm/radeon/evergreen.c
3672
WREG32(CB_PERF_CTR2_SEL_1, 0);
sys/dev/pci/drm/radeon/evergreen.c
3673
WREG32(CB_PERF_CTR3_SEL_0, 0);
sys/dev/pci/drm/radeon/evergreen.c
3674
WREG32(CB_PERF_CTR3_SEL_1, 0);
sys/dev/pci/drm/radeon/evergreen.c
3677
WREG32(CB_COLOR0_BASE, 0);
sys/dev/pci/drm/radeon/evergreen.c
3678
WREG32(CB_COLOR1_BASE, 0);
sys/dev/pci/drm/radeon/evergreen.c
3679
WREG32(CB_COLOR2_BASE, 0);
sys/dev/pci/drm/radeon/evergreen.c
3680
WREG32(CB_COLOR3_BASE, 0);
sys/dev/pci/drm/radeon/evergreen.c
3681
WREG32(CB_COLOR4_BASE, 0);
sys/dev/pci/drm/radeon/evergreen.c
3682
WREG32(CB_COLOR5_BASE, 0);
sys/dev/pci/drm/radeon/evergreen.c
3683
WREG32(CB_COLOR6_BASE, 0);
sys/dev/pci/drm/radeon/evergreen.c
3684
WREG32(CB_COLOR7_BASE, 0);
sys/dev/pci/drm/radeon/evergreen.c
3685
WREG32(CB_COLOR8_BASE, 0);
sys/dev/pci/drm/radeon/evergreen.c
3686
WREG32(CB_COLOR9_BASE, 0);
sys/dev/pci/drm/radeon/evergreen.c
3687
WREG32(CB_COLOR10_BASE, 0);
sys/dev/pci/drm/radeon/evergreen.c
3688
WREG32(CB_COLOR11_BASE, 0);
sys/dev/pci/drm/radeon/evergreen.c
3692
WREG32(i, 0);
sys/dev/pci/drm/radeon/evergreen.c
3694
WREG32(i, 0);
sys/dev/pci/drm/radeon/evergreen.c
3698
WREG32(HDP_MISC_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
3701
WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
sys/dev/pci/drm/radeon/evergreen.c
3703
WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
sys/dev/pci/drm/radeon/evergreen.c
3908
WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
sys/dev/pci/drm/radeon/evergreen.c
3914
WREG32(DMA_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
3975
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/evergreen.c
3981
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/evergreen.c
3989
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/evergreen.c
3995
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/evergreen.c
4018
WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
sys/dev/pci/drm/radeon/evergreen.c
4023
WREG32(DMA_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
4377
WREG32(RLC_CNTL, mask);
sys/dev/pci/drm/radeon/evergreen.c
4390
WREG32(RLC_HB_CNTL, 0);
sys/dev/pci/drm/radeon/evergreen.c
4401
WREG32(TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK, always_on_bitmap);
sys/dev/pci/drm/radeon/evergreen.c
4402
WREG32(TN_RLC_LB_PARAMS, 0x00601004);
sys/dev/pci/drm/radeon/evergreen.c
4403
WREG32(TN_RLC_LB_INIT_SIMD_MASK, 0xffffffff);
sys/dev/pci/drm/radeon/evergreen.c
4404
WREG32(TN_RLC_LB_CNTR_INIT, 0x00000000);
sys/dev/pci/drm/radeon/evergreen.c
4405
WREG32(TN_RLC_LB_CNTR_MAX, 0x00002000);
sys/dev/pci/drm/radeon/evergreen.c
4408
WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
sys/dev/pci/drm/radeon/evergreen.c
4409
WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
sys/dev/pci/drm/radeon/evergreen.c
4411
WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
sys/dev/pci/drm/radeon/evergreen.c
4412
WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
sys/dev/pci/drm/radeon/evergreen.c
4414
WREG32(RLC_HB_BASE, 0);
sys/dev/pci/drm/radeon/evergreen.c
4415
WREG32(RLC_HB_RPTR, 0);
sys/dev/pci/drm/radeon/evergreen.c
4416
WREG32(RLC_HB_WPTR, 0);
sys/dev/pci/drm/radeon/evergreen.c
4417
WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
sys/dev/pci/drm/radeon/evergreen.c
4418
WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
sys/dev/pci/drm/radeon/evergreen.c
4420
WREG32(RLC_MC_CNTL, 0);
sys/dev/pci/drm/radeon/evergreen.c
4421
WREG32(RLC_UCODE_CNTL, 0);
sys/dev/pci/drm/radeon/evergreen.c
4426
WREG32(RLC_UCODE_ADDR, i);
sys/dev/pci/drm/radeon/evergreen.c
4427
WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/evergreen.c
4431
WREG32(RLC_UCODE_ADDR, i);
sys/dev/pci/drm/radeon/evergreen.c
4432
WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/evergreen.c
4436
WREG32(RLC_UCODE_ADDR, i);
sys/dev/pci/drm/radeon/evergreen.c
4437
WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/evergreen.c
4440
WREG32(RLC_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/evergreen.c
4468
WREG32(CAYMAN_DMA1_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
4470
WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
sys/dev/pci/drm/radeon/evergreen.c
4472
WREG32(DMA_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
4473
WREG32(GRBM_INT_CNTL, 0);
sys/dev/pci/drm/radeon/evergreen.c
4474
WREG32(SRBM_INT_CNTL, 0);
sys/dev/pci/drm/radeon/evergreen.c
4476
WREG32(INT_MASK + crtc_offsets[i], 0);
sys/dev/pci/drm/radeon/evergreen.c
4478
WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0);
sys/dev/pci/drm/radeon/evergreen.c
4482
WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
sys/dev/pci/drm/radeon/evergreen.c
4483
WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
sys/dev/pci/drm/radeon/evergreen.c
4565
WREG32(CP_INT_CNTL, cp_int_cntl);
sys/dev/pci/drm/radeon/evergreen.c
4567
WREG32(DMA_CNTL, dma_cntl);
sys/dev/pci/drm/radeon/evergreen.c
4570
WREG32(CAYMAN_DMA1_CNTL, dma_cntl1);
sys/dev/pci/drm/radeon/evergreen.c
4572
WREG32(GRBM_INT_CNTL, grbm_int_cntl);
sys/dev/pci/drm/radeon/evergreen.c
4583
WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK);
sys/dev/pci/drm/radeon/evergreen.c
4593
WREG32(TN_CG_THERMAL_INT_CTRL, thermal_int);
sys/dev/pci/drm/radeon/evergreen.c
4595
WREG32(CG_THERMAL_INT, thermal_int);
sys/dev/pci/drm/radeon/evergreen.c
4629
WREG32(GRPH_INT_STATUS + crtc_offsets[j],
sys/dev/pci/drm/radeon/evergreen.c
4635
WREG32(VBLANK_STATUS + crtc_offsets[j],
sys/dev/pci/drm/radeon/evergreen.c
4638
WREG32(VLINE_STATUS + crtc_offsets[j],
sys/dev/pci/drm/radeon/evergreen.c
4695
WREG32(IH_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
4838
WREG32(SRBM_INT_ACK, 0x1);
sys/dev/pci/drm/radeon/evergreen.c
4913
WREG32(IH_RB_RPTR, rptr);
sys/dev/pci/drm/radeon/evergreen.c
63
WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
sys/dev/pci/drm/radeon/evergreen.c
74
WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
sys/dev/pci/drm/radeon/evergreen.c
75
WREG32(EVERGREEN_CG_IND_DATA, (v));
sys/dev/pci/drm/radeon/evergreen.c
85
WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
sys/dev/pci/drm/radeon/evergreen.c
96
WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
sys/dev/pci/drm/radeon/evergreen.c
97
WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
sys/dev/pci/drm/radeon/evergreen_hdmi.c
215
WREG32(AFMT_AVI_INFO0 + offset,
sys/dev/pci/drm/radeon/evergreen_hdmi.c
217
WREG32(AFMT_AVI_INFO1 + offset,
sys/dev/pci/drm/radeon/evergreen_hdmi.c
219
WREG32(AFMT_AVI_INFO2 + offset,
sys/dev/pci/drm/radeon/evergreen_hdmi.c
221
WREG32(AFMT_AVI_INFO3 + offset,
sys/dev/pci/drm/radeon/evergreen_hdmi.c
254
WREG32(DCCG_AUDIO_DTO0_CNTL, value);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
262
WREG32(DCCG_AUDIO_DTO_SOURCE, value);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
268
WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
269
WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
279
WREG32(DCCG_AUDIO_DTO1_CNTL, value);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
288
WREG32(DCCG_AUDIO_DTO_SOURCE, value);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
304
WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
305
WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
313
WREG32(HDMI_VBI_PACKET_CONTROL + offset,
sys/dev/pci/drm/radeon/evergreen_hdmi.c
353
WREG32(HDMI_CONTROL + offset, val);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
361
WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
sys/dev/pci/drm/radeon/evergreen_hdmi.c
364
WREG32(AFMT_60958_0 + offset,
sys/dev/pci/drm/radeon/evergreen_hdmi.c
367
WREG32(AFMT_60958_1 + offset,
sys/dev/pci/drm/radeon/evergreen_hdmi.c
370
WREG32(AFMT_60958_2 + offset,
sys/dev/pci/drm/radeon/evergreen_hdmi.c
378
WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
sys/dev/pci/drm/radeon/evergreen_hdmi.c
381
WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
sys/dev/pci/drm/radeon/evergreen_hdmi.c
416
WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,
sys/dev/pci/drm/radeon/evergreen_hdmi.c
424
WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,
sys/dev/pci/drm/radeon/evergreen_hdmi.c
433
WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
462
WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset,
sys/dev/pci/drm/radeon/evergreen_hdmi.c
475
WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
478
WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset,
sys/dev/pci/drm/radeon/evergreen_hdmi.c
484
WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
66
WREG32(AZ_HOT_PLUG_CONTROL, tmp);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
82
WREG32(HDMI_ACR_PACKET_CONTROL + offset,
sys/dev/pci/drm/radeon/evergreen_hdmi.c
85
WREG32(HDMI_ACR_PACKET_CONTROL + offset,
sys/dev/pci/drm/radeon/evergreen_hdmi.c
89
WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));
sys/dev/pci/drm/radeon/evergreen_hdmi.c
90
WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
92
WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz));
sys/dev/pci/drm/radeon/evergreen_hdmi.c
93
WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
95
WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz));
sys/dev/pci/drm/radeon/evergreen_hdmi.c
96
WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz);
sys/dev/pci/drm/radeon/kv_dpm.c
196
WREG32(config_regs->offset << 2, data);
sys/dev/pci/drm/radeon/kv_smc.c
164
WREG32(SMC_IND_DATA_0, data);
sys/dev/pci/drm/radeon/kv_smc.c
177
WREG32(SMC_IND_DATA_0, data);
sys/dev/pci/drm/radeon/kv_smc.c
210
WREG32(SMC_IND_DATA_0, data);
sys/dev/pci/drm/radeon/kv_smc.c
34
WREG32(SMC_MESSAGE_0, id & SMC_MSG_MASK);
sys/dev/pci/drm/radeon/kv_smc.c
69
WREG32(SMC_MSG_ARG_0, parameter);
sys/dev/pci/drm/radeon/kv_smc.c
82
WREG32(SMC_IND_INDEX_0, smc_address);
sys/dev/pci/drm/radeon/ni.c
1069
WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
sys/dev/pci/drm/radeon/ni.c
1070
WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
sys/dev/pci/drm/radeon/ni.c
1089
WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
sys/dev/pci/drm/radeon/ni.c
1090
WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
sys/dev/pci/drm/radeon/ni.c
1098
WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
sys/dev/pci/drm/radeon/ni.c
1099
WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
sys/dev/pci/drm/radeon/ni.c
1101
WREG32(GB_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/ni.c
1102
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/ni.c
1104
WREG32(DMIF_ADDR_CALC, gb_addr_config);
sys/dev/pci/drm/radeon/ni.c
1105
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/ni.c
1106
WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
sys/dev/pci/drm/radeon/ni.c
1107
WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
sys/dev/pci/drm/radeon/ni.c
1108
WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/ni.c
1109
WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/ni.c
1110
WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/ni.c
1129
WREG32(GB_BACKEND_MAP, tmp);
sys/dev/pci/drm/radeon/ni.c
1134
WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
sys/dev/pci/drm/radeon/ni.c
1135
WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
sys/dev/pci/drm/radeon/ni.c
1136
WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
sys/dev/pci/drm/radeon/ni.c
1137
WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
sys/dev/pci/drm/radeon/ni.c
1142
WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
sys/dev/pci/drm/radeon/ni.c
1143
WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
sys/dev/pci/drm/radeon/ni.c
1146
WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
sys/dev/pci/drm/radeon/ni.c
1150
WREG32(SX_DEBUG_1, sx_debug_1);
sys/dev/pci/drm/radeon/ni.c
1155
WREG32(SMX_DC_CTL0, smx_dc_ctl0);
sys/dev/pci/drm/radeon/ni.c
1157
WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
sys/dev/pci/drm/radeon/ni.c
1160
WREG32(VGT_OFFCHIP_LDS_BASE, 0);
sys/dev/pci/drm/radeon/ni.c
1161
WREG32(SQ_LSTMP_RING_BASE, 0);
sys/dev/pci/drm/radeon/ni.c
1162
WREG32(SQ_HSTMP_RING_BASE, 0);
sys/dev/pci/drm/radeon/ni.c
1163
WREG32(SQ_ESTMP_RING_BASE, 0);
sys/dev/pci/drm/radeon/ni.c
1164
WREG32(SQ_GSTMP_RING_BASE, 0);
sys/dev/pci/drm/radeon/ni.c
1165
WREG32(SQ_VSTMP_RING_BASE, 0);
sys/dev/pci/drm/radeon/ni.c
1166
WREG32(SQ_PSTMP_RING_BASE, 0);
sys/dev/pci/drm/radeon/ni.c
1168
WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
sys/dev/pci/drm/radeon/ni.c
1170
WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
sys/dev/pci/drm/radeon/ni.c
1174
WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
sys/dev/pci/drm/radeon/ni.c
1179
WREG32(VGT_NUM_INSTANCES, 1);
sys/dev/pci/drm/radeon/ni.c
1181
WREG32(CP_PERFMON_CNTL, 0);
sys/dev/pci/drm/radeon/ni.c
1183
WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
sys/dev/pci/drm/radeon/ni.c
1188
WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
sys/dev/pci/drm/radeon/ni.c
1189
WREG32(SQ_CONFIG, (VC_ENABLE |
sys/dev/pci/drm/radeon/ni.c
1194
WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
sys/dev/pci/drm/radeon/ni.c
1196
WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
sys/dev/pci/drm/radeon/ni.c
1199
WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
sys/dev/pci/drm/radeon/ni.c
1202
WREG32(VGT_GS_VERTEX_REUSE, 16);
sys/dev/pci/drm/radeon/ni.c
1203
WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
sys/dev/pci/drm/radeon/ni.c
1205
WREG32(CB_PERF_CTR0_SEL_0, 0);
sys/dev/pci/drm/radeon/ni.c
1206
WREG32(CB_PERF_CTR0_SEL_1, 0);
sys/dev/pci/drm/radeon/ni.c
1207
WREG32(CB_PERF_CTR1_SEL_0, 0);
sys/dev/pci/drm/radeon/ni.c
1208
WREG32(CB_PERF_CTR1_SEL_1, 0);
sys/dev/pci/drm/radeon/ni.c
1209
WREG32(CB_PERF_CTR2_SEL_0, 0);
sys/dev/pci/drm/radeon/ni.c
1210
WREG32(CB_PERF_CTR2_SEL_1, 0);
sys/dev/pci/drm/radeon/ni.c
1211
WREG32(CB_PERF_CTR3_SEL_0, 0);
sys/dev/pci/drm/radeon/ni.c
1212
WREG32(CB_PERF_CTR3_SEL_1, 0);
sys/dev/pci/drm/radeon/ni.c
1216
WREG32(HDP_MISC_CNTL, tmp);
sys/dev/pci/drm/radeon/ni.c
1219
WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
sys/dev/pci/drm/radeon/ni.c
1221
WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
sys/dev/pci/drm/radeon/ni.c
1242
WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
sys/dev/pci/drm/radeon/ni.c
1245
WREG32(VM_INVALIDATE_REQUEST, 1);
sys/dev/pci/drm/radeon/ni.c
1260
WREG32(MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/radeon/ni.c
1268
WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
sys/dev/pci/drm/radeon/ni.c
1274
WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
sys/dev/pci/drm/radeon/ni.c
1275
WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
sys/dev/pci/drm/radeon/ni.c
1279
WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
sys/dev/pci/drm/radeon/ni.c
1280
WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
sys/dev/pci/drm/radeon/ni.c
1281
WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
sys/dev/pci/drm/radeon/ni.c
1282
WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
sys/dev/pci/drm/radeon/ni.c
1284
WREG32(VM_CONTEXT0_CNTL2, 0);
sys/dev/pci/drm/radeon/ni.c
1285
WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
sys/dev/pci/drm/radeon/ni.c
1288
WREG32(0x15D4, 0);
sys/dev/pci/drm/radeon/ni.c
1289
WREG32(0x15D8, 0);
sys/dev/pci/drm/radeon/ni.c
1290
WREG32(0x15DC, 0);
sys/dev/pci/drm/radeon/ni.c
1298
WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
sys/dev/pci/drm/radeon/ni.c
1299
WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2),
sys/dev/pci/drm/radeon/ni.c
1301
WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
sys/dev/pci/drm/radeon/ni.c
1306
WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
sys/dev/pci/drm/radeon/ni.c
1308
WREG32(VM_CONTEXT1_CNTL2, 4);
sys/dev/pci/drm/radeon/ni.c
1309
WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
sys/dev/pci/drm/radeon/ni.c
1342
WREG32(VM_CONTEXT0_CNTL, 0);
sys/dev/pci/drm/radeon/ni.c
1343
WREG32(VM_CONTEXT1_CNTL, 0);
sys/dev/pci/drm/radeon/ni.c
1345
WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
sys/dev/pci/drm/radeon/ni.c
1349
WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
sys/dev/pci/drm/radeon/ni.c
1353
WREG32(VM_L2_CNTL2, 0);
sys/dev/pci/drm/radeon/ni.c
1354
WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
sys/dev/pci/drm/radeon/ni.c
1369
WREG32(SRBM_GFX_CNTL, RINGID(ring));
sys/dev/pci/drm/radeon/ni.c
1370
WREG32(CP_INT_CNTL, cp_int_cntl);
sys/dev/pci/drm/radeon/ni.c
1438
WREG32(CP_ME_CNTL, 0);
sys/dev/pci/drm/radeon/ni.c
1442
WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
sys/dev/pci/drm/radeon/ni.c
1443
WREG32(SCRATCH_UMSK, 0);
sys/dev/pci/drm/radeon/ni.c
1486
WREG32(CP_RB0_WPTR, ring->wptr);
sys/dev/pci/drm/radeon/ni.c
1489
WREG32(CP_RB1_WPTR, ring->wptr);
sys/dev/pci/drm/radeon/ni.c
1492
WREG32(CP_RB2_WPTR, ring->wptr);
sys/dev/pci/drm/radeon/ni.c
1508
WREG32(CP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/ni.c
1510
WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/ni.c
1511
WREG32(CP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/ni.c
1514
WREG32(CP_ME_RAM_WADDR, 0);
sys/dev/pci/drm/radeon/ni.c
1516
WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/ni.c
1518
WREG32(CP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/ni.c
1519
WREG32(CP_ME_RAM_WADDR, 0);
sys/dev/pci/drm/radeon/ni.c
1520
WREG32(CP_ME_RAM_RADDR, 0);
sys/dev/pci/drm/radeon/ni.c
1639
WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
sys/dev/pci/drm/radeon/ni.c
1647
WREG32(GRBM_SOFT_RESET, 0);
sys/dev/pci/drm/radeon/ni.c
1650
WREG32(CP_SEM_WAIT_TIMER, 0x0);
sys/dev/pci/drm/radeon/ni.c
1651
WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
sys/dev/pci/drm/radeon/ni.c
1654
WREG32(CP_RB_WPTR_DELAY, 0);
sys/dev/pci/drm/radeon/ni.c
1656
WREG32(CP_DEBUG, (1 << 27));
sys/dev/pci/drm/radeon/ni.c
1659
WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
sys/dev/pci/drm/radeon/ni.c
1660
WREG32(SCRATCH_UMSK, 0xff);
sys/dev/pci/drm/radeon/ni.c
1673
WREG32(cp_rb_cntl[i], rb_cntl);
sys/dev/pci/drm/radeon/ni.c
1677
WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
sys/dev/pci/drm/radeon/ni.c
1678
WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
sys/dev/pci/drm/radeon/ni.c
1684
WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
sys/dev/pci/drm/radeon/ni.c
1693
WREG32(cp_rb_rptr[i], 0);
sys/dev/pci/drm/radeon/ni.c
1694
WREG32(cp_rb_wptr[i], ring->wptr);
sys/dev/pci/drm/radeon/ni.c
1820
WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
sys/dev/pci/drm/radeon/ni.c
1826
WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/ni.c
1833
WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/ni.c
1897
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/ni.c
1903
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/ni.c
1911
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/ni.c
1917
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/ni.c
53
WREG32(TN_SMC_IND_INDEX_0, (reg));
sys/dev/pci/drm/radeon/ni.c
64
WREG32(TN_SMC_IND_INDEX_0, (reg));
sys/dev/pci/drm/radeon/ni.c
65
WREG32(TN_SMC_IND_DATA_0, (v));
sys/dev/pci/drm/radeon/ni.c
657
WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
sys/dev/pci/drm/radeon/ni.c
658
WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
sys/dev/pci/drm/radeon/ni.c
662
WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
sys/dev/pci/drm/radeon/ni.c
663
WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
sys/dev/pci/drm/radeon/ni.c
668
WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/ni.c
671
WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
sys/dev/pci/drm/radeon/ni.c
672
WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
sys/dev/pci/drm/radeon/ni.c
673
WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
sys/dev/pci/drm/radeon/ni.c
980
WREG32((0x2c14 + j), 0x00000000);
sys/dev/pci/drm/radeon/ni.c
981
WREG32((0x2c18 + j), 0x00000000);
sys/dev/pci/drm/radeon/ni.c
982
WREG32((0x2c1c + j), 0x00000000);
sys/dev/pci/drm/radeon/ni.c
983
WREG32((0x2c20 + j), 0x00000000);
sys/dev/pci/drm/radeon/ni.c
984
WREG32((0x2c24 + j), 0x00000000);
sys/dev/pci/drm/radeon/ni.c
987
WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
sys/dev/pci/drm/radeon/ni.c
988
WREG32(SRBM_INT_CNTL, 0x1);
sys/dev/pci/drm/radeon/ni.c
989
WREG32(SRBM_INT_ACK, 0x1);
sys/dev/pci/drm/radeon/ni_dma.c
110
WREG32(reg, (ring->wptr << 2) & 0x3fffc);
sys/dev/pci/drm/radeon/ni_dma.c
167
WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl);
sys/dev/pci/drm/radeon/ni_dma.c
172
WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl);
sys/dev/pci/drm/radeon/ni_dma.c
205
WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
sys/dev/pci/drm/radeon/ni_dma.c
206
WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
sys/dev/pci/drm/radeon/ni_dma.c
214
WREG32(DMA_RB_CNTL + reg_offset, rb_cntl);
sys/dev/pci/drm/radeon/ni_dma.c
217
WREG32(DMA_RB_RPTR + reg_offset, 0);
sys/dev/pci/drm/radeon/ni_dma.c
218
WREG32(DMA_RB_WPTR + reg_offset, 0);
sys/dev/pci/drm/radeon/ni_dma.c
221
WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset,
sys/dev/pci/drm/radeon/ni_dma.c
223
WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset,
sys/dev/pci/drm/radeon/ni_dma.c
229
WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8);
sys/dev/pci/drm/radeon/ni_dma.c
236
WREG32(DMA_IB_CNTL + reg_offset, ib_cntl);
sys/dev/pci/drm/radeon/ni_dma.c
240
WREG32(DMA_CNTL + reg_offset, dma_cntl);
sys/dev/pci/drm/radeon/ni_dma.c
243
WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2);
sys/dev/pci/drm/radeon/ni_dma.c
245
WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE);
sys/dev/pci/drm/radeon/ni_dpm.c
1039
WREG32(SMC_SCRATCH0, parameter);
sys/dev/pci/drm/radeon/ni_dpm.c
1539
WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
sys/dev/pci/drm/radeon/ni_dpm.c
1540
WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
sys/dev/pci/drm/radeon/ni_dpm.c
1544
WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
sys/dev/pci/drm/radeon/ni_dpm.c
1545
WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
sys/dev/pci/drm/radeon/ni_dpm.c
1549
WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
sys/dev/pci/drm/radeon/ni_dpm.c
1550
WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
sys/dev/pci/drm/radeon/ni_dpm.c
1554
WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
sys/dev/pci/drm/radeon/ni_dpm.c
1555
WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
sys/dev/pci/drm/radeon/ni_dpm.c
1563
WREG32(MC_CG_CONFIG, mc_cg_config);
sys/dev/pci/drm/radeon/ni_dpm.c
2886
WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
sys/dev/pci/drm/radeon/ni_dpm.c
2887
WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
sys/dev/pci/drm/radeon/ni_dpm.c
2888
WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
sys/dev/pci/drm/radeon/ni_dpm.c
2889
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
sys/dev/pci/drm/radeon/ni_dpm.c
2890
WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
sys/dev/pci/drm/radeon/ni_dpm.c
2891
WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
sys/dev/pci/drm/radeon/ni_dpm.c
2892
WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
sys/dev/pci/drm/radeon/ni_dpm.c
2893
WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
sys/dev/pci/drm/radeon/ni_dpm.c
2894
WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
sys/dev/pci/drm/radeon/ni_dpm.c
2895
WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
sys/dev/pci/drm/radeon/ni_dpm.c
2896
WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
sys/dev/pci/drm/radeon/ni_dpm.c
2897
WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
sys/dev/pci/drm/radeon/ni_dpm.c
2898
WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
sys/dev/pci/drm/radeon/ni_dpm.c
3157
WREG32(CG_CAC_CTRL, reg);
sys/dev/pci/drm/radeon/ni_dpm.c
3360
WREG32(SQ_CAC_THRESHOLD, reg);
sys/dev/pci/drm/radeon/ni_dpm.c
3367
WREG32(MC_CG_CONFIG, reg);
sys/dev/pci/drm/radeon/ni_dpm.c
3372
WREG32(MC_CG_DATAPORT, reg);
sys/dev/pci/drm/radeon/ni_dpm.c
3472
WREG32(CG_BIF_REQ_AND_RSP, bif);
sys/dev/pci/drm/radeon/ni_dpm.c
3487
WREG32(CG_BIF_REQ_AND_RSP, bif);
sys/dev/pci/drm/radeon/r100.c
1115
WREG32(RADEON_CP_RB_WPTR, ring->wptr);
sys/dev/pci/drm/radeon/r100.c
1131
WREG32(RADEON_CP_ME_RAM_ADDR, 0);
sys/dev/pci/drm/radeon/r100.c
1133
WREG32(RADEON_CP_ME_RAM_DATAH,
sys/dev/pci/drm/radeon/r100.c
1135
WREG32(RADEON_CP_ME_RAM_DATAL,
sys/dev/pci/drm/radeon/r100.c
1197
WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
sys/dev/pci/drm/radeon/r100.c
1204
WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
sys/dev/pci/drm/radeon/r100.c
1208
WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
sys/dev/pci/drm/radeon/r100.c
1210
WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
sys/dev/pci/drm/radeon/r100.c
1211
WREG32(RADEON_CP_RB_RPTR_WR, 0);
sys/dev/pci/drm/radeon/r100.c
1213
WREG32(RADEON_CP_RB_WPTR, ring->wptr);
sys/dev/pci/drm/radeon/r100.c
1216
WREG32(R_00070C_CP_RB_RPTR_ADDR,
sys/dev/pci/drm/radeon/r100.c
1218
WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
sys/dev/pci/drm/radeon/r100.c
1221
WREG32(R_000770_SCRATCH_UMSK, 0xff);
sys/dev/pci/drm/radeon/r100.c
1224
WREG32(R_000770_SCRATCH_UMSK, 0);
sys/dev/pci/drm/radeon/r100.c
1227
WREG32(RADEON_CP_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
1230
WREG32(RADEON_CP_CSQ_MODE,
sys/dev/pci/drm/radeon/r100.c
1233
WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
sys/dev/pci/drm/radeon/r100.c
1234
WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
sys/dev/pci/drm/radeon/r100.c
1235
WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
sys/dev/pci/drm/radeon/r100.c
1277
WREG32(RADEON_CP_CSQ_MODE, 0);
sys/dev/pci/drm/radeon/r100.c
1278
WREG32(RADEON_CP_CSQ_CNTL, 0);
sys/dev/pci/drm/radeon/r100.c
1279
WREG32(R_000770_SCRATCH_UMSK, 0);
sys/dev/pci/drm/radeon/r100.c
174
WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/r100.c
181
WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
sys/dev/pci/drm/radeon/r100.c
193
WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/r100.c
2566
WREG32(RADEON_BUS_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
2575
WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
sys/dev/pci/drm/radeon/r100.c
2577
WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
sys/dev/pci/drm/radeon/r100.c
2579
WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
sys/dev/pci/drm/radeon/r100.c
2600
WREG32(RADEON_CP_CSQ_CNTL, 0);
sys/dev/pci/drm/radeon/r100.c
2602
WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
sys/dev/pci/drm/radeon/r100.c
2603
WREG32(RADEON_CP_RB_RPTR_WR, 0);
sys/dev/pci/drm/radeon/r100.c
2604
WREG32(RADEON_CP_RB_WPTR, 0);
sys/dev/pci/drm/radeon/r100.c
2605
WREG32(RADEON_CP_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
2610
WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
sys/dev/pci/drm/radeon/r100.c
2616
WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
sys/dev/pci/drm/radeon/r100.c
2621
WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
sys/dev/pci/drm/radeon/r100.c
2624
WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
sys/dev/pci/drm/radeon/r100.c
2648
WREG32(RADEON_OV0_SCALE_CNTL, 0);
sys/dev/pci/drm/radeon/r100.c
2649
WREG32(RADEON_SUBPIC_CNTL, 0);
sys/dev/pci/drm/radeon/r100.c
2650
WREG32(RADEON_VIPH_CONTROL, 0);
sys/dev/pci/drm/radeon/r100.c
2651
WREG32(RADEON_I2C_CNTL_1, 0);
sys/dev/pci/drm/radeon/r100.c
2652
WREG32(RADEON_DVI_I2C_CNTL_1, 0);
sys/dev/pci/drm/radeon/r100.c
2653
WREG32(RADEON_CAP0_TRIG_CNTL, 0);
sys/dev/pci/drm/radeon/r100.c
2654
WREG32(RADEON_CAP1_TRIG_CNTL, 0);
sys/dev/pci/drm/radeon/r100.c
2713
WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
sys/dev/pci/drm/radeon/r100.c
2714
WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
sys/dev/pci/drm/radeon/r100.c
2715
WREG32(RADEON_DAC_CNTL2, dac2_cntl);
sys/dev/pci/drm/radeon/r100.c
2818
WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
sys/dev/pci/drm/radeon/r100.c
2827
WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
sys/dev/pci/drm/radeon/r100.c
2853
WREG32(RADEON_CONFIG_CNTL, temp);
sys/dev/pci/drm/radeon/r100.c
2903
WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
sys/dev/pci/drm/radeon/r100.c
2905
WREG32(RADEON_CLOCK_CNTL_INDEX, save);
sys/dev/pci/drm/radeon/r100.c
2930
WREG32(RADEON_CLOCK_CNTL_DATA, v);
sys/dev/pci/drm/radeon/r100.c
2962
WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
sys/dev/pci/drm/radeon/r100.c
2964
WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
sys/dev/pci/drm/radeon/r100.c
3026
WREG32(RADEON_CP_CSQ_ADDR, i << 2);
sys/dev/pci/drm/radeon/r100.c
3032
WREG32(RADEON_CP_CSQ_ADDR, i << 2);
sys/dev/pci/drm/radeon/r100.c
3038
WREG32(RADEON_CP_CSQ_ADDR, i << 2);
sys/dev/pci/drm/radeon/r100.c
3154
WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
sys/dev/pci/drm/radeon/r100.c
3155
WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
sys/dev/pci/drm/radeon/r100.c
3156
WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
sys/dev/pci/drm/radeon/r100.c
3163
WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
sys/dev/pci/drm/radeon/r100.c
3274
WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
sys/dev/pci/drm/radeon/r100.c
3380
WREG32(R300_MC_IND_INDEX, temp);
sys/dev/pci/drm/radeon/r100.c
3540
WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
sys/dev/pci/drm/radeon/r100.c
3550
WREG32(RS400_DISP1_REQ_CNTL1, (temp |
sys/dev/pci/drm/radeon/r100.c
3556
WREG32(RS400_DMIF_MEM_CNTL1, (temp |
sys/dev/pci/drm/radeon/r100.c
3632
WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
sys/dev/pci/drm/radeon/r100.c
3642
WREG32(RS400_DISP2_REQ_CNTL1, (temp |
sys/dev/pci/drm/radeon/r100.c
3648
WREG32(RS400_DISP2_REQ_CNTL2, (temp |
sys/dev/pci/drm/radeon/r100.c
3652
WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
sys/dev/pci/drm/radeon/r100.c
3653
WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
sys/dev/pci/drm/radeon/r100.c
3654
WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
sys/dev/pci/drm/radeon/r100.c
3655
WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
sys/dev/pci/drm/radeon/r100.c
3682
WREG32(scratch, 0xCAFEDEAD);
sys/dev/pci/drm/radeon/r100.c
3738
WREG32(scratch, 0xCAFEDEAD);
sys/dev/pci/drm/radeon/r100.c
376
WREG32(voltage->gpio.reg, tmp);
sys/dev/pci/drm/radeon/r100.c
3796
WREG32(R_000740_CP_CSQ_CNTL, 0);
sys/dev/pci/drm/radeon/r100.c
3811
WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
sys/dev/pci/drm/radeon/r100.c
3812
WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
sys/dev/pci/drm/radeon/r100.c
3814
WREG32(R_000050_CRTC_GEN_CNTL,
sys/dev/pci/drm/radeon/r100.c
3817
WREG32(R_000420_OV0_SCALE_CNTL,
sys/dev/pci/drm/radeon/r100.c
3819
WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
sys/dev/pci/drm/radeon/r100.c
3821
WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
sys/dev/pci/drm/radeon/r100.c
3823
WREG32(R_0003F8_CRTC2_GEN_CNTL,
sys/dev/pci/drm/radeon/r100.c
3827
WREG32(R_000360_CUR2_OFFSET,
sys/dev/pci/drm/radeon/r100.c
3835
WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
sys/dev/pci/drm/radeon/r100.c
3837
WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
sys/dev/pci/drm/radeon/r100.c
3841
WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
sys/dev/pci/drm/radeon/r100.c
3842
WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
sys/dev/pci/drm/radeon/r100.c
3844
WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
sys/dev/pci/drm/radeon/r100.c
385
WREG32(voltage->gpio.reg, tmp);
sys/dev/pci/drm/radeon/r100.c
3863
WREG32(R_00014C_MC_AGP_LOCATION,
sys/dev/pci/drm/radeon/r100.c
3866
WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
sys/dev/pci/drm/radeon/r100.c
3868
WREG32(R_00015C_AGP_BASE_2,
sys/dev/pci/drm/radeon/r100.c
3871
WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
sys/dev/pci/drm/radeon/r100.c
3872
WREG32(R_000170_AGP_BASE, 0);
sys/dev/pci/drm/radeon/r100.c
3874
WREG32(R_00015C_AGP_BASE_2, 0);
sys/dev/pci/drm/radeon/r100.c
3880
WREG32(R_000148_MC_FB_LOCATION,
sys/dev/pci/drm/radeon/r100.c
4027
WREG32(RADEON_CP_CSQ_CNTL, 0);
sys/dev/pci/drm/radeon/r100.c
4031
WREG32(RADEON_CP_RB_CNTL, 0);
sys/dev/pci/drm/radeon/r100.c
4035
WREG32(RADEON_SCRATCH_UMSK, 0);
sys/dev/pci/drm/radeon/r100.c
474
WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
478
WREG32(RADEON_CRTC_GEN_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
505
WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
509
WREG32(RADEON_CRTC_GEN_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
581
WREG32(RADEON_FP_GEN_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
589
WREG32(RADEON_FP2_GEN_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
677
WREG32(RADEON_AIC_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
679
WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
sys/dev/pci/drm/radeon/r100.c
680
WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
sys/dev/pci/drm/radeon/r100.c
682
WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
sys/dev/pci/drm/radeon/r100.c
684
WREG32(RADEON_AIC_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
699
WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
sys/dev/pci/drm/radeon/r100.c
700
WREG32(RADEON_AIC_LO_ADDR, 0);
sys/dev/pci/drm/radeon/r100.c
701
WREG32(RADEON_AIC_HI_ADDR, 0);
sys/dev/pci/drm/radeon/r100.c
729
WREG32(R_000040_GEN_INT_CNTL, 0);
sys/dev/pci/drm/radeon/r100.c
749
WREG32(RADEON_GEN_INT_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
761
WREG32(R_000040_GEN_INT_CNTL, 0);
sys/dev/pci/drm/radeon/r100.c
765
WREG32(R_000044_GEN_INT_STATUS, tmp);
sys/dev/pci/drm/radeon/r100.c
776
WREG32(RADEON_GEN_INT_STATUS, irqs);
sys/dev/pci/drm/radeon/r100.c
834
WREG32(RADEON_AIC_CNTL, msi_rearm);
sys/dev/pci/drm/radeon/r100.c
835
WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
sys/dev/pci/drm/radeon/r100.c
838
WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
sys/dev/pci/drm/radeon/r300.c
1336
WREG32(R_00014C_MC_AGP_LOCATION,
sys/dev/pci/drm/radeon/r300.c
1339
WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
sys/dev/pci/drm/radeon/r300.c
1340
WREG32(R_00015C_AGP_BASE_2,
sys/dev/pci/drm/radeon/r300.c
1343
WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
sys/dev/pci/drm/radeon/r300.c
1344
WREG32(R_000170_AGP_BASE, 0);
sys/dev/pci/drm/radeon/r300.c
1345
WREG32(R_00015C_AGP_BASE_2, 0);
sys/dev/pci/drm/radeon/r300.c
1351
WREG32(R_000148_MC_FB_LOCATION,
sys/dev/pci/drm/radeon/r300.c
392
WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
sys/dev/pci/drm/radeon/r300.c
399
WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
sys/dev/pci/drm/radeon/r300.c
401
WREG32(R300_RB2D_DSTCACHE_MODE,
sys/dev/pci/drm/radeon/r300.c
429
WREG32(RADEON_CP_CSQ_CNTL, 0);
sys/dev/pci/drm/radeon/r300.c
431
WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
sys/dev/pci/drm/radeon/r300.c
432
WREG32(RADEON_CP_RB_RPTR_WR, 0);
sys/dev/pci/drm/radeon/r300.c
433
WREG32(RADEON_CP_RB_WPTR, 0);
sys/dev/pci/drm/radeon/r300.c
434
WREG32(RADEON_CP_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/r300.c
439
WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
sys/dev/pci/drm/radeon/r300.c
443
WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
sys/dev/pci/drm/radeon/r300.c
452
WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
sys/dev/pci/drm/radeon/r300.c
455
WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
sys/dev/pci/drm/radeon/r300.c
66
WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
sys/dev/pci/drm/radeon/r300.c
77
WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
sys/dev/pci/drm/radeon/r300.c
78
WREG32(RADEON_PCIE_DATA, (v));
sys/dev/pci/drm/radeon/r420.c
132
WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
sys/dev/pci/drm/radeon/r420.c
135
WREG32(R300_GB_TILE_CONFIG, tmp);
sys/dev/pci/drm/radeon/r420.c
141
WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
sys/dev/pci/drm/radeon/r420.c
143
WREG32(R300_RB2D_DSTCACHE_MODE,
sys/dev/pci/drm/radeon/r420.c
171
WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
sys/dev/pci/drm/radeon/r420.c
182
WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
sys/dev/pci/drm/radeon/r420.c
184
WREG32(R_0001FC_MC_IND_DATA, v);
sys/dev/pci/drm/radeon/r420.c
97
WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
sys/dev/pci/drm/radeon/r520.c
144
WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
sys/dev/pci/drm/radeon/r520.c
149
WREG32(R_000134_HDP_FB_LOCATION,
sys/dev/pci/drm/radeon/r520.c
79
WREG32(0x4128, 0xFF);
sys/dev/pci/drm/radeon/r600.c
1002
WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
sys/dev/pci/drm/radeon/r600.c
1005
WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
sys/dev/pci/drm/radeon/r600.c
1029
WREG32(DC_HPD1_CONTROL, 0);
sys/dev/pci/drm/radeon/r600.c
1032
WREG32(DC_HPD2_CONTROL, 0);
sys/dev/pci/drm/radeon/r600.c
1035
WREG32(DC_HPD3_CONTROL, 0);
sys/dev/pci/drm/radeon/r600.c
1038
WREG32(DC_HPD4_CONTROL, 0);
sys/dev/pci/drm/radeon/r600.c
1042
WREG32(DC_HPD5_CONTROL, 0);
sys/dev/pci/drm/radeon/r600.c
1045
WREG32(DC_HPD6_CONTROL, 0);
sys/dev/pci/drm/radeon/r600.c
1053
WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
sys/dev/pci/drm/radeon/r600.c
1056
WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
sys/dev/pci/drm/radeon/r600.c
1059
WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
sys/dev/pci/drm/radeon/r600.c
1089
WREG32(HDP_DEBUG1, 0);
sys/dev/pci/drm/radeon/r600.c
1092
WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
sys/dev/pci/drm/radeon/r600.c
1094
WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
sys/dev/pci/drm/radeon/r600.c
1095
WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
sys/dev/pci/drm/radeon/r600.c
1096
WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
sys/dev/pci/drm/radeon/r600.c
1142
WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
sys/dev/pci/drm/radeon/r600.c
1145
WREG32(VM_L2_CNTL2, 0);
sys/dev/pci/drm/radeon/r600.c
1146
WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
sys/dev/pci/drm/radeon/r600.c
1152
WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1153
WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1154
WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
sys/dev/pci/drm/radeon/r600.c
1155
WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1156
WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1157
WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1158
WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1159
WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1160
WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1161
WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1162
WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1163
WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1164
WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1165
WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1166
WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
sys/dev/pci/drm/radeon/r600.c
1167
WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
sys/dev/pci/drm/radeon/r600.c
1168
WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
sys/dev/pci/drm/radeon/r600.c
1169
WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
sys/dev/pci/drm/radeon/r600.c
1170
WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
sys/dev/pci/drm/radeon/r600.c
1171
WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
sys/dev/pci/drm/radeon/r600.c
1173
WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
sys/dev/pci/drm/radeon/r600.c
1176
WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
sys/dev/pci/drm/radeon/r600.c
1193
WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
sys/dev/pci/drm/radeon/r600.c
1196
WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
sys/dev/pci/drm/radeon/r600.c
1198
WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
sys/dev/pci/drm/radeon/r600.c
1202
WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1203
WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1204
WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1205
WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1206
WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1207
WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1208
WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1209
WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1210
WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1211
WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1212
WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1213
WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1214
WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1215
WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1216
WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1217
WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1234
WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
sys/dev/pci/drm/radeon/r600.c
1237
WREG32(VM_L2_CNTL2, 0);
sys/dev/pci/drm/radeon/r600.c
1238
WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
sys/dev/pci/drm/radeon/r600.c
1244
WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1245
WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1246
WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
sys/dev/pci/drm/radeon/r600.c
1247
WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1248
WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1249
WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1250
WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1251
WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1252
WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1253
WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1254
WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1255
WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1256
WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
sys/dev/pci/drm/radeon/r600.c
1257
WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
sys/dev/pci/drm/radeon/r600.c
1259
WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
sys/dev/pci/drm/radeon/r600.c
126
WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
sys/dev/pci/drm/radeon/r600.c
1283
WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
sys/dev/pci/drm/radeon/r600.c
1285
WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
sys/dev/pci/drm/radeon/r600.c
1295
WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
sys/dev/pci/drm/radeon/r600.c
1297
WREG32(R_0028FC_MC_DATA, v);
sys/dev/pci/drm/radeon/r600.c
1298
WREG32(R_0028F8_MC_INDEX, 0x7F);
sys/dev/pci/drm/radeon/r600.c
1310
WREG32((0x2c14 + j), 0x00000000);
sys/dev/pci/drm/radeon/r600.c
1311
WREG32((0x2c18 + j), 0x00000000);
sys/dev/pci/drm/radeon/r600.c
1312
WREG32((0x2c1c + j), 0x00000000);
sys/dev/pci/drm/radeon/r600.c
1313
WREG32((0x2c20 + j), 0x00000000);
sys/dev/pci/drm/radeon/r600.c
1314
WREG32((0x2c24 + j), 0x00000000);
sys/dev/pci/drm/radeon/r600.c
1316
WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
sys/dev/pci/drm/radeon/r600.c
1323
WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
sys/dev/pci/drm/radeon/r600.c
1328
WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
sys/dev/pci/drm/radeon/r600.c
1330
WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
sys/dev/pci/drm/radeon/r600.c
1334
WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
sys/dev/pci/drm/radeon/r600.c
1336
WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
sys/dev/pci/drm/radeon/r600.c
1340
WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
sys/dev/pci/drm/radeon/r600.c
1341
WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
sys/dev/pci/drm/radeon/r600.c
1343
WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
sys/dev/pci/drm/radeon/r600.c
1346
WREG32(MC_VM_FB_LOCATION, tmp);
sys/dev/pci/drm/radeon/r600.c
1347
WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
sys/dev/pci/drm/radeon/r600.c
1348
WREG32(HDP_NONSURFACE_INFO, (2 << 7));
sys/dev/pci/drm/radeon/r600.c
1349
WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
sys/dev/pci/drm/radeon/r600.c
1351
WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
sys/dev/pci/drm/radeon/r600.c
1352
WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
sys/dev/pci/drm/radeon/r600.c
1353
WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
sys/dev/pci/drm/radeon/r600.c
1355
WREG32(MC_VM_AGP_BASE, 0);
sys/dev/pci/drm/radeon/r600.c
1356
WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
sys/dev/pci/drm/radeon/r600.c
1357
WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
sys/dev/pci/drm/radeon/r600.c
137
WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
sys/dev/pci/drm/radeon/r600.c
138
WREG32(R600_RCU_DATA, (v));
sys/dev/pci/drm/radeon/r600.c
148
WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
sys/dev/pci/drm/radeon/r600.c
1563
WREG32(R600_BIOS_3_SCRATCH, tmp);
sys/dev/pci/drm/radeon/r600.c
159
WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
sys/dev/pci/drm/radeon/r600.c
160
WREG32(R600_UVD_CTX_DATA, (v));
sys/dev/pci/drm/radeon/r600.c
1699
WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
sys/dev/pci/drm/radeon/r600.c
1701
WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
sys/dev/pci/drm/radeon/r600.c
1704
WREG32(RLC_CNTL, 0);
sys/dev/pci/drm/radeon/r600.c
1710
WREG32(DMA_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1787
WREG32(R_008020_GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/r600.c
1793
WREG32(R_008020_GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/r600.c
1801
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/r600.c
1807
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/r600.c
1831
WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
sys/dev/pci/drm/radeon/r600.c
1833
WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
sys/dev/pci/drm/radeon/r600.c
1836
WREG32(RLC_CNTL, 0);
sys/dev/pci/drm/radeon/r600.c
1841
WREG32(DMA_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1859
WREG32(BUS_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1869
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/r600.c
1871
WREG32(SRBM_SOFT_RESET, 0);
sys/dev/pci/drm/radeon/r600.c
2076
WREG32((0x2c14 + j), 0x00000000);
sys/dev/pci/drm/radeon/r600.c
2077
WREG32((0x2c18 + j), 0x00000000);
sys/dev/pci/drm/radeon/r600.c
2078
WREG32((0x2c1c + j), 0x00000000);
sys/dev/pci/drm/radeon/r600.c
2079
WREG32((0x2c20 + j), 0x00000000);
sys/dev/pci/drm/radeon/r600.c
2080
WREG32((0x2c24 + j), 0x00000000);
sys/dev/pci/drm/radeon/r600.c
2083
WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
sys/dev/pci/drm/radeon/r600.c
2140
WREG32(GB_TILING_CONFIG, tiling_config);
sys/dev/pci/drm/radeon/r600.c
2141
WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
sys/dev/pci/drm/radeon/r600.c
2142
WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
sys/dev/pci/drm/radeon/r600.c
2143
WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
sys/dev/pci/drm/radeon/r600.c
2146
WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
sys/dev/pci/drm/radeon/r600.c
2147
WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
sys/dev/pci/drm/radeon/r600.c
2150
WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
sys/dev/pci/drm/radeon/r600.c
2151
WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
sys/dev/pci/drm/radeon/r600.c
2153
WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
sys/dev/pci/drm/radeon/r600.c
2157
WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
sys/dev/pci/drm/radeon/r600.c
2163
WREG32(SX_DEBUG_1, tmp);
sys/dev/pci/drm/radeon/r600.c
2171
WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
sys/dev/pci/drm/radeon/r600.c
2173
WREG32(DB_DEBUG, 0);
sys/dev/pci/drm/radeon/r600.c
2175
WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
sys/dev/pci/drm/radeon/r600.c
2178
WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
sys/dev/pci/drm/radeon/r600.c
2179
WREG32(VGT_NUM_INSTANCES, 0);
sys/dev/pci/drm/radeon/r600.c
2181
WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
sys/dev/pci/drm/radeon/r600.c
2182
WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
sys/dev/pci/drm/radeon/r600.c
2198
WREG32(SQ_MS_FIFO_SIZES, tmp);
sys/dev/pci/drm/radeon/r600.c
2280
WREG32(SQ_CONFIG, sq_config);
sys/dev/pci/drm/radeon/r600.c
2281
WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
sys/dev/pci/drm/radeon/r600.c
2282
WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
sys/dev/pci/drm/radeon/r600.c
2283
WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
sys/dev/pci/drm/radeon/r600.c
2284
WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
sys/dev/pci/drm/radeon/r600.c
2285
WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
sys/dev/pci/drm/radeon/r600.c
2291
WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
sys/dev/pci/drm/radeon/r600.c
2293
WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
sys/dev/pci/drm/radeon/r600.c
2297
WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
sys/dev/pci/drm/radeon/r600.c
2299
WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
sys/dev/pci/drm/radeon/r600.c
2303
WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
sys/dev/pci/drm/radeon/r600.c
2307
WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
sys/dev/pci/drm/radeon/r600.c
2312
WREG32(VGT_STRMOUT_EN, 0);
sys/dev/pci/drm/radeon/r600.c
2330
WREG32(VGT_ES_PER_GS, 128);
sys/dev/pci/drm/radeon/r600.c
2331
WREG32(VGT_GS_PER_ES, tmp);
sys/dev/pci/drm/radeon/r600.c
2332
WREG32(VGT_GS_PER_VS, 2);
sys/dev/pci/drm/radeon/r600.c
2333
WREG32(VGT_GS_VERTEX_REUSE, 16);
sys/dev/pci/drm/radeon/r600.c
2336
WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
sys/dev/pci/drm/radeon/r600.c
2337
WREG32(VGT_STRMOUT_EN, 0);
sys/dev/pci/drm/radeon/r600.c
2338
WREG32(SX_MISC, 0);
sys/dev/pci/drm/radeon/r600.c
2339
WREG32(PA_SC_MODE_CNTL, 0);
sys/dev/pci/drm/radeon/r600.c
2340
WREG32(PA_SC_AA_CONFIG, 0);
sys/dev/pci/drm/radeon/r600.c
2341
WREG32(PA_SC_LINE_STIPPLE, 0);
sys/dev/pci/drm/radeon/r600.c
2342
WREG32(SPI_INPUT_Z, 0);
sys/dev/pci/drm/radeon/r600.c
2343
WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
sys/dev/pci/drm/radeon/r600.c
2344
WREG32(CB_COLOR7_FRAG, 0);
sys/dev/pci/drm/radeon/r600.c
2347
WREG32(CB_COLOR0_BASE, 0);
sys/dev/pci/drm/radeon/r600.c
2348
WREG32(CB_COLOR1_BASE, 0);
sys/dev/pci/drm/radeon/r600.c
2349
WREG32(CB_COLOR2_BASE, 0);
sys/dev/pci/drm/radeon/r600.c
2350
WREG32(CB_COLOR3_BASE, 0);
sys/dev/pci/drm/radeon/r600.c
2351
WREG32(CB_COLOR4_BASE, 0);
sys/dev/pci/drm/radeon/r600.c
2352
WREG32(CB_COLOR5_BASE, 0);
sys/dev/pci/drm/radeon/r600.c
2353
WREG32(CB_COLOR6_BASE, 0);
sys/dev/pci/drm/radeon/r600.c
2354
WREG32(CB_COLOR7_BASE, 0);
sys/dev/pci/drm/radeon/r600.c
2355
WREG32(CB_COLOR7_FRAG, 0);
sys/dev/pci/drm/radeon/r600.c
2375
WREG32(TC_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
2378
WREG32(HDP_HOST_PATH_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
2382
WREG32(ARB_POP, tmp);
sys/dev/pci/drm/radeon/r600.c
2384
WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
sys/dev/pci/drm/radeon/r600.c
2385
WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
sys/dev/pci/drm/radeon/r600.c
2387
WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
sys/dev/pci/drm/radeon/r600.c
2388
WREG32(VC_ENHANCE, 0);
sys/dev/pci/drm/radeon/r600.c
2401
WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
sys/dev/pci/drm/radeon/r600.c
2413
WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
sys/dev/pci/drm/radeon/r600.c
2415
WREG32(PCIE_PORT_DATA, (v));
sys/dev/pci/drm/radeon/r600.c
2427
WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
sys/dev/pci/drm/radeon/r600.c
2428
WREG32(SCRATCH_UMSK, 0);
sys/dev/pci/drm/radeon/r600.c
2640
WREG32(R600_CP_RB_WPTR, ring->wptr);
sys/dev/pci/drm/radeon/r600.c
2654
WREG32(CP_RB_CNTL,
sys/dev/pci/drm/radeon/r600.c
2661
WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
sys/dev/pci/drm/radeon/r600.c
2664
WREG32(GRBM_SOFT_RESET, 0);
sys/dev/pci/drm/radeon/r600.c
2666
WREG32(CP_ME_RAM_WADDR, 0);
sys/dev/pci/drm/radeon/r600.c
2669
WREG32(CP_ME_RAM_WADDR, 0);
sys/dev/pci/drm/radeon/r600.c
2671
WREG32(CP_ME_RAM_DATA,
sys/dev/pci/drm/radeon/r600.c
2675
WREG32(CP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/r600.c
2677
WREG32(CP_PFP_UCODE_DATA,
sys/dev/pci/drm/radeon/r600.c
2680
WREG32(CP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/r600.c
2681
WREG32(CP_ME_RAM_WADDR, 0);
sys/dev/pci/drm/radeon/r600.c
2682
WREG32(CP_ME_RAM_RADDR, 0);
sys/dev/pci/drm/radeon/r600.c
2712
WREG32(R_0086D8_CP_ME_CNTL, cp_me);
sys/dev/pci/drm/radeon/r600.c
2724
WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
sys/dev/pci/drm/radeon/r600.c
2727
WREG32(GRBM_SOFT_RESET, 0);
sys/dev/pci/drm/radeon/r600.c
2735
WREG32(CP_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
2736
WREG32(CP_SEM_WAIT_TIMER, 0x0);
sys/dev/pci/drm/radeon/r600.c
2739
WREG32(CP_RB_WPTR_DELAY, 0);
sys/dev/pci/drm/radeon/r600.c
2742
WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
sys/dev/pci/drm/radeon/r600.c
2743
WREG32(CP_RB_RPTR_WR, 0);
sys/dev/pci/drm/radeon/r600.c
2745
WREG32(CP_RB_WPTR, ring->wptr);
sys/dev/pci/drm/radeon/r600.c
2748
WREG32(CP_RB_RPTR_ADDR,
sys/dev/pci/drm/radeon/r600.c
2750
WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
sys/dev/pci/drm/radeon/r600.c
2751
WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
sys/dev/pci/drm/radeon/r600.c
2754
WREG32(SCRATCH_UMSK, 0xff);
sys/dev/pci/drm/radeon/r600.c
2757
WREG32(SCRATCH_UMSK, 0);
sys/dev/pci/drm/radeon/r600.c
2761
WREG32(CP_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
2763
WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
sys/dev/pci/drm/radeon/r600.c
2764
WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
sys/dev/pci/drm/radeon/r600.c
2835
WREG32(scratch, 0xCAFEDEAD);
sys/dev/pci/drm/radeon/r600.c
3201
WREG32(CONFIG_CNTL, temp);
sys/dev/pci/drm/radeon/r600.c
3409
WREG32(scratch, 0xCAFEDEAD);
sys/dev/pci/drm/radeon/r600.c
346
WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/r600.c
3536
WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
sys/dev/pci/drm/radeon/r600.c
3539
WREG32(SRBM_SOFT_RESET, 0);
sys/dev/pci/drm/radeon/r600.c
3543
WREG32(RLC_CNTL, 0);
sys/dev/pci/drm/radeon/r600.c
3548
WREG32(RLC_CNTL, RLC_ENABLE);
sys/dev/pci/drm/radeon/r600.c
3561
WREG32(RLC_HB_CNTL, 0);
sys/dev/pci/drm/radeon/r600.c
3563
WREG32(RLC_HB_BASE, 0);
sys/dev/pci/drm/radeon/r600.c
3564
WREG32(RLC_HB_RPTR, 0);
sys/dev/pci/drm/radeon/r600.c
3565
WREG32(RLC_HB_WPTR, 0);
sys/dev/pci/drm/radeon/r600.c
3566
WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
sys/dev/pci/drm/radeon/r600.c
3567
WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
sys/dev/pci/drm/radeon/r600.c
3568
WREG32(RLC_MC_CNTL, 0);
sys/dev/pci/drm/radeon/r600.c
3569
WREG32(RLC_UCODE_CNTL, 0);
sys/dev/pci/drm/radeon/r600.c
3574
WREG32(RLC_UCODE_ADDR, i);
sys/dev/pci/drm/radeon/r600.c
3575
WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/r600.c
3579
WREG32(RLC_UCODE_ADDR, i);
sys/dev/pci/drm/radeon/r600.c
3580
WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/r600.c
3583
WREG32(RLC_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/r600.c
3597
WREG32(IH_CNTL, ih_cntl);
sys/dev/pci/drm/radeon/r600.c
3598
WREG32(IH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/radeon/r600.c
3609
WREG32(IH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/radeon/r600.c
3610
WREG32(IH_CNTL, ih_cntl);
sys/dev/pci/drm/radeon/r600.c
3612
WREG32(IH_RB_RPTR, 0);
sys/dev/pci/drm/radeon/r600.c
3613
WREG32(IH_RB_WPTR, 0);
sys/dev/pci/drm/radeon/r600.c
3622
WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
sys/dev/pci/drm/radeon/r600.c
3624
WREG32(DMA_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
3625
WREG32(GRBM_INT_CNTL, 0);
sys/dev/pci/drm/radeon/r600.c
3626
WREG32(DxMODE_INT_MASK, 0);
sys/dev/pci/drm/radeon/r600.c
3627
WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
sys/dev/pci/drm/radeon/r600.c
3628
WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
sys/dev/pci/drm/radeon/r600.c
3630
WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
sys/dev/pci/drm/radeon/r600.c
3631
WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
sys/dev/pci/drm/radeon/r600.c
3633
WREG32(DC_HPD1_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3635
WREG32(DC_HPD2_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3637
WREG32(DC_HPD3_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3639
WREG32(DC_HPD4_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3642
WREG32(DC_HPD5_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3644
WREG32(DC_HPD6_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3646
WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
sys/dev/pci/drm/radeon/r600.c
3648
WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
sys/dev/pci/drm/radeon/r600.c
3651
WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3653
WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3656
WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
sys/dev/pci/drm/radeon/r600.c
3657
WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
sys/dev/pci/drm/radeon/r600.c
3659
WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3661
WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3663
WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3665
WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3667
WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3697
WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8);
sys/dev/pci/drm/radeon/r600.c
3705
WREG32(INTERRUPT_CNTL, interrupt_cntl);
sys/dev/pci/drm/radeon/r600.c
3707
WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
sys/dev/pci/drm/radeon/r600.c
3718
WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
sys/dev/pci/drm/radeon/r600.c
3719
WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
sys/dev/pci/drm/radeon/r600.c
3721
WREG32(IH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/radeon/r600.c
3724
WREG32(IH_RB_RPTR, 0);
sys/dev/pci/drm/radeon/r600.c
3725
WREG32(IH_RB_WPTR, 0);
sys/dev/pci/drm/radeon/r600.c
3732
WREG32(IH_CNTL, ih_cntl);
sys/dev/pci/drm/radeon/r600.c
3873
WREG32(CP_INT_CNTL, cp_int_cntl);
sys/dev/pci/drm/radeon/r600.c
3874
WREG32(DMA_CNTL, dma_cntl);
sys/dev/pci/drm/radeon/r600.c
3875
WREG32(DxMODE_INT_MASK, mode_int);
sys/dev/pci/drm/radeon/r600.c
3876
WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
sys/dev/pci/drm/radeon/r600.c
3877
WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
sys/dev/pci/drm/radeon/r600.c
3878
WREG32(GRBM_INT_CNTL, grbm_int_cntl);
sys/dev/pci/drm/radeon/r600.c
3880
WREG32(DC_HPD1_INT_CONTROL, hpd1);
sys/dev/pci/drm/radeon/r600.c
3881
WREG32(DC_HPD2_INT_CONTROL, hpd2);
sys/dev/pci/drm/radeon/r600.c
3882
WREG32(DC_HPD3_INT_CONTROL, hpd3);
sys/dev/pci/drm/radeon/r600.c
3883
WREG32(DC_HPD4_INT_CONTROL, hpd4);
sys/dev/pci/drm/radeon/r600.c
3885
WREG32(DC_HPD5_INT_CONTROL, hpd5);
sys/dev/pci/drm/radeon/r600.c
3886
WREG32(DC_HPD6_INT_CONTROL, hpd6);
sys/dev/pci/drm/radeon/r600.c
3887
WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
sys/dev/pci/drm/radeon/r600.c
3888
WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
sys/dev/pci/drm/radeon/r600.c
3890
WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
sys/dev/pci/drm/radeon/r600.c
3891
WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
sys/dev/pci/drm/radeon/r600.c
3894
WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
sys/dev/pci/drm/radeon/r600.c
3895
WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
sys/dev/pci/drm/radeon/r600.c
3896
WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
sys/dev/pci/drm/radeon/r600.c
3897
WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
sys/dev/pci/drm/radeon/r600.c
3898
WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
sys/dev/pci/drm/radeon/r600.c
3901
WREG32(CG_THERMAL_INT, thermal_int);
sys/dev/pci/drm/radeon/r600.c
3903
WREG32(RV770_CG_THERMAL_INT, thermal_int);
sys/dev/pci/drm/radeon/r600.c
3938
WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
sys/dev/pci/drm/radeon/r600.c
3940
WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
sys/dev/pci/drm/radeon/r600.c
3942
WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
sys/dev/pci/drm/radeon/r600.c
3944
WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
sys/dev/pci/drm/radeon/r600.c
3946
WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
sys/dev/pci/drm/radeon/r600.c
3948
WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
sys/dev/pci/drm/radeon/r600.c
3953
WREG32(DC_HPD1_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3957
WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3964
WREG32(DC_HPD2_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3968
WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3975
WREG32(DC_HPD3_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3979
WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3985
WREG32(DC_HPD4_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3991
WREG32(DC_HPD5_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3996
WREG32(DC_HPD6_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
4001
WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
sys/dev/pci/drm/radeon/r600.c
4006
WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
sys/dev/pci/drm/radeon/r600.c
4012
WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
4018
WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
4022
WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
4057
WREG32(IH_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
4324
WREG32(IH_RB_RPTR, rptr);
sys/dev/pci/drm/radeon/r600.c
4391
WREG32(HDP_DEBUG1, 0);
sys/dev/pci/drm/radeon/r600.c
4394
WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
sys/dev/pci/drm/radeon/r600.c
4552
WREG32(MM_CFGREGS_CNTL, 0x8);
sys/dev/pci/drm/radeon/r600.c
4554
WREG32(MM_CFGREGS_CNTL, 0);
sys/dev/pci/drm/radeon/r600.c
4568
WREG32(0x541c, tmp | 0x8);
sys/dev/pci/drm/radeon/r600.c
4569
WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
sys/dev/pci/drm/radeon/r600.c
4574
WREG32(MM_CFGREGS_CNTL, 0);
sys/dev/pci/drm/radeon/r600.c
4616
WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
sys/dev/pci/drm/radeon/r600.c
873
WREG32(DC_HPD1_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
881
WREG32(DC_HPD2_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
889
WREG32(DC_HPD3_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
897
WREG32(DC_HPD4_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
905
WREG32(DC_HPD5_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
914
WREG32(DC_HPD6_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
927
WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
935
WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
943
WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
975
WREG32(DC_HPD1_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
978
WREG32(DC_HPD2_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
981
WREG32(DC_HPD3_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
984
WREG32(DC_HPD4_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
988
WREG32(DC_HPD5_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
991
WREG32(DC_HPD6_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
999
WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
sys/dev/pci/drm/radeon/r600_dma.c
106
WREG32(DMA_RB_CNTL, rb_cntl);
sys/dev/pci/drm/radeon/r600_dma.c
126
WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
sys/dev/pci/drm/radeon/r600_dma.c
127
WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
sys/dev/pci/drm/radeon/r600_dma.c
135
WREG32(DMA_RB_CNTL, rb_cntl);
sys/dev/pci/drm/radeon/r600_dma.c
138
WREG32(DMA_RB_RPTR, 0);
sys/dev/pci/drm/radeon/r600_dma.c
139
WREG32(DMA_RB_WPTR, 0);
sys/dev/pci/drm/radeon/r600_dma.c
142
WREG32(DMA_RB_RPTR_ADDR_HI,
sys/dev/pci/drm/radeon/r600_dma.c
144
WREG32(DMA_RB_RPTR_ADDR_LO,
sys/dev/pci/drm/radeon/r600_dma.c
150
WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
sys/dev/pci/drm/radeon/r600_dma.c
157
WREG32(DMA_IB_CNTL, ib_cntl);
sys/dev/pci/drm/radeon/r600_dma.c
161
WREG32(DMA_CNTL, dma_cntl);
sys/dev/pci/drm/radeon/r600_dma.c
164
WREG32(DMA_MODE, 1);
sys/dev/pci/drm/radeon/r600_dma.c
167
WREG32(DMA_RB_WPTR, ring->wptr << 2);
sys/dev/pci/drm/radeon/r600_dma.c
169
WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);
sys/dev/pci/drm/radeon/r600_dma.c
88
WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc);
sys/dev/pci/drm/radeon/r600_dpm.c
249
WREG32(CG_RLC_REQ_AND_RSP, 0x2);
sys/dev/pci/drm/radeon/r600_dpm.c
257
WREG32(CG_RLC_REQ_AND_RSP, 0x0);
sys/dev/pci/drm/radeon/r600_dpm.c
259
WREG32(GRBM_PWR_CNTL, 0x1);
sys/dev/pci/drm/radeon/r600_dpm.c
338
WREG32(CG_BSP, BSP(p) | BSU(u));
sys/dev/pci/drm/radeon/r600_dpm.c
345
WREG32(CG_RT, FLS(l_to_m) | FMS(m_to_h));
sys/dev/pci/drm/radeon/r600_dpm.c
346
WREG32(CG_LT, FHS(h_to_m) | FMS(m_to_l));
sys/dev/pci/drm/radeon/r600_dpm.c
352
WREG32(CG_FFCT_0 + (index * 4), UTC_0(u_t) | DTC_0(d_t));
sys/dev/pci/drm/radeon/r600_dpm.c
370
WREG32(CG_FTV, vrv);
sys/dev/pci/drm/radeon/r600_dpm.c
522
WREG32(LOWER_GPIO_ENABLE, mask & 0xffffffff);
sys/dev/pci/drm/radeon/r600_dpm.c
523
WREG32(UPPER_GPIO_ENABLE, upper_32_bits(mask));
sys/dev/pci/drm/radeon/r600_dpm.c
533
WREG32(CTXSW_VID_LOWER_GPIO_CNTL + (ix * 4), pins & 0xffffffff);
sys/dev/pci/drm/radeon/r600_dpm.c
538
WREG32(VID_UPPER_GPIO_CNTL, tmp);
sys/dev/pci/drm/radeon/r600_dpm.c
548
WREG32(GPIOPAD_MASK, gpio);
sys/dev/pci/drm/radeon/r600_dpm.c
552
WREG32(GPIOPAD_EN, gpio);
sys/dev/pci/drm/radeon/r600_dpm.c
556
WREG32(GPIOPAD_A, gpio);
sys/dev/pci/drm/radeon/r600_hdmi.c
169
WREG32(AZ_HOT_PLUG_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600_hdmi.c
223
WREG32(HDMI0_AVI_INFO0 + offset,
sys/dev/pci/drm/radeon/r600_hdmi.c
225
WREG32(HDMI0_AVI_INFO1 + offset,
sys/dev/pci/drm/radeon/r600_hdmi.c
227
WREG32(HDMI0_AVI_INFO2 + offset,
sys/dev/pci/drm/radeon/r600_hdmi.c
229
WREG32(HDMI0_AVI_INFO3 + offset,
sys/dev/pci/drm/radeon/r600_hdmi.c
254
WREG32(HDMI0_AUDIO_INFO0 + offset,
sys/dev/pci/drm/radeon/r600_hdmi.c
256
WREG32(HDMI0_AUDIO_INFO1 + offset,
sys/dev/pci/drm/radeon/r600_hdmi.c
309
WREG32(DCCG_AUDIO_DTO0_PHASE, 24000 * 100);
sys/dev/pci/drm/radeon/r600_hdmi.c
310
WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
sys/dev/pci/drm/radeon/r600_hdmi.c
311
WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
sys/dev/pci/drm/radeon/r600_hdmi.c
313
WREG32(DCCG_AUDIO_DTO1_PHASE, 24000 * 100);
sys/dev/pci/drm/radeon/r600_hdmi.c
314
WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
sys/dev/pci/drm/radeon/r600_hdmi.c
315
WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
sys/dev/pci/drm/radeon/r600_hdmi.c
429
WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
sys/dev/pci/drm/radeon/r600_hdmi.c
497
WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
sys/dev/pci/drm/radeon/radeon.h
2585
WREG32(reg, tmp_); \
sys/dev/pci/drm/radeon/radeon_agp.c
374
WREG32(RADEON_AGP_CNTL, RREG32(RADEON_AGP_CNTL) | 0x000e0000);
sys/dev/pci/drm/radeon/radeon_atombios.c
4106
WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
sys/dev/pci/drm/radeon/radeon_atombios.c
4107
WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
sys/dev/pci/drm/radeon/radeon_atombios.c
4109
WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
sys/dev/pci/drm/radeon/radeon_atombios.c
4110
WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
sys/dev/pci/drm/radeon/radeon_atombios.c
4140
WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
sys/dev/pci/drm/radeon/radeon_atombios.c
4163
WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
sys/dev/pci/drm/radeon/radeon_atombios.c
4165
WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
sys/dev/pci/drm/radeon/radeon_atombios.c
4345
WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
sys/dev/pci/drm/radeon/radeon_atombios.c
4346
WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
sys/dev/pci/drm/radeon/radeon_atombios.c
4347
WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
sys/dev/pci/drm/radeon/radeon_atombios.c
4349
WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
sys/dev/pci/drm/radeon/radeon_atombios.c
4350
WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
sys/dev/pci/drm/radeon/radeon_atombios.c
4351
WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
sys/dev/pci/drm/radeon/radeon_atombios.c
4405
WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
sys/dev/pci/drm/radeon/radeon_atombios.c
4407
WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
sys/dev/pci/drm/radeon/radeon_atombios.c
4488
WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
sys/dev/pci/drm/radeon/radeon_atombios.c
4490
WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
sys/dev/pci/drm/radeon/radeon_audio.c
65
WREG32(reg, v);
sys/dev/pci/drm/radeon/radeon_bios.c
406
WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
sys/dev/pci/drm/radeon/radeon_bios.c
409
WREG32(AVIVO_D1VGA_CONTROL,
sys/dev/pci/drm/radeon/radeon_bios.c
412
WREG32(AVIVO_D2VGA_CONTROL,
sys/dev/pci/drm/radeon/radeon_bios.c
415
WREG32(AVIVO_VGA_RENDER_CONTROL,
sys/dev/pci/drm/radeon/radeon_bios.c
418
WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
sys/dev/pci/drm/radeon/radeon_bios.c
423
WREG32(R600_BUS_CNTL, bus_cntl);
sys/dev/pci/drm/radeon/radeon_bios.c
425
WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
sys/dev/pci/drm/radeon/radeon_bios.c
426
WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
sys/dev/pci/drm/radeon/radeon_bios.c
427
WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
sys/dev/pci/drm/radeon/radeon_bios.c
429
WREG32(R600_ROM_CNTL, rom_cntl);
sys/dev/pci/drm/radeon/radeon_bios.c
453
WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
sys/dev/pci/drm/radeon/radeon_bios.c
455
WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
sys/dev/pci/drm/radeon/radeon_bios.c
457
WREG32(AVIVO_D1VGA_CONTROL,
sys/dev/pci/drm/radeon/radeon_bios.c
460
WREG32(AVIVO_D2VGA_CONTROL,
sys/dev/pci/drm/radeon/radeon_bios.c
463
WREG32(AVIVO_VGA_RENDER_CONTROL,
sys/dev/pci/drm/radeon/radeon_bios.c
470
WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
sys/dev/pci/drm/radeon/radeon_bios.c
478
WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
sys/dev/pci/drm/radeon/radeon_bios.c
480
WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
sys/dev/pci/drm/radeon/radeon_bios.c
486
WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
sys/dev/pci/drm/radeon/radeon_bios.c
493
WREG32(RADEON_VIPH_CONTROL, viph_control);
sys/dev/pci/drm/radeon/radeon_bios.c
494
WREG32(R600_BUS_CNTL, bus_cntl);
sys/dev/pci/drm/radeon/radeon_bios.c
495
WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
sys/dev/pci/drm/radeon/radeon_bios.c
496
WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
sys/dev/pci/drm/radeon/radeon_bios.c
497
WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
sys/dev/pci/drm/radeon/radeon_bios.c
498
WREG32(R600_ROM_CNTL, rom_cntl);
sys/dev/pci/drm/radeon/radeon_bios.c
542
WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
sys/dev/pci/drm/radeon/radeon_bios.c
544
WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
sys/dev/pci/drm/radeon/radeon_bios.c
546
WREG32(AVIVO_D1VGA_CONTROL,
sys/dev/pci/drm/radeon/radeon_bios.c
549
WREG32(AVIVO_D2VGA_CONTROL,
sys/dev/pci/drm/radeon/radeon_bios.c
552
WREG32(AVIVO_VGA_RENDER_CONTROL,
sys/dev/pci/drm/radeon/radeon_bios.c
555
WREG32(R600_ROM_CNTL,
sys/dev/pci/drm/radeon/radeon_bios.c
560
WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
sys/dev/pci/drm/radeon/radeon_bios.c
561
WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
sys/dev/pci/drm/radeon/radeon_bios.c
563
WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
sys/dev/pci/drm/radeon/radeon_bios.c
565
WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
sys/dev/pci/drm/radeon/radeon_bios.c
567
WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
sys/dev/pci/drm/radeon/radeon_bios.c
569
WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
sys/dev/pci/drm/radeon/radeon_bios.c
574
WREG32(RADEON_VIPH_CONTROL, viph_control);
sys/dev/pci/drm/radeon/radeon_bios.c
575
WREG32(R600_BUS_CNTL, bus_cntl);
sys/dev/pci/drm/radeon/radeon_bios.c
576
WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
sys/dev/pci/drm/radeon/radeon_bios.c
577
WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
sys/dev/pci/drm/radeon/radeon_bios.c
578
WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
sys/dev/pci/drm/radeon/radeon_bios.c
579
WREG32(R600_ROM_CNTL, rom_cntl);
sys/dev/pci/drm/radeon/radeon_bios.c
580
WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
sys/dev/pci/drm/radeon/radeon_bios.c
581
WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
sys/dev/pci/drm/radeon/radeon_bios.c
582
WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
sys/dev/pci/drm/radeon/radeon_bios.c
583
WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
sys/dev/pci/drm/radeon/radeon_bios.c
584
WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
sys/dev/pci/drm/radeon/radeon_bios.c
585
WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
sys/dev/pci/drm/radeon/radeon_bios.c
612
WREG32(RADEON_SEPROM_CNTL1,
sys/dev/pci/drm/radeon/radeon_bios.c
615
WREG32(RADEON_GPIOPAD_A, 0);
sys/dev/pci/drm/radeon/radeon_bios.c
616
WREG32(RADEON_GPIOPAD_EN, 0);
sys/dev/pci/drm/radeon/radeon_bios.c
617
WREG32(RADEON_GPIOPAD_MASK, 0);
sys/dev/pci/drm/radeon/radeon_bios.c
620
WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
sys/dev/pci/drm/radeon/radeon_bios.c
623
WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
sys/dev/pci/drm/radeon/radeon_bios.c
626
WREG32(AVIVO_D1VGA_CONTROL,
sys/dev/pci/drm/radeon/radeon_bios.c
629
WREG32(AVIVO_D2VGA_CONTROL,
sys/dev/pci/drm/radeon/radeon_bios.c
632
WREG32(AVIVO_VGA_RENDER_CONTROL,
sys/dev/pci/drm/radeon/radeon_bios.c
638
WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
sys/dev/pci/drm/radeon/radeon_bios.c
639
WREG32(RADEON_VIPH_CONTROL, viph_control);
sys/dev/pci/drm/radeon/radeon_bios.c
640
WREG32(RV370_BUS_CNTL, bus_cntl);
sys/dev/pci/drm/radeon/radeon_bios.c
641
WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
sys/dev/pci/drm/radeon/radeon_bios.c
642
WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
sys/dev/pci/drm/radeon/radeon_bios.c
643
WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
sys/dev/pci/drm/radeon/radeon_bios.c
644
WREG32(RADEON_GPIOPAD_A, gpiopad_a);
sys/dev/pci/drm/radeon/radeon_bios.c
645
WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
sys/dev/pci/drm/radeon/radeon_bios.c
646
WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
sys/dev/pci/drm/radeon/radeon_bios.c
680
WREG32(RADEON_SEPROM_CNTL1,
sys/dev/pci/drm/radeon/radeon_bios.c
685
WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
sys/dev/pci/drm/radeon/radeon_bios.c
689
WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
sys/dev/pci/drm/radeon/radeon_bios.c
691
WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
sys/dev/pci/drm/radeon/radeon_bios.c
694
WREG32(RADEON_CRTC_GEN_CNTL,
sys/dev/pci/drm/radeon/radeon_bios.c
699
WREG32(RADEON_CRTC2_GEN_CNTL,
sys/dev/pci/drm/radeon/radeon_bios.c
704
WREG32(RADEON_CRTC_EXT_CNTL,
sys/dev/pci/drm/radeon/radeon_bios.c
710
WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
sys/dev/pci/drm/radeon/radeon_bios.c
716
WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
sys/dev/pci/drm/radeon/radeon_bios.c
717
WREG32(RADEON_VIPH_CONTROL, viph_control);
sys/dev/pci/drm/radeon/radeon_bios.c
719
WREG32(RV370_BUS_CNTL, bus_cntl);
sys/dev/pci/drm/radeon/radeon_bios.c
721
WREG32(RADEON_BUS_CNTL, bus_cntl);
sys/dev/pci/drm/radeon/radeon_bios.c
722
WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
sys/dev/pci/drm/radeon/radeon_bios.c
724
WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
sys/dev/pci/drm/radeon/radeon_bios.c
726
WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
sys/dev/pci/drm/radeon/radeon_bios.c
728
WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
sys/dev/pci/drm/radeon/radeon_combios.c
2911
WREG32(reg, val);
sys/dev/pci/drm/radeon/radeon_combios.c
2921
WREG32(reg, val);
sys/dev/pci/drm/radeon/radeon_combios.c
2965
WREG32(reg, val);
sys/dev/pci/drm/radeon/radeon_combios.c
2975
WREG32(reg, val);
sys/dev/pci/drm/radeon/radeon_combios.c
3028
WREG32(addr, val);
sys/dev/pci/drm/radeon/radeon_combios.c
3033
WREG32(addr, val);
sys/dev/pci/drm/radeon/radeon_combios.c
3043
WREG32(addr, tmp);
sys/dev/pci/drm/radeon/radeon_combios.c
3053
WREG32(addr, tmp);
sys/dev/pci/drm/radeon/radeon_combios.c
3215
WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
sys/dev/pci/drm/radeon/radeon_combios.c
3221
WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
sys/dev/pci/drm/radeon/radeon_combios.c
3242
WREG32(RADEON_MEM_CNTL, mem_cntl);
sys/dev/pci/drm/radeon/radeon_combios.c
3281
WREG32(RADEON_MEM_CNTL, mem_cntl);
sys/dev/pci/drm/radeon/radeon_combios.c
3319
WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
sys/dev/pci/drm/radeon/radeon_combios.c
3433
WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
sys/dev/pci/drm/radeon/radeon_combios.c
3434
WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
sys/dev/pci/drm/radeon/radeon_combios.c
3435
WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
sys/dev/pci/drm/radeon/radeon_combios.c
3451
WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
sys/dev/pci/drm/radeon/radeon_combios.c
3553
WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
sys/dev/pci/drm/radeon/radeon_combios.c
3554
WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
sys/dev/pci/drm/radeon/radeon_combios.c
3589
WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
sys/dev/pci/drm/radeon/radeon_combios.c
3624
WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
sys/dev/pci/drm/radeon/radeon_cursor.c
101
WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/radeon_cursor.c
103
WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/radeon_cursor.c
104
WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |
sys/dev/pci/drm/radeon/radeon_cursor.c
110
WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH,
sys/dev/pci/drm/radeon/radeon_cursor.c
113
WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH,
sys/dev/pci/drm/radeon/radeon_cursor.c
117
WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/radeon_cursor.c
119
WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/radeon_cursor.c
120
WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
sys/dev/pci/drm/radeon/radeon_cursor.c
124
WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/radeon_cursor.c
129
WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_cursor.c
132
WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_cursor.c
218
WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
sys/dev/pci/drm/radeon/radeon_cursor.c
219
WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
sys/dev/pci/drm/radeon/radeon_cursor.c
220
WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/radeon_cursor.c
223
WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
sys/dev/pci/drm/radeon/radeon_cursor.c
224
WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
sys/dev/pci/drm/radeon/radeon_cursor.c
225
WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/radeon_cursor.c
234
WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/radeon_cursor.c
238
WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/radeon_cursor.c
243
WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/radeon_cursor.c
44
WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
sys/dev/pci/drm/radeon/radeon_cursor.c
51
WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
sys/dev/pci/drm/radeon/radeon_cursor.c
58
WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
sys/dev/pci/drm/radeon/radeon_cursor.c
99
WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/radeon_device.c
224
WREG32(reg, tmp);
sys/dev/pci/drm/radeon/radeon_device.c
253
WREG32(RADEON_SURFACE_CNTL, 0);
sys/dev/pci/drm/radeon/radeon_device.c
916
WREG32(reg*4, val);
sys/dev/pci/drm/radeon/radeon_display.c
100
WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/radeon_display.c
102
WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
sys/dev/pci/drm/radeon/radeon_display.c
103
WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
sys/dev/pci/drm/radeon/radeon_display.c
104
WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
sys/dev/pci/drm/radeon/radeon_display.c
106
WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/radeon_display.c
107
WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
sys/dev/pci/drm/radeon/radeon_display.c
109
WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/radeon_display.c
114
WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/radeon_display.c
133
WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/radeon_display.c
136
WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/radeon_display.c
138
WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/radeon_display.c
140
WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/radeon_display.c
144
WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/radeon_display.c
146
WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/radeon_display.c
147
WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/radeon_display.c
148
WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/radeon_display.c
150
WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
sys/dev/pci/drm/radeon/radeon_display.c
151
WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
sys/dev/pci/drm/radeon/radeon_display.c
152
WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
sys/dev/pci/drm/radeon/radeon_display.c
154
WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/radeon_display.c
155
WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
sys/dev/pci/drm/radeon/radeon_display.c
157
WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/radeon_display.c
162
WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/radeon_display.c
168
WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/radeon_display.c
173
WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/radeon_display.c
176
WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/radeon_display.c
179
WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/radeon_display.c
183
WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/radeon_display.c
188
WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/radeon_display.c
207
WREG32(RADEON_DAC_CNTL2, dac2_cntl);
sys/dev/pci/drm/radeon/radeon_display.c
214
WREG32(RADEON_PALETTE_30_DATA,
sys/dev/pci/drm/radeon/radeon_display.c
58
WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/radeon_display.c
60
WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/radeon_display.c
61
WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/radeon_display.c
62
WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/radeon_display.c
64
WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
sys/dev/pci/drm/radeon/radeon_display.c
65
WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
sys/dev/pci/drm/radeon/radeon_display.c
66
WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
sys/dev/pci/drm/radeon/radeon_display.c
68
WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
sys/dev/pci/drm/radeon/radeon_display.c
69
WREG32(AVIVO_DC_LUT_RW_MODE, 0);
sys/dev/pci/drm/radeon/radeon_display.c
70
WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
sys/dev/pci/drm/radeon/radeon_display.c
77
WREG32(AVIVO_DC_LUT_30_COLOR,
sys/dev/pci/drm/radeon/radeon_display.c
96
WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/radeon_display.c
98
WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/radeon_display.c
99
WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
101
WREG32(chan->rec.mask_clk_reg, tmp);
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
110
WREG32(AUX_CONTROL + aux_offset[instance], tmp);
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
113
WREG32(AUX_SW_CONTROL + aux_offset[instance],
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
115
WREG32(AUX_SW_CONTROL + aux_offset[instance],
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
121
WREG32(AUX_SW_DATA + aux_offset[instance],
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
125
WREG32(AUX_SW_DATA + aux_offset[instance],
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
129
WREG32(AUX_SW_DATA + aux_offset[instance],
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
133
WREG32(AUX_SW_DATA + aux_offset[instance],
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
139
WREG32(AUX_SW_DATA + aux_offset[instance],
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
145
WREG32(AUX_SW_INTERRUPT_CONTROL + aux_offset[instance], AUX_SW_DONE_ACK);
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
148
WREG32(AUX_SW_CONTROL + aux_offset[instance],
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
178
WREG32(AUX_SW_DATA + aux_offset[instance],
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
193
WREG32(AUX_SW_INTERRUPT_CONTROL + aux_offset[instance], AUX_SW_DONE_ACK);
sys/dev/pci/drm/radeon/radeon_drv.c
902
WREG32(RADEON_PALETTE_30_DATA,
sys/dev/pci/drm/radeon/radeon_fence.c
75
WREG32(drv->scratch_reg, seq);
sys/dev/pci/drm/radeon/radeon_i2c.c
115
WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
sys/dev/pci/drm/radeon/radeon_i2c.c
118
WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
sys/dev/pci/drm/radeon/radeon_i2c.c
129
WREG32(rec->mask_clk_reg, temp);
sys/dev/pci/drm/radeon/radeon_i2c.c
134
WREG32(rec->a_clk_reg, temp);
sys/dev/pci/drm/radeon/radeon_i2c.c
137
WREG32(rec->a_data_reg, temp);
sys/dev/pci/drm/radeon/radeon_i2c.c
141
WREG32(rec->en_clk_reg, temp);
sys/dev/pci/drm/radeon/radeon_i2c.c
144
WREG32(rec->en_data_reg, temp);
sys/dev/pci/drm/radeon/radeon_i2c.c
148
WREG32(rec->mask_clk_reg, temp);
sys/dev/pci/drm/radeon/radeon_i2c.c
152
WREG32(rec->mask_data_reg, temp);
sys/dev/pci/drm/radeon/radeon_i2c.c
167
WREG32(rec->mask_clk_reg, temp);
sys/dev/pci/drm/radeon/radeon_i2c.c
171
WREG32(rec->mask_data_reg, temp);
sys/dev/pci/drm/radeon/radeon_i2c.c
216
WREG32(rec->en_clk_reg, val);
sys/dev/pci/drm/radeon/radeon_i2c.c
229
WREG32(rec->en_data_reg, val);
sys/dev/pci/drm/radeon/radeon_i2c.c
446
WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
sys/dev/pci/drm/radeon/radeon_i2c.c
560
WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
sys/dev/pci/drm/radeon/radeon_i2c.c
564
WREG32(i2c_data, (p->addr << 1) & 0xff);
sys/dev/pci/drm/radeon/radeon_i2c.c
565
WREG32(i2c_data, 0);
sys/dev/pci/drm/radeon/radeon_i2c.c
566
WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
sys/dev/pci/drm/radeon/radeon_i2c.c
570
WREG32(i2c_cntl_0, reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
581
WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
sys/dev/pci/drm/radeon/radeon_i2c.c
593
WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
sys/dev/pci/drm/radeon/radeon_i2c.c
597
WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
sys/dev/pci/drm/radeon/radeon_i2c.c
598
WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
sys/dev/pci/drm/radeon/radeon_i2c.c
602
WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
sys/dev/pci/drm/radeon/radeon_i2c.c
613
WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
sys/dev/pci/drm/radeon/radeon_i2c.c
620
WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
sys/dev/pci/drm/radeon/radeon_i2c.c
624
WREG32(i2c_data, (p->addr << 1) & 0xff);
sys/dev/pci/drm/radeon/radeon_i2c.c
625
WREG32(i2c_data, p->buf[j]);
sys/dev/pci/drm/radeon/radeon_i2c.c
626
WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
sys/dev/pci/drm/radeon/radeon_i2c.c
630
WREG32(i2c_cntl_0, reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
641
WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
sys/dev/pci/drm/radeon/radeon_i2c.c
651
WREG32(i2c_cntl_0, 0);
sys/dev/pci/drm/radeon/radeon_i2c.c
652
WREG32(i2c_cntl_1, 0);
sys/dev/pci/drm/radeon/radeon_i2c.c
653
WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
sys/dev/pci/drm/radeon/radeon_i2c.c
661
WREG32(RADEON_BIOS_6_SCRATCH, tmp);
sys/dev/pci/drm/radeon/radeon_i2c.c
694
WREG32(rec->mask_clk_reg, tmp);
sys/dev/pci/drm/radeon/radeon_i2c.c
699
WREG32(rec->mask_data_reg, tmp);
sys/dev/pci/drm/radeon/radeon_i2c.c
705
WREG32(rec->a_clk_reg, tmp);
sys/dev/pci/drm/radeon/radeon_i2c.c
710
WREG32(rec->a_data_reg, tmp);
sys/dev/pci/drm/radeon/radeon_i2c.c
716
WREG32(rec->en_clk_reg, tmp);
sys/dev/pci/drm/radeon/radeon_i2c.c
721
WREG32(rec->en_data_reg, tmp);
sys/dev/pci/drm/radeon/radeon_i2c.c
726
WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
sys/dev/pci/drm/radeon/radeon_i2c.c
729
WREG32(0x494, saved2 | 0x1);
sys/dev/pci/drm/radeon/radeon_i2c.c
731
WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
sys/dev/pci/drm/radeon/radeon_i2c.c
763
WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
sys/dev/pci/drm/radeon/radeon_i2c.c
766
WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
sys/dev/pci/drm/radeon/radeon_i2c.c
768
WREG32(AVIVO_DC_I2C_RESET, 0);
sys/dev/pci/drm/radeon/radeon_i2c.c
770
WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
sys/dev/pci/drm/radeon/radeon_i2c.c
771
WREG32(AVIVO_DC_I2C_DATA, 0);
sys/dev/pci/drm/radeon/radeon_i2c.c
773
WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
sys/dev/pci/drm/radeon/radeon_i2c.c
774
WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
sys/dev/pci/drm/radeon/radeon_i2c.c
777
WREG32(AVIVO_DC_I2C_CONTROL1, reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
778
WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
sys/dev/pci/drm/radeon/radeon_i2c.c
789
WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
sys/dev/pci/drm/radeon/radeon_i2c.c
807
WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
sys/dev/pci/drm/radeon/radeon_i2c.c
810
WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
sys/dev/pci/drm/radeon/radeon_i2c.c
812
WREG32(AVIVO_DC_I2C_RESET, 0);
sys/dev/pci/drm/radeon/radeon_i2c.c
814
WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
sys/dev/pci/drm/radeon/radeon_i2c.c
815
WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
sys/dev/pci/drm/radeon/radeon_i2c.c
816
WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
sys/dev/pci/drm/radeon/radeon_i2c.c
819
WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
sys/dev/pci/drm/radeon/radeon_i2c.c
820
WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
sys/dev/pci/drm/radeon/radeon_i2c.c
831
WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
sys/dev/pci/drm/radeon/radeon_i2c.c
847
WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
sys/dev/pci/drm/radeon/radeon_i2c.c
850
WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
sys/dev/pci/drm/radeon/radeon_i2c.c
852
WREG32(AVIVO_DC_I2C_RESET, 0);
sys/dev/pci/drm/radeon/radeon_i2c.c
854
WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
sys/dev/pci/drm/radeon/radeon_i2c.c
856
WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
sys/dev/pci/drm/radeon/radeon_i2c.c
858
WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
sys/dev/pci/drm/radeon/radeon_i2c.c
859
WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
sys/dev/pci/drm/radeon/radeon_i2c.c
862
WREG32(AVIVO_DC_I2C_CONTROL1, reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
863
WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
sys/dev/pci/drm/radeon/radeon_i2c.c
874
WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
sys/dev/pci/drm/radeon/radeon_i2c.c
886
WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
sys/dev/pci/drm/radeon/radeon_i2c.c
889
WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
sys/dev/pci/drm/radeon/radeon_i2c.c
891
WREG32(AVIVO_DC_I2C_RESET, 0);
sys/dev/pci/drm/radeon/radeon_i2c.c
893
WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
sys/dev/pci/drm/radeon/radeon_i2c.c
894
WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
sys/dev/pci/drm/radeon/radeon_i2c.c
895
WREG32(0x494, saved2);
sys/dev/pci/drm/radeon/radeon_i2c.c
898
WREG32(RADEON_BIOS_6_SCRATCH, tmp);
sys/dev/pci/drm/radeon/radeon_irq_kms.c
619
WREG32(reg, tmp |= mask);
sys/dev/pci/drm/radeon/radeon_irq_kms.c
622
WREG32(reg, tmp & ~mask);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
203
WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
204
WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
205
WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
206
WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
207
WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
208
WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
209
WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
210
WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
44
WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
45
WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
46
WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
542
WREG32(gen_cntl_reg, gen_cntl_val);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
546
WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
550
WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
552
WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
554
WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
555
WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
556
WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
678
WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
679
WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
681
WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
682
WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
715
WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
716
WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
717
WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
725
WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
726
WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
727
WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
728
WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
100
WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1000
WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
105
WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1105
WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1108
WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1111
WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1112
WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
115
WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1203
WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1222
WREG32(RADEON_DAC_CNTL, dac_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
125
WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1250
WREG32(RADEON_DAC_CNTL2, dac2_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1275
WREG32(RADEON_DAC_CNTL2, dac2_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
128
WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1280
WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1282
WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1284
WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1287
WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1318
WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
132
WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1320
WREG32(RADEON_CRTC2_GEN_CNTL,
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1325
WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1327
WREG32(RADEON_DAC_EXT_CNTL,
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1333
WREG32(RADEON_TV_DAC_CNTL,
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1341
WREG32(RADEON_TV_DAC_CNTL,
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1361
WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1362
WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1363
WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1364
WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1365
WREG32(RADEON_DAC_CNTL2, dac_cntl2);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1389
WREG32(RADEON_DAC_CNTL2, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1398
WREG32(RADEON_TV_MASTER_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1408
WREG32(RADEON_TV_DAC_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1415
WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1427
WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1428
WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1429
WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1430
WREG32(RADEON_DAC_CNTL2, dac_cntl2);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1465
WREG32(RADEON_GPIO_MONID, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1467
WREG32(RADEON_FP2_GEN_CNTL, (RADEON_FP2_ON |
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1473
WREG32(RADEON_DISP_OUTPUT_CNTL, (RADEON_DISP_DAC_SOURCE_RMX |
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1476
WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN |
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1479
WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1480
WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1481
WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1482
WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1483
WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1484
WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1486
WREG32(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1487
WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1488
WREG32(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1489
WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1506
WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1507
WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1508
WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1509
WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1510
WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1511
WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1512
WREG32(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1513
WREG32(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1514
WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1515
WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1516
WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1517
WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1518
WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1519
WREG32(RADEON_GPIO_MONID, gpio_monid);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1599
WREG32(RADEON_CRTC_EXT_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1604
WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1610
WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1613
WREG32(RADEON_DISP_HW_DEBUG, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1622
WREG32(RADEON_TV_DAC_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1637
WREG32(RADEON_DAC_EXT_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1640
WREG32(RADEON_DAC_CNTL2, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1653
WREG32(RADEON_DAC_CNTL2, dac_cntl2);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1654
WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1655
WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1658
WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1660
WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1662
WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1665
WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
243
WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
244
WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
245
WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
248
WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
543
WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
544
WREG32(RADEON_DAC_CNTL, dac_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
545
WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
593
WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
596
WREG32(RADEON_DAC_CNTL2, dac2_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
603
WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
606
WREG32(RADEON_DAC_CNTL2, dac2_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
626
WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
664
WREG32(RADEON_CRTC_EXT_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
681
WREG32(RADEON_DAC_EXT_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
685
WREG32(RADEON_DAC_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
692
WREG32(RADEON_DAC_MACRO_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
700
WREG32(RADEON_DAC_CNTL, dac_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
701
WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
702
WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
703
WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
742
WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
864
WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
865
WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
866
WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
908
WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
97
WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
284
WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
296
WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
308
WREG32(RADEON_TV_HOST_WRITE_DATA, value);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
310
WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
311
WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
319
WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
330
WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
331
WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
339
WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
395
WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
418
WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
419
WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
420
WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
746
WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST |
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
755
WREG32(RADEON_TV_DAC_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
776
WREG32(RADEON_TV_RGB_CNTL, tv_rgb_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
777
WREG32(RADEON_TV_HTOTAL, const_ptr->hor_total - 1);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
778
WREG32(RADEON_TV_HDISP, const_ptr->hor_resolution - 1);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
779
WREG32(RADEON_TV_HSTART, const_ptr->hor_start);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
781
WREG32(RADEON_TV_VTOTAL, const_ptr->ver_total - 1);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
782
WREG32(RADEON_TV_VDISP, const_ptr->ver_resolution - 1);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
783
WREG32(RADEON_TV_FTOTAL, tv_ftotal);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
784
WREG32(RADEON_TV_VSCALER_CNTL1, tv_vscaler_cntl1);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
785
WREG32(RADEON_TV_VSCALER_CNTL2, tv_vscaler_cntl2);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
787
WREG32(RADEON_TV_Y_FALL_CNTL, tv_y_fall_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
788
WREG32(RADEON_TV_Y_RISE_CNTL, tv_y_rise_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
789
WREG32(RADEON_TV_Y_SAW_TOOTH_CNTL, tv_y_saw_tooth_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
791
WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST |
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
800
WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST));
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
803
WREG32(RADEON_TV_SYNC_CNTL, (RADEON_SYNC_PUB | RADEON_TV_SYNC_IO_DRIVE));
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
804
WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
805
WREG32(RADEON_TV_MODULATOR_CNTL1, tv_modulator_cntl1);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
806
WREG32(RADEON_TV_MODULATOR_CNTL2, tv_modulator_cntl2);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
807
WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, (RADEON_Y_RED_EN |
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
812
WREG32(RADEON_TV_CRC_CNTL, 0);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
814
WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
816
WREG32(RADEON_TV_GAIN_LIMIT_SETTINGS, ((0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) |
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
818
WREG32(RADEON_TV_LINEAR_GAIN_SETTINGS, ((0x100 << RADEON_UV_GAIN_SHIFT) |
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
821
WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
sys/dev/pci/drm/radeon/radeon_ttm.c
850
WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
sys/dev/pci/drm/radeon/radeon_ttm.c
852
WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
sys/dev/pci/drm/radeon/rs400.c
150
WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
sys/dev/pci/drm/radeon/rs400.c
151
WREG32(RS480_AGP_BASE_2, 0);
sys/dev/pci/drm/radeon/rs400.c
158
WREG32(RADEON_BUS_CNTL, tmp);
sys/dev/pci/drm/radeon/rs400.c
160
WREG32(RADEON_MC_AGP_LOCATION, tmp);
sys/dev/pci/drm/radeon/rs400.c
162
WREG32(RADEON_BUS_CNTL, tmp);
sys/dev/pci/drm/radeon/rs400.c
304
WREG32(RS480_NB_MC_INDEX, reg & 0xff);
sys/dev/pci/drm/radeon/rs400.c
306
WREG32(RS480_NB_MC_INDEX, 0xff);
sys/dev/pci/drm/radeon/rs400.c
316
WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
sys/dev/pci/drm/radeon/rs400.c
317
WREG32(RS480_NB_MC_DATA, (v));
sys/dev/pci/drm/radeon/rs400.c
318
WREG32(RS480_NB_MC_INDEX, 0xff);
sys/dev/pci/drm/radeon/rs400.c
413
WREG32(R_000148_MC_FB_LOCATION,
sys/dev/pci/drm/radeon/rs600.c
128
WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/rs600.c
131
WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/rs600.c
134
WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/rs600.c
137
WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/rs600.c
139
WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/rs600.c
152
WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/rs600.c
212
WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp);
sys/dev/pci/drm/radeon/rs600.c
215
WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp);
sys/dev/pci/drm/radeon/rs600.c
218
WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp);
sys/dev/pci/drm/radeon/rs600.c
221
WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp);
sys/dev/pci/drm/radeon/rs600.c
243
WREG32(voltage->gpio.reg, tmp);
sys/dev/pci/drm/radeon/rs600.c
252
WREG32(voltage->gpio.reg, tmp);
sys/dev/pci/drm/radeon/rs600.c
335
WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/rs600.c
353
WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/rs600.c
394
WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/rs600.c
402
WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/rs600.c
419
WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
sys/dev/pci/drm/radeon/rs600.c
423
WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
sys/dev/pci/drm/radeon/rs600.c
446
WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
sys/dev/pci/drm/radeon/rs600.c
450
WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
sys/dev/pci/drm/radeon/rs600.c
477
WREG32(RADEON_CP_CSQ_CNTL, 0);
sys/dev/pci/drm/radeon/rs600.c
479
WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
sys/dev/pci/drm/radeon/rs600.c
480
WREG32(RADEON_CP_RB_RPTR_WR, 0);
sys/dev/pci/drm/radeon/rs600.c
481
WREG32(RADEON_CP_RB_WPTR, 0);
sys/dev/pci/drm/radeon/rs600.c
482
WREG32(RADEON_CP_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/rs600.c
488
WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
sys/dev/pci/drm/radeon/rs600.c
492
WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
sys/dev/pci/drm/radeon/rs600.c
497
WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
sys/dev/pci/drm/radeon/rs600.c
500
WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
sys/dev/pci/drm/radeon/rs600.c
505
WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
sys/dev/pci/drm/radeon/rs600.c
508
WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
sys/dev/pci/drm/radeon/rs600.c
576
WREG32(RADEON_BUS_CNTL, tmp);
sys/dev/pci/drm/radeon/rs600.c
683
WREG32(R_000040_GEN_INT_CNTL, 0);
sys/dev/pci/drm/radeon/rs600.c
706
WREG32(R_000040_GEN_INT_CNTL, tmp);
sys/dev/pci/drm/radeon/rs600.c
707
WREG32(R_006540_DxMODE_INT_MASK, mode_int);
sys/dev/pci/drm/radeon/rs600.c
708
WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
sys/dev/pci/drm/radeon/rs600.c
709
WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
sys/dev/pci/drm/radeon/rs600.c
711
WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
sys/dev/pci/drm/radeon/rs600.c
728
WREG32(R_006534_D1MODE_VBLANK_STATUS,
sys/dev/pci/drm/radeon/rs600.c
732
WREG32(R_006D34_D2MODE_VBLANK_STATUS,
sys/dev/pci/drm/radeon/rs600.c
738
WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/rs600.c
743
WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/rs600.c
755
WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
sys/dev/pci/drm/radeon/rs600.c
761
WREG32(R_000044_GEN_INT_STATUS, irqs);
sys/dev/pci/drm/radeon/rs600.c
770
WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
sys/dev/pci/drm/radeon/rs600.c
771
WREG32(R_000040_GEN_INT_CNTL, 0);
sys/dev/pci/drm/radeon/rs600.c
772
WREG32(R_006540_DxMODE_INT_MASK, 0);
sys/dev/pci/drm/radeon/rs600.c
840
WREG32(RADEON_BUS_CNTL, msi_rearm);
sys/dev/pci/drm/radeon/rs600.c
841
WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
sys/dev/pci/drm/radeon/rs600.c
844
WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
sys/dev/pci/drm/radeon/rs600.c
923
WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
sys/dev/pci/drm/radeon/rs600.c
924
WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
sys/dev/pci/drm/radeon/rs600.c
925
WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
sys/dev/pci/drm/radeon/rs600.c
926
WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
sys/dev/pci/drm/radeon/rs600.c
936
WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
sys/dev/pci/drm/radeon/rs600.c
948
WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
sys/dev/pci/drm/radeon/rs600.c
950
WREG32(R_000074_MC_IND_DATA, v);
sys/dev/pci/drm/radeon/rs600.c
979
WREG32(R_000134_HDP_FB_LOCATION,
sys/dev/pci/drm/radeon/rs690.c
249
WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
sys/dev/pci/drm/radeon/rs690.c
622
WREG32(R_006C9C_DCP_CONTROL, 0);
sys/dev/pci/drm/radeon/rs690.c
624
WREG32(R_006C9C_DCP_CONTROL, 2);
sys/dev/pci/drm/radeon/rs690.c
634
WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
sys/dev/pci/drm/radeon/rs690.c
645
WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
sys/dev/pci/drm/radeon/rs690.c
646
WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);
sys/dev/pci/drm/radeon/rs690.c
647
WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
sys/dev/pci/drm/radeon/rs690.c
648
WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);
sys/dev/pci/drm/radeon/rs690.c
657
WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
sys/dev/pci/drm/radeon/rs690.c
659
WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
sys/dev/pci/drm/radeon/rs690.c
669
WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
sys/dev/pci/drm/radeon/rs690.c
671
WREG32(R_00007C_MC_DATA, v);
sys/dev/pci/drm/radeon/rs690.c
672
WREG32(R_000078_MC_INDEX, 0x7F);
sys/dev/pci/drm/radeon/rs690.c
690
WREG32(R_000134_HDP_FB_LOCATION,
sys/dev/pci/drm/radeon/rs780_dpm.c
278
WREG32(FVTHROT_PWM_CTRL_REG1,
sys/dev/pci/drm/radeon/rs780_dpm.c
282
WREG32(FVTHROT_PWM_US_REG0, RS780_FVTHROTPWMUSREG0_DFLT);
sys/dev/pci/drm/radeon/rs780_dpm.c
283
WREG32(FVTHROT_PWM_US_REG1, RS780_FVTHROTPWMUSREG1_DFLT);
sys/dev/pci/drm/radeon/rs780_dpm.c
284
WREG32(FVTHROT_PWM_DS_REG0, RS780_FVTHROTPWMDSREG0_DFLT);
sys/dev/pci/drm/radeon/rs780_dpm.c
285
WREG32(FVTHROT_PWM_DS_REG1, RS780_FVTHROTPWMDSREG1_DFLT);
sys/dev/pci/drm/radeon/rs780_dpm.c
291
WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG2,
sys/dev/pci/drm/radeon/rs780_dpm.c
295
WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG3,
sys/dev/pci/drm/radeon/rs780_dpm.c
298
WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG4,
sys/dev/pci/drm/radeon/rs780_dpm.c
323
WREG32(FVTHROT_UTC0, RS780_FVTHROTUTC0_DFLT);
sys/dev/pci/drm/radeon/rs780_dpm.c
324
WREG32(FVTHROT_UTC1, RS780_FVTHROTUTC1_DFLT);
sys/dev/pci/drm/radeon/rs780_dpm.c
325
WREG32(FVTHROT_UTC2, RS780_FVTHROTUTC2_DFLT);
sys/dev/pci/drm/radeon/rs780_dpm.c
326
WREG32(FVTHROT_UTC3, RS780_FVTHROTUTC3_DFLT);
sys/dev/pci/drm/radeon/rs780_dpm.c
327
WREG32(FVTHROT_UTC4, RS780_FVTHROTUTC4_DFLT);
sys/dev/pci/drm/radeon/rs780_dpm.c
329
WREG32(FVTHROT_DTC0, RS780_FVTHROTDTC0_DFLT);
sys/dev/pci/drm/radeon/rs780_dpm.c
330
WREG32(FVTHROT_DTC1, RS780_FVTHROTDTC1_DFLT);
sys/dev/pci/drm/radeon/rs780_dpm.c
331
WREG32(FVTHROT_DTC2, RS780_FVTHROTDTC2_DFLT);
sys/dev/pci/drm/radeon/rs780_dpm.c
332
WREG32(FVTHROT_DTC3, RS780_FVTHROTDTC3_DFLT);
sys/dev/pci/drm/radeon/rs780_dpm.c
333
WREG32(FVTHROT_DTC4, RS780_FVTHROTDTC4_DFLT);
sys/dev/pci/drm/radeon/rs780_dpm.c
354
WREG32(FVTHROT_FB_US_REG0, RS780_FVTHROTFBUSREG0_DFLT);
sys/dev/pci/drm/radeon/rs780_dpm.c
355
WREG32(FVTHROT_FB_US_REG1, RS780_FVTHROTFBUSREG1_DFLT);
sys/dev/pci/drm/radeon/rs780_dpm.c
356
WREG32(FVTHROT_FB_DS_REG0, RS780_FVTHROTFBDSREG0_DFLT);
sys/dev/pci/drm/radeon/rs780_dpm.c
357
WREG32(FVTHROT_FB_DS_REG1, RS780_FVTHROTFBDSREG1_DFLT);
sys/dev/pci/drm/radeon/rs780_dpm.c
366
WREG32(FVTHROT_TARGET_REG, 30000000 / pi->refresh_rate);
sys/dev/pci/drm/radeon/rs780_dpm.c
367
WREG32(FVTHROT_CB1, 1000000 * 5 / pi->refresh_rate);
sys/dev/pci/drm/radeon/rs780_dpm.c
368
WREG32(FVTHROT_CB2, 1000000 * 10 / pi->refresh_rate);
sys/dev/pci/drm/radeon/rs780_dpm.c
369
WREG32(FVTHROT_CB3, 1000000 * 30 / pi->refresh_rate);
sys/dev/pci/drm/radeon/rs780_dpm.c
370
WREG32(FVTHROT_CB4, 1000000 * 50 / pi->refresh_rate);
sys/dev/pci/drm/radeon/rv515.c
1227
WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
sys/dev/pci/drm/radeon/rv515.c
1238
WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
sys/dev/pci/drm/radeon/rv515.c
1239
WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);
sys/dev/pci/drm/radeon/rv515.c
1240
WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
sys/dev/pci/drm/radeon/rv515.c
1241
WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);
sys/dev/pci/drm/radeon/rv515.c
137
WREG32(R_000300_VGA_RENDER_CONTROL,
sys/dev/pci/drm/radeon/rv515.c
202
WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
sys/dev/pci/drm/radeon/rv515.c
204
WREG32(MC_IND_INDEX, 0);
sys/dev/pci/drm/radeon/rv515.c
215
WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
sys/dev/pci/drm/radeon/rv515.c
216
WREG32(MC_IND_DATA, (v));
sys/dev/pci/drm/radeon/rv515.c
217
WREG32(MC_IND_INDEX, 0);
sys/dev/pci/drm/radeon/rv515.c
277
WREG32(R_000300_VGA_RENDER_CONTROL, 0);
sys/dev/pci/drm/radeon/rv515.c
286
WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
sys/dev/pci/drm/radeon/rv515.c
288
WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/rv515.c
289
WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
sys/dev/pci/drm/radeon/rv515.c
300
WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
sys/dev/pci/drm/radeon/rv515.c
303
WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/rv515.c
304
WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
sys/dev/pci/drm/radeon/rv515.c
321
WREG32(R600_BIF_FB_EN, 0);
sys/dev/pci/drm/radeon/rv515.c
325
WREG32(R700_MC_CITF_CNTL, blackout);
sys/dev/pci/drm/radeon/rv515.c
327
WREG32(R600_CITF_CNTL, blackout);
sys/dev/pci/drm/radeon/rv515.c
339
WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/rv515.c
344
WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/rv515.c
359
WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
sys/dev/pci/drm/radeon/rv515.c
361
WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
sys/dev/pci/drm/radeon/rv515.c
364
WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
sys/dev/pci/drm/radeon/rv515.c
366
WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
sys/dev/pci/drm/radeon/rv515.c
370
WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
sys/dev/pci/drm/radeon/rv515.c
372
WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
sys/dev/pci/drm/radeon/rv515.c
375
WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
sys/dev/pci/drm/radeon/rv515.c
384
WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/rv515.c
389
WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/rv515.c
394
WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/rv515.c
413
WREG32(R700_MC_CITF_CNTL, tmp);
sys/dev/pci/drm/radeon/rv515.c
415
WREG32(R600_CITF_CNTL, tmp);
sys/dev/pci/drm/radeon/rv515.c
417
WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN);
sys/dev/pci/drm/radeon/rv515.c
424
WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/rv515.c
435
WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
sys/dev/pci/drm/radeon/rv515.c
437
WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
sys/dev/pci/drm/radeon/rv515.c
451
WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
sys/dev/pci/drm/radeon/rv515.c
456
WREG32(R_000134_HDP_FB_LOCATION,
sys/dev/pci/drm/radeon/rv515.c
685
WREG32(0x659C + crtc->crtc_offset, 0x0);
sys/dev/pci/drm/radeon/rv515.c
686
WREG32(0x6594 + crtc->crtc_offset, 0x705);
sys/dev/pci/drm/radeon/rv515.c
687
WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
sys/dev/pci/drm/radeon/rv515.c
688
WREG32(0x65D8 + crtc->crtc_offset, 0x0);
sys/dev/pci/drm/radeon/rv515.c
689
WREG32(0x65B0 + crtc->crtc_offset, 0x0);
sys/dev/pci/drm/radeon/rv515.c
690
WREG32(0x65C0 + crtc->crtc_offset, 0x0);
sys/dev/pci/drm/radeon/rv515.c
691
WREG32(0x65D4 + crtc->crtc_offset, 0x0);
sys/dev/pci/drm/radeon/rv515.c
692
WREG32(index_reg, 0x0);
sys/dev/pci/drm/radeon/rv515.c
693
WREG32(data_reg, 0x841880A8);
sys/dev/pci/drm/radeon/rv515.c
694
WREG32(index_reg, 0x1);
sys/dev/pci/drm/radeon/rv515.c
695
WREG32(data_reg, 0x84208680);
sys/dev/pci/drm/radeon/rv515.c
696
WREG32(index_reg, 0x2);
sys/dev/pci/drm/radeon/rv515.c
697
WREG32(data_reg, 0xBFF880B0);
sys/dev/pci/drm/radeon/rv515.c
698
WREG32(index_reg, 0x100);
sys/dev/pci/drm/radeon/rv515.c
699
WREG32(data_reg, 0x83D88088);
sys/dev/pci/drm/radeon/rv515.c
700
WREG32(index_reg, 0x101);
sys/dev/pci/drm/radeon/rv515.c
701
WREG32(data_reg, 0x84608680);
sys/dev/pci/drm/radeon/rv515.c
702
WREG32(index_reg, 0x102);
sys/dev/pci/drm/radeon/rv515.c
703
WREG32(data_reg, 0xBFF080D0);
sys/dev/pci/drm/radeon/rv515.c
704
WREG32(index_reg, 0x200);
sys/dev/pci/drm/radeon/rv515.c
705
WREG32(data_reg, 0x83988068);
sys/dev/pci/drm/radeon/rv515.c
706
WREG32(index_reg, 0x201);
sys/dev/pci/drm/radeon/rv515.c
707
WREG32(data_reg, 0x84A08680);
sys/dev/pci/drm/radeon/rv515.c
708
WREG32(index_reg, 0x202);
sys/dev/pci/drm/radeon/rv515.c
709
WREG32(data_reg, 0xBFF080F8);
sys/dev/pci/drm/radeon/rv515.c
710
WREG32(index_reg, 0x300);
sys/dev/pci/drm/radeon/rv515.c
711
WREG32(data_reg, 0x83588058);
sys/dev/pci/drm/radeon/rv515.c
712
WREG32(index_reg, 0x301);
sys/dev/pci/drm/radeon/rv515.c
713
WREG32(data_reg, 0x84E08660);
sys/dev/pci/drm/radeon/rv515.c
714
WREG32(index_reg, 0x302);
sys/dev/pci/drm/radeon/rv515.c
715
WREG32(data_reg, 0xBFF88120);
sys/dev/pci/drm/radeon/rv515.c
716
WREG32(index_reg, 0x400);
sys/dev/pci/drm/radeon/rv515.c
717
WREG32(data_reg, 0x83188040);
sys/dev/pci/drm/radeon/rv515.c
718
WREG32(index_reg, 0x401);
sys/dev/pci/drm/radeon/rv515.c
719
WREG32(data_reg, 0x85008660);
sys/dev/pci/drm/radeon/rv515.c
720
WREG32(index_reg, 0x402);
sys/dev/pci/drm/radeon/rv515.c
721
WREG32(data_reg, 0xBFF88150);
sys/dev/pci/drm/radeon/rv515.c
722
WREG32(index_reg, 0x500);
sys/dev/pci/drm/radeon/rv515.c
723
WREG32(data_reg, 0x82D88030);
sys/dev/pci/drm/radeon/rv515.c
724
WREG32(index_reg, 0x501);
sys/dev/pci/drm/radeon/rv515.c
725
WREG32(data_reg, 0x85408640);
sys/dev/pci/drm/radeon/rv515.c
726
WREG32(index_reg, 0x502);
sys/dev/pci/drm/radeon/rv515.c
727
WREG32(data_reg, 0xBFF88180);
sys/dev/pci/drm/radeon/rv515.c
728
WREG32(index_reg, 0x600);
sys/dev/pci/drm/radeon/rv515.c
729
WREG32(data_reg, 0x82A08018);
sys/dev/pci/drm/radeon/rv515.c
730
WREG32(index_reg, 0x601);
sys/dev/pci/drm/radeon/rv515.c
731
WREG32(data_reg, 0x85808620);
sys/dev/pci/drm/radeon/rv515.c
732
WREG32(index_reg, 0x602);
sys/dev/pci/drm/radeon/rv515.c
733
WREG32(data_reg, 0xBFF081B8);
sys/dev/pci/drm/radeon/rv515.c
734
WREG32(index_reg, 0x700);
sys/dev/pci/drm/radeon/rv515.c
735
WREG32(data_reg, 0x82608010);
sys/dev/pci/drm/radeon/rv515.c
736
WREG32(index_reg, 0x701);
sys/dev/pci/drm/radeon/rv515.c
737
WREG32(data_reg, 0x85A08600);
sys/dev/pci/drm/radeon/rv515.c
738
WREG32(index_reg, 0x702);
sys/dev/pci/drm/radeon/rv515.c
739
WREG32(data_reg, 0x800081F0);
sys/dev/pci/drm/radeon/rv515.c
740
WREG32(index_reg, 0x800);
sys/dev/pci/drm/radeon/rv515.c
741
WREG32(data_reg, 0x8228BFF8);
sys/dev/pci/drm/radeon/rv515.c
742
WREG32(index_reg, 0x801);
sys/dev/pci/drm/radeon/rv515.c
743
WREG32(data_reg, 0x85E085E0);
sys/dev/pci/drm/radeon/rv515.c
744
WREG32(index_reg, 0x802);
sys/dev/pci/drm/radeon/rv515.c
745
WREG32(data_reg, 0xBFF88228);
sys/dev/pci/drm/radeon/rv515.c
746
WREG32(index_reg, 0x10000);
sys/dev/pci/drm/radeon/rv515.c
747
WREG32(data_reg, 0x82A8BF00);
sys/dev/pci/drm/radeon/rv515.c
748
WREG32(index_reg, 0x10001);
sys/dev/pci/drm/radeon/rv515.c
749
WREG32(data_reg, 0x82A08CC0);
sys/dev/pci/drm/radeon/rv515.c
750
WREG32(index_reg, 0x10002);
sys/dev/pci/drm/radeon/rv515.c
751
WREG32(data_reg, 0x8008BEF8);
sys/dev/pci/drm/radeon/rv515.c
752
WREG32(index_reg, 0x10100);
sys/dev/pci/drm/radeon/rv515.c
753
WREG32(data_reg, 0x81F0BF28);
sys/dev/pci/drm/radeon/rv515.c
754
WREG32(index_reg, 0x10101);
sys/dev/pci/drm/radeon/rv515.c
755
WREG32(data_reg, 0x83608CA0);
sys/dev/pci/drm/radeon/rv515.c
756
WREG32(index_reg, 0x10102);
sys/dev/pci/drm/radeon/rv515.c
757
WREG32(data_reg, 0x8018BED0);
sys/dev/pci/drm/radeon/rv515.c
758
WREG32(index_reg, 0x10200);
sys/dev/pci/drm/radeon/rv515.c
759
WREG32(data_reg, 0x8148BF38);
sys/dev/pci/drm/radeon/rv515.c
760
WREG32(index_reg, 0x10201);
sys/dev/pci/drm/radeon/rv515.c
761
WREG32(data_reg, 0x84408C80);
sys/dev/pci/drm/radeon/rv515.c
762
WREG32(index_reg, 0x10202);
sys/dev/pci/drm/radeon/rv515.c
763
WREG32(data_reg, 0x8008BEB8);
sys/dev/pci/drm/radeon/rv515.c
764
WREG32(index_reg, 0x10300);
sys/dev/pci/drm/radeon/rv515.c
765
WREG32(data_reg, 0x80B0BF78);
sys/dev/pci/drm/radeon/rv515.c
766
WREG32(index_reg, 0x10301);
sys/dev/pci/drm/radeon/rv515.c
767
WREG32(data_reg, 0x85008C20);
sys/dev/pci/drm/radeon/rv515.c
768
WREG32(index_reg, 0x10302);
sys/dev/pci/drm/radeon/rv515.c
769
WREG32(data_reg, 0x8020BEA0);
sys/dev/pci/drm/radeon/rv515.c
770
WREG32(index_reg, 0x10400);
sys/dev/pci/drm/radeon/rv515.c
771
WREG32(data_reg, 0x8028BF90);
sys/dev/pci/drm/radeon/rv515.c
772
WREG32(index_reg, 0x10401);
sys/dev/pci/drm/radeon/rv515.c
773
WREG32(data_reg, 0x85E08BC0);
sys/dev/pci/drm/radeon/rv515.c
774
WREG32(index_reg, 0x10402);
sys/dev/pci/drm/radeon/rv515.c
775
WREG32(data_reg, 0x8018BE90);
sys/dev/pci/drm/radeon/rv515.c
776
WREG32(index_reg, 0x10500);
sys/dev/pci/drm/radeon/rv515.c
777
WREG32(data_reg, 0xBFB8BFB0);
sys/dev/pci/drm/radeon/rv515.c
778
WREG32(index_reg, 0x10501);
sys/dev/pci/drm/radeon/rv515.c
779
WREG32(data_reg, 0x86C08B40);
sys/dev/pci/drm/radeon/rv515.c
780
WREG32(index_reg, 0x10502);
sys/dev/pci/drm/radeon/rv515.c
781
WREG32(data_reg, 0x8010BE90);
sys/dev/pci/drm/radeon/rv515.c
782
WREG32(index_reg, 0x10600);
sys/dev/pci/drm/radeon/rv515.c
783
WREG32(data_reg, 0xBF58BFC8);
sys/dev/pci/drm/radeon/rv515.c
784
WREG32(index_reg, 0x10601);
sys/dev/pci/drm/radeon/rv515.c
785
WREG32(data_reg, 0x87A08AA0);
sys/dev/pci/drm/radeon/rv515.c
786
WREG32(index_reg, 0x10602);
sys/dev/pci/drm/radeon/rv515.c
787
WREG32(data_reg, 0x8010BE98);
sys/dev/pci/drm/radeon/rv515.c
788
WREG32(index_reg, 0x10700);
sys/dev/pci/drm/radeon/rv515.c
789
WREG32(data_reg, 0xBF10BFF0);
sys/dev/pci/drm/radeon/rv515.c
790
WREG32(index_reg, 0x10701);
sys/dev/pci/drm/radeon/rv515.c
791
WREG32(data_reg, 0x886089E0);
sys/dev/pci/drm/radeon/rv515.c
792
WREG32(index_reg, 0x10702);
sys/dev/pci/drm/radeon/rv515.c
793
WREG32(data_reg, 0x8018BEB0);
sys/dev/pci/drm/radeon/rv515.c
794
WREG32(index_reg, 0x10800);
sys/dev/pci/drm/radeon/rv515.c
795
WREG32(data_reg, 0xBED8BFE8);
sys/dev/pci/drm/radeon/rv515.c
796
WREG32(index_reg, 0x10801);
sys/dev/pci/drm/radeon/rv515.c
797
WREG32(data_reg, 0x89408940);
sys/dev/pci/drm/radeon/rv515.c
798
WREG32(index_reg, 0x10802);
sys/dev/pci/drm/radeon/rv515.c
799
WREG32(data_reg, 0xBFE8BED8);
sys/dev/pci/drm/radeon/rv515.c
800
WREG32(index_reg, 0x20000);
sys/dev/pci/drm/radeon/rv515.c
801
WREG32(data_reg, 0x80008000);
sys/dev/pci/drm/radeon/rv515.c
802
WREG32(index_reg, 0x20001);
sys/dev/pci/drm/radeon/rv515.c
803
WREG32(data_reg, 0x90008000);
sys/dev/pci/drm/radeon/rv515.c
804
WREG32(index_reg, 0x20002);
sys/dev/pci/drm/radeon/rv515.c
805
WREG32(data_reg, 0x80008000);
sys/dev/pci/drm/radeon/rv515.c
806
WREG32(index_reg, 0x20003);
sys/dev/pci/drm/radeon/rv515.c
807
WREG32(data_reg, 0x80008000);
sys/dev/pci/drm/radeon/rv515.c
808
WREG32(index_reg, 0x20100);
sys/dev/pci/drm/radeon/rv515.c
809
WREG32(data_reg, 0x80108000);
sys/dev/pci/drm/radeon/rv515.c
810
WREG32(index_reg, 0x20101);
sys/dev/pci/drm/radeon/rv515.c
811
WREG32(data_reg, 0x8FE0BF70);
sys/dev/pci/drm/radeon/rv515.c
812
WREG32(index_reg, 0x20102);
sys/dev/pci/drm/radeon/rv515.c
813
WREG32(data_reg, 0xBFE880C0);
sys/dev/pci/drm/radeon/rv515.c
814
WREG32(index_reg, 0x20103);
sys/dev/pci/drm/radeon/rv515.c
815
WREG32(data_reg, 0x80008000);
sys/dev/pci/drm/radeon/rv515.c
816
WREG32(index_reg, 0x20200);
sys/dev/pci/drm/radeon/rv515.c
817
WREG32(data_reg, 0x8018BFF8);
sys/dev/pci/drm/radeon/rv515.c
818
WREG32(index_reg, 0x20201);
sys/dev/pci/drm/radeon/rv515.c
819
WREG32(data_reg, 0x8F80BF08);
sys/dev/pci/drm/radeon/rv515.c
820
WREG32(index_reg, 0x20202);
sys/dev/pci/drm/radeon/rv515.c
821
WREG32(data_reg, 0xBFD081A0);
sys/dev/pci/drm/radeon/rv515.c
822
WREG32(index_reg, 0x20203);
sys/dev/pci/drm/radeon/rv515.c
823
WREG32(data_reg, 0xBFF88000);
sys/dev/pci/drm/radeon/rv515.c
824
WREG32(index_reg, 0x20300);
sys/dev/pci/drm/radeon/rv515.c
825
WREG32(data_reg, 0x80188000);
sys/dev/pci/drm/radeon/rv515.c
826
WREG32(index_reg, 0x20301);
sys/dev/pci/drm/radeon/rv515.c
827
WREG32(data_reg, 0x8EE0BEC0);
sys/dev/pci/drm/radeon/rv515.c
828
WREG32(index_reg, 0x20302);
sys/dev/pci/drm/radeon/rv515.c
829
WREG32(data_reg, 0xBFB082A0);
sys/dev/pci/drm/radeon/rv515.c
830
WREG32(index_reg, 0x20303);
sys/dev/pci/drm/radeon/rv515.c
831
WREG32(data_reg, 0x80008000);
sys/dev/pci/drm/radeon/rv515.c
832
WREG32(index_reg, 0x20400);
sys/dev/pci/drm/radeon/rv515.c
833
WREG32(data_reg, 0x80188000);
sys/dev/pci/drm/radeon/rv515.c
834
WREG32(index_reg, 0x20401);
sys/dev/pci/drm/radeon/rv515.c
835
WREG32(data_reg, 0x8E00BEA0);
sys/dev/pci/drm/radeon/rv515.c
836
WREG32(index_reg, 0x20402);
sys/dev/pci/drm/radeon/rv515.c
837
WREG32(data_reg, 0xBF8883C0);
sys/dev/pci/drm/radeon/rv515.c
838
WREG32(index_reg, 0x20403);
sys/dev/pci/drm/radeon/rv515.c
839
WREG32(data_reg, 0x80008000);
sys/dev/pci/drm/radeon/rv515.c
840
WREG32(index_reg, 0x20500);
sys/dev/pci/drm/radeon/rv515.c
841
WREG32(data_reg, 0x80188000);
sys/dev/pci/drm/radeon/rv515.c
842
WREG32(index_reg, 0x20501);
sys/dev/pci/drm/radeon/rv515.c
843
WREG32(data_reg, 0x8D00BE90);
sys/dev/pci/drm/radeon/rv515.c
844
WREG32(index_reg, 0x20502);
sys/dev/pci/drm/radeon/rv515.c
845
WREG32(data_reg, 0xBF588500);
sys/dev/pci/drm/radeon/rv515.c
846
WREG32(index_reg, 0x20503);
sys/dev/pci/drm/radeon/rv515.c
847
WREG32(data_reg, 0x80008008);
sys/dev/pci/drm/radeon/rv515.c
848
WREG32(index_reg, 0x20600);
sys/dev/pci/drm/radeon/rv515.c
849
WREG32(data_reg, 0x80188000);
sys/dev/pci/drm/radeon/rv515.c
850
WREG32(index_reg, 0x20601);
sys/dev/pci/drm/radeon/rv515.c
851
WREG32(data_reg, 0x8BC0BE98);
sys/dev/pci/drm/radeon/rv515.c
852
WREG32(index_reg, 0x20602);
sys/dev/pci/drm/radeon/rv515.c
853
WREG32(data_reg, 0xBF308660);
sys/dev/pci/drm/radeon/rv515.c
854
WREG32(index_reg, 0x20603);
sys/dev/pci/drm/radeon/rv515.c
855
WREG32(data_reg, 0x80008008);
sys/dev/pci/drm/radeon/rv515.c
856
WREG32(index_reg, 0x20700);
sys/dev/pci/drm/radeon/rv515.c
857
WREG32(data_reg, 0x80108000);
sys/dev/pci/drm/radeon/rv515.c
858
WREG32(index_reg, 0x20701);
sys/dev/pci/drm/radeon/rv515.c
859
WREG32(data_reg, 0x8A80BEB0);
sys/dev/pci/drm/radeon/rv515.c
860
WREG32(index_reg, 0x20702);
sys/dev/pci/drm/radeon/rv515.c
861
WREG32(data_reg, 0xBF0087C0);
sys/dev/pci/drm/radeon/rv515.c
862
WREG32(index_reg, 0x20703);
sys/dev/pci/drm/radeon/rv515.c
863
WREG32(data_reg, 0x80008008);
sys/dev/pci/drm/radeon/rv515.c
864
WREG32(index_reg, 0x20800);
sys/dev/pci/drm/radeon/rv515.c
865
WREG32(data_reg, 0x80108000);
sys/dev/pci/drm/radeon/rv515.c
866
WREG32(index_reg, 0x20801);
sys/dev/pci/drm/radeon/rv515.c
867
WREG32(data_reg, 0x8920BED0);
sys/dev/pci/drm/radeon/rv515.c
868
WREG32(index_reg, 0x20802);
sys/dev/pci/drm/radeon/rv515.c
869
WREG32(data_reg, 0xBED08920);
sys/dev/pci/drm/radeon/rv515.c
870
WREG32(index_reg, 0x20803);
sys/dev/pci/drm/radeon/rv515.c
871
WREG32(data_reg, 0x80008010);
sys/dev/pci/drm/radeon/rv515.c
872
WREG32(index_reg, 0x30000);
sys/dev/pci/drm/radeon/rv515.c
873
WREG32(data_reg, 0x90008000);
sys/dev/pci/drm/radeon/rv515.c
874
WREG32(index_reg, 0x30001);
sys/dev/pci/drm/radeon/rv515.c
875
WREG32(data_reg, 0x80008000);
sys/dev/pci/drm/radeon/rv515.c
876
WREG32(index_reg, 0x30100);
sys/dev/pci/drm/radeon/rv515.c
877
WREG32(data_reg, 0x8FE0BF90);
sys/dev/pci/drm/radeon/rv515.c
878
WREG32(index_reg, 0x30101);
sys/dev/pci/drm/radeon/rv515.c
879
WREG32(data_reg, 0xBFF880A0);
sys/dev/pci/drm/radeon/rv515.c
880
WREG32(index_reg, 0x30200);
sys/dev/pci/drm/radeon/rv515.c
881
WREG32(data_reg, 0x8F60BF40);
sys/dev/pci/drm/radeon/rv515.c
882
WREG32(index_reg, 0x30201);
sys/dev/pci/drm/radeon/rv515.c
883
WREG32(data_reg, 0xBFE88180);
sys/dev/pci/drm/radeon/rv515.c
884
WREG32(index_reg, 0x30300);
sys/dev/pci/drm/radeon/rv515.c
885
WREG32(data_reg, 0x8EC0BF00);
sys/dev/pci/drm/radeon/rv515.c
886
WREG32(index_reg, 0x30301);
sys/dev/pci/drm/radeon/rv515.c
887
WREG32(data_reg, 0xBFC88280);
sys/dev/pci/drm/radeon/rv515.c
888
WREG32(index_reg, 0x30400);
sys/dev/pci/drm/radeon/rv515.c
889
WREG32(data_reg, 0x8DE0BEE0);
sys/dev/pci/drm/radeon/rv515.c
890
WREG32(index_reg, 0x30401);
sys/dev/pci/drm/radeon/rv515.c
891
WREG32(data_reg, 0xBFA083A0);
sys/dev/pci/drm/radeon/rv515.c
892
WREG32(index_reg, 0x30500);
sys/dev/pci/drm/radeon/rv515.c
893
WREG32(data_reg, 0x8CE0BED0);
sys/dev/pci/drm/radeon/rv515.c
894
WREG32(index_reg, 0x30501);
sys/dev/pci/drm/radeon/rv515.c
895
WREG32(data_reg, 0xBF7884E0);
sys/dev/pci/drm/radeon/rv515.c
896
WREG32(index_reg, 0x30600);
sys/dev/pci/drm/radeon/rv515.c
897
WREG32(data_reg, 0x8BA0BED8);
sys/dev/pci/drm/radeon/rv515.c
898
WREG32(index_reg, 0x30601);
sys/dev/pci/drm/radeon/rv515.c
899
WREG32(data_reg, 0xBF508640);
sys/dev/pci/drm/radeon/rv515.c
900
WREG32(index_reg, 0x30700);
sys/dev/pci/drm/radeon/rv515.c
901
WREG32(data_reg, 0x8A60BEE8);
sys/dev/pci/drm/radeon/rv515.c
902
WREG32(index_reg, 0x30701);
sys/dev/pci/drm/radeon/rv515.c
903
WREG32(data_reg, 0xBF2087A0);
sys/dev/pci/drm/radeon/rv515.c
904
WREG32(index_reg, 0x30800);
sys/dev/pci/drm/radeon/rv515.c
905
WREG32(data_reg, 0x8900BF00);
sys/dev/pci/drm/radeon/rv515.c
906
WREG32(index_reg, 0x30801);
sys/dev/pci/drm/radeon/rv515.c
907
WREG32(data_reg, 0xBF008900);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1195
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
814
WREG32(SQM_RATIO, sqm_ratio);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
825
WREG32(ARB_RFSH_RATE, arb_refresh_rate);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
989
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/pci/drm/radeon/rv730_dpm.c
406
WREG32(MC_ARB_RFSH_RATE, arb_refresh_rate);
sys/dev/pci/drm/radeon/rv730_dpm.c
419
WREG32(MC_ARB_DRAM_TIMING_3, dram_timing);
sys/dev/pci/drm/radeon/rv730_dpm.c
420
WREG32(MC_ARB_DRAM_TIMING2_3, dram_timing2);
sys/dev/pci/drm/radeon/rv730_dpm.c
429
WREG32(MC_ARB_DRAM_TIMING_2, dram_timing);
sys/dev/pci/drm/radeon/rv730_dpm.c
430
WREG32(MC_ARB_DRAM_TIMING2_2, dram_timing2);
sys/dev/pci/drm/radeon/rv730_dpm.c
439
WREG32(MC_ARB_DRAM_TIMING_1, dram_timing);
sys/dev/pci/drm/radeon/rv730_dpm.c
440
WREG32(MC_ARB_DRAM_TIMING2_1, dram_timing2);
sys/dev/pci/drm/radeon/rv730_dpm.c
443
WREG32(MC_ARB_DRAM_TIMING, old_dram_timing);
sys/dev/pci/drm/radeon/rv730_dpm.c
444
WREG32(MC_ARB_DRAM_TIMING2, old_dram_timing2);
sys/dev/pci/drm/radeon/rv730_dpm.c
482
WREG32(MC4_IO_DQ_PAD_CNTL_D0_I0, mc4_io_pad_cntl);
sys/dev/pci/drm/radeon/rv730_dpm.c
483
WREG32(MC4_IO_DQ_PAD_CNTL_D0_I1, mc4_io_pad_cntl);
sys/dev/pci/drm/radeon/rv730_dpm.c
488
WREG32(MC4_IO_QS_PAD_CNTL_D0_I0, mc4_io_pad_cntl);
sys/dev/pci/drm/radeon/rv730_dpm.c
489
WREG32(MC4_IO_QS_PAD_CNTL_D0_I1, mc4_io_pad_cntl);
sys/dev/pci/drm/radeon/rv770.c
1000
WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
1002
WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
sys/dev/pci/drm/radeon/rv770.c
1013
WREG32((0x2c14 + j), 0x00000000);
sys/dev/pci/drm/radeon/rv770.c
1014
WREG32((0x2c18 + j), 0x00000000);
sys/dev/pci/drm/radeon/rv770.c
1015
WREG32((0x2c1c + j), 0x00000000);
sys/dev/pci/drm/radeon/rv770.c
1016
WREG32((0x2c20 + j), 0x00000000);
sys/dev/pci/drm/radeon/rv770.c
1017
WREG32((0x2c24 + j), 0x00000000);
sys/dev/pci/drm/radeon/rv770.c
1029
WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
sys/dev/pci/drm/radeon/rv770.c
1034
WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
sys/dev/pci/drm/radeon/rv770.c
1036
WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
sys/dev/pci/drm/radeon/rv770.c
1040
WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
sys/dev/pci/drm/radeon/rv770.c
1042
WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
sys/dev/pci/drm/radeon/rv770.c
1046
WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
sys/dev/pci/drm/radeon/rv770.c
1048
WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
sys/dev/pci/drm/radeon/rv770.c
1051
WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
sys/dev/pci/drm/radeon/rv770.c
1054
WREG32(MC_VM_FB_LOCATION, tmp);
sys/dev/pci/drm/radeon/rv770.c
1055
WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
sys/dev/pci/drm/radeon/rv770.c
1056
WREG32(HDP_NONSURFACE_INFO, (2 << 7));
sys/dev/pci/drm/radeon/rv770.c
1057
WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
sys/dev/pci/drm/radeon/rv770.c
1059
WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
sys/dev/pci/drm/radeon/rv770.c
1060
WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
sys/dev/pci/drm/radeon/rv770.c
1061
WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
sys/dev/pci/drm/radeon/rv770.c
1063
WREG32(MC_VM_AGP_BASE, 0);
sys/dev/pci/drm/radeon/rv770.c
1064
WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
sys/dev/pci/drm/radeon/rv770.c
1065
WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
sys/dev/pci/drm/radeon/rv770.c
1084
WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
sys/dev/pci/drm/radeon/rv770.c
1085
WREG32(SCRATCH_UMSK, 0);
sys/dev/pci/drm/radeon/rv770.c
1098
WREG32(CP_RB_CNTL,
sys/dev/pci/drm/radeon/rv770.c
1105
WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
sys/dev/pci/drm/radeon/rv770.c
1108
WREG32(GRBM_SOFT_RESET, 0);
sys/dev/pci/drm/radeon/rv770.c
1111
WREG32(CP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/rv770.c
1113
WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/rv770.c
1114
WREG32(CP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/rv770.c
1117
WREG32(CP_ME_RAM_WADDR, 0);
sys/dev/pci/drm/radeon/rv770.c
1119
WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/rv770.c
1121
WREG32(CP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/rv770.c
1122
WREG32(CP_ME_RAM_WADDR, 0);
sys/dev/pci/drm/radeon/rv770.c
1123
WREG32(CP_ME_RAM_RADDR, 0);
sys/dev/pci/drm/radeon/rv770.c
1145
WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
sys/dev/pci/drm/radeon/rv770.c
1154
WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
sys/dev/pci/drm/radeon/rv770.c
1161
WREG32(MPLL_CNTL_MODE, tmp);
sys/dev/pci/drm/radeon/rv770.c
1289
WREG32((0x2c14 + j), 0x00000000);
sys/dev/pci/drm/radeon/rv770.c
1290
WREG32((0x2c18 + j), 0x00000000);
sys/dev/pci/drm/radeon/rv770.c
1291
WREG32((0x2c1c + j), 0x00000000);
sys/dev/pci/drm/radeon/rv770.c
1292
WREG32((0x2c20 + j), 0x00000000);
sys/dev/pci/drm/radeon/rv770.c
1293
WREG32((0x2c24 + j), 0x00000000);
sys/dev/pci/drm/radeon/rv770.c
1297
WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
sys/dev/pci/drm/radeon/rv770.c
1311
WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1);
sys/dev/pci/drm/radeon/rv770.c
1313
WREG32(SPI_CONFIG_CNTL, 0);
sys/dev/pci/drm/radeon/rv770.c
1376
WREG32(GB_TILING_CONFIG, gb_tiling_config);
sys/dev/pci/drm/radeon/rv770.c
1377
WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
sys/dev/pci/drm/radeon/rv770.c
1378
WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
sys/dev/pci/drm/radeon/rv770.c
1379
WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));
sys/dev/pci/drm/radeon/rv770.c
1380
WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));
sys/dev/pci/drm/radeon/rv770.c
1382
WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff));
sys/dev/pci/drm/radeon/rv770.c
1383
WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff));
sys/dev/pci/drm/radeon/rv770.c
1384
WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff));
sys/dev/pci/drm/radeon/rv770.c
1387
WREG32(CGTS_SYS_TCC_DISABLE, 0);
sys/dev/pci/drm/radeon/rv770.c
1388
WREG32(CGTS_TCC_DISABLE, 0);
sys/dev/pci/drm/radeon/rv770.c
1389
WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
sys/dev/pci/drm/radeon/rv770.c
1390
WREG32(CGTS_USER_TCC_DISABLE, 0);
sys/dev/pci/drm/radeon/rv770.c
1394
WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
sys/dev/pci/drm/radeon/rv770.c
1395
WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
sys/dev/pci/drm/radeon/rv770.c
1398
WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
sys/dev/pci/drm/radeon/rv770.c
1401
WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
sys/dev/pci/drm/radeon/rv770.c
1404
WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
sys/dev/pci/drm/radeon/rv770.c
1408
WREG32(SX_DEBUG_1, sx_debug_1);
sys/dev/pci/drm/radeon/rv770.c
1413
WREG32(SMX_DC_CTL0, smx_dc_ctl0);
sys/dev/pci/drm/radeon/rv770.c
1416
WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
sys/dev/pci/drm/radeon/rv770.c
1422
WREG32(SMX_SAR_CTL0, 0x00003f3f);
sys/dev/pci/drm/radeon/rv770.c
1437
WREG32(DB_DEBUG3, db_debug3);
sys/dev/pci/drm/radeon/rv770.c
1442
WREG32(DB_DEBUG4, db_debug4);
sys/dev/pci/drm/radeon/rv770.c
1445
WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
sys/dev/pci/drm/radeon/rv770.c
1449
WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
sys/dev/pci/drm/radeon/rv770.c
1453
WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
sys/dev/pci/drm/radeon/rv770.c
1455
WREG32(VGT_NUM_INSTANCES, 1);
sys/dev/pci/drm/radeon/rv770.c
1457
WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
sys/dev/pci/drm/radeon/rv770.c
1459
WREG32(CP_PERFMON_CNTL, 0);
sys/dev/pci/drm/radeon/rv770.c
1475
WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
sys/dev/pci/drm/radeon/rv770.c
1496
WREG32(SQ_CONFIG, sq_config);
sys/dev/pci/drm/radeon/rv770.c
1498
WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
sys/dev/pci/drm/radeon/rv770.c
1502
WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
sys/dev/pci/drm/radeon/rv770.c
1512
WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
sys/dev/pci/drm/radeon/rv770.c
1514
WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
sys/dev/pci/drm/radeon/rv770.c
1517
WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
sys/dev/pci/drm/radeon/rv770.c
1525
WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
sys/dev/pci/drm/radeon/rv770.c
1526
WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
sys/dev/pci/drm/radeon/rv770.c
1527
WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
sys/dev/pci/drm/radeon/rv770.c
1528
WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
sys/dev/pci/drm/radeon/rv770.c
1529
WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
sys/dev/pci/drm/radeon/rv770.c
1530
WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
sys/dev/pci/drm/radeon/rv770.c
1531
WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
sys/dev/pci/drm/radeon/rv770.c
1532
WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
sys/dev/pci/drm/radeon/rv770.c
1534
WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
sys/dev/pci/drm/radeon/rv770.c
1538
WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
sys/dev/pci/drm/radeon/rv770.c
1541
WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
sys/dev/pci/drm/radeon/rv770.c
1563
WREG32(VGT_ES_PER_GS, 128);
sys/dev/pci/drm/radeon/rv770.c
1564
WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
sys/dev/pci/drm/radeon/rv770.c
1565
WREG32(VGT_GS_PER_VS, 2);
sys/dev/pci/drm/radeon/rv770.c
1568
WREG32(VGT_GS_VERTEX_REUSE, 16);
sys/dev/pci/drm/radeon/rv770.c
1569
WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
sys/dev/pci/drm/radeon/rv770.c
1570
WREG32(VGT_STRMOUT_EN, 0);
sys/dev/pci/drm/radeon/rv770.c
1571
WREG32(SX_MISC, 0);
sys/dev/pci/drm/radeon/rv770.c
1572
WREG32(PA_SC_MODE_CNTL, 0);
sys/dev/pci/drm/radeon/rv770.c
1573
WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
sys/dev/pci/drm/radeon/rv770.c
1574
WREG32(PA_SC_AA_CONFIG, 0);
sys/dev/pci/drm/radeon/rv770.c
1575
WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
sys/dev/pci/drm/radeon/rv770.c
1576
WREG32(PA_SC_LINE_STIPPLE, 0);
sys/dev/pci/drm/radeon/rv770.c
1577
WREG32(SPI_INPUT_Z, 0);
sys/dev/pci/drm/radeon/rv770.c
1578
WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
sys/dev/pci/drm/radeon/rv770.c
1579
WREG32(CB_COLOR7_FRAG, 0);
sys/dev/pci/drm/radeon/rv770.c
1582
WREG32(CB_COLOR0_BASE, 0);
sys/dev/pci/drm/radeon/rv770.c
1583
WREG32(CB_COLOR1_BASE, 0);
sys/dev/pci/drm/radeon/rv770.c
1584
WREG32(CB_COLOR2_BASE, 0);
sys/dev/pci/drm/radeon/rv770.c
1585
WREG32(CB_COLOR3_BASE, 0);
sys/dev/pci/drm/radeon/rv770.c
1586
WREG32(CB_COLOR4_BASE, 0);
sys/dev/pci/drm/radeon/rv770.c
1587
WREG32(CB_COLOR5_BASE, 0);
sys/dev/pci/drm/radeon/rv770.c
1588
WREG32(CB_COLOR6_BASE, 0);
sys/dev/pci/drm/radeon/rv770.c
1589
WREG32(CB_COLOR7_BASE, 0);
sys/dev/pci/drm/radeon/rv770.c
1591
WREG32(TCP_CNTL, 0);
sys/dev/pci/drm/radeon/rv770.c
1594
WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
sys/dev/pci/drm/radeon/rv770.c
1596
WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
sys/dev/pci/drm/radeon/rv770.c
1598
WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
sys/dev/pci/drm/radeon/rv770.c
1600
WREG32(VC_ENHANCE, 0);
sys/dev/pci/drm/radeon/rv770.c
2068
WREG32(0x541c, tmp | 0x8);
sys/dev/pci/drm/radeon/rv770.c
2069
WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
sys/dev/pci/drm/radeon/rv770.c
2074
WREG32(MM_CFGREGS_CNTL, 0);
sys/dev/pci/drm/radeon/rv770.c
809
WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/rv770.c
812
WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/rv770.c
815
WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/rv770.c
819
WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
sys/dev/pci/drm/radeon/rv770.c
820
WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
sys/dev/pci/drm/radeon/rv770.c
822
WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
sys/dev/pci/drm/radeon/rv770.c
823
WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
sys/dev/pci/drm/radeon/rv770.c
825
WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/rv770.c
827
WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/rv770.c
840
WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/rv770.c
907
WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
sys/dev/pci/drm/radeon/rv770.c
910
WREG32(VM_L2_CNTL2, 0);
sys/dev/pci/drm/radeon/rv770.c
911
WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
sys/dev/pci/drm/radeon/rv770.c
917
WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
918
WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
919
WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
921
WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
922
WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
923
WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
924
WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
925
WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
926
WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
sys/dev/pci/drm/radeon/rv770.c
927
WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
sys/dev/pci/drm/radeon/rv770.c
928
WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
sys/dev/pci/drm/radeon/rv770.c
929
WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
sys/dev/pci/drm/radeon/rv770.c
931
WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
sys/dev/pci/drm/radeon/rv770.c
934
WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
sys/dev/pci/drm/radeon/rv770.c
951
WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
sys/dev/pci/drm/radeon/rv770.c
954
WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
sys/dev/pci/drm/radeon/rv770.c
956
WREG32(VM_L2_CNTL2, 0);
sys/dev/pci/drm/radeon/rv770.c
957
WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
sys/dev/pci/drm/radeon/rv770.c
960
WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
961
WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
962
WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
963
WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
964
WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
965
WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
966
WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
984
WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
sys/dev/pci/drm/radeon/rv770.c
987
WREG32(VM_L2_CNTL2, 0);
sys/dev/pci/drm/radeon/rv770.c
988
WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
sys/dev/pci/drm/radeon/rv770.c
994
WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
995
WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
996
WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
997
WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
998
WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
999
WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770_dpm.c
1358
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770_dpm.c
157
WREG32(CG_CGTT_LOCAL_0, mgcg_cgtt_local0);
sys/dev/pci/drm/radeon/rv770_dpm.c
158
WREG32(CG_CGTT_LOCAL_1, (RV770_MGCGTTLOCAL1_DFLT & 0xFFFFCFFF));
sys/dev/pci/drm/radeon/rv770_dpm.c
1587
WREG32(S0_VID_LOWER_SMIO_CNTL, vid_smio_cntl);
sys/dev/pci/drm/radeon/rv770_dpm.c
161
WREG32(CGTS_SM_CTRL_REG, RV770_MGCGCGTSSMCTRL_DFLT);
sys/dev/pci/drm/radeon/rv770_dpm.c
163
WREG32(CG_CGTT_LOCAL_0, 0xFFFFFFFF);
sys/dev/pci/drm/radeon/rv770_dpm.c
164
WREG32(CG_CGTT_LOCAL_1, 0xFFFFCFFF);
sys/dev/pci/drm/radeon/rv770_dpm.c
762
WREG32(MC_ARB_SQM_RATIO, sqm_ratio);
sys/dev/pci/drm/radeon/rv770_dpm.c
769
WREG32(MC_ARB_RFSH_RATE, arb_refresh_rate);
sys/dev/pci/drm/radeon/rv770_dpm.c
811
WREG32(MPLL_TIME,
sys/dev/pci/drm/radeon/rv770_dpm.c
837
WREG32(CG_BSP, pi->dsp);
sys/dev/pci/drm/radeon/rv770_dpm.c
852
WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
sys/dev/pci/drm/radeon/rv770_dpm.c
866
WREG32(CG_TPC, R600_TPC_DFLT);
sys/dev/pci/drm/radeon/rv770_dpm.c
871
WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
sys/dev/pci/drm/radeon/rv770_dpm.c
886
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770_dpm.c
893
WREG32(CG_FTV, pi->vrc);
sys/dev/pci/drm/radeon/rv770_dpm.c
898
WREG32(CG_FTV, 0);
sys/dev/pci/drm/radeon/rv770_smc.c
278
WREG32(SMC_SRAM_ADDR, addr);
sys/dev/pci/drm/radeon/rv770_smc.c
308
WREG32(SMC_SRAM_DATA, data);
sys/dev/pci/drm/radeon/rv770_smc.c
341
WREG32(SMC_SRAM_DATA, data);
sys/dev/pci/drm/radeon/rv770_smc.c
374
WREG32(SMC_ISR_FFD8_FFDB + i, tmp);
sys/dev/pci/drm/radeon/rv770_smc.c
463
WREG32(SMC_SRAM_DATA, 0);
sys/dev/pci/drm/radeon/rv770_smc.c
615
WREG32(SMC_SRAM_DATA, value);
sys/dev/pci/drm/radeon/si.c
1607
WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
sys/dev/pci/drm/radeon/si.c
1608
WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
sys/dev/pci/drm/radeon/si.c
1613
WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
sys/dev/pci/drm/radeon/si.c
1614
WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
sys/dev/pci/drm/radeon/si.c
1616
WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
sys/dev/pci/drm/radeon/si.c
1617
WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
sys/dev/pci/drm/radeon/si.c
1623
WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
sys/dev/pci/drm/radeon/si.c
1625
WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/si.c
1629
WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
sys/dev/pci/drm/radeon/si.c
1630
WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
sys/dev/pci/drm/radeon/si.c
1631
WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
sys/dev/pci/drm/radeon/si.c
1980
WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/si.c
1983
WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
sys/dev/pci/drm/radeon/si.c
2415
WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/si.c
2416
WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/si.c
2423
WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/si.c
2424
WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
sys/dev/pci/drm/radeon/si.c
2428
WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
sys/dev/pci/drm/radeon/si.c
2431
WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
sys/dev/pci/drm/radeon/si.c
2432
WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
sys/dev/pci/drm/radeon/si.c
2704
WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
sys/dev/pci/drm/radeon/si.c
2919
WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
sys/dev/pci/drm/radeon/si.c
2940
WREG32(GRBM_GFX_INDEX, data);
sys/dev/pci/drm/radeon/si.c
2990
WREG32(SPI_STATIC_THREAD_MGMT_3, data);
sys/dev/pci/drm/radeon/si.c
3064
WREG32(PA_SC_RASTER_CONFIG, data);
sys/dev/pci/drm/radeon/si.c
3169
WREG32((0x2c14 + j), 0x00000000);
sys/dev/pci/drm/radeon/si.c
3170
WREG32((0x2c18 + j), 0x00000000);
sys/dev/pci/drm/radeon/si.c
3171
WREG32((0x2c1c + j), 0x00000000);
sys/dev/pci/drm/radeon/si.c
3172
WREG32((0x2c20 + j), 0x00000000);
sys/dev/pci/drm/radeon/si.c
3173
WREG32((0x2c24 + j), 0x00000000);
sys/dev/pci/drm/radeon/si.c
3176
WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
sys/dev/pci/drm/radeon/si.c
3177
WREG32(SRBM_INT_CNTL, 1);
sys/dev/pci/drm/radeon/si.c
3178
WREG32(SRBM_INT_ACK, 1);
sys/dev/pci/drm/radeon/si.c
3182
WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
sys/dev/pci/drm/radeon/si.c
3254
WREG32(GB_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/si.c
3255
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/si.c
3256
WREG32(DMIF_ADDR_CALC, gb_addr_config);
sys/dev/pci/drm/radeon/si.c
3257
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/si.c
3258
WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
sys/dev/pci/drm/radeon/si.c
3259
WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
sys/dev/pci/drm/radeon/si.c
3261
WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/si.c
3262
WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/si.c
3263
WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
sys/dev/pci/drm/radeon/si.c
3285
WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
sys/dev/pci/drm/radeon/si.c
3287
WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
sys/dev/pci/drm/radeon/si.c
3290
WREG32(SX_DEBUG_1, sx_debug_1);
sys/dev/pci/drm/radeon/si.c
3292
WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
sys/dev/pci/drm/radeon/si.c
3294
WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
sys/dev/pci/drm/radeon/si.c
3299
WREG32(VGT_NUM_INSTANCES, 1);
sys/dev/pci/drm/radeon/si.c
3301
WREG32(CP_PERFMON_CNTL, 0);
sys/dev/pci/drm/radeon/si.c
3303
WREG32(SQ_CONFIG, 0);
sys/dev/pci/drm/radeon/si.c
3305
WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
sys/dev/pci/drm/radeon/si.c
3308
WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
sys/dev/pci/drm/radeon/si.c
3311
WREG32(VGT_GS_VERTEX_REUSE, 16);
sys/dev/pci/drm/radeon/si.c
3312
WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
sys/dev/pci/drm/radeon/si.c
3314
WREG32(CB_PERFCOUNTER0_SELECT0, 0);
sys/dev/pci/drm/radeon/si.c
3315
WREG32(CB_PERFCOUNTER0_SELECT1, 0);
sys/dev/pci/drm/radeon/si.c
3316
WREG32(CB_PERFCOUNTER1_SELECT0, 0);
sys/dev/pci/drm/radeon/si.c
3317
WREG32(CB_PERFCOUNTER1_SELECT1, 0);
sys/dev/pci/drm/radeon/si.c
3318
WREG32(CB_PERFCOUNTER2_SELECT0, 0);
sys/dev/pci/drm/radeon/si.c
3319
WREG32(CB_PERFCOUNTER2_SELECT1, 0);
sys/dev/pci/drm/radeon/si.c
3320
WREG32(CB_PERFCOUNTER3_SELECT0, 0);
sys/dev/pci/drm/radeon/si.c
3321
WREG32(CB_PERFCOUNTER3_SELECT1, 0);
sys/dev/pci/drm/radeon/si.c
3325
WREG32(HDP_MISC_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
3328
WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
sys/dev/pci/drm/radeon/si.c
3330
WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
sys/dev/pci/drm/radeon/si.c
3443
WREG32(CP_ME_CNTL, 0);
sys/dev/pci/drm/radeon/si.c
3447
WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
sys/dev/pci/drm/radeon/si.c
3448
WREG32(SCRATCH_UMSK, 0);
sys/dev/pci/drm/radeon/si.c
3483
WREG32(CP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/si.c
3485
WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/si.c
3486
WREG32(CP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/si.c
3492
WREG32(CP_CE_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/si.c
3494
WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/si.c
3495
WREG32(CP_CE_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/si.c
3501
WREG32(CP_ME_RAM_WADDR, 0);
sys/dev/pci/drm/radeon/si.c
3503
WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/si.c
3504
WREG32(CP_ME_RAM_WADDR, 0);
sys/dev/pci/drm/radeon/si.c
3510
WREG32(CP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/si.c
3512
WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/si.c
3513
WREG32(CP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/si.c
3517
WREG32(CP_CE_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/si.c
3519
WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/si.c
3520
WREG32(CP_CE_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/si.c
3524
WREG32(CP_ME_RAM_WADDR, 0);
sys/dev/pci/drm/radeon/si.c
3526
WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/si.c
3527
WREG32(CP_ME_RAM_WADDR, 0);
sys/dev/pci/drm/radeon/si.c
3530
WREG32(CP_PFP_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/si.c
3531
WREG32(CP_CE_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/si.c
3532
WREG32(CP_ME_RAM_WADDR, 0);
sys/dev/pci/drm/radeon/si.c
3533
WREG32(CP_ME_RAM_RADDR, 0);
sys/dev/pci/drm/radeon/si.c
3637
WREG32(CP_SEM_WAIT_TIMER, 0x0);
sys/dev/pci/drm/radeon/si.c
3638
WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
sys/dev/pci/drm/radeon/si.c
3641
WREG32(CP_RB_WPTR_DELAY, 0);
sys/dev/pci/drm/radeon/si.c
3643
WREG32(CP_DEBUG, 0);
sys/dev/pci/drm/radeon/si.c
3644
WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
sys/dev/pci/drm/radeon/si.c
3654
WREG32(CP_RB0_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
3657
WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
sys/dev/pci/drm/radeon/si.c
3659
WREG32(CP_RB0_WPTR, ring->wptr);
sys/dev/pci/drm/radeon/si.c
3662
WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
sys/dev/pci/drm/radeon/si.c
3663
WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
sys/dev/pci/drm/radeon/si.c
3666
WREG32(SCRATCH_UMSK, 0xff);
sys/dev/pci/drm/radeon/si.c
3669
WREG32(SCRATCH_UMSK, 0);
sys/dev/pci/drm/radeon/si.c
3673
WREG32(CP_RB0_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
3675
WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
sys/dev/pci/drm/radeon/si.c
3685
WREG32(CP_RB1_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
3688
WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
sys/dev/pci/drm/radeon/si.c
3690
WREG32(CP_RB1_WPTR, ring->wptr);
sys/dev/pci/drm/radeon/si.c
3693
WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
sys/dev/pci/drm/radeon/si.c
3694
WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
sys/dev/pci/drm/radeon/si.c
3697
WREG32(CP_RB1_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
3699
WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
sys/dev/pci/drm/radeon/si.c
3709
WREG32(CP_RB2_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
3712
WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
sys/dev/pci/drm/radeon/si.c
3714
WREG32(CP_RB2_WPTR, ring->wptr);
sys/dev/pci/drm/radeon/si.c
3717
WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
sys/dev/pci/drm/radeon/si.c
3718
WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
sys/dev/pci/drm/radeon/si.c
3721
WREG32(CP_RB2_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
3723
WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
sys/dev/pci/drm/radeon/si.c
3860
WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
sys/dev/pci/drm/radeon/si.c
3866
WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/si.c
3872
WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/si.c
3934
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/si.c
3940
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/si.c
3948
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/si.c
3954
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/si.c
3973
WREG32(CG_SPLL_FUNC_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
3977
WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
sys/dev/pci/drm/radeon/si.c
3987
WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
sys/dev/pci/drm/radeon/si.c
3991
WREG32(MPLL_CNTL_MODE, tmp);
sys/dev/pci/drm/radeon/si.c
4000
WREG32(SPLL_CNTL_MODE, tmp);
sys/dev/pci/drm/radeon/si.c
4004
WREG32(CG_SPLL_FUNC_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
4008
WREG32(CG_SPLL_FUNC_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
4012
WREG32(SPLL_CNTL_MODE, tmp);
sys/dev/pci/drm/radeon/si.c
4029
WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
sys/dev/pci/drm/radeon/si.c
4033
WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/si.c
4037
WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/si.c
4129
WREG32((0x2c14 + j), 0x00000000);
sys/dev/pci/drm/radeon/si.c
4130
WREG32((0x2c18 + j), 0x00000000);
sys/dev/pci/drm/radeon/si.c
4131
WREG32((0x2c1c + j), 0x00000000);
sys/dev/pci/drm/radeon/si.c
4132
WREG32((0x2c20 + j), 0x00000000);
sys/dev/pci/drm/radeon/si.c
4133
WREG32((0x2c24 + j), 0x00000000);
sys/dev/pci/drm/radeon/si.c
4135
WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
sys/dev/pci/drm/radeon/si.c
4143
WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
sys/dev/pci/drm/radeon/si.c
4145
WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
sys/dev/pci/drm/radeon/si.c
4147
WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
sys/dev/pci/drm/radeon/si.c
4149
WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
sys/dev/pci/drm/radeon/si.c
4153
WREG32(MC_VM_FB_LOCATION, tmp);
sys/dev/pci/drm/radeon/si.c
4155
WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
sys/dev/pci/drm/radeon/si.c
4156
WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
sys/dev/pci/drm/radeon/si.c
4157
WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
sys/dev/pci/drm/radeon/si.c
4158
WREG32(MC_VM_AGP_BASE, 0);
sys/dev/pci/drm/radeon/si.c
4159
WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
sys/dev/pci/drm/radeon/si.c
4160
WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
sys/dev/pci/drm/radeon/si.c
4259
WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
sys/dev/pci/drm/radeon/si.c
4262
WREG32(VM_INVALIDATE_REQUEST, 1);
sys/dev/pci/drm/radeon/si.c
4277
WREG32(MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/radeon/si.c
4285
WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
sys/dev/pci/drm/radeon/si.c
4291
WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
sys/dev/pci/drm/radeon/si.c
4292
WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
sys/dev/pci/drm/radeon/si.c
4296
WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
sys/dev/pci/drm/radeon/si.c
4297
WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
sys/dev/pci/drm/radeon/si.c
4298
WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
sys/dev/pci/drm/radeon/si.c
4299
WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
sys/dev/pci/drm/radeon/si.c
4301
WREG32(VM_CONTEXT0_CNTL2, 0);
sys/dev/pci/drm/radeon/si.c
4302
WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
sys/dev/pci/drm/radeon/si.c
4305
WREG32(0x15D4, 0);
sys/dev/pci/drm/radeon/si.c
4306
WREG32(0x15D8, 0);
sys/dev/pci/drm/radeon/si.c
4307
WREG32(0x15DC, 0);
sys/dev/pci/drm/radeon/si.c
4311
WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
sys/dev/pci/drm/radeon/si.c
4312
WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1);
sys/dev/pci/drm/radeon/si.c
4319
WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
sys/dev/pci/drm/radeon/si.c
4322
WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
sys/dev/pci/drm/radeon/si.c
4327
WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
sys/dev/pci/drm/radeon/si.c
4329
WREG32(VM_CONTEXT1_CNTL2, 4);
sys/dev/pci/drm/radeon/si.c
4330
WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
sys/dev/pci/drm/radeon/si.c
4367
WREG32(VM_CONTEXT0_CNTL, 0);
sys/dev/pci/drm/radeon/si.c
4368
WREG32(VM_CONTEXT1_CNTL, 0);
sys/dev/pci/drm/radeon/si.c
4370
WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
sys/dev/pci/drm/radeon/si.c
4373
WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
sys/dev/pci/drm/radeon/si.c
4377
WREG32(VM_L2_CNTL2, 0);
sys/dev/pci/drm/radeon/si.c
4378
WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
sys/dev/pci/drm/radeon/si.c
5136
WREG32(CP_INT_CNTL_RING0, tmp);
sys/dev/pci/drm/radeon/si.c
5168
WREG32(UVD_CGC_CTRL, tmp);
sys/dev/pci/drm/radeon/si.c
5181
WREG32(UVD_CGC_CTRL, tmp);
sys/dev/pci/drm/radeon/si.c
5193
WREG32(RLC_CNTL, data);
sys/dev/pci/drm/radeon/si.c
5207
WREG32(RLC_CNTL, rlc);
sys/dev/pci/drm/radeon/si.c
5220
WREG32(DMA_PG, data);
sys/dev/pci/drm/radeon/si.c
5227
WREG32(DMA_PGFSM_WRITE, 0x00002000);
sys/dev/pci/drm/radeon/si.c
5228
WREG32(DMA_PGFSM_CONFIG, 0x100010ff);
sys/dev/pci/drm/radeon/si.c
5231
WREG32(DMA_PGFSM_WRITE, 0);
sys/dev/pci/drm/radeon/si.c
5241
WREG32(RLC_TTOP_D, tmp);
sys/dev/pci/drm/radeon/si.c
5245
WREG32(RLC_PG_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
5249
WREG32(RLC_AUTO_PG_CTRL, tmp);
sys/dev/pci/drm/radeon/si.c
5253
WREG32(RLC_AUTO_PG_CTRL, tmp);
sys/dev/pci/drm/radeon/si.c
5263
WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
sys/dev/pci/drm/radeon/si.c
5267
WREG32(RLC_PG_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
5269
WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
sys/dev/pci/drm/radeon/si.c
5276
WREG32(RLC_AUTO_PG_CTRL, tmp);
sys/dev/pci/drm/radeon/si.c
5327
WREG32(RLC_PG_AO_CU_MASK, tmp);
sys/dev/pci/drm/radeon/si.c
5332
WREG32(RLC_MAX_PG_CU, tmp);
sys/dev/pci/drm/radeon/si.c
5345
WREG32(RLC_GCPM_GENERAL_3, 0x00000080);
sys/dev/pci/drm/radeon/si.c
5349
WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
sys/dev/pci/drm/radeon/si.c
5350
WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
sys/dev/pci/drm/radeon/si.c
5351
WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff);
sys/dev/pci/drm/radeon/si.c
5357
WREG32(RLC_SERDES_WR_CTRL, 0x007000ff);
sys/dev/pci/drm/radeon/si.c
5372
WREG32(RLC_CGCG_CGLS_CTRL, data);
sys/dev/pci/drm/radeon/si.c
5384
WREG32(CGTS_SM_CTRL_REG, data);
sys/dev/pci/drm/radeon/si.c
5390
WREG32(CP_MEM_SLP_CNTL, data);
sys/dev/pci/drm/radeon/si.c
5396
WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
sys/dev/pci/drm/radeon/si.c
5400
WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
sys/dev/pci/drm/radeon/si.c
5401
WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
sys/dev/pci/drm/radeon/si.c
5402
WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff);
sys/dev/pci/drm/radeon/si.c
5409
WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
sys/dev/pci/drm/radeon/si.c
5414
WREG32(CP_MEM_SLP_CNTL, data);
sys/dev/pci/drm/radeon/si.c
5419
WREG32(CGTS_SM_CTRL_REG, data);
sys/dev/pci/drm/radeon/si.c
5423
WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
sys/dev/pci/drm/radeon/si.c
5424
WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
sys/dev/pci/drm/radeon/si.c
5425
WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff);
sys/dev/pci/drm/radeon/si.c
5444
WREG32(UVD_CGC_CTRL, data);
sys/dev/pci/drm/radeon/si.c
5456
WREG32(UVD_CGC_CTRL, data);
sys/dev/pci/drm/radeon/si.c
5489
WREG32(mc_cg_registers[i], data);
sys/dev/pci/drm/radeon/si.c
5506
WREG32(mc_cg_registers[i], data);
sys/dev/pci/drm/radeon/si.c
5525
WREG32(DMA_POWER_CNTL + offset, data);
sys/dev/pci/drm/radeon/si.c
5526
WREG32(DMA_CLK_CTRL + offset, 0x00000100);
sys/dev/pci/drm/radeon/si.c
5537
WREG32(DMA_POWER_CNTL + offset, data);
sys/dev/pci/drm/radeon/si.c
5542
WREG32(DMA_CLK_CTRL + offset, data);
sys/dev/pci/drm/radeon/si.c
5578
WREG32(HDP_HOST_PATH_CNTL, data);
sys/dev/pci/drm/radeon/si.c
5594
WREG32(HDP_MEM_POWER_LS, data);
sys/dev/pci/drm/radeon/si.c
5765
WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
sys/dev/pci/drm/radeon/si.c
5766
WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
sys/dev/pci/drm/radeon/si.c
5771
WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
sys/dev/pci/drm/radeon/si.c
5772
WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
sys/dev/pci/drm/radeon/si.c
5792
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/si.c
5795
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/si.c
5801
WREG32(RLC_CNTL, 0);
sys/dev/pci/drm/radeon/si.c
5810
WREG32(RLC_CNTL, RLC_ENABLE);
sys/dev/pci/drm/radeon/si.c
5837
WREG32(RLC_LB_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
5841
WREG32(SPI_LB_CU_MASK, 0x00ff);
sys/dev/pci/drm/radeon/si.c
5860
WREG32(RLC_RL_BASE, 0);
sys/dev/pci/drm/radeon/si.c
5861
WREG32(RLC_RL_SIZE, 0);
sys/dev/pci/drm/radeon/si.c
5862
WREG32(RLC_LB_CNTL, 0);
sys/dev/pci/drm/radeon/si.c
5863
WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
sys/dev/pci/drm/radeon/si.c
5864
WREG32(RLC_LB_CNTR_INIT, 0);
sys/dev/pci/drm/radeon/si.c
5865
WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
sys/dev/pci/drm/radeon/si.c
5867
WREG32(RLC_MC_CNTL, 0);
sys/dev/pci/drm/radeon/si.c
5868
WREG32(RLC_UCODE_CNTL, 0);
sys/dev/pci/drm/radeon/si.c
5880
WREG32(RLC_UCODE_ADDR, i);
sys/dev/pci/drm/radeon/si.c
5881
WREG32(RLC_UCODE_DATA, le32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/si.c
5887
WREG32(RLC_UCODE_ADDR, i);
sys/dev/pci/drm/radeon/si.c
5888
WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
sys/dev/pci/drm/radeon/si.c
5891
WREG32(RLC_UCODE_ADDR, 0);
sys/dev/pci/drm/radeon/si.c
5907
WREG32(IH_CNTL, ih_cntl);
sys/dev/pci/drm/radeon/si.c
5908
WREG32(IH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/radeon/si.c
5919
WREG32(IH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/radeon/si.c
5920
WREG32(IH_CNTL, ih_cntl);
sys/dev/pci/drm/radeon/si.c
5922
WREG32(IH_RB_RPTR, 0);
sys/dev/pci/drm/radeon/si.c
5923
WREG32(IH_RB_WPTR, 0);
sys/dev/pci/drm/radeon/si.c
5935
WREG32(CP_INT_CNTL_RING0, tmp);
sys/dev/pci/drm/radeon/si.c
5936
WREG32(CP_INT_CNTL_RING1, 0);
sys/dev/pci/drm/radeon/si.c
5937
WREG32(CP_INT_CNTL_RING2, 0);
sys/dev/pci/drm/radeon/si.c
5939
WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/si.c
5941
WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/si.c
5942
WREG32(GRBM_INT_CNTL, 0);
sys/dev/pci/drm/radeon/si.c
5943
WREG32(SRBM_INT_CNTL, 0);
sys/dev/pci/drm/radeon/si.c
5945
WREG32(INT_MASK + crtc_offsets[i], 0);
sys/dev/pci/drm/radeon/si.c
5947
WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0);
sys/dev/pci/drm/radeon/si.c
5950
WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
sys/dev/pci/drm/radeon/si.c
5981
WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8);
sys/dev/pci/drm/radeon/si.c
5989
WREG32(INTERRUPT_CNTL, interrupt_cntl);
sys/dev/pci/drm/radeon/si.c
5991
WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
sys/dev/pci/drm/radeon/si.c
6002
WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
sys/dev/pci/drm/radeon/si.c
6003
WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
sys/dev/pci/drm/radeon/si.c
6005
WREG32(IH_RB_CNTL, ih_rb_cntl);
sys/dev/pci/drm/radeon/si.c
6008
WREG32(IH_RB_RPTR, 0);
sys/dev/pci/drm/radeon/si.c
6009
WREG32(IH_RB_WPTR, 0);
sys/dev/pci/drm/radeon/si.c
6016
WREG32(IH_CNTL, ih_cntl);
sys/dev/pci/drm/radeon/si.c
6083
WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
sys/dev/pci/drm/radeon/si.c
6084
WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
sys/dev/pci/drm/radeon/si.c
6085
WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
sys/dev/pci/drm/radeon/si.c
6087
WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl);
sys/dev/pci/drm/radeon/si.c
6088
WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);
sys/dev/pci/drm/radeon/si.c
6090
WREG32(GRBM_INT_CNTL, grbm_int_cntl);
sys/dev/pci/drm/radeon/si.c
6105
WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK);
sys/dev/pci/drm/radeon/si.c
6116
WREG32(CG_THERMAL_INT, thermal_int);
sys/dev/pci/drm/radeon/si.c
6144
WREG32(GRPH_INT_STATUS + crtc_offsets[j],
sys/dev/pci/drm/radeon/si.c
6150
WREG32(VBLANK_STATUS + crtc_offsets[j],
sys/dev/pci/drm/radeon/si.c
6153
WREG32(VLINE_STATUS + crtc_offsets[j],
sys/dev/pci/drm/radeon/si.c
6210
WREG32(IH_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
6346
WREG32(SRBM_INT_ACK, 0x1);
sys/dev/pci/drm/radeon/si.c
6419
WREG32(IH_RB_RPTR, rptr);
sys/dev/pci/drm/radeon/si.c
6970
WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
sys/dev/pci/drm/radeon/si.c
7377
WREG32(THM_CLK_CNTL, data);
sys/dev/pci/drm/radeon/si.c
7383
WREG32(MISC_CLK_CNTL, data);
sys/dev/pci/drm/radeon/si.c
7388
WREG32(CG_CLKPIN_CNTL, data);
sys/dev/pci/drm/radeon/si.c
7393
WREG32(CG_CLKPIN_CNTL_2, data);
sys/dev/pci/drm/radeon/si.c
7399
WREG32(MPLL_BYPASSCLK_SEL, data);
sys/dev/pci/drm/radeon/si.c
7404
WREG32(SPLL_CNTL_MODE, data);
sys/dev/pci/drm/radeon/si_dpm.c
2608
WREG32(CG_CAC_CTRL, reg);
sys/dev/pci/drm/radeon/si_dpm.c
2703
WREG32(config_regs->offset << 2, data);
sys/dev/pci/drm/radeon/si_dpm.c
3159
WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
sys/dev/pci/drm/radeon/si_dpm.c
3331
WREG32(SMC_SCRATCH0, parameter);
sys/dev/pci/drm/radeon/si_dpm.c
3549
WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
sys/dev/pci/drm/radeon/si_dpm.c
3560
WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
sys/dev/pci/drm/radeon/si_dpm.c
3640
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/pci/drm/radeon/si_dpm.c
3659
WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
sys/dev/pci/drm/radeon/si_dpm.c
3703
WREG32(CG_BSP, pi->dsp);
sys/dev/pci/drm/radeon/si_dpm.c
3717
WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
sys/dev/pci/drm/radeon/si_dpm.c
3733
WREG32(CG_TPC, R600_TPC_DFLT);
sys/dev/pci/drm/radeon/si_dpm.c
3738
WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
sys/dev/pci/drm/radeon/si_dpm.c
3752
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/pci/drm/radeon/si_dpm.c
3759
WREG32(CG_FTV, pi->vrc);
sys/dev/pci/drm/radeon/si_dpm.c
3764
WREG32(CG_FTV, 0);
sys/dev/pci/drm/radeon/si_dpm.c
4712
WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
sys/dev/pci/drm/radeon/si_dpm.c
4713
WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
sys/dev/pci/drm/radeon/si_dpm.c
5488
WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
sys/dev/pci/drm/radeon/si_dpm.c
5489
WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
sys/dev/pci/drm/radeon/si_dpm.c
5490
WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
sys/dev/pci/drm/radeon/si_dpm.c
5491
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
sys/dev/pci/drm/radeon/si_dpm.c
5492
WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
sys/dev/pci/drm/radeon/si_dpm.c
5493
WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
sys/dev/pci/drm/radeon/si_dpm.c
5494
WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
sys/dev/pci/drm/radeon/si_dpm.c
5495
WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
sys/dev/pci/drm/radeon/si_dpm.c
5496
WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
sys/dev/pci/drm/radeon/si_dpm.c
5497
WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
sys/dev/pci/drm/radeon/si_dpm.c
5498
WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
sys/dev/pci/drm/radeon/si_dpm.c
5499
WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
sys/dev/pci/drm/radeon/si_dpm.c
5500
WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
sys/dev/pci/drm/radeon/si_dpm.c
5501
WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
sys/dev/pci/drm/radeon/si_dpm.c
5910
WREG32(CG_THERMAL_INT, thermal_int);
sys/dev/pci/drm/radeon/si_dpm.c
5919
WREG32(CG_THERMAL_INT, thermal_int);
sys/dev/pci/drm/radeon/si_dpm.c
5966
WREG32(CG_FDO_CTRL2, tmp);
sys/dev/pci/drm/radeon/si_dpm.c
5970
WREG32(CG_FDO_CTRL2, tmp);
sys/dev/pci/drm/radeon/si_dpm.c
6132
WREG32(CG_FDO_CTRL0, tmp);
sys/dev/pci/drm/radeon/si_dpm.c
6209
WREG32(CG_TACH_CTRL, tmp);
sys/dev/pci/drm/radeon/si_dpm.c
6225
WREG32(CG_FDO_CTRL2, tmp);
sys/dev/pci/drm/radeon/si_dpm.c
6229
WREG32(CG_FDO_CTRL2, tmp);
sys/dev/pci/drm/radeon/si_dpm.c
6249
WREG32(CG_TACH_CTRL, tmp);
sys/dev/pci/drm/radeon/si_dpm.c
6254
WREG32(CG_FDO_CTRL2, tmp);
sys/dev/pci/drm/radeon/si_smc.c
104
WREG32(SMC_IND_DATA_0, data);
sys/dev/pci/drm/radeon/si_smc.c
180
WREG32(SMC_MESSAGE_0, msg);
sys/dev/pci/drm/radeon/si_smc.c
265
WREG32(SMC_IND_INDEX_0, ucode_start_address);
sys/dev/pci/drm/radeon/si_smc.c
271
WREG32(SMC_IND_DATA_0, data);
sys/dev/pci/drm/radeon/si_smc.c
306
WREG32(SMC_IND_DATA_0, value);
sys/dev/pci/drm/radeon/si_smc.c
41
WREG32(SMC_IND_INDEX_0, smc_address);
sys/dev/pci/drm/radeon/si_smc.c
71
WREG32(SMC_IND_DATA_0, data);
sys/dev/pci/drm/radeon/sumo_dpm.c
110
WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK));
sys/dev/pci/drm/radeon/sumo_dpm.c
111
WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK));
sys/dev/pci/drm/radeon/sumo_dpm.c
113
WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK));
sys/dev/pci/drm/radeon/sumo_dpm.c
114
WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK));
sys/dev/pci/drm/radeon/sumo_dpm.c
137
WREG32(CG_GCOOR, PHC(grs) | SDC(p) | SU(u));
sys/dev/pci/drm/radeon/sumo_dpm.c
168
WREG32(CG_SCRATCH2, 0x01B60A17);
sys/dev/pci/drm/radeon/sumo_dpm.c
335
WREG32(CG_BSP_0, pi->psp);
sys/dev/pci/drm/radeon/sumo_dpm.c
353
WREG32(CG_BSP_0 + (i * 4), pi->dsp);
sys/dev/pci/drm/radeon/sumo_dpm.c
355
WREG32(CG_BSP_0 + (i * 4), pi->psp);
sys/dev/pci/drm/radeon/sumo_dpm.c
358
WREG32(CG_BSP_0 + (BOOST_DPM_LEVEL * 4), pi->psp);
sys/dev/pci/drm/radeon/sumo_dpm.c
365
WREG32(CG_AT_0, value);
sys/dev/pci/drm/radeon/sumo_dpm.c
367
WREG32(CG_AT_1, value);
sys/dev/pci/drm/radeon/sumo_dpm.c
369
WREG32(CG_AT_2, value);
sys/dev/pci/drm/radeon/sumo_dpm.c
371
WREG32(CG_AT_3, value);
sys/dev/pci/drm/radeon/sumo_dpm.c
373
WREG32(CG_AT_4, value);
sys/dev/pci/drm/radeon/sumo_dpm.c
375
WREG32(CG_AT_5, value);
sys/dev/pci/drm/radeon/sumo_dpm.c
377
WREG32(CG_AT_6, value);
sys/dev/pci/drm/radeon/sumo_dpm.c
379
WREG32(CG_AT_7, value);
sys/dev/pci/drm/radeon/sumo_dpm.c
452
WREG32(CG_FTV, vrc);
sys/dev/pci/drm/radeon/sumo_dpm.c
457
WREG32(CG_FTV, 0);
sys/dev/pci/drm/radeon/sumo_dpm.c
468
WREG32(CG_SSP, SSTU(u) | SST(p));
sys/dev/pci/drm/radeon/sumo_dpm.c
501
WREG32(CG_SCLK_DPM_CTRL_6, dpm_ctrl);
sys/dev/pci/drm/radeon/sumo_dpm.c
515
WREG32(CG_SCLK_DPM_CTRL_11, dpm_ctrl);
sys/dev/pci/drm/radeon/sumo_dpm.c
525
WREG32(CG_DPM_VOLTAGE_CNTL, voltage_cntl);
sys/dev/pci/drm/radeon/sumo_dpm.c
541
WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
sys/dev/pci/drm/radeon/sumo_dpm.c
746
WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);
sys/dev/pci/drm/radeon/sumo_dpm.c
806
WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);
sys/dev/pci/drm/radeon/sumo_dpm.c
882
WREG32(DOUT_SCRATCH3, v);
sys/dev/pci/drm/radeon/sumo_dpm.c
901
WREG32(DEEP_SLEEP_CNTL2, deep_sleep_cntl2);
sys/dev/pci/drm/radeon/sumo_dpm.c
902
WREG32(DEEP_SLEEP_CNTL, deep_sleep_cntl);
sys/dev/pci/drm/radeon/sumo_dpm.c
935
WREG32(CG_SCLK_DPM_CTRL_5, cg_sclk_dpm_ctrl_5);
sys/dev/pci/drm/radeon/sumo_dpm.c
946
WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
sys/dev/pci/drm/radeon/sumo_dpm.c
979
WREG32(CG_SCLK_DPM_CTRL_4, cg_sclk_dpm_ctrl_4);
sys/dev/pci/drm/radeon/sumo_smc.c
45
WREG32(GFX_INT_REQ, gfx_int_req);
sys/dev/pci/drm/radeon/sumo_smc.c
66
WREG32(GFX_INT_REQ, gfx_int_req);
sys/dev/pci/drm/radeon/trinity_dpm.c
339
WREG32(CG_PG_CTRL, SP(p) | SU(u));
sys/dev/pci/drm/radeon/trinity_dpm.c
369
WREG32(CGTS_SM_CTRL_REG, CGTS_SM_CTRL_REG_ENABLE);
sys/dev/pci/drm/radeon/trinity_dpm.c
371
WREG32(CGTS_SM_CTRL_REG, CGTS_SM_CTRL_REG_DISABLE);
sys/dev/pci/drm/radeon/trinity_dpm.c
422
WREG32(seq[i], seq[i+1]);
sys/dev/pci/drm/radeon/trinity_dpm.c
893
WREG32(CG_MISC_REG, tmp);
sys/dev/pci/drm/radeon/trinity_smc.c
115
WREG32(SMC_INT_REQ, 1);
sys/dev/pci/drm/radeon/trinity_smc.c
125
WREG32(SMC_INT_REQ, 0);
sys/dev/pci/drm/radeon/trinity_smc.c
34
WREG32(SMC_MESSAGE_0, id);
sys/dev/pci/drm/radeon/uvd_v1_0.c
123
WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
sys/dev/pci/drm/radeon/uvd_v1_0.c
124
WREG32(UVD_VCPU_CACHE_SIZE0, size);
sys/dev/pci/drm/radeon/uvd_v1_0.c
128
WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
sys/dev/pci/drm/radeon/uvd_v1_0.c
129
WREG32(UVD_VCPU_CACHE_SIZE1, size);
sys/dev/pci/drm/radeon/uvd_v1_0.c
134
WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
sys/dev/pci/drm/radeon/uvd_v1_0.c
135
WREG32(UVD_VCPU_CACHE_SIZE2, size);
sys/dev/pci/drm/radeon/uvd_v1_0.c
139
WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
sys/dev/pci/drm/radeon/uvd_v1_0.c
143
WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
sys/dev/pci/drm/radeon/uvd_v1_0.c
145
WREG32(UVD_FW_START, *((uint32_t *)rdev->uvd.cpu_addr));
sys/dev/pci/drm/radeon/uvd_v1_0.c
217
WREG32(MC_CONFIG, 0);
sys/dev/pci/drm/radeon/uvd_v1_0.c
218
WREG32(MC_CONFIG, 1 << 4);
sys/dev/pci/drm/radeon/uvd_v1_0.c
219
WREG32(RS_DQ_RD_RET_CONF, 0x3f);
sys/dev/pci/drm/radeon/uvd_v1_0.c
220
WREG32(MC_CONFIG, 0x1f);
sys/dev/pci/drm/radeon/uvd_v1_0.c
274
WREG32(UVD_CGC_GATE, 0);
sys/dev/pci/drm/radeon/uvd_v1_0.c
285
WREG32(UVD_SOFT_RESET, LMI_SOFT_RESET | VCPU_SOFT_RESET |
sys/dev/pci/drm/radeon/uvd_v1_0.c
295
WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
sys/dev/pci/drm/radeon/uvd_v1_0.c
303
WREG32(UVD_LMI_SWAP_CNTL, lmi_swap_cntl);
sys/dev/pci/drm/radeon/uvd_v1_0.c
304
WREG32(UVD_MP_SWAP_CNTL, mp_swap_cntl);
sys/dev/pci/drm/radeon/uvd_v1_0.c
306
WREG32(UVD_MPC_SET_MUXA0, 0x40c2040);
sys/dev/pci/drm/radeon/uvd_v1_0.c
307
WREG32(UVD_MPC_SET_MUXA1, 0x0);
sys/dev/pci/drm/radeon/uvd_v1_0.c
308
WREG32(UVD_MPC_SET_MUXB0, 0x40c2040);
sys/dev/pci/drm/radeon/uvd_v1_0.c
309
WREG32(UVD_MPC_SET_MUXB1, 0x0);
sys/dev/pci/drm/radeon/uvd_v1_0.c
310
WREG32(UVD_MPC_SET_ALU, 0);
sys/dev/pci/drm/radeon/uvd_v1_0.c
311
WREG32(UVD_MPC_SET_MUX, 0x88);
sys/dev/pci/drm/radeon/uvd_v1_0.c
314
WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);
sys/dev/pci/drm/radeon/uvd_v1_0.c
318
WREG32(UVD_VCPU_CNTL, 1 << 9);
sys/dev/pci/drm/radeon/uvd_v1_0.c
326
WREG32(UVD_SOFT_RESET, 0);
sys/dev/pci/drm/radeon/uvd_v1_0.c
358
WREG32(UVD_RBC_RB_CNTL, 0x11010101);
sys/dev/pci/drm/radeon/uvd_v1_0.c
361
WREG32(UVD_RBC_RB_WPTR_CNTL, 0);
sys/dev/pci/drm/radeon/uvd_v1_0.c
364
WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
sys/dev/pci/drm/radeon/uvd_v1_0.c
368
WREG32(UVD_RBC_RB_RPTR, 0x0);
sys/dev/pci/drm/radeon/uvd_v1_0.c
371
WREG32(UVD_RBC_RB_WPTR, ring->wptr);
sys/dev/pci/drm/radeon/uvd_v1_0.c
374
WREG32(UVD_RBC_RB_BASE, ring->gpu_addr);
sys/dev/pci/drm/radeon/uvd_v1_0.c
394
WREG32(UVD_RBC_RB_CNTL, 0x11010101);
sys/dev/pci/drm/radeon/uvd_v1_0.c
402
WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);
sys/dev/pci/drm/radeon/uvd_v1_0.c
406
WREG32(UVD_VCPU_CNTL, 0x0);
sys/dev/pci/drm/radeon/uvd_v1_0.c
427
WREG32(UVD_CONTEXT_ID, 0xCAFEDEAD);
sys/dev/pci/drm/radeon/uvd_v1_0.c
70
WREG32(UVD_RBC_RB_WPTR, ring->wptr);
sys/dev/pci/drm/radeon/uvd_v2_2.c
115
WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
sys/dev/pci/drm/radeon/uvd_v2_2.c
116
WREG32(UVD_VCPU_CACHE_SIZE0, size);
sys/dev/pci/drm/radeon/uvd_v2_2.c
120
WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
sys/dev/pci/drm/radeon/uvd_v2_2.c
121
WREG32(UVD_VCPU_CACHE_SIZE1, size);
sys/dev/pci/drm/radeon/uvd_v2_2.c
126
WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
sys/dev/pci/drm/radeon/uvd_v2_2.c
127
WREG32(UVD_VCPU_CACHE_SIZE2, size);
sys/dev/pci/drm/radeon/uvd_v2_2.c
131
WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
sys/dev/pci/drm/radeon/uvd_v2_2.c
135
WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
sys/dev/pci/drm/radeon/uvd_v2_2.c
196
WREG32(UVD_VCPU_CHIP_ID, chip_id);
sys/dev/pci/drm/radeon/uvd_v4_2.c
52
WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
sys/dev/pci/drm/radeon/uvd_v4_2.c
53
WREG32(UVD_VCPU_CACHE_SIZE0, size);
sys/dev/pci/drm/radeon/uvd_v4_2.c
57
WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
sys/dev/pci/drm/radeon/uvd_v4_2.c
58
WREG32(UVD_VCPU_CACHE_SIZE1, size);
sys/dev/pci/drm/radeon/uvd_v4_2.c
63
WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
sys/dev/pci/drm/radeon/uvd_v4_2.c
64
WREG32(UVD_VCPU_CACHE_SIZE2, size);
sys/dev/pci/drm/radeon/uvd_v4_2.c
68
WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
sys/dev/pci/drm/radeon/uvd_v4_2.c
72
WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
sys/dev/pci/drm/radeon/uvd_v4_2.c
75
WREG32(UVD_GP_SCRATCH4, rdev->uvd.max_handles);
sys/dev/pci/drm/radeon/vce_v1_0.c
100
WREG32(VCE_RB_WPTR2, ring->wptr);
sys/dev/pci/drm/radeon/vce_v1_0.c
110
WREG32(VCE_CLOCK_GATING_A, tmp);
sys/dev/pci/drm/radeon/vce_v1_0.c
115
WREG32(VCE_UENC_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v1_0.c
119
WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v1_0.c
123
WREG32(VCE_CLOCK_GATING_A, tmp);
sys/dev/pci/drm/radeon/vce_v1_0.c
128
WREG32(VCE_UENC_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v1_0.c
132
WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v1_0.c
142
WREG32(VCE_CLOCK_GATING_A, tmp);
sys/dev/pci/drm/radeon/vce_v1_0.c
147
WREG32(VCE_CLOCK_GATING_B, tmp);
sys/dev/pci/drm/radeon/vce_v1_0.c
151
WREG32(VCE_UENC_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v1_0.c
155
WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v1_0.c
225
WREG32(VCE_CLOCK_GATING_B, 0);
sys/dev/pci/drm/radeon/vce_v1_0.c
229
WREG32(VCE_LMI_CTRL, 0x00398000);
sys/dev/pci/drm/radeon/vce_v1_0.c
231
WREG32(VCE_LMI_SWAP_CNTL, 0);
sys/dev/pci/drm/radeon/vce_v1_0.c
232
WREG32(VCE_LMI_SWAP_CNTL1, 0);
sys/dev/pci/drm/radeon/vce_v1_0.c
233
WREG32(VCE_LMI_VM_CTRL, 0);
sys/dev/pci/drm/radeon/vce_v1_0.c
235
WREG32(VCE_VCPU_SCRATCH7, RADEON_MAX_VCE_HANDLES);
sys/dev/pci/drm/radeon/vce_v1_0.c
239
WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
sys/dev/pci/drm/radeon/vce_v1_0.c
240
WREG32(VCE_VCPU_CACHE_SIZE0, size);
sys/dev/pci/drm/radeon/vce_v1_0.c
244
WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
sys/dev/pci/drm/radeon/vce_v1_0.c
245
WREG32(VCE_VCPU_CACHE_SIZE1, size);
sys/dev/pci/drm/radeon/vce_v1_0.c
249
WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
sys/dev/pci/drm/radeon/vce_v1_0.c
250
WREG32(VCE_VCPU_CACHE_SIZE2, size);
sys/dev/pci/drm/radeon/vce_v1_0.c
254
WREG32(VCE_LMI_FW_START_KEYSEL, rdev->vce.keyselect);
sys/dev/pci/drm/radeon/vce_v1_0.c
298
WREG32(VCE_RB_RPTR, ring->wptr);
sys/dev/pci/drm/radeon/vce_v1_0.c
299
WREG32(VCE_RB_WPTR, ring->wptr);
sys/dev/pci/drm/radeon/vce_v1_0.c
300
WREG32(VCE_RB_BASE_LO, ring->gpu_addr);
sys/dev/pci/drm/radeon/vce_v1_0.c
301
WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
sys/dev/pci/drm/radeon/vce_v1_0.c
302
WREG32(VCE_RB_SIZE, ring->ring_size / 4);
sys/dev/pci/drm/radeon/vce_v1_0.c
305
WREG32(VCE_RB_RPTR2, ring->wptr);
sys/dev/pci/drm/radeon/vce_v1_0.c
306
WREG32(VCE_RB_WPTR2, ring->wptr);
sys/dev/pci/drm/radeon/vce_v1_0.c
307
WREG32(VCE_RB_BASE_LO2, ring->gpu_addr);
sys/dev/pci/drm/radeon/vce_v1_0.c
308
WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
sys/dev/pci/drm/radeon/vce_v1_0.c
309
WREG32(VCE_RB_SIZE2, ring->ring_size / 4);
sys/dev/pci/drm/radeon/vce_v1_0.c
98
WREG32(VCE_RB_WPTR, ring->wptr);
sys/dev/pci/drm/radeon/vce_v2_0.c
100
WREG32(VCE_CGTT_CLK_OVERRIDE, 0);
sys/dev/pci/drm/radeon/vce_v2_0.c
105
WREG32(VCE_CGTT_CLK_OVERRIDE, 7);
sys/dev/pci/drm/radeon/vce_v2_0.c
139
WREG32(VCE_CLOCK_GATING_A, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
144
WREG32(VCE_UENC_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
149
WREG32(VCE_CLOCK_GATING_B, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
166
WREG32(VCE_CLOCK_GATING_B, 0xf7);
sys/dev/pci/drm/radeon/vce_v2_0.c
168
WREG32(VCE_LMI_CTRL, 0x00398000);
sys/dev/pci/drm/radeon/vce_v2_0.c
170
WREG32(VCE_LMI_SWAP_CNTL, 0);
sys/dev/pci/drm/radeon/vce_v2_0.c
171
WREG32(VCE_LMI_SWAP_CNTL1, 0);
sys/dev/pci/drm/radeon/vce_v2_0.c
172
WREG32(VCE_LMI_VM_CTRL, 0);
sys/dev/pci/drm/radeon/vce_v2_0.c
174
WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8);
sys/dev/pci/drm/radeon/vce_v2_0.c
178
WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
sys/dev/pci/drm/radeon/vce_v2_0.c
179
WREG32(VCE_VCPU_CACHE_SIZE0, size);
sys/dev/pci/drm/radeon/vce_v2_0.c
183
WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
sys/dev/pci/drm/radeon/vce_v2_0.c
184
WREG32(VCE_VCPU_CACHE_SIZE1, size);
sys/dev/pci/drm/radeon/vce_v2_0.c
188
WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
sys/dev/pci/drm/radeon/vce_v2_0.c
189
WREG32(VCE_VCPU_CACHE_SIZE2, size);
sys/dev/pci/drm/radeon/vce_v2_0.c
46
WREG32(VCE_CLOCK_GATING_B, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
50
WREG32(VCE_UENC_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
54
WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
56
WREG32(VCE_CGTT_CLK_OVERRIDE, 0);
sys/dev/pci/drm/radeon/vce_v2_0.c
61
WREG32(VCE_CLOCK_GATING_B, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
66
WREG32(VCE_UENC_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
70
WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
86
WREG32(VCE_CLOCK_GATING_B, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
92
WREG32(VCE_UENC_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
97
WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);