WRITE_DATA_DST_SEL
WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
WRITE_DATA_DST_SEL(8) |
WRITE_DATA_DST_SEL(8) |
WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
WRITE_DATA_DST_SEL(8) |
ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
WRITE_DATA_DST_SEL(0)));
WRITE_DATA_DST_SEL(0)));
WRITE_DATA_DST_SEL(0)));
WRITE_DATA_DST_SEL(0)));
WRITE_DATA_DST_SEL(0)));
WRITE_DATA_DST_SEL(0)));
WRITE_DATA_DST_SEL(0)));
WRITE_DATA_DST_SEL(0)));
WRITE_DATA_DST_SEL(0)));
WRITE_DATA_DST_SEL(0)));
WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
WRITE_DATA_DST_SEL(8) |
WRITE_DATA_DST_SEL(8) |
ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
WRITE_DATA_DST_SEL(0) |
ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
WRITE_DATA_DST_SEL(8) |
WRITE_DATA_DST_SEL(8) |
WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
WRITE_DATA_DST_SEL(0) |
ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
radeon_ring_write(ring, WRITE_DATA_DST_SEL(1));
WRITE_DATA_DST_SEL(0)));
WRITE_DATA_DST_SEL(0)));
WRITE_DATA_DST_SEL(0)));
WRITE_DATA_DST_SEL(0)));
WRITE_DATA_DST_SEL(0)));
WRITE_DATA_DST_SEL(0)));
WRITE_DATA_DST_SEL(0)));
WRITE_DATA_DST_SEL(0)));