sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c

39

WREG8(AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2);

sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c

44

WREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

38

WREG8(NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2);

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

43

WREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0);

sys/dev/pci/drm/radeon/r100.c

2915

WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);

sys/dev/pci/drm/radeon/r100.c

2928

WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));

sys/dev/pci/drm/radeon/r100.c

3809

WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);

sys/dev/pci/drm/radeon/r100.c

3840

WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);

sys/dev/pci/drm/radeon/r100.c

3853

WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);

sys/dev/pci/drm/radeon/radeon_display.c

209

WREG8(RADEON_PALETTE_INDEX, 0);

sys/dev/pci/drm/radeon/radeon_display.c

72

WREG8(AVIVO_DC_LUT_RW_INDEX, 0);

sys/dev/pci/drm/radeon/radeon_drv.c

900

WREG8(RADEON_PALETTE_INDEX, index);

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

288

WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL);

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

290

WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0);