WRITE4
WRITE4(sc, sc->sc_regs.irqstatus_clear0, ~0);
WRITE4(sc, sc->sc_regs.irqstatus_clear1, ~0);
WRITE4(sc, sc->sc_regs.setdataout,
WRITE4(sc, sc->sc_regs.cleardataout,
WRITE4(sc, sc->sc_regs.oe, reg);
WRITE4(sc, sc->sc_regs.irqstatus0, 1 << GPIO_PIN_TO_OFFSET(gpio));
WRITE4(sc, sc->sc_regs.irqstatus_clear0, 1 << GPIO_PIN_TO_OFFSET(gpio));
WRITE4(sc, sc->sc_regs.irqstatus_set0, 1 << GPIO_PIN_TO_OFFSET(gpio));
WRITE4(sc, sc->sc_regs.fallingdetect, fe);
WRITE4(sc, sc->sc_regs.risingdetect, re);
WRITE4(sc, sc->sc_regs.leveldetect0, l0);
WRITE4(sc, sc->sc_regs.leveldetect1, l1);
WRITE4(sc, RTSX_HDBAR, dmap->dm_segs[0].ds_addr);
WRITE4(sc, RTSX_HDBCTLR, dmaflags);
WRITE4(sc, RTSX_HCBCTLR, RTSX_STOP_CMD);
WRITE4(sc, RTSX_HDBCTLR, RTSX_STOP_DMA);
WRITE4(sc, RTSX_BIPR, status);
WRITE4(sc, RTSX_BIPR, status);
WRITE4(sc, RTSX_BIER,
WRITE4(sc, RTSX_HAIMR, RTSX_HAIMR_BUSY |
WRITE4(sc, RTSX_HAIMR,
WRITE4(sc, RTSX_HCBAR, sc->regs4[0]);
WRITE4(sc, RTSX_HCBCTLR, sc->regs4[1]);
WRITE4(sc, RTSX_HDBAR, sc->regs4[2]);
WRITE4(sc, RTSX_HDBCTLR, sc->regs4[3]);
WRITE4(sc, RTSX_HAIMR, sc->regs4[4]);
WRITE4(sc, RTSX_BIER, sc->regs4[5]);
WRITE4(sc, RTSX_HCBAR, sc->dmap_cmd->dm_segs[0].ds_addr);
WRITE4(sc, RTSX_HCBCTLR,
WRITE4(AGP_AMD751_ATTBASE, gatt->ag_physical);
WRITE4(AGP_AMD751_ATTBASE, asc->gatt->ag_physical);
WRITE4(AGP_AMD751_TLBCTRL, 1);
WRITE4(AGP_I810_PGTBL_CTL, isc->gatt->ag_physical | 1);
WRITE4(sc, ALI_SCR, reg);
WRITE4(sc, ALI_RTSR, reg | 0x80);
WRITE4(sc, ALI_SCR, ALI_SCR_RESET);
WRITE4(sc, ALI_FIFOCR1, 0x83838383);
WRITE4(sc, ALI_FIFOCR2, 0x83838383);
WRITE4(sc, ALI_FIFOCR3, 0x83838383);
WRITE4(sc, ALI_INTERFACECR, ALI_IF_PO); /* XXX pcm out only */
WRITE4(sc, ALI_INTERRUPTCR, 0x00000000);
WRITE4(sc, ALI_INTERRUPTSR, 0x00000000);
WRITE4(sc, ALI_SCR, control);
WRITE4(sc, ALI_DMACR, val);
WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(port));
WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(chan->port));
WRITE4(sc, port + ALI_OFF_BDBAR, sc->sc_cddma + offs);
WRITE4(sc, ALI_DMACR, val);