sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

309

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

338

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

340

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

342

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

344

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

346

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_PQ_WPTR_POLL_CNTL1,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

351

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_EOP_RPTR,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

355

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

248

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

277

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_LO,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

279

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

281

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

283

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

285

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_PQ_WPTR_POLL_CNTL1,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

290

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_EOP_RPTR,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

294

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

557

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_DEQUEUE_REQUEST, type);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

94

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_CONFIG, sh_mem_config);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

95

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_BASES, sh_mem_bases);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5453

WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5455

WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5457

WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6082

WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1931

WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1943

WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2607

WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2608

WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2688

WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2689

WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2695

WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2700

WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3257

WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3460

WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3462

WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3529

WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp | 0x80);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3686

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3688

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3692

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3696

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3701

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3707

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3709

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3711

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3713

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3718

WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3720

WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3724

WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3728

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3730

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3734

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3738

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3740

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3744

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3746

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3766

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3770

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3772

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3776

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3778

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3782

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3799

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3811

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3814

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3818

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3819

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3820

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3821

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3822

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3823

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3824

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3825

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1239

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1240

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1245

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1313

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1315

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1322

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1330

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1734

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1736

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1809

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp | 0x80);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1966

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1968

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1972

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1976

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1981

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1987

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1989

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1991

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1993

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1998

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2000

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2004

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2008

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2010

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2014

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2018

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2020

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2024

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2026

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2045

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2049

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2051

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2055

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2057

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2061

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2079

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2091

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2094

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2098

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2099

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2100

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2101

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2102

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2103

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2104

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2105

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

718

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

730

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

102

WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

115

WREG32_SOC15_RLC(GC, 0,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

120

WREG32_SOC15_RLC(

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

171

WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

188

WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

193

WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

205

WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

215

WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

363

WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

97

WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

98

WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

99

WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

135

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_BASE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

136

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

137

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

141

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_LOW_ADDR,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

154

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

159

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

218

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL, tmp);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

239

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL, tmp);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

244

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL2, tmp);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

256

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL3, tmp);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

267

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL4, tmp);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

466

WREG32_SOC15_RLC(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL, tmp);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

210

WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

212

WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

215

WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

217

WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

228

WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

229

WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

230

WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

337

WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);