sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

228

WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

214

WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

975

WREG32_SOC15_IP(GC, reg, tmp) :

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

976

WREG32_SOC15_IP(MMHUB, reg, tmp);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5441

WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9080

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9086

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9133

WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9139

WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9248

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9262

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9294

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9308

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9339

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9437

WREG32_SOC15_IP(GC, target, tmp);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9447

WREG32_SOC15_IP(GC, target, tmp);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2228

WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6339

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6347

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6396

WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6404

WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6514

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6528

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6560

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6574

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6605

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6714

WREG32_SOC15_IP(GC, target, tmp);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6724

WREG32_SOC15_IP(GC, target, tmp);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1893

WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4721

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4729

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4772

WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4780

WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4890

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4904

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4936

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4950

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4981

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5989

WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5995

WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6051

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6087

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

502

WREG32_SOC15_IP(MMHUB, reg, tmp);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

530

WREG32_SOC15_IP(MMHUB, reg, tmp);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

398

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

401

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

571

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

574

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

635

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

637

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

639

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

713

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

717

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

718

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

719

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

720

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

722

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

723

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

724

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

725

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

729

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

731

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

738

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

742

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

744

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

749

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

751

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

758

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

778

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

779

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

789

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

823

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

831

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

421

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

424

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

479

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

481

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

483

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

551

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

562

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

566

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

567

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

568

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

569

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

571

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

572

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

573

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

574

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

579

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

581

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

588

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

592

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

594

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

599

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

600

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

606

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

623

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

624

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

635

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

651

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

660

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

670

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

678

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

232

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

235

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

402

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

405

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

468

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

494

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

506

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

510

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

511

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

512

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

513

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

515

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

516

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

517

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

518

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

522

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

524

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

528

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

530

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

537

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

538

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

544

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

547

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

548

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

561

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

562

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

573

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

580

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

586

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

595

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

602

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

607

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

615

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

770

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

774

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

776

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

234

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev,

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

238

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev,

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

406

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

409

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

461

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), mcu_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

498

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

502

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

503

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

504

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

505

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

507

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

508

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

509

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

510

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

514

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

516

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

520

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

522

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

533

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

534

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

540

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

543

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

544

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

557

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

558

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

569

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

576

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

582

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

590

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

597

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), temp);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

602

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

610

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

720

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL), tmp);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

722

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

724

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

729

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL), tmp);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

767

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), tmp);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

769

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0);

sys/dev/pci/drm/amd/amdgpu/soc15.c

500

WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp);