sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

1017

WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

234

WREG32_PLL_P(RADEON_PPLL_REF_DIV,

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

261

WREG32_PLL_P(RADEON_P2PLL_REF_DIV,

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

864

WREG32_PLL_P(RADEON_PIXCLKS_CNTL,

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

868

WREG32_PLL_P(RADEON_P2PLL_CNTL,

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

876

WREG32_PLL_P(RADEON_P2PLL_REF_DIV,

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

880

WREG32_PLL_P(RADEON_P2PLL_DIV_0,

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

884

WREG32_PLL_P(RADEON_P2PLL_DIV_0,

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

893

WREG32_PLL_P(RADEON_P2PLL_CNTL,

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

912

WREG32_PLL_P(RADEON_PIXCLKS_CNTL,

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

945

WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

948

WREG32_PLL_P(RADEON_PPLL_CNTL,

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

971

WREG32_PLL_P(RADEON_PPLL_REF_DIV,

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

976

WREG32_PLL_P(RADEON_PPLL_REF_DIV,

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

981

WREG32_PLL_P(RADEON_PPLL_REF_DIV,

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

985

WREG32_PLL_P(RADEON_PPLL_DIV_3,

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

989

WREG32_PLL_P(RADEON_PPLL_DIV_3,

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

998

WREG32_PLL_P(RADEON_PPLL_CNTL,

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

121

WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

758

WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL);

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

760

WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET);

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

764

WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET);

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

769

WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf);

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

770

WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL);

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

772

WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK);

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

773

WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP);