sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1519

WREG32_PLL(reg, tmp_); \

sys/dev/pci/drm/radeon/r100.c

2721

WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);

sys/dev/pci/drm/radeon/r100.c

3897

WREG32_PLL(R_00000D_SCLK_CNTL, tmp);

sys/dev/pci/drm/radeon/r100.c

437

WREG32_PLL(SCLK_CNTL, sclk_cntl);

sys/dev/pci/drm/radeon/r100.c

438

WREG32_PLL(SCLK_CNTL2, sclk_cntl2);

sys/dev/pci/drm/radeon/r100.c

439

WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);

sys/dev/pci/drm/radeon/r300.c

1368

WREG32_PLL(R_00000D_SCLK_CNTL, tmp);

sys/dev/pci/drm/radeon/r420.c

204

WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);

sys/dev/pci/drm/radeon/r520.c

87

WREG32_PLL(0x000D, tmp);

sys/dev/pci/drm/radeon/radeon.h

2594

WREG32_PLL(reg, tmp_); \

sys/dev/pci/drm/radeon/radeon_clocks.c

486

WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

490

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

496

WREG32_PLL(RADEON_SPLL_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

502

WREG32_PLL(RADEON_SPLL_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

509

WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

518

WREG32_PLL(RADEON_SPLL_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

522

WREG32_PLL(RADEON_SPLL_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

528

WREG32_PLL(RADEON_SPLL_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

549

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

555

WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

580

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

603

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

608

WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

613

WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

629

WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

638

WREG32_PLL(R300_SCLK_CNTL2, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

656

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

661

WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

666

WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

682

WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

687

WREG32_PLL(RADEON_MCLK_MISC, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

719

WREG32_PLL(RADEON_MCLK_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

724

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

731

WREG32_PLL(R300_SCLK_CNTL2, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

742

WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

747

WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

771

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

787

WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

799

WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

813

WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

820

WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

834

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

846

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

850

WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

856

WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

873

WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

879

WREG32_PLL(R300_SCLK_CNTL2, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

890

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

894

WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

901

WREG32_PLL(RADEON_MCLK_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

907

WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

924

WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

951

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

961

WREG32_PLL(R300_SCLK_CNTL2, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

969

WREG32_PLL(RADEON_MCLK_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

978

WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

991

WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

997

WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_combios.c

2990

WREG32_PLL(reg, val);

sys/dev/pci/drm/radeon/radeon_combios.c

3107

WREG32_PLL(addr, val);

sys/dev/pci/drm/radeon/radeon_combios.c

3120

WREG32_PLL(addr, tmp);

sys/dev/pci/drm/radeon/radeon_combios.c

3159

WREG32_PLL(RADEON_MCLK_CNTL,

sys/dev/pci/drm/radeon/radeon_combios.c

3163

WREG32_PLL

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

1022

WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

891

WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

916

WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

996

WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

133

WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1595

WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1669

WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

661

WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

704

WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

286

WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B);

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

295

WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test);

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

759

WREG32_PLL(RADEON_TV_PLL_CNTL, tv_pll_cntl);

sys/dev/pci/drm/radeon/rs600.c

274

WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);

sys/dev/pci/drm/radeon/rs600.c

286

WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);

sys/dev/pci/drm/radeon/rs600.c

293

WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);

sys/dev/pci/drm/radeon/rs600.c

301

WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);

sys/dev/pci/drm/radeon/rs600.c

308

WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);

sys/dev/pci/drm/radeon/rv515.c

155

WREG32_PLL(0x000D, tmp);

sys/dev/pci/drm/radeon/rv515.c

479

WREG32_PLL(R_00000F_CP_DYN_CNTL,

sys/dev/pci/drm/radeon/rv515.c

481

WREG32_PLL(R_000011_E2_DYN_CNTL,

sys/dev/pci/drm/radeon/rv515.c

483

WREG32_PLL(R_000013_IDCT_DYN_CNTL,