sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

501

WREG32_FIELD15_PREREG(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2129

WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2257

WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2259

WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2292

WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4377

WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4471

WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1806

WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1922

WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1924

WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1957

WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3254

WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3348

WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1377

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1523

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1540

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1543

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1559

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1964

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2065

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2328

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3156

WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3196

WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3235

WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

357

WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, SPARE, 0x1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

183

WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

402

WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

187

WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

407

WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

179

WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

399

WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

184

WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

392

WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

158

WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

154

WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

237

WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

389

WREG32_FIELD15_PREREG(NBIO, 0, BIF_BX0_BIF_DOORBELL_INT_CNTL,