sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

534

WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

513

WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0);

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

117

WREG32_FIELD15(DF, 0, DF_CS_AON0_CoherentSlaveModeCtrlA0,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10211

WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5345

WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5478

WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5480

WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5515

WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7033

WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7126

WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1809

WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2922

WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3121

WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3128

WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3130

WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3140

WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3684

WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3786

WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4070

WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5940

WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6038

WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6074

WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6107

WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6119

WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6123

WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6133

WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6142

WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

137

WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

366

WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

181

WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

381

WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

185

WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

407

WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2206

WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2208

WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);

sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c

141

WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);

sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c

151

WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c

154

WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2);

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

158

WREG32_FIELD15(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN,

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

109

WREG32_FIELD15(NBIO, 0, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

107

WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

211

WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

647

WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL_ALDE,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

650

WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

372

WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL_ALDEBARAN,

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

375

WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL, ENABLE, 1);