sys/arch/luna88k/dev/lunaws.c

176

setsioreg(sc->sc_ctl, WR5, sc->sc_wr[WR5]);

sys/arch/luna88k/dev/siotty.c

153

setsioreg(sc->sc_ctl, WR5, sc->sc_wr[WR5]);

sys/arch/luna88k/dev/siotty.c

385

sc->sc_wr[WR5] &= 0x9f;

sys/arch/luna88k/dev/siotty.c

388

sc->sc_wr[WR3] |= WR3_RX7BIT; sc->sc_wr[WR5] |= WR5_TX7BIT;

sys/arch/luna88k/dev/siotty.c

391

sc->sc_wr[WR3] |= WR3_RX8BIT; sc->sc_wr[WR5] |= WR5_TX8BIT;

sys/arch/luna88k/dev/siotty.c

405

setsioreg(sc->sc_ctl, WR5, sc->sc_wr[WR5]);

sys/arch/luna88k/dev/siotty.c

424

wr5 = sc->sc_wr[WR5];

sys/arch/luna88k/dev/siotty.c

448

sc->sc_wr[WR5] = wr5;

sys/arch/luna88k/dev/siotty.c

449

setsioreg(sc->sc_ctl, WR5, wr5);

sys/arch/luna88k/dev/siotty.c

671

setsioreg(sio, WR5, ch0_regs[WR5]);

sys/arch/luna88k/stand/boot/sio.c

212

sioreg(REG(0, WR5), WR5_TX8BIT | WR5_TXENBL | WR5_DTR | WR5_RTS); /* Tx */

sys/arch/luna88k/stand/boot/sio.c

221

sioreg(REG(1, WR5), WR5_TX8BIT | WR5_TXENBL); /* Tx */