WR4
setsioreg(sc->sc_ctl, WR4, sc->sc_wr[WR4]);
setsioreg(sc->sc_ctl, WR4, sc->sc_wr[WR4]);
sc->sc_wr[WR4] = wr4;
setsioreg(sc->sc_ctl, WR4, sc->sc_wr[WR4]);
setsioreg(sio, WR4, ch0_regs[WR4]);
sioreg(REG(0, WR4), WR4_BAUD96 | WR4_STOP1 | WR4_NPARITY); /* Tx/Rx */
sioreg(REG(1, WR4), WR4_BAUD96 | WR4_STOP1 | WR4_NPARITY); /* Tx/Rx */
WR4(sc, GENET_MDIO_CMD,
WR4(sc, GENET_MDIO_CMD,
WR4(sc, GENET_EXT_RGMII_OOB_CTRL, val);
WR4(sc, GENET_UMAC_CMD, val);
WR4(sc, GENET_TX_DESC_ADDRESS_LO(index), (uint32_t)paddr);
WR4(sc, GENET_TX_DESC_ADDRESS_HI(index), (uint32_t)(paddr >> 32));
WR4(sc, GENET_TX_DESC_STATUS(index), status);
WR4(sc, GENET_RX_DESC_ADDRESS_LO(index), (uint32_t)paddr);
WR4(sc, GENET_RX_DESC_ADDRESS_HI(index), (uint32_t)(paddr >> 32));
WR4(sc, GENET_RX_DMA_CONS_INDEX(qid), sc->sc_rx.cidx);
WR4(sc, GENET_INTRL2_CPU_CLEAR_MASK,
WR4(sc, GENET_INTRL2_CPU_SET_MASK, 0xffffffff);
WR4(sc, GENET_INTRL2_CPU_CLEAR, 0xffffffff);
WR4(sc, GENET_UMAC_MDF_ADDR0(n), addr0);
WR4(sc, GENET_UMAC_MDF_ADDR1(n), addr1);
WR4(sc, GENET_UMAC_CMD, cmd);
WR4(sc, GENET_UMAC_MDF_CTRL, mdf_ctrl);
WR4(sc, GENET_UMAC_CMD, val);
WR4(sc, GENET_RX_DMA_CTRL, val);
WR4(sc, GENET_TX_DMA_CTRL, val);
WR4(sc, GENET_UMAC_TX_FLUSH, 1);
WR4(sc, GENET_UMAC_TX_FLUSH, 0);
WR4(sc, GENET_UMAC_CMD, val);
WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, val);
WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, val);
WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, 0);
WR4(sc, GENET_UMAC_CMD, 0);
WR4(sc, GENET_UMAC_CMD,
WR4(sc, GENET_UMAC_CMD, 0);
WR4(sc, GENET_UMAC_MIB_CTRL, GENET_UMAC_MIB_RESET_RUNT |
WR4(sc, GENET_UMAC_MIB_CTRL, 0);
WR4(sc, GENET_UMAC_MAX_FRAME_LEN, 1536);
WR4(sc, GENET_RBUF_CTRL, val);
WR4(sc, GENET_RBUF_TBUF_SIZE_CTRL, 1);
WR4(sc, GENET_TX_SCB_BURST_SIZE, 0x08);
WR4(sc, GENET_TX_DMA_READ_PTR_LO(qid), 0);
WR4(sc, GENET_TX_DMA_READ_PTR_HI(qid), 0);
WR4(sc, GENET_TX_DMA_CONS_INDEX(qid), sc->sc_tx.cidx);
WR4(sc, GENET_TX_DMA_PROD_INDEX(qid), sc->sc_tx.pidx);
WR4(sc, GENET_TX_DMA_RING_BUF_SIZE(qid),
WR4(sc, GENET_TX_DMA_START_ADDR_LO(qid), 0);
WR4(sc, GENET_TX_DMA_START_ADDR_HI(qid), 0);
WR4(sc, GENET_TX_DMA_END_ADDR_LO(qid),
WR4(sc, GENET_TX_DMA_END_ADDR_HI(qid), 0);
WR4(sc, GENET_TX_DMA_MBUF_DONE_THRES(qid), 1);
WR4(sc, GENET_TX_DMA_FLOW_PERIOD(qid), 0);
WR4(sc, GENET_TX_DMA_WRITE_PTR_LO(qid), 0);
WR4(sc, GENET_TX_DMA_WRITE_PTR_HI(qid), 0);
WR4(sc, GENET_TX_DMA_RING_CFG, __BIT(qid)); /* enable */
WR4(sc, GENET_TX_DMA_CTRL, val);
WR4(sc, GENET_RX_SCB_BURST_SIZE, 0x08);
WR4(sc, GENET_RX_DMA_WRITE_PTR_LO(qid), 0);
WR4(sc, GENET_RX_DMA_WRITE_PTR_HI(qid), 0);
WR4(sc, GENET_RX_DMA_PROD_INDEX(qid), sc->sc_rx.pidx);
WR4(sc, GENET_RX_DMA_CONS_INDEX(qid), sc->sc_rx.cidx);
WR4(sc, GENET_RX_DMA_RING_BUF_SIZE(qid),
WR4(sc, GENET_RX_DMA_START_ADDR_LO(qid), 0);
WR4(sc, GENET_RX_DMA_START_ADDR_HI(qid), 0);
WR4(sc, GENET_RX_DMA_END_ADDR_LO(qid),
WR4(sc, GENET_RX_DMA_END_ADDR_HI(qid), 0);
WR4(sc, GENET_RX_DMA_XON_XOFF_THRES(qid),
WR4(sc, GENET_RX_DMA_READ_PTR_LO(qid), 0);
WR4(sc, GENET_RX_DMA_READ_PTR_HI(qid), 0);
WR4(sc, GENET_RX_DMA_RING_CFG, __BIT(qid)); /* enable */
WR4(sc, GENET_RX_DMA_CTRL, val);
WR4(sc, GENET_SYS_PORT_CTRL,
WR4(sc, GENET_UMAC_MAC0, val);
WR4(sc, GENET_UMAC_MAC1, val);
WR4(sc, GENET_UMAC_CMD, val);
WR4(sc, GENET_TX_DMA_PROD_INDEX(qid), sc->sc_tx.pidx);
WR4(sc, GENET_INTRL2_CPU_CLEAR, val);